INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4060
14-stage binary ripple counter with
oscillator
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

FEATURES terminals (RS, RTC and CTC), ten buffered outputs (Q3 to
Q9 and Q11 to Q13) and an overriding asynchronous
• All active components on chip
master reset (MR).
• RC or crystal oscillator configuration The oscillator configuration allows design of either RC or
• Output capability: standard (except for RTC and CTC) crystal oscillator circuits. The oscillator may be replaced by
an external clock signal at input RS. In this case keep the
• ICC category: MSI
other oscillator pins (RTC and CTC) floating.
The counter advances on the negative-going transition of
GENERAL DESCRIPTION
RS. A HIGH level on MR resets the counter (Q3 to Q9 and
The 74HC/HCT4060 are high-speed Si-gate CMOS Q11 to Q13 = LOW), independent of other input conditions.
devices and are pin compatible with “4060” of the “4000B”
In the HCT version, the MR input is TTL compatible, but
series. They are specified in compliance with JEDEC
the RS input has CMOS input switching levels and can be
standard no. 7A.
driven by a TTL output by using a pull-up resistor to VCC.
The 74HC/HCT4060 are 14-stage ripple-carry
counter/dividers and oscillators with three oscillator

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
RS to Q3 31 31 ns
Qn to Qn+1 6 6 ns
tPHL MR to Qn 17 18 ns
fmax maximum clock frequency 87 88 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1, 2 and 3 40 40 pF

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
3. For formula on dynamic power dissipation see next pages.

ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990 2
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2, 3 Q11 to Q13 counter outputs
7, 5, 4, 6, 14, 13, 15 Q3 to Q9 counter outputs
8 GND ground (0 V)
9 CTC external capacitor connection
10 RTC external resistor connection
11 RS clock input/oscillator pin
12 MR master reset
16 VCC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

DYNAMIC POWER DISSIPATION FOR 74HC

PARAMETER VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1)

total dynamic power 2.0 CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 60 × VCC
dissipation when using the 4.5 CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC
on-chip oscillator (PD) 6.0 CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 3 800 × VCC

Note
1. GND = 0 V; Tamb = 25 °C

DYNAMIC POWER DISSIPATION FOR 74HCT

PARAMETER VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1)

total dynamic power
dissipation when using the 4.5 CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC
on-chip oscillator (PD)
Notes
1. GND = 0 V; Tamb = 25 °C
2. Where: fo = output frequency in MHz
fosc = oscillator frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
Ct = timing capacitance in pF
VCC = supply voltage in V

Fig.4 Functional diagram.

APPLICATIONS
• Control counters
• Timers
• Frequency dividers
• Time-delay circuits

December 1990 4
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

Fig.5 Logic diagram.

Fig.6 Timing diagram.

December 1990 5
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

DC CHARACTERISTICS FOR 74HC

Output capability: standard (except for RTC and CTC)
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C) TEST CONDITIONS

SYM- 74HC
PARAMETER UNIT V VI OTHER
BOL +25 −40 to +85 −40 to +125
CC
(V)
min. typ. max. min. max. min. max.
VIH HIGH level input voltage 1.5 1.3 1.5 1.5 V 2.0
MR input 3.15 2.4 3.15 3.15 4.5
4.2 3.1 4.2 4.2 6.0
VIL LOW level input voltage 0.8 0.5 0.5 0.5 V 2.0
MR input 2.1 1.35 1.35 1.35 4.5
2.8 1.8 1.8 1.8 6.0
VIH HIGH level input voltage 1.7 1.7 1.7 V 2.0
RS input 3.6 3.6 3.6 4.5
4.8 4.8 4.8 6.0
VIL LOW level input voltage 0.3 0.3 0.3 V 2.0
RS input 0.9 0.9 0.9 4.5
1.2 1.2 1.2 6.0
VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 RS=GND −IO = 2.6 mA
RTC output 5.48 5.34 5.2 6.0 and −IO = 3.3 mA
MR=GND
3.98 3.84 3.7 V 4.5 RS=VCC −IO = 0.65 mA
5.48 5.34 5.2 6.0 and −IO = 0.85 mA
MR=VCC
1.9 2.0 1.9 1.9 V 2.0 RS=GND −IO = 20 µA
4.4 4.5 4.4 4.4 4.5 and −IO = 20 µA
5.9 6.0 5.9 5.9 6.0 MR=GND −IO = 20 µA
1.9 2.0 1.9 1.9 V 2.0 RS=VCC −IO = 20 µA
4.4 4.5 4.4 4.4 4.5 and −IO = 20 µA
5.9 6.0 5.9 5.9 6.0 MR=VCC −IO = 20 µA
VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 RS=VIH −IO = 3.2 mA
CTC output 5.48 5.34 5.2 6.0 and −IO = 4.2 mA
MR=VIL
VOH HIGH level output voltage 1.9 2.0 1.9 1.9 V 2.0 VIH −IO = 20 µA
except RTC output 4.4 4.5 4.4 4.4 4.5 or −IO = 20 µA
5.9 6.0 5.9 5.9 6.0 VIL −IO = 20 µA
VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 VIH −IO = 4.0 mA
except RTC and CTC 5.48 5.34 5.2 6.0 or −IO = 5.2 mA
outputs VIL
VOL LOW level output voltage 0.26 0.33 0.4 4.5 RS=VCC IO = 2.6 mA
RTC output 0.26 0.33 0.4 6.0 and IO = 3.3 mA
MR=GND
0 0.1 0.1 0.1 V 2.0 RS=VCC IO = 20 µA
0 0.1 0.1 0.1 4.5 and IO = 20 µA
0 0.1 0.1 0.1 6.0 MR=GND IO = 20 µA

December 1990 6
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

Tamb (°C) TEST CONDITIONS

SYM- 74HC
PARAMETER UNIT V VI OTHER
BOL +25 −40 to +85 −40 to +125
CC
(V)
min. typ. max. min. max. min. max.
VOL LOW level output voltage 0.26 0.33 0.4 V 4.5 RS=VIL IO = 3.2 mA
CTC output 0.26 0.33 0.4 6.0 and IO = 4.2 mA
MR=VIH
VOL LOW level output voltage 0 0.1 0.1 0.1 V 2.0 VIH IO = 20 µA
except RTC output 0 0.1 0.1 0.1 4.5 or IO = 20 µA
0 0.1 0.1 0.1 6.0 VIL IO = 20 µA
VOL LOW level output voltage 0.26 0.33 0.4 V 4.5 VIH IO = 4.0 mA
except RTC and CTC 0.26 0.33 0.4 6.0 or IO = 5.2 mA
outputs VIL
±II input leakage current 0.1 1.0 1.0 µA 6.0 VCC
or
GND
ICC quiescent supply current 8.0 80.0 160.0 µA 6.0 VCC IO = 0
or
GND

December 1990 7
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
99 300 375 450 2.0
propagation delay
tPHL/ tPLH 36 60 75 90 ns 4.5 Fig.12
RS to Q3
29 51 64 77 6.0
22 80 100 120 2.0
propagation delay
tPHL/ tPLH 8 16 20 24 ns 4.5 Fig.14
Qn to Qn+1
6 14 17 20 6.0
55 175 220 265 2.0
propagation delay
tPHL 20 35 44 53 ns 4.5 Fig.13
MR to Qn
16 30 37 45 6.0
19 75 95 110 2.0
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.12
6 13 16 19 6.0
80 17 100 120 2.0
clock pulse width
tW 16 6 20 24 ns 4.5 Fig.12
RS; HIGH or LOW
14 5 17 20 6.0
80 25 100 120 2.0
master reset pulse
tW 16 9 20 24 ns 4.5 Fig.13
width MR; HIGH
14 7 17 20 6.0
100 28 125 150 2.0
removal time
trem 20 10 25 30 ns 4.5 Fig.13
MR to RS
17 8 21 26 6.0
6.0 26 4.8 4.0 2.0
maximum clock pulse
fmax 30 80 24 20 MHz 4.5 Fig.12
frequency
35 95 28 24 6.0

December 1990 8
December 1990

Philips Semiconductors
DC CHARACTERISTICS FOR 74HCT

oscillator
14-stage binary ripple counter with
Output capability: standard (except for RTC and CTC)
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C) TEST CONDITIONS
74HCT
SYMBOL PARAMETER UNIT VCC VI OTHER
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
VIH HIGH level input voltage 2.0 2.0 2.0 V 4.5 to 5.5 note 2
VIL LOW level input voltage 0.8 0.8 0.8 V 4.5 to 5.5 note 2
VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 RS=GND and MR=GND −IO = 2.6 mA
RTC output 3.98 3.84 3.7 V 4.5 RS = VCC and MR = VCC −IO = 0.65 mA
4.4 4.5 4.4 4.4 V 4.5 RS=GND and MR=GND −IO = 20 µA
4.4 4.5 4.4 4.4 V 4.5 RS=VCC and MR=VCC −IO = 20 µA
VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 RS = VIH and MR = VIL −IO = 3.2 mA
CTC output
VOH HIGH level output voltage 4.4 4.5 4.4 4.4 V 4.5 VIH or VIL −IO = 20 µA
9

except RTC output

VOH HIGH level output voltage 3.98 3.84 3.7 V 4.5 VIH or VIL −IO = 4.0 mA
except RTC and CTC
outputs
VOL LOW level output voltage 0.26 0.33 0.4 V 4.5 RS=VCC and MR=GND IO = 2.6 mA
RTC output 0 0.1 0.1 0.1 V 4.5 RS=VCC and MR=GND IO = 20 µA
VOL LOW level output voltage 0.26 0.33 0.4 V 4.5 RS = VIL and MR = VIH IO = 3.2 mA
CTC output
VOL LOW level output voltage 0 0.1 0.1 0.1 V 4.5 VIH or VIL IO = 20 µA
except RTC output

74HC/HCT4060
VOL LOW level output voltage 0.26 0.33 0.4 V 4.5 VIH or VIL IO = 4.0 mA
except RTC and CTC

Product specification
outputs
±I input leakage current 0.1 1.0 1.0 µA 5.5 VCC or GND
ICC quiescent supply current 8.0 80.0 160.0 µA 5.5 VCC or GND IO = 0
∆ICC additional quiescent supply 100 360 450 490 µA 4.5 to 5.5 VCC − 2.1 V other inputs at
current per input pin for unit VCC or GND;
load coefficient is 1 (note 1) IO = 0
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

Notes
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
2. Only input MR (pin 12) has TTL input switching levels for the HCT versions.

INPUT UNIT LOAD COEFFICIENT

MR 0.40

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER UNIT V WAVEFORMS
+25 −40 to +85 −40 to +125 CC
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 33 66 83 99 ns 4.5 Fig.12
RS to Q3
tPHL/ tPLH propagation delay 8 16 20 24 ns 4.5 Fig.14
Qn to Qn+1
tPHL propagation delay 21 44 55 66 ns 4.5 Fig.13
MR to Qn
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.12

tW clock pulse width 16 6 20 24 ns 4.5 Fig.12

RS; HIGH or LOW
tW master reset pulse 16 6 20 24 ns 4.5 Fig.13
width MR; HIGH
trem removal time 26 13 33 39 ns 4.5 Fig.13
MR to RS
fmax maximum clock pulse 30 80 24 20 MHz 4.5 Fig.12
frequency

December 1990 10
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

MBA333
14
g halfpage
handbook,
max.
fs
(mA/V)
12
typ.
10

8
min.

4
Fig.7 Test set-up for measuring forward
transconductance gfs = dio / dvi at vo is 2
0 1 2 3 4 5 6
constant (see also graph Fig.8); VCC (V)
MR = LOW.
Fig.8 Typical forward transconductance gfs as a
function of the supply voltage VCC at
Tamb = 25 °C.

RC OSCILLATOR

Typical formula for oscillator frequency:

1
f osc = --------------------------------
2.5 × R t × C t
Fig.9 RC oscillator frequency as a function of
Rt and Ct at VCC = 2.0 to 6.0 V; Tamb = 25 °C.
Ct curve at Rt = 100 kΩ; R2 = 200 kΩ.
Rt curve at Ct = 1 nF; R2 = 2 × Rt. Fig.10 Example of a RC oscillator.

TIMING COMPONENT LIMITATIONS

The oscillator frequency is mainly determined by RtCt, provided R2 ≈ 2Rt and R2C2 << RtCt. The function of R2 is to
minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance
C2 should be kept as small as possible. In consideration of accuracy, Ct must be larger than the inherent stray
capacitance. Rt must be larger than the “ON” resistance in series with it, which typically is 280 Ω at VCC = 2.0 V, 130 Ω at
VCC = 4.5 V and 100 Ω at VCC = 6.0 V.
The recommended values for these components to maintain agreement with the typical oscillation formula are:
Ct > 50 pF, up to any practical value,
10 kΩ < Rt < 1 MΩ.
In order to avoid start-up problems, Rt ≥ 1 kΩ.

December 1990 11
Philips Semiconductors Product specification

14-stage binary ripple counter with oscillator 74HC/HCT4060

TYPICAL CRYSTAL OSCILLATOR

In Fig.11, R2 is the power limiting resistor.
For starting and maintaining oscillation a minimum
transconductance is necessary, so R2 should not
be too large. A practical value for R2 is 2.2 kΩ.

Fig.11 External components connection for a crystal oscillator.

AC WAVEFORMS

(1) HC : VM = 50%; VI = GND to VCC. (1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.12 Waveforms showing the clock (RS) to Fig.13 Waveforms showing the master reset (MR)
output (Q3) propagation delays, the clock pulse width, the master reset to output (Qn)
pulse width, the output transition times and propagation delays and the master reset to
the maximum clock frequency. clock (RS) removal time.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.14 Waveforms showing the output (Qn) to Qn+1 propagation delays.

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990 12