SECOND SEMESTER 2020-2021

(COURSE HANDOUT PART II)

Date: 15/03/2021
In addition to Part I (General Handout for all courses appended to the timetable) this portion gives
further specific details regarding the course.

Course No : CS G553
Course Title : Reconfigurable Computing
Instructors/in-charge : PAWAN SHARMA, GEORGE TOM

1) Scope and Objective

The scope of the course is to cover a broad range of backgrounds and design experience using
Hardware Description Language to develop the knowledge required to use FPGAs to prototype digital
design concepts. The introduction of reconfigurable devices has established a large area of research
under the name reconfigurable computing which, in particular, comprises the investigation of self-
adaptive hardware systems. These systems are capable to exchange, update, or extend hardware
functionality after production at runtime. With the power of dynamic and partial reconfiguration,
reconfigurable systems may be implemented more cost and power efficient on smaller devices or faster
compared to its ASIC counterparts.
The purpose of the course is to instruct students about the possibilities of developing interest in rapidly
growing adaptive hardware and corresponding design techniques by providing them the necessary
knowledge for understanding and designing reconfigurable hardware systems and studying
applications benefiting from dynamic hardware reconfiguration.

2) Contents
The course covers the following aspects of FPGA design:
• Reconfigurable computing systems (Fine and coarse grained architectures and technology)
• Design and implementation (Algorithms and steps to implement algorithms to FPGAs)
• Partial Reconfiguration
• Logic Synthesis and technology mapping
• Temporal partitioning (Techniques to reconfigure systems over time)
• Temporal placement (Techniques and algorithms to exploit the possibility of partial and
dynamic hardware reconfiguration)
• On-line communication (State-of-the-art techniques about how modules can communicate
data at run-time)
• Applications (applications benefiting from dynamic hardware reconfiguration and verification
using Xilinx System Design tools and Boards).

3) Background
Background for the course is a basic knowledge in the following areas: digital design, optimization
algorithms, and computer architecture.

4) Text Book
1. Scott Hauck, André DeHon, Reconfigurable Computing - The Theory and Practice of FPGA
Based Computation, The Morgan Kaufmann Series in Systems on Silicon, 2007.
 5) Reference Book
1. Wolf Wayne, FPGA Based System Design, Pearson Edu, 2004.
2. C Bobda, Introduction to Reconfigurable Computing: Architectures, Algorithms, and
Applications, Springer, 2007.
3. Dirk Koch, Partial Reconfiguration on FPGAs, Architectures, Tools and Applications. Springer
ISBN 978-1-4614-1224-3, 2013.
4. Giovanni De Micheli, synthesis and optimization of digital circuits, Tata McGraw-Hill, 2003

1. Course Plan

Lecture No. Learning Objectives Topics to be covered

1-4 Introduction Introduction application and comparison

• General Purpose Computing
• Domain Specific Computing
• Application Specific Computing
• Reconfigurable Computing
5-6 Reconfigurable Programmable logic, an overview of
Computing Hardware • PLA, PAL, SPLD and CPLD
To be Hardware Description Modeling with HDLs
discussed in Languages • Verilog/VHDL
Lab

7-8 Reconfigurable FPGA Architecture, FPGA Fabrics

Computing Device Configuration
• SRAM Based-FPGAs
• Permanently Programmed FPGAs
Programmable I/O, Circuit Design of FPGA Fabrics, Architecture
of FPGA Fabrics, Case Studies (Xilinx, Altera, Actel etc).
9-12 Reconfigurable Fine - Grained and Course - Grained Reconfigurable
Computing Architecture Architecture, Case Studies.
13-16 Programming Logic Design Process
Reconfigurable Systems • Design
• Integration
• FPGA Design Flow
Implementation Approaches
• Run Time Reconfiguration (RTR)
• Partial Reconfiguration (PR)
17-24 Mapping Designs to Logic Implementation for FPGAs, Syntax-Directed Translation
Reconfigurable Platform Logic Synthesis
• Two-Level Logic Synthesis
• Multi-Level Logic Synthesis
LUT-Based Technology Mapping
25-35 High-Level Synthesis for Modeling
Reconfigurable Devices • DFG, CFG
(Behavioral Design) Introduction to Binding, Scheduling and Allocation, Temporal
Partitioning
Temporal Partitioning Algorithms
• ASAP
• ALAP
35-39 Temporal Placement and Offline and Online Temporal Placement
Routing Routing Cost, Routing-Conscious Placement
39-40 Online Communication Communication at run-time between modules on the
Reconfigurable Device
2. Evaluation Scheme
EC Evaluation Duration Marks Date and Time Nature of
No. Component (min) (Weightage %) Component

1 Mid-term examination 120 Min 30% To be announced Closed Book

4 Regular Labs NA 10% To be announced Open Book
5 Lab Assignments NA 20% To be announced Open Book
6 Comprehensive Exam 120 Min 40% As announced in Open Book
the Time Table

3. Lab
This course has lab components using Xilinx Vivado, Xilinx System Generator.

Practical Name of the experiment No of

No sessions
1. Introduction to Verilog, Modelling Styles (Lecture) 1
2. Basics of Verilog HDL (Lecture) 1
3. Simple Programs in Verilog (Exercise) 1
4. Demonstration of Design, Synthesis and Implementation of digital block on 1
FPGA (Demo + Exercise)
5. Deign of Counter on FPGA (Demo + Exercise) 1
6. Deign of Counter on FPGA (Exercise) 1
7. FSM Design using Verilog (Lecture + Exercise) 1
8. Lab Assignment 1 (Demonstration by Students) 2
9.
10. VIO (Virtual Input/output) IP for Debugging (Lecture + Demo) 1
11. Implementation of ALU using VIO (Exercise) 3
12.
13.
14. Integrated Logic Analyzer IP (Demo) 1
15. System Generator (Demo) 1
16. Lab Assignment 2 (Demonstration by Students) 2
17.
18. Vivado HLS (Demo + Exercise) 1
20. Practice Labs
21.

4. Makeup
Make-up will be given on genuine grounds only. Prior application should be made for seeking the
make- up examination.

Instructor - in - charge
CS G553

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