COEN-4710 Computer Hardware

Lecture 3
Processor Part 1: Datapath and Control (Ch.4)

Cristinel Ababei
Marquette University
Department of Electrical and Computer Engineering

Page 1

Goals of this Chapter

❖Design a datapath and control that implement
the RISC-V instruction set architecture (ISA).
❖By the end of this chapter, you should:
◆Be able to design a datapath for an instruction set
◆Be able to design a control logic for the datapath
◆Understand the importance of the clocking
methodology on the processor design
❖We will examine two RISC-V implementations
◆A simplified version
◆A more realistic pipelined version

Page 2

Page 1
 What are datapath and control?

❖ Datapath
◆ The path the “data” follow and undergo computations.
◆ Realized by the hardware components connected in a way to
perform operations on data such that machine instructions are
implemented.
❖ Control
◆ Control is the sequential logic that reconfigures the Datapath to
allow the “data” to flow properly through the hardware
components.
◆ Responsible with the generation of all control signals to
“orchestrate” the correct flow of data through Datapath!
◆ Can be implemented as finite state-machine(s).
◆ Can also be implemented as a computer inside of a computer
(microcode).

Page 3

Design Process
1. Select a subset of the instruction set to
implement. Simple subset, shows most
aspects
◆Memory reference: ld, sd
◆Arithmetic/logical: add, sub, and, or
◆Control transfer: beq
2. Order the steps within instruction cycle
(performed during instruction execution)
3. Select the hardware components.
4. Connect the hardware components.
5. Design the control to make the components
work together properly.
Page 4

Page 2
 Order the steps: F I D E
❖ FIDE – the sequence of activities that
happens during instruction execution
1. Fetch (the instruction)
2. “Increment” (the Program Counter)
3. Decode (the Instruction Register)
4. Execute (using datapath hardware)

Page 5

Fetch and Increment Hardware

Instruction
Instruction Memory Instruction
address Adder

PC

Page 6

Page 3
 Fetch and Increment Connections

Adder

4
Increment by
4 for next
instruction

Instruction
PC Instruction
address
Memory Instruction

64-bit
register
Page 7

Decode and Execute

❖Decode
◆Takes the Instruction Register (IR) and computes
the bits needed to control the datapath (R/W flags,
enables, mux selects, etc.)
◆We will work more on the control later
❖Execute
◆Take the inputs specified by the instruction, and
complete the required operation

Page 8

Page 4
 Instruction Execution
❖PC → instruction memory, fetch instruction
❖Register numbers → register file, read
registers
❖Depending on instruction class
◆Use ALU to calculate
➢ Arithmetic result
➢ Memory address for load/store
➢ Branch comparison
◆Access data memory for load/store
◆PC  target address or PC + 4

Page 9

R-format Example: “ADD” Instruction

funct7 rs2 rs1 funct3 rd opcode

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x9,x20,x21
0 21 20 0 9 51

0000000 10101 10100 000 01001 0110011

❖ For the execute step of FIDE, what hardware

do we need?

Page 10

10

Page 5
 R-Format Instructions - Hardware
❖Read two register operands
❖Perform arithmetic/logical operation
❖Write register result

Page 11

11

With Hardware Connections

0010

rs1 [19-15] read reg1

read data1
rs2 [24-20] read reg2
read data2
zero
rd [11-7] write reg
ALU
write data result

Registers

Page 12

12

Page 6
 Complete “Add” Datapath

PC Adder

read reg1
read data1
read reg2
read data2
Instruction write reg
zero
ALU
Memory write data result

Registers
Page 13

13

Complete Add Datapath

PC Adder

read reg1
read data1
read reg2
read data2
Instruction write reg
zero
ALU
Memory write data result

Registers
Page 14

14

Page 7
 Complete Add Datapath

PC Adder

read reg1
read data1
read reg2
read data2
Instruction write reg
zero
ALU
Memory write data result

Registers
Page 15

15

Complete Add Datapath

PC Adder

rs1 [19-15]
read reg1
read data1
rs2 [24-20]
read reg2
read data2
Instruction rd [11-7]
write reg
zero
ALU
Memory write data result

Registers
Page 16

16

Page 8
 Complete Add Datapath

PC Adder

0010

rs1 [19-15]
read reg1
read data1
rs2 [24-20]
read reg2
read data2
Instruction rd [11-7]
write reg
zero
ALU
Memory write data result

Registers
Page 17

17

Complete Add Datapath

PC Adder

0010

rs1 [19-15]
read reg1
read data1
rs2 [24-20]
read reg2
read data2
Instruction rd [11-7] write reg
zero
ALU
Memory write data result

Registers
Page 18

18

Page 9
 Control of R-format Instructions
❖ Simplicity favors regularity!
◆ and, or, add, subtract, set-on-less-than all use the same
datapath
❖ Need to decode the instructions to control the ALU.
◆ Input: Function codes for each (recall from Chapter 2)
◆ Output: ALU control lines (will look at later)

Page 19

19

ALU Decoding for R-format

ALU
Control

rs1 [19-15]
zero
rs2 [24-20] ALU
result
rd [11-7]

Page 20

20

Page 10
 R-format Datapath and Control

PC Adder

ALU
Control

read reg1
read data1
Instruction read reg2
read data2 zero
Memory write reg ALU
write data result

Registers
Page 21

21

R-format Datapath and Control

PC Adder

4
ALU
Control

read reg1
read data1
Instruction read reg2
read data2 zero
Memory write reg ALU
write data result

Registers
Page 22

22

Page 11
 R-format Datapath and Control

PC Adder

4
ALU
Control

rs1 [19-15]
read reg1
read data1
Instruction rs2 [24-20]
read reg2
read data2 zero
Memory rd [11-7]
write reg ALU
write data result

Registers
Page 23

23

R-format Datapath and Control

PC Adder

4
ALU
Control

rs1 [19-15]
read reg1
read data1
Instruction rs2 [24-20]
read reg2
read data2 zero
Memory rd [11-7]
write reg ALU
write data result

Registers
Page 24

24

Page 12
 R-format Datapath and Control

PC Adder

4
ALU
Control

rs1 [19-15]
read reg1
read data1
Instruction rs2 [24-20]
read reg2
read data2 zero
Memory rd [11-7]
write reg ALU
write data result

Registers
Page 25

25

R-format Datapath and Control

PC Adder

4
ALU
Control

rs1 [19-15]
read reg1
read data1
Instruction rs2 [24-20]
read reg2
read data2 zero
Memory rd [11-7]
write reg ALU
write data result

Registers
Page 26

26

Page 13
 R-format Datapath and Control

PC Adder

4
ALU
Control

rs1 [19-15]
read reg1
read data1
Instruction rs2 [24-20]
read reg2
read data2 zero
Memory rd [11-7]
write reg ALU
write data result

Registers
Page 27

27

Load/Store Instructions - Hardware

❖Read register operands
❖Calculate address using 12-bit offset
◆Use ALU, but sign-extend offset
❖Load: Read memory and update register
❖Store: Write register value to memory

Page 28

28

Page 14
 I-format Instructions
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits

❖ Immediate arithmetic and load instructions

◆ rs1: source or base address register number
◆ immediate: constant operand, or offset added to base
address
➢ 2s-complement, sign extended

Page 29

29

S-format Instructions
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

❖ Different immediate format for store instructions

◆ rs1: base address register number
◆ rs2: source operand register number
◆ immediate: offset added to base address
➢ Split so that rs1 and rs2 fields always in the same place

Page 30

30

Page 15
 Composing the Elements
❖First-cut datapath does an instruction in one
clock cycle
◆Each datapath element can only do one function
at a time
◆Hence, we need separate instruction and data
memories
❖Use multiplexers where alternate data
sources are used for different instructions

Page 31

31

R-Type/Load/Store Datapath

Page 32

32

Page 16
 Branch Instructions
❖Read register operands
❖Compare operands
◆Use ALU, subtract and check Zero output
❖Calculate target address
◆Sign-extend displacement
◆Shift left 1 place (halfword displacement)
◆Add to PC value

Page 33

33

SB-format - Branch Addressing

❖SB format:
imm imm
[10:5] rs2 rs1 funct3 [4:1] opcode

imm[12] imm[11]

◼ PC-relative addressing
◼ Target address = PC + immediate × 2
❖Branch to a labeled instruction if a condition
is true
◆Otherwise, continue sequentially
❖beq rs1, rs2, L1
◆if (rs1 == rs2) branch to instruction labeled L1

Page 34

34

Page 17
 Branch Instructions

Just
re-routes
wires

Sign-bit wire
replicated

Page 35

35

Full Datapath (Without Control Shown)

Page 36

36

Page 18
 Overall Control
❖Split into two Controllers (for now…)
❖Divide and Conquer
1. “ALU Control” unit
➢ Uses 2-bit ALUOp generated by Main Control unit
➢ Uses also Funct7 and Funct3 fields from Instruction
➢ Generates control signals ALUOperation (4 bits) that control
directly the function executed by the ALU
2. “Main Control” unit
➢ Control signals derived from instruction (Opcode)
➢ Generates a 2-bit ALUOp used by ALU Control

Page 37

37

1) “ALU Control” Unit

❖ Generates “ALUOperation” control signals (4 bits)
◆ Based on inputs: ALUOp, Funct7, and Funct3
❖ ALUOp (2 Bits) derived from opcode by “Main Control” unit
❖ Can be implemented by simple combinational logic
◆ By logic synthesis from Truth Table on next slide

ALUOp Values

Page 38

38

Page 19
 ALU Control – Truth Table
❖ Input signals:
◆ ALUOp (2 bits), Funct7 (7 bits, Instruction[31-25], Funct3 (3 bits,
Instruction [14-12])
❖ Output signals:
◆ ALUOperation control signals (4 bits)

Truth Table
ALUOperat
ion

❖ Table from Figure 4.13 in Textbook

Page 39

39

2) “Main Control” Unit

❖ Generates control signals for: Register file, data memory,
multiplexers, AND gate (branch related), ALUOp (2 bits),
etc.
❖ Control signals derived from instruction Opcode

Page 40

40

Page 20
 Main Control – Truth Table
❖ Input signals:
◆ Opcode (7 bits, Instruction [6-0])
❖ Output signals:
◆ ALUOp (2 bits, used by ALU Control), ALUSrc, MemtoReg, RegWrite, etc.
Truth Table
ALUOp Values

❖ Table from Figure 4.22 in Textbook

Page 41

41

Datapath With Control

Page 42

42

Page 21
 R-Type Instruction

Instr.[31-25,14-12]

Page 43

43

Load Instruction

Instr.[31-25,14-12]

Page 44

44

Page 22
 BEQ Instruction

Instr.[31-25,14-12]

Page 45

45

Control table:
New control
Instruction
Type
ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 signal:
SUBGTZ
R-type 0 0 1 0 0 0 1 0 0
LW 1 1 1 1 0 0 0 0 0
SW 1 X 0 0 1 0 0 0 0
BEQ 0 X 0 0 0 1 0 1 0
SUBGTZ 0 0 1 0 0 0 1 0 1 Page 46

46

Page 23
 Practice – Performance Analysis
❖ Calculate cycle time assuming:
◆ memory (2ns), ALU and adders (2ns), register file access (1ns)

Instr.[31-25,14-12]

Page 47

47

Limitations of single-cycle operations

❖Each instruction uses the ENTIRE datapath,

until it finishes.
◆Clock cycle time based on slowest instruction
◆What if we add more stuff, like floating-point?
➢ Worst-case time delay drastically exceeds average
➢ Need really long cycle time to accommodate

❖Goal: Use as much of the hardware as much

of the time as possible
◆ PIPELINING: Break the datapath into smaller chunks, and let
new instructions start while others are finishing

Page 48

48

Page 24