A 2-to-4 Binary Decoders

w which is implemented by using NOT and AND gates. Two NOT gates or inverters provide the
complement of inputs.

A common enable line is connected to each AND gate such that when EN= 0 all the outputs are
zero and if EN=1, depends on the inputs A and B, outputs are produced. Each output represents
one of the minterms of the 2 input variables.

It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along
with truth table. This is constructed with a principle of max terms as outputs. To generate the
minterms, we have to use NAND gates which act as inverters. If both inputs are zero (A = B =
0), Y0 will be zero , if A = 0 and B= 1, then Y1 will be 1 and so on.

Therefore, only one output will be low for any combinations of inputs at a given time and all
other outputs will be high. This type of decoders is available in IC forms so that 3 to 8, 4 to 16,
and 5 to 32 decoders can also be made depends on the application requirement.

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3-to-8 Decoder
In a 3-to-8 decoder, three inputs are decoded into eight outputs. It has three inputs as A, B, and C
and eight output from Y0 through Y7. Based on the combinations of the three inputs, only one of
the eight outputs is selected.

The figure below shows the truth table of a 3-to-8 decoder. Enable input is provided to activate
the decoded output depends on the input combinations A, B and C. Suppose if A = B=1 and C=
0, then the output Y6 is 1 and all other outputs are zero. So from the truth table, minterms
represents the each output equation and are given as
Using the above min term expressions for each output, the circuit of 3-to-8 decoder is can be
implemented by using three NOT gates and eight AND gates. Each NOT gate provides the
complement of the input and AND gates generates one of the minterms.
Also enable input activate the decoded output depends on the input data. The logic diagram of
this decoder is shown below.

Only one of eight outputs is high at a given time for a particular input combination, that why this
decoder is also called as 1-of-8 decoder. Suppose, when ABC = 011, then only AND gate 4 has
all inputs high, thus Y3 is high.

Also, 3-bit binary numbers at the input is converted to eight digits at the output (which is
equivalent to octal number system), that’s how; it is also called as a binary-to-octal decoder

It is also possible represent the each output equation using max terms. In such case, inversion
operation is performed in the logic circuit than that of circuit with min terms. The figure below
shows the truth table of 3-to-8 line decoder using NAND gates. Each output in the table gives a
max term representation.

At a given time only one output is low and all other outputs will be high. For example, when
A=B= 1 and C=0, then the output Y6 is zero and all other outputs are high as shown in below
figure.
From the above table , a 3-to-8 line decoder is designed by using three NAND gates and three
NOT gates. NOT gates generate the complement of input while the NAND gates generate max
terms of each output as shown in below figure.

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4-to-16 Decoder
A 4-to-16 decoder consists of 4 inputs and 16 outputs. Similar to all the decoders discussed
above, in this also only one output will be low at a given time and all other outputs are high
(using maxterms).

The truth table of this type of decoder is shown below. If the input to this decoder is 1000, then
output Y8 will be low and all other outputs will be high as shown in figure. This will be so on for
all the input combinations.

From the above truth table, a 4-to-16 decoder can be implemented by using 4 NOT gates and 16
decoding NAND gates. For decoding all possible combinations of 4 bits input, sixteen (24 = 16)
decoding gates are required.

It is important to note that all the NAND gates are implemented on this circuit produce the active
low outputs as shown in figure.

Since it selects one of 16 outputs based in the particular input combination, these decoders are
also called as 1-of-16 decoder. And also its output represents the sixteen digits as hexadecimal
number system, this type of decoder is also called as a binary-to-hexadecimal decoder.
It is possible to combine or cascade two or more decoders to produce a decoder with larger
number of input bits with the use of enable input of decoder. The cascade combination of two 3-
to-8 line decoder is given below figure. It consists of four inputs A, B, C and Enable E and 16
outputs Y0 to Y7.

One of the input variable is used as enable input of the first 3-to-4 decoder and this same input is
complemented and connected as enable input of the second decoder. The decoder to be enabled
is decided by the most significant input variable and other input variables are fed to each
decoder.

When enable input is zero then the top decoder is enabled while the other is disabled. Then the
top decoder eight outputs generate the minterms 0000 to 0111. Likewise, when enable is 1, the
lower decoder is enabled and top one is disabled. Thus the bottom decoder outputs generate
minterms from 1000 to 1111.
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output lines. One of these
outputs will be active High based on the combination of inputs present, when the decoder is enabled.
That means decoder detects a particular code. The outputs of the decoder are nothing but the min
terms of ‘n’ input variables lines

, when it is enabled.

2 to 4 Decoder

Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block diagram
of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The
Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0
Y2=E.A1.A0′
 Y1=E.A1′.A0
Y0=E.A1′.A0′

Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables A1
& A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will be
equal to zero.

Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to
16 decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.
Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower-order decoders.

 3 to 8 decoder
 4 to 16 decoder

3 to 8 Decoder

In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know that 2 to 4

We can find the number of lower order decoders required for implementing higher order decoder
using the following formula.

Requirednumberoflowerorderdecoders=m2m1

Where,

m1
is the number of outputs of lower order decoder.

m2
is the number of outputs of higher order decoder.

Here, m1

= 4 and m2

= 8. Substitute, these two values in the above formula.

Requirednumberof2to4decoders=84=2

Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.
The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of input A2 is
connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y3 to Y0. These are the
lower four min terms. The input, A2 is directly connected to Enable, E of upper 2 to 4 decoder
in order to get the outputs, Y7 to Y4. These are the higher four min terms.

4 to 16 Decoder

In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8

We know the following formula for finding the number of lower order decoders required.

Requirednumberoflowerorderdecoders=m2m1

Substitute, m1

= 8 and m2

= 16 in the above formula.

Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder. The block
diagram of 4 to 16 decoder using 3 to 8 decoders is shown in the following figure.

The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input, A3
is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y7 to Y0. These are
the lower eight min terms. The input, A3 is directly connected to Enable, E of upper 3 to 8
decoder in order to get the outputs, Y15 to Y8. These are the higher eight min terms.
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the
input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is
optional to represent the enable signal in encoders.

4 to 2 Encoder

Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block diagram
of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as

A1=Y3+Y2
A0=Y3+Y1

We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.
The above circuit diagram contains two OR gates. These OR gates encode the four inputs with
two bits

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to binary
encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is shown in
the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.

Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1

We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.
The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.

Drawbacks of Encoder

Following are the drawbacks of normal encoder.

 There is an ambiguity, when all outputs of encoder are equal to zero. Because, it could be
the code corresponding to the inputs, when only least significant input is one or when all
inputs are zero.

 If more than one input is active High, then the encoder produces an output, which may
not be the correct code. For example, if both Y3 and Y6 are ‘1’, then the encoder
produces 111 at the output. This is neither equivalent code corresponding to Y3, when it
is ‘1’ nor the equivalent code corresponding to Y6, when it is ‘1’.

So, to overcome these difficulties, we should assign priorities to each input of encoder. Then, the
output of encoder will be the binary

code corresponding to the active High input s

, which has higher priority. This encoder is called as priority encoder.

Priority Encoder

A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. Here, the
input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even
if more than one input is ‘1’ at the same time, the output will be the binary

code corresponding to the input, which is having higher priority.

We considered one more output, V in order to know, whether the code available at outputs is
valid or not.

 If at least one input of the encoder is ‘1’, then the code available at outputs is a valid one.
In this case, the output, V will be equal to 1.

 If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one. In
this case, the output, V will be equal to 0.

The Truth table of 4 to 2 priority encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0 V
0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

Use 4 variable K-maps for getting simplified expressions for each output.

The simplified Boolean functions are

A1=Y3+Y2

A0=Y3+Y2′Y1

Similarly, we will get the Boolean function of output, V as

V=Y3+Y2+Y1+Y0

We can implement the above Boolean functions using logic gates. The circuit diagram of 4 to 2
priority encoder is shown in the following figure.
The above circuit diagram contains two 2-input OR gates, one 4-input OR gate, one 2input AND
gate & an inverter. Here AND gate & inverter combination are used for producing a valid code at
the outputs, even when multiple inputs are equal to ‘1’ at the same time. Hence, this circuit
encodes the four inputs with two bits based on the priority assigned to each input.