TPS51396A

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SLVSEY3C – FEBRUARY 2019 – REVISED APRIL 2021
SLVSEY3C – FEBRUARY 2019 – REVISED APRIL 2021

TPS51396A 4.5-V to 24-V, 8-A Synchronous Step-Down Voltage Regulator with ULQ™
Mode for Extended Battery Life
The key feature of the TPS51396A is its ULQ (Ultra
1 Features Low Quiescent) feature to enable low-bias current and
• Input voltage range: 4.5 V to 24 V large duty operation. The ULQ feature is extremely
• D-CAP3™ architecture control for fast transient beneficial for long battery life in low power operation.
response The TPS51396A operates with a supply input voltage
• Output voltage range: 0.6 V to 7 V ranging from 4.5 V to 24 V. It uses DCAP3 control
• 1% feedback voltage accuracy (25°C) mode to provide a fast transient response, good
• Continual output current: 8 A line, load regulation, no requirement for external
• Integrated 19.5-mΩ and 9.5-mΩ RDS(on) internal compensation, and supports low equivalent series
power switch resistance (ESR) output capacitors such as specialty
• ULQ™ operation to enable long battery life during polymer and ultra-low ESR ceramic capacitors.
system standby
The TPS51396A provides complete protection OVP,
• Eco-Mode™ and OOA mode selectable for light
UVP, OCP, OTP, and UVLO. It is combined power
load running by MODE pin
good signal and output discharge function.
• 600-kHz, 800-kHz and 1-MHz selectable switching
frequency by MODE pin The MODE pin in the TPS51396A can be used to set
• Out-of-Audio (OOA) light- load operation with Eco-Mode or OOA mode for light load operation. The
switching frequency over 25 kHz Eco-Mode maintains high efficiency during light load
• Large duty operation support operation, and OOA mode operations with switching
• Adjustable soft-start time by SS pin frequency larger than 25 kHz even no loading.
• Power good indicator
The TPS51396A supports both an internal and
• Built-in output discharge function
external soft-start time option. It has the internal fixed
• Cycle-by-cycle over current protection
soft-start time of 1.3 ms. If the application needs
• Latched output for OV and UV protections
longer soft-start time, the external SS pin can be used
• Non-latched for OT and UVLO protections
to achieve it by connecting the external capacitor.
• 20-pin 3.0-mm × 3.0-mm HotRod™ VQFN package
The TPS51396A is available in a 20-pin 3.0-
2 Applications mm × 3.0-mm HotRod package and the junction
• Notebook, DTV and STB temperature is specified from –40°C to 125°C.
• Telecom and networking, point-of-load (POL)
Device Information
• IPCs, factory automation
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Distributed power systems
TPS51396A VQFN (20) 3.00 mm × 3.00 mm
3 Description
(1) For all available packages, see the orderable addendum at
The TPS51396A is a cost-effective, high-voltage the end of the data sheet.
input, high-efficiency synchronous buck converter with
integrated FETs.
L 100
TPS51396A
VIN VOUT
VIN SW 95
VCC
CIN
90
CBST COUT R1
RM_H
EN VBST
Efficiency (%)

RM_L 85
MODE
FB 80
PGOOD R2
PGOOD
75

VCC 70 VVIN=6V, VOUT=5V,FSW=600kHz

R5 SS
VVIN=8.4V,VOUT=5V,FSW=600kHz
C1 AGND PGND Could be floating 65 VVIN=12V, VOUT=5V,FSW=600kHz
Css VVIN=19V, VOUT=5V,FSW=600kHz
60
0.001 0.01 0.1 1 10
Typical Application I-Load (A) D034

Efficiency vs Output Current ECO-mode

An©IMPORTANT
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Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 17
2 Applications..................................................................... 1 8.1 Application Information............................................. 17
3 Description.......................................................................1 8.2 1V Output Typical Application................................... 17
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................22
5 Pin Configuration and Functions...................................3 10 Layout...........................................................................23
6 Specifications.................................................................. 4 10.1 Layout Guidelines................................................... 23
6.1 Absolute Maximum Ratings........................................ 4 10.2 Layout Example...................................................... 23
6.2 ESD Ratings............................................................... 4 11 Device and Documentation Support..........................24
6.3 Recommended Operating Conditions.........................4 11.1 Device Support........................................................24
6.4 Thermal Information....................................................5 11.2 Receiving Notification of Documentation Updates.. 24
6.5 Electrical Characteristics.............................................5 11.3 Support Resources................................................. 24
6.6 Typical Characteristics................................................ 7 11.4 Trademarks............................................................. 24
7 Detailed Description...................................................... 11 11.5 Electrostatic Discharge Caution.............................. 24
7.1 Overview................................................................... 11 11.6 Glossary.................................................................. 24
7.2 Functional Block Diagram......................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................13 Information.................................................................... 25
7.4 Device Functional Modes..........................................14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2020) to Revision C (April 2021) Page
• First public release..............................................................................................................................................1
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Updated title........................................................................................................................................................1
• Added table note to the Recommended Operating Conditions ......................................................................... 4

Changes from Revision A (April 2020) to Revision B (April 2020) Page

• Changed marketing status from NDA Restrictions to Select Disclosure. .......................................................... 1

Changes from Revision * (February 2019) to Revision A (April 2020) Page

• Changed marketing status from Advance Information to Production release. ...................................................1

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5 Pin Configuration and Functions

SW SW GND VCC NC

7 176

3
4
20 19 18 16

BST 1 15 MODE

6
6
3 3
VIN 2 14 FB

4 4
3 13

7
7
VIN GND AGND

VIN 4 12 EN

VIN 5 11 SS

7 6

3
4
6 7 8 9 10
SW GND GND PGOOD NC

Figure 5-1. RJE Package 20-Pin VQFN (Top View)

Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST 1 I
BST and SW, 0.1 μF is recommended.
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
VIN 2,3,4,5 P
GND.
SW 6,19,20 O Switch node terminal. Connect the output inductor to this pin.
GND 7,8,18,Pad G Power GND terminal for the controller circuit and the internal circuitry.
Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over
PGOOD 9 O
voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
SS 11 I
capacitor is connected, the soft-start time is about 1.3 ms.
NC 10,16 Not connect. Can be connected to GND plane for better thermal achieved.
Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal pull
EN 12 I
down current to disable converter if leave this pin open.
AGND 13 G Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
FB 14 I
AGND.
Llight load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND, the
MODE 15 I
different MODE options are shown in Table 7-1
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
VCC 17 O
this pin with a 1-μF capacitor.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 26 V
VBST –0.3 31 V
Input voltage VBST-SW –0.3 6 V
EN, MODE, FB, SS –0.3 6 V
PGND, AGND –0.3 0.3 V
SW –2 26 V
Output voltage SW (10-ns transient) –3 28 V
PGOOD –0.3 6 V
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT

Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

V(ESD)
discharge Charged-device model (CDM), per JEDEC specification JESD22- V C101(2) ±500 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN(1) 4.5 24 V
VBST –0.3 29 V
Input voltage VBST-SW –0.3 5.5 V
EN, MODE, FB, SS –0.3 5.5 V
PGND, AGND –0.3 0.3 V
SW –2 24 V
Output voltage SW (10-ns transient) –3 26 V
PGOOD –0.3 5.5 V
IOUT Output current 8 A
TJ Operating junction temperature –40 125 °C

(1) Max DC input (inlcude tolerance) should be not over 24 V.

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6.4 Thermal Information

TPS51396A
THERMAL METRIC(1) RJE (VQFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 44.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.3 °C/W
RθJB Junction-to-board thermal resistance 13.3 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 13.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 16.1 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range VIN 4.5 24 V
IVIN VIN supply current No load, VEN = 3.3 V, Switching 90 uA
IVINSDN Shutdown supply current No load, VEN = 0 V 2 uA
VCC OUTPUT
VVIN > 5.0 V 4.85 5 5.15 V
VCC VCC output voltage
VVIN = 4.5 V 4.5 V
ICC VCC current limit 20 mA
FEEDBACK VOLTAGE
TJ = 25°C 594 600 606 mV
VFB FB voltage
TJ = -40°C to 125°C 592 600 611 mV
DUTY CYCLE and FREQUENCY CONTROL
FSW Switching frequency TJ = 25°C , FSW = 600 kHz,Vo = 1 V 600 kHz
TON(MIN) SW minumum on time TJ = 25°C 60 ns
TOFF(MIN) SW minimum off time TJ = 25°C, VFB = 0.5 V 190 ns
MOSFET and DRIVERS
RDS(ON)H High side switch resistance TJ = 25°C 19.5 mΩ
RDS(ON)L Low side switch resistance TJ = 25°C 9.5 mΩ
OOA FUNCTION
TOOA OOA mode operation period 28 us
OUTPUT DISCHARGE and SOFT START
RDIS Discharge resistance TJ = 25°C, VEN = 0 V 420 Ω
TSS Soft start time Internal soft-start time, SS floating 1.3 ms
ISS Soft start charge current 5 uA
POWER GOOD
TPGDLY PG start-up delay PG from low to high 1 ms
VFB falling (fault) 85 %
VFB rising (good) 90 %
VPGTH PG threshold
VFB rising (fault) 115 %
VFB falling (good) 110 %
VPG_L PG sink current capability IOL = 4 mA 0.4 V
IPGLK PG leak current VPGOOD = 5.5 V 1 uA

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TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted

PARAMETER TEST CONDITION MIN TYP MAX UNIT
CURRENT LIMIT
IOCL Over current threshold Valley current set point 8.1 9.8 12 A
INOCL Negative over current threshold 3.9 A
LOGIC THRESHOLD
VENH EN high-level input voltage 1.2 1.4 V
VENL EN low-level input voltage 0.8 1.05 V
Enable internal pull down
IEN VEN = 0.8 V 2 µA
current
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP OVP trip threshold 125 %
tOVPDLY OVP prop deglitch TJ = 25°C 20 us
VUVP UVP trip threshold 60 %
tUVPDLY UVP prop deglitch 256 us
UVLO
Wake up 4.2 4.4 V
VUVLOVIN VIN UVLO threshold Shutdown 3.6 3.8 V
Hysteresis 0.4 V
OVER TEMPERATURE PROTECTION
TOTP OTP trip threshold(1) Shutdown temperature 150 °C
TOTPHSY OTP hysteresis(1) Hysteresis 20 °C

(1) Not production tested

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6.6 Typical Characteristics

TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)

480 3.25

3
470

Shutdown Current (uA)

2.75
Supply Current (uA)

460 2.5

2.25
450

2
440
1.75

430 1.5
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature ( OC) Junction Temperature (OC) D002
D001

VEN = 5 V VEN = 0 V

Figure 6-1. Supply Current vs Junction Figure 6-2. Shutdown Current vs Temperature
Temperature
615 1.36

1.34
VFB Feedback Voltage (mV)

610
EN On Voltage (V)

605 1.32

600 1.3

595 1.28

590 1.26
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature ( OC) Junction Temperature (OC) D004
D003

Figure 6-3. Feedback Voltage vs Junction Figure 6-4. Enable On Voltage vs Junction
Temperature Temperature
1.13 27.5

1.12 25
High-Side RDS(on) (m:)
EN Off Voltage (V)

1.11 22.5

1.1 20

1.09 17.5

1.08 15
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (OC) D005 Junction Temperature (OC) D011

Figure 6-5. Enable Off Voltage vs Junction Figure 6-6. High-Side RDS(on) vs Junction
Temperature Temperature

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16 130

14 128
Low-side RDS(on) (m:)

OVP Threshold (%)

12 126

10 124

8 122

6 120
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (OC) Juncition Temperature (OC) D006
D012

Figure 6-7. Low-Side RDS(on) vs Junction Figure 6-8. OVP Threshold vs Junction
Temperature Temperature
64 440

63 435

Discharge Resistor (:)

UVP Threshold (%)

62 430

61 425

60 420

59 415
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (OC) Junction Temperature ( OC) D008
D007

Figure 6-9. UVP Threshold vs Junction Figure 6-10. Discharge Resistor vs Junction
Temperature Temperature
11 1.35

10.6 1.33
Valley Current Limit (A)

Soft-start Time (ms)

10.2 1.31

9.8 1.29

9.4 1.27

9 1.25
-50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130
Junction Temperature (OC) D009
Junction Temperature (OC) D010

Figure 6-11. Valley Current Limit vs Junction Figure 6-12. Soft-Start Time vs Junction
Temperature Temperature

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100 100

95 90
80
90
70
Efficiency (%)

Efficiency (%)
85 60
80 50

75 40
30
70
VVIN=12V,VOUT=1V 20 VVIN=12V, VOUT=1V
65 VVIN=12V,VOUT=3.3V 10 VVIN=12V, VOUT=3.3V
VVIN=12V,VOUT=5V VVIN=12V, VOUT=5V
60 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
I-Load (A) D027
I-Load (A) D028

Figure 6-13. Efficiency, Eco-mode, FSW = 600 kHz Figure 6-14. Efficiency, OOA-mode, FSW = 600 kHz
100 100
90
90
80
70
80
Efficiency (%)

Efficiency (%)
60
70 50
40
60
30

VVIN=12V, VOUT=1V 20 VVIN=12V, VOUT=1V

50
VVIN=12V, VOUT=3.3V 10 VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V VVIN=12V, VOUT=5V
40 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
I-Load (A) D030 I-Load (A) D031

Figure 6-15. Efficiency, Eco-mode, FSW = 1 MHz Figure 6-16. Efficiency, OOA-mode, FSW = 1 MHz
700 700
VVIN=5V,VOUT=1V VVIN=5V,VOUT=1V
600 VVIN=8.4V,VOUT=1V 600 VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V VVIN=12V,VOUT=1V
Switching Frequency (kHz)

Switching Frequency (kHz)

VVIN=19V,VOUT=1V VVIN=19V,VOUT=1V
500 500

400 400

300 300

200 200

100 100

0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
I-Load (A) D023
I-Load (A) D036

Figure 6-17. FSW Load Regulation, Eco-mode, FSW Figure 6-18. FSW Load Regulation, OOA-mode, FSW
= 600 kHz = 600 kHz

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900 900
VVIN=5V,VOUT=1V VVIN=5V, VOUT=1V
800 VVIN=8.4V,VOUT=1V 800 VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V VVIN=12V,VOUT=1V
Switching Frequency (kHz)

Switching Frequency (kHz)

700 VVIN=19V,VOUT=1V 700 VVIN=19V,VOUT=1V
600 600

500 500

400 400

300 300

200 200

100 100

0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
I-Load (A) D038
I-Load (A) D039

Figure 6-19. FSW Load Regulation, Eco-mode, FSW Figure 6-20. FSW Load Regulation, OOA-mode, FSW
= 800 kHz = 800 kHz
1100 1100
VVIN=12V, VOUT=1V VVIN=12V, VOUT=1V
1000 1000
VVIN=12V,VOUT=3.3V VVIN=12V,VOUT=3.3V
900 VVIN=12V,VOUT=5V 900 VVIN=12V,VOUT=5V
Switching Frequency (kHz)

Switching Frequency (kHz)

800 800
700 700
600 600
500 500
400 400
300 300
200 200
100 100
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
I-Load (A) D052
I-Load (A) D053

Figure 6-21. FSW Load Regulation, Eco-mode, FSW Figure 6-22. FSW Load Regulation, OOA-mode, FSW
= 1 MHz = 1 MHz

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7 Detailed Description
7.1 Overview
The TPS51396A is 8-A integrated FET synchronous buck converter which operates from 4.5-V to 24-V input
voltage (VIN), and the output is from 0.6 V to 7 V. The proprietary D-CAP3 mode enables low external
component count, ease of design, optimization of the power design for cost, size, and efficiency. The key feature
of the TPS51396A is ultra-low quiescent current (ULQ) mode. This feature is beneficial for long battery life in
system standby mode. The device employs D-CAP3 mode control that provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology provides seamless
transition between CCM operating mode at higher load condition and DCM operation at lighter load condition.
Eco-mode allows the TPS51396A to maintain high efficiency at light load. OOA (out of audio) mode makes
switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. The
TPS51396A is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP
or SP-CAP, and ultra-low ESR ceramic capacitors.

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7.2 Functional Block Diagram

PG high
PGOOD
threshold +
UV threshold
+ UV
Delay
+
+ OV PG low
threshold VIN
OV threshold
FB
+
LDO VCC
0.6 V VREGOK 4.2 V /
3.8 V
+
+
+PWM
+ Control Logic
VBST
SS
VIN

x On/Off time
x Minimum On/Off
x TON Extension
Ripple injection
x OVP/UVP/TSD SW
XCON
x OOA/SKIP
SW Internal SS x Soft-Start
x PGOOD
SS
PGND

One shot +
OCL

EN threshold +
EN + ZC

+
NOCL
+ THOK
150°C /20°C

AGND
Light load operation set /
Discharge control
Switching frequency set

MODE

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7.3 Feature Description

7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary DCAP3 mode control. The DCAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both
low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS51396A
also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation
circuit is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS51396A is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in Equation 1.

1
fp
2 u S u LOUT u COUT
(1)

At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS51396A. The low-frequency L-C double pole has a 180 degree drop in phase. At the output
filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS51396A has an internal 1.3-ms soft start, and also an external SS pin is provided for setting higher
soft-start time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a larger soft start time, it can be set by connecting a capacitor on SS pin. When the
EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 2:

Css(nF) u VREF(V)
Tss
Iss(PA)
(2)

where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS51396A can support large duty operations by its internal TON extension function. When the VIN/VOUT
<1.6, and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and
also improve the performance of the load transient performance.

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7.3.4 Power Good

The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A 100 kΩ pullup resistor is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
• the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
• in an OVP, UVP, or thermal shutdown event
• during the soft-start period.
7.3.5 Over Current Protection and Undervoltage Protection
The TPS51396A has the over current protection and undervoltage protection. The output over current limit
(OCL) is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the
OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch
current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current
is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse,
even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered
and the current is being limited, the output voltage tends to drop because the load demand is higher than what
the converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will be latched after a wait time of 256us. When the over current condition is removed, the
output voltage is latched till the EN is toggled or re-power the power input.
7.3.6 Over Voltage Protection
The TPS51396A has the over voltage protection feature. When the output voltage becomes higher than 125% of
the target voltage, the OVP comparator output goes high, the output will be discharged after a wait time of 20 µs.
When the over voltage condition is removed, the output voltage is latched till the EN is toggled or re-power the
power input.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS51396A has the discharge function by using internal MOSFET about 420Ω RDS(on), which is connected
to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.9 Thermal Shutdown
The TPS51396A monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS51396A has a MODE pin which can setup three different modes of operation for light load running
and 600 kHz/800 kHz/1 MHz switching frequency at heavy load .The light load running includes out-of-audio
mode ,advanced Eco-mode and force CCM mode.

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7.4.2 Advanced Eco-mode™ Control

The advanced Eco-mode™ control scheme to maintain high light load efficiency. As the output current decreases
from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost
the same as it was in the continuous conduction mode so that it takes longer time to discharge the output
capacitor with smaller load current to the level of the reference voltage. This makes the switching frequency
lower, proportional to the load current, and keeps the light load efficiency high. The light load current where the
transition to Eco-mode™ operation happens ( IOUT(LL) ) can be calculated from Equation 3.

1 (V -V ) × VOUT
IOUT(LL) = × IN OUT
2 × LOUT × FSW VIN (3)

After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Out of Audio Mode
Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above audible
frequency towards a virtual no-load condition. During Out-of-Audio operation, the OOA control circuit monitors
the states of both high-side and low-side MOSFETs and forces them switching if both MOSFETs are off for
more than 28 μs. When both high-side and low-side MOSFETs are off for more than 28 μs during a light-load
condition, the lowside FET will be on for discharge till reverse OC happens or output voltage drops to trigger the
high-side FET on. This mode initiates one cycle of the low-side MOSFET and the high-side MOSFET turning on.
Then, both MOSFETs stay turned off waiting for another 28 μs.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
7.4.4 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in Table 7-1 . The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom resistor
(RM_L) is shown in Table 7-1, and 1% resistors are recommended. It is important that the voltage for the MODE
pin is derived from the VCC rail only since internally this voltage is referenced to detect the MODE option. The
MODE pin setting can be reset only by a VIN power cycling or EN toggle.
Table 7-1. MODE Pin Resistor Settings
RM_H(kΩ) RM_L (kΩ) Light Load Operation Switching Frequency (kHz)
330 5.1 Eco-mode 600
330 15 Eco-mode 800
330 27 Eco-mode 1000
300 43 OOA mode 600
150 33 OOA mode 800
160 51 OOA mode 1000

Figure 7-1 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn
on threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the
first mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.

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EN threshold
1.2V

EN
VCC UVLO
4.2V
VCC
MODE6

MODE1
MODE

500us 100us Tss

90% VOUT

1ms
VOUT

PGOOD

Figure 7-1. Power-Up Sequence

7.4.5 Standby Operation

The TPS51396A can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when float, the part is disabled by
default.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The schematic of Figure 8-1 shows a typical application for TPS51396A with 1-V output. This design converts an
input voltage range of 4.5 V to 24 V down to 1 V with a maximum output current of 8 A.
8.2 1V Output Typical Application

Figure 8-1. 1V/8A Reference Design with Eco-mode, Fsw = 600 kHz

8.2.1 Design Requirements

Table 8-1 lists the design parameters for this example.
Table 8-1. Design Parameters
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT
VOUT Output voltage 1 V
IOUT Output current 8 A
ΔVOUT Transient response 0 A - 8 A load step,2.5A/us ±40 mV
VIN Input voltage 4.5 12 24 V
VOUT(ripple) Output voltage ripple (CCM) 18 mV(P-P)
FSW Switching frequency 600 kHz
Light load operating mode Eco-mode
TA Ambient temperature 25 °C

8.2.2 Detailed Design Procedure

8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See Equation 4

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R UPPER
VOUT 0 . 6 u (1 )
R LOWER
(4)

8.2.2.1.2 Inductor Selection

The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the
output capacitor should have a ripple current rating higher than the inductor ripple current. See Table 8-2 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 5 and Equation 6. It is
important that the inductor is rated to handle these currents.

§ 2·
¨2 1 §¨ VOUT u ( VIN (max) VOUT ) ·¸ ¸
IL RMS ¨ I OUT u ¸
¨ 12 ¨© VIN (max) u L OUT u FSW ¸¹ ¸
© ¹
(5)

IL(ripple)
IL(peak) IOUT
2 (6)

During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in Table 8-2.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple).
Table 8-2. Recommended Component Values
RUPPER
VOUT (V) RLOWER (kΩ) Fsw (kHz) LOUT (µH) COUT(min) (µF) COUT(max) (µF) CFF (PF)
(kΩ)
600 0.47 66 500 -
0.6 10 0 800 0.33 66 500 -
1000 0.27 66 500 -
600 0.68 66 500 -
1 30 20 800 0.47 66 500 -
1000 0.33 66 500 -
600 1.5 66 500 47-330
3.3 20 90 800 1.2 66 500 47-330
1000 1 66 500 47-330
600 2.2 66 500 47-330
5.0 30 220 800 1.5 66 500 47-330
1000 1.2 66 500 47-330

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8.2.2.1.4 Input Capacitor Selection

The TPS51396A requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in Equation 7.

IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW (7)

TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by Equation 8:

VOUT (VIN(min)-VOUT )
ICIN(rms) = IOUT × ×
VIN(min) VIN(min) (8)

A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.

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8.2.3 Application Curves

Figure 8-2 through Figure 8-15 apply to the circuit of Figure 8-1. VIN = 12 V. TJ = 25°C unless otherwise
specified.

95 1.01
VVIN=5V, VOUT=1V
1.008 VVIN=8.4V,VOUT=1V
90
1.006 VVIN=12V, VOUT=1V
85 VVIN=19V, VOUT=1V
1.004
Efficiency (%)

80 1.002

Output (V)
75 1
0.998
70
0.996
65 VVIN=5V, VOUT=1V 0.994
VVIN=8.4V,VOUT=1V
60 VVIN=12V, VOUT=1V 0.992
VVIN=19V, VOUT=1V 0.99
55 0.001 0.01 0.1 1 10
0.001 0.01 0.1 1 10 I-Load (A)
I-Load (A) D019
D033
Figure 8-3. Load Regulation ,Fsw = 600 kHz
Figure 8-2. Efficiency Curve, Fsw = 600 kHz
800 700

700 600
Swtiching Frequency (kHz)

Switching Frequency (kHz)

500
600
400
500
300
400
200
VVIN=5V,VOUT=1V
300 VVIN=8.4V,VOUT=1V
100 VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
200 0
4 6 8 10 12 14 16 18 20 22 24 0 1 2 3 4 5 6 7 8
VIN (V) D025
I-Load (A) D047

IOUT = 8 A

Figure 8-4. Switching Frequency vs Input Voltage Figure 8-5. Switching Frequency vs Output Load
1.01 1.01
1.008 1.008
1.006 1.006
1.004 1.004
Output Voltage (V)

Output Voltage (V)

1.002 1.002
1 1
0.998 0.998
0.996 0.996
0.994 0.994
0.992 0.992
0.99 0.99
4 6 8 10 12 14 16 18 20 22 24 4 6 8 10 12 14 16 18 20 22 24
VIN (V) D027
VIN (V) D026

Figure 8-6. Line Regulation,IOUT = 0.01 A Figure 8-7. Line Regulation,IOUT = 8 A

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Vout=20mV/div (AC coupled)

Vout=20mV/div (AC coupled)

SW=5V/div

SW=5V/div
200us/div 2us/div
Figure 8-8. Output Voltage Ripple, IOUT = 0.01 A Figure 8-9. Output Voltage Ripple, IOUT = 8 A

EN=2V/div EN=2V/div

Vout=1V/div Vout=1V/div

IL=5A/div IL=5A/div

2ms/div
400us/div
Figure 8-10. Start-Up Through EN, IOUT = 4A
Figure 8-11. Shut-down Through EN, IOUT = 4A

Vin=10V/div Vin=10V/div

Vout=1V/div Vout=1V/div

IL=5A/div IL=5A/div

4ms/div 4ms/div

Figure 8-12. Start Up Relative to VIN Rising, IOUT = 4 Figure 8-13. Start Up Relative to VIN Falling, IOUT =
A 4A

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Vout=50mV/div (AC coupled) Vout=50mV/div (AC coupled)

Iout=5A/div
Iout=5A/div

200us/div 200us/div
A.Slew Rate=2.5A/us A.Slew Rate=2.5A/us

Figure 8-14. Transient Response, 0.8 A to 7.2 A Figure 8-15. Transient Response, 0 A to 8 A

9 Power Supply Recommendations

The TPS51396A is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 to 24
V. TPS51396A is a buck converter. The input supply voltage must be greater than the desired output voltage
for proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS51396A circuit, additional input bulk capacitance is recommended, typical
values are 100 μF to 470 μF.

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10 Layout
10.1 Layout Guidelines
• TI recommends a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch ×
3-inch, four-layer PCB with 2-oz copper is used as example.
• Place the decoupling capacitors right across VIN and VCC as close as possible.
• Place output inductor and capacitors with IC at the same layer, SW routing should be as short as possible
to minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitor and also as close to the output pin as possible.
• Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
• Feedback could be 20 mil and must be routed away from the switching node, BST node or other high
efficiency signal.
• VIN trace must be wide to reduce the trace impedance and provide enough current capability.
• Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
Figure 10-1 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 8-1. Resistor divider for EN is not used in the circuit of Figure 8-1, but are shown in the
layout for reference.

VIN
VOUT
SW

GND GND
AGND

Figure 10-1. Top-Layer Layout

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Eco-mode™, D-CAP3™, ULQ™, Eco-Mode™, HotRod™, DCAP3™, and TI E2E™ are trademarks of Texas
Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS51396ARJER ACTIVE VQFN-HR RJE 20 3000 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 51396A

TPS51396ARJET ACTIVE VQFN-HR RJE 20 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 51396A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 21-May-2021

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51396ARJER VQFN- RJE 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
HR
TPS51396ARJET VQFN- RJE 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-May-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51396ARJER VQFN-HR RJE 20 3000 367.0 367.0 35.0
TPS51396ARJET VQFN-HR RJE 20 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RJE 20 VQFN-HR - 1 mm max height
3 x 3, 0.45 mm pitch QUAD FLATPACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224683/A

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