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Varianta 2

The document describes a binary-decimal code conversion circuit. It contains a truth table that defines the circuit's logic functions and input-output mapping. The circuit is then optimized by finding common logical terms between the functions. This results in a simplified representation using AND and OR gates.

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0% found this document useful (0 votes)
37 views4 pages

Varianta 2

The document describes a binary-decimal code conversion circuit. It contains a truth table that defines the circuit's logic functions and input-output mapping. The circuit is then optimized by finding common logical terms between the functions. This results in a simplified representation using AND and OR gates.

Uploaded by

VicuPopusoi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Varianta 2

Codul binar-zecimal la intare 8 4 2 (-3)


Codul binar-zecimal la iesire 5 2 1 1

Tabelul de adevar
    8 4 2 -3   5 2 1 1
Keyboar Zecima
x1 x2 x3 x4   f1 f2 f3 f4
d l
0 0 0 0 0 0   0 0 0 0
5 1 0 1 0 1   0 0 0 1
2 2 0 0 1 0   0 0 1 1
7 3 0 1 1 1   0 1 0 1
4 4 0 1 0 0   0 1 1 1
9 5 1 0 0 1   1 0 0 0
6 6 0 1 1 0   1 0 1 0
B 7 1 0 1 1   1 1 0 0
8 8 1 0 0 0   1 1 1 0
D 9 1 1 0 1   1 1 1 1
  10 0 0 0 1   * * * *
  11 0 0 1 1   * * * *
  12 1 0 1 0   * * * *
  13 1 1 0 0   * * * *
  14 1 1 1 0   * * * *
  15 1 1 1 1   * * * *

Minimizarea functiei y1
x1x
2 00 01 11 10
x3x
4 1
00 * 1
01 * 1 1
11 * * 1 2
10 1 * *
x1x Minimizarea functiei y2
2 00 01 11 10
x3x 4
4
00 1 * 1
01 * 1
11 * 1 * 1
10 * *
3

1
2

Minimizarea functiei y3
x1x 3
2 00 01 11 10
x3x 2
4
00 1
* 1 1
01 * 1
4
11 * *
10 1 1 * *
Minimizarea functiei y4
x1x
2 00 01 11 10
x3x 1
4
00 1 *
01 * 1 1 2
3
11 * 1 *
10 1 * *
y1  x1  x2 x3 x4  SI / SAU
y2  x1 x2  x3 x4  x1 x4  x2 x3 x4  SI / SAU
y3  x1 x2  x1 x4  x2 x4  x3 x4  SI / SAU
y4  x2 x3  x1 x4  x1 x2 x3  SI / SAU

y1  x1 ( x2 x3 x4 )  SI  NU / SI  NU

y2  ( x1 x2 )( x3 x4 )( x1 x4 )( x2 x3 x4 )  SI  NU / SI  NU

y3  ( x1 x2 )( x1 x4 )( x2 x4 )( x3 x4 )  SI  NU / SI  NU
y4  ( x2 x3 )( x1 x4 )( x1 x2 x3 )  SI  NU / SI  NU

Depistarea partilor comune

y1  x1  x2 x3 x4  SI / SAU
y2  x1 x2  x3 x4  x1 x4  x2 x3 x4  SI / SAU

y3  x1 x2  x1 x4  x2 x4  x3 x4  SI / SAU

y4  x2 x3  x1 x4  x1 x2 x3  SI / SAU

z  x1 x2  x1 x4

y1  x1  x2 x3 x4  SI / SAU
y2  z  x3 x4  x2 x3 x4  SI / SAU
y3  z  x2 x4  x3 x4  SI / SAU
y4  x2 x3  x1 x4  x1 x2 x3  SI / SAU

z  ( x1 x2 )( x1 x4 )

y1  x1 ( x2 x3 x4 )  SI  NU / SI  NU

y2  z ( x3 x4 )( x2 x3 x4 )  SI  NU / SI  NU

y3  z ( x2 x4 )( x3 x4 )  SI  NU / SI  NU
y4  ( x2 x3 )( x1 x4 )( x1 x2 x3 )  SI  NU / SI  NU
Circuitul logic in setul de elmente SI-NU/SI-NU

Diagrama in timp in setul de elmente SI-NU/SI-NU

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