5 4 3 2 1

SYSTEM DC/DC
Project code: 91.4CQ01.001 TPS51125 36

JM41/JM51 Discrete Block Diagram PCB P/N

REVISION
: 48.4CQ01.0SB
: 08274-1
INPUTS

DCBATOUT
OUTPUTS
5V_S5(6A)
3D3V_S5(5A)

D 5V_AUX_S5 D

UMA LVDS 3D3V_AUX_S5

PCB STACKUP
UMA CRT Switchable LVDS LCD
Thermal Sensor 19 RT8202 37
CLK GEN. Intel CPU DIS LVDS Graphic RGB CRT
TOP L1
SMSC ICS9LPRS365B Penryn SFF DIS CRT 40, 41 S L2 INPUTS OUTPUTS
EMC2103 27 3 VCC/GND L3
DCBATOUT 1D05V_S0(10A)
4,5,6 S L4
HOST BUS 38
VRAM(DDR3) VCC/GND L5 RT8202
667/800/[email protected]
4
64Mbx16x4 (512MB)
DDR3 Cantiga-GS SFF
57 GND/VCC L6 INPUTS OUTPUTS
800/1066 17,18
MHz AGTL+ CPU I/F
S L7 DCBATOUT 1D5V_S3(11A)

DDR Memory I/F BOTTOM L8

PCIe x 16 RT9026 39
C
DDR3 INTEGRATED GRAHPICS
LVDS, CRT I/F
ATI M92-S2 CRT
C

800/1066 17,18
MHz CRT INPUTS OUTPUTS
7,8,9,10,11,12 BD
53,54,55,56 HDMI
X4 DMI 20 HDMI 5V_S5 DDR_VREF_S3
C-Link0
400MHz (1.2A)

CHARGER
23 LAN TXFM RJ45 MAX8731A 41
ICH9M SFF Giga LAN
Atheros AR8131
INT.SPKR 6 PCIe ports INPUTS OUTPUTS
1.5W PCI/PCI BRIDGE
Codec AZALIA ACPI 2.0 CHG_PWR
Int MIC Realtek DCBATOUT
4 SATA 18V 6.0A
ALC269Q 22 12 USB 2.0/1.1 ports
19 Mini 1 Card CPU DC/DC
ETHERNET (10/100/1000MbE)
MINI BD WLAN ADP3207A
B High Definition Audio PCIe x1 *3port 35 B

LPC I/F
Line Out USB 3 Port Mini 2 Card INPUTS OUTPUTS
Serial Peripheral I/F
Matrix Storage Technology(DO) 3G DCBATOUT
VCC_CORE
Active Managemnet Technology(DO)
25 0~1.3V
CRT 64A
MIC In
LPC BUS VGA
BD 13,14,15,16 ISL6263A
40
20
SATA INPUTS OUTPUTS
USB LPC
SATA CRT BD Camera KBC
Winbond DEBUG VCC_GFXCORE
HDD SATA 2 Port 20
17 WPCE773LA0DG SPI BIOS CONN. DCBATOUT
(7A)
28 (2MB)
29
A
SATA CARDREADER POWER BD MINI BD DIS A

ODD SATA BD 1 Port 26 3 Port 25

24 Touch INT. Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
USB Blue Tooth Pad 30 KB 28 Taipei Hsien 221, Taiwan, R.O.C.
SATA CARDREADER BD Title
24 MS/MS Pro/xD
SSD/HDD SATA 2 Port 24 /MMC/SD BLOCK DIAGRAM
Size Document Number Rev
Custom
21 JM41_Discrete -1
Date: Tuesday, April 07, 2009 Sheet 1 of 48
5 4 3 2 1
 A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions page 92 Hub strapping configuration
Signal
ICH9 EDS 642879 Rev.1.5
and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller
Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister.
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

1 DIS
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reference
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 2 of 48
 A B C D E

1D05V_S0 3D3V_S0
3D3V_S0 R215
R220 R222
1 2 1D05V_CLK_S0

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1 2 3D3V_48MPW R_S0 C522 C516 C508 C512 C515 C532 3D3V_CLK_S0 1 2

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C525 C541 C517 C507 C526 C548 C549
0R0603-PAD

1
SC1U10V3KX-3GP

SC4D7U10V5ZY-3GP
C523 C524
0R0603-PAD 0R0603-PAD

SC4D7U6D3V3KX-GP

2
2

2
DY

4 4
3D3V_48MPW R_S0

C579
3D3V_CLK_S0 1D05V_CLK_S0
1 2
3D3V_S0
R210
R209 SC27P50V2JN-2-GP

2
U35

16

46
62
23

19
27
43
52
33
56
4

9
43 VGA_CLK_REQ# 1 2 CR#_G 1 2 X2
CL=20pF±0.2pF X-14D31818M-35GP

VDD48

VDDPLL3

VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
VDDPCI
VDDREF
82.30005.891

1
1KR2J-1-GP 10KR2J-3-GP C542 82.30005.951
CPUT0 61 CLK_CPU_BCLK 4 CPU
3D3V_S0 1 2 60
CPUC0 CLK_CPU_BCLK# 4
GEN_XTAL_OUT 3 58
SC27P50V2JN-2-GP GEN_XTAL_IN 2
X1 CPUT1_F
57
CLK_MCH_BCLK 7 NB
X2 CPUC1_F CLK_MCH_BCLK# 7
4
3
2
1
RN25 54
SRN10KJ-6-GP
R230 CPUT2_ITP/SRCT8
53
CLK_PCIE_ICH 14 SB DMI
CPUC2_ITP/SRCC8 CLK_PCIE_ICH# 14
14 CLK48_ICH 2 1 CLK_48 17 USB_48MHZ/FSLA
RN24 33R2F-3-GP 51
5
6
7
8

CR#_D R227 2 SRCT7/CR#_F

8 CLK_MCH_OE# 1 8 4,8 CPU_SEL0 1 2K2R2J-2-GP SRCC7/CR#_E 50 CR#_E
14 SATACLKREQ# 2 7 CR#_C 14 PM_STPPCI# 45
CR#_H PCI_STOP#
25 LAN_CLKREQ# 3 6 14 PM_STPCPU# 44 CPU_STOP# SRCT6 48 CLK_PCIE_MINI1 25 Wireless
25 W LAN_CLKREQ# 4 5 CR#_E 47 CLK_PCIE_MINI1# 25
SRCC6
3 SRN470J-3-GP G81 41 CLK_PCIE_LAN 25
3
SRCT10
16,17,18 SMBC_ICH 1GAP-CLOSE
2 SMBC_CKG 7 SCLK SRCC10 42 CLK_PCIE_LAN# 25 LAN
1 2 SMBD_CKG 6
16,17,18 SMBD_ICH SDATA
GAP-CLOSE 40 CR#_H
RN31 G80 SRCT11/CR#_H
63 39 CR#_G
3D3V_S0 PCLKCLK5 CK_PWRGD/PD# SRCC11/CR#_G
1 8
2 7 PCLKCLK4 37
3 6 PCLKCLK2
14 CLK_PW RGD SRCT9
38
CLK_PCIE_VGA 42 VGA
SRCC9 CLK_PCIE_VGA# 42
4 5 CPU_SEL2_R 8 PCI0/CR#_A
10 PCI1/CR#_B SRCT4 34 CLK_MCH_3GPLL 8 NB CLK
PCLKCLK2 11 35 CLK_MCH_3GPLL# 8
SRN10KJ-6-GP PCI2/TME SRCC4
4,8 CPU_SEL2 12 PCI3
PCLKCLK4 13 31 CR#_C
PCLKCLK5 PCI4/27_SELECT SRCT3/CR#_C CR#_D
14 PCI_F5/ITP_EN SRCC3/CR#_D 32

RN32 28
1 8 CPU_SEL2_R SRCT2/SATAT
29
CLK_PCIE_SATA 13 SB SATA
14 CLK_ICH14 SRCC2/SATAC CLK_PCIE_SATA# 13
29 PCLK_FW H 2 7 PCLKCLK2 4,8 CPU_SEL1 64
PCLKCLK4 CPU_SEL2_R FSLB/TEST_MODE
28 PCLK_KBC 3 6 5 REF0/FSLC/TEST_SEL
14 PCLK_ICH 4 5 PCLKCLK5 24 DREFSSCLK 8
27MHZ_NONSS/SRCT1/SE1
55 NC#55 27MHZ_SS/SRCC1/SE2 25 DREFSSCLK# 8 NB CLK
SRN33J-7-GP DY
CLK_ICH14 1 2 20 NB CLK

GNDSRC
GNDSRC
GNDSRC
GNDCPU
DREFCLK 8

GNDREF
SRCT0/DOTT_96

GNDPCI
DY EC48 SC22P50V2JN-4GP 21

GND48
SRCC0/DOTC_96 DREFCLK# 8
PCLK_ICH 1 2 (96 MHz)

GND

GND

GND
PCLK_KBC
DY EC45 SC22P50V2JN-4GP
1 2
DY EC46 SC22P50V2JN-4GP ICS9LPRS365BKLFT-GP-U

18
15
1

22
30
36
49
59
26

65
2 CLK48_ICH 2
1
EC44
2
SC22P50V2JN-4GP
71.09365.A03
2nd = 71.08513.003
EMI capacitor for Antenna team suggestion 3RD = 71.00875.C03
ICS9LPRS365YGLFT setting table
PIN NAME DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair SEL2 SEL1 SEL0
PCI0/CR#_A Byte 5, bit 6 CPU FSB
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
FSC FSB FSA
Byte 5, bit 5 PIN NAME DESCRIPTION 1 0 1 100M X
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 1 0 0 1 133M 533M
PCI1/CR#_B Byte 5, bit 4 0 = SRC3 enabled (default)
166M 667M
0 = CR#_B controls SRC1 pair (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair 0 1 1
1= CR#_B controls SRC4 pair SRCC3/CR#_D Byte 5, bit 0
200M 800M
0 = CR#_D controls SRC1 pair (default) 0 1 0
0 = Overclocking of CPU and SRC Allowed 1= CR#_D controls SRC4 pair
PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed 0 0 0 266M 1067M
Byte 6, bit 7
0 = SRC7# enabled (default)
1
PCI3 SRCC7/CR#_E 1= CR#_F controls SRC6
DIS 1

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# Byte 6, bit 6
PCI4/27M_SEL 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# 0 = SRC7 enabled (default)
SRCT7/CR#_F 1= CR#_F controls SRC8 Wistron Corporation
0 =SRC8/SRC8# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PCI_F5/ITP_EN 1 = ITP/ITP# Byte 6, bit 5 Taipei Hsien 221, Taiwan, R.O.C.
0 = SRC11# enabled (default)
Byte 5, bit 3 SRCC11/CR#_G 1= CR#_G controls SRC9 Title
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 6, bit 4 Clock Generator
SRCT3/CR#_C Byte 5, bit 2 0 = SRC11 enabled (default) Size Document Number Rev
0 = CR#_C controls SRC0 pair (default), SRCT11/CR#_H 1= CR#_H controls SRC10
JM41_Discrete -1
1= CR#_C controls SRC2 pair
Date: Monday, April 06, 2009 Sheet 3 of 48
A B C D E
 A B C D E

H_A#[35..3]
7 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 7

1 H_DSTBN#[3..0]
H_DSTBN#[3..0] 7
CPU1A 1 OF 6 TP4 TPAD14-GP
H_A#3 P2 M4 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 7 H_DSTBP#[3..0] 7
H_A#4 V4 J5 H_BNR# 7
H_A#5 A4# BNR# Place testpoint on H_D#[63..0]
4 W1 A5# BPRI# L5 H_BPRI# 7 H_D#[63..0] 7 4
H_A#6 T4 H_IERR# with a GND
A6#

1
ADDR GROUP 0
H_A#7 AA1 N5 0.1" away
A7# DEFER# H_DEFER# 7
H_A#8 AB4 F38 H_DRDY# 7
H_A#9 A8# DRDY# R178
T2 A9# DBSY# J1 H_DBSY# 7
H_A#10 AC5 56R2F-1-GP
A10#

CONTROL
H_A#11 AD2 M2 H_BREQ#0 7

2
H_A#12 A11# BR0#
AD4 A12#
H_A#13 AA5 B40 H_IERR#
H_A#14 A13# IERR#
AE5 A14# INIT# D8 H_INIT# 13
H_A#15 AB2
H_A#16 A15#
AC1 A16# LOCK# N1 H_LOCK# 7
7 H_ADSTB#0 Y4 ADSTB0# H_CPURST# 7
G5 CPU1B 2 OF 6
7 H_REQ#[4..0] RESET# H_RS#[2..0] 7
H_REQ#0 R1 K2 H_RS#0 H_D#0 F40 AP44 H_D#32
H_REQ#1 R5 REQ0# RS0# H_RS#1 H_D#1 D0# D32# H_D#33
REQ1# RS1# H4 G43 D1# D33# AR43
H_REQ#2 U1 K4 H_RS#2 H_D#2 E43 AH40 H_D#34
H_REQ#3 P4 REQ2# RS2# H_D#3 D2# D34# H_D#35
REQ3# TRDY# L1 H_TRDY# 7 J43 D3# D35# AF40

DATA GROUP 0
H_REQ#4 W5 H_D#4 H40 AJ43 H_D#36
REQ4# H_THERMDA H_D#5 D4# D36# H_D#37
HIT# H2 H_HIT# 7 H44 D5# D37# AG41
H_A#17 AN1 F2 H_HITM# 7 H_D#6 G39 AF44 H_D#38
A17# HITM# D6# D38#

1
H_A#18 AK4 H_D#7 E41 AH44 H_D#39
A18# D7# D39#

DATA GROUP 2
H_A#19 AG1 AY8 C417 H_D#8 L41 AM44 H_D#40
H_A#20 A19# BPM0# SC2200P50V2KX-2GP H_D#9 D8# D40# H_D#41
ADDR GROUP 1

AT4 BA7 K44 AN43

2
H_A#21 A20# BPM1# H_THERMDC H_D#10 D9# D41# H_D#42
AK2 A21# BPM2# BA5 DY N41 D10# D42# AM40
H_A#22 AT2 AY2 H_D#11 T40 AK40 H_D#43
H_A#23 A22# BPM3# H_D#12 D11# D43# H_D#44
AH2 AV10 M40 AG43
Close to NB
XDP/ITP SIGNALS

H_A#24 A23# PRDY# XDP_BPM#5 H_D#13 D12# D44# H_D#45

AF4 A24# PREQ# AV2 G41 D13# D45# AP40
H_A#25 AJ5 AV4 XDP_TCK H_D#14 M44 AN41 H_D#46
3 H_A#26 A25# TCK XDP_TDI 1D05V_S0 H_D#15 D14# D46# H_D#47 3
AH4 A26# TDI AW7 L43 D15# D47# AL41
H_A#27 AM4 AU1 XDP_TDO K40 AK44 H_DSTBN#2 7
A27# TDO 7 H_DSTBN#0 DSTBN0# DSTBN2#
H_A#28 AP4 AW5 XDP_TMS J41 AL43 H_DSTBP#2 7
A28# TMS 7 H_DSTBP#0 DSTBP0# DSTBP2#
H_A#29 AR5 AV8 XDP_TRST# P40 AJ41 H_DINV#2 7
A29# TRST# 7 H_DINV#0 DINV0# DINV2#

1
H_A#30 AJ1 J7 XDP_DBRESET#
H_A#31 A30# DBR#
AL1 A31#
H_A#32 AM2 R182 H_D#16 P44 AV38 H_D#48
H_A#33 A32# 56R2F-1-GP H_D#17 D16# D48# H_D#49
AU5 A33# THERMAL V40 D17# D49# AT44
H_A#34 AP2 H_D#18 V44 AV40 H_D#50

2
H_A#35 A34# CPU_PROCHOT#_1 H_D#19 D18# D50# H_D#51
AR1 A35# PROCHOT# D38 AB44 D19# D51# AU41
AN5 BB34 H_THERMDA 27 H_D#20 R41 AW41 H_D#52
7 H_ADSTB#1 ADSTB1# THRMDA D20# D52#

DATA GROUP 1
BD34 H_THERMDC 27 H_D#21 W41 AR41 H_D#53
THRMDC H_D#22 D21# D53# H_D#54
13 H_A20M# C7 A20M# N43 D22# D54# BA37
13 H_FERR# D4 B10 PM_THRMTRIP-A# 8,13,32 H_D#23 U41 BB38 H_D#55
FERR# THERMTRIP# D23# D55#
ICH

DATA GROUP 3
13 H_IGNNE# F10 H_D#24 AA41 AY36 H_D#56
IGNNE# PM_THRMTRIP# should connect to H_D#25 D24# D56# H_D#57
AB40 D25# D57# AT40
F8 ICH9 and MCH without T-ing H_D#26 AD40 BC35 H_D#58
13 H_STPCLK# STPCLK# D26# D58#
C9 H CLK PH @ page48 H_D#27 AC41 BC39 H_D#59
13 H_INTR LINT0 D27# D59#
13 H_NMI C5 A35 CLK_CPU_BCLK 3 H_D#28 AA43 BA41 H_D#60
LINT1 BCLK0 1D05V_S0 H_D#29 D28# D60# H_D#61
13 H_SMI# E5 SMI# BCLK1 C35 CLK_CPU_BCLK# 3 Y40 D29# D61# BB40
H_D#30 Y44 BA35 H_D#62
H_D#31 D30# D62# H_D#63
V2 RSVD#V2 T44 D31# D63# AU43

2
RESERVED

Y2 RSVD#Y2 7 H_DSTBN#1 U43 DSTBN1# DSTBN3# AY40 H_DSTBN#3 7

AG5 RSVD#AG5 7 H_DSTBP#1 W43 DSTBP1# DSTBP3# AY38 H_DSTBP#3 7
AL5 Layout Note: 1KR2F-3-GP R43 BC37
RSVD#AL5 7 H_DINV#1 DINV1# DINV3# H_DINV#3 7
J9 "CPU_GTLREF0" R152
RSVD#J9 0.5" max length. CPU_GTLREF0
F4 AW43 AE43 COMP0 R1581 2 27D4R2F-L1-GP

1 1
RSVD#F4 C422 TEST1 GTLREF COMP0
H8 RSVD#H8 E37 TEST1 MISC COMP1 AD44 COMP1 R1601 2 54D9R2F-L1-GP

1
DY TPAD14-GP TEST2 D40 AE1 COMP2 R1621 2 27D4R2F-L1-GP

SC1KP50V2KX-1GP
2 R153 TP63 RSVD_CPU_12 TEST2 COMP2 2
1 C43 TEST3 COMP3 AF2 COMP3 R1611 2 54D9R2F-L1-GP
2KR2F-3-GP TEST4 AE41

2
TPAD14-GP TP2 TEST4
1RSVD_CPU_13AY10 TEST5 DPRSTP# G7 H_DPRSTP# 8,13,34
TPAD14-GP TP50 1RSVD_CPU_14
AC43 B8 H_DPSLP# 13

2
TEST6 DPSLP#
DPWR# C41 H_DPW R# 7
PENRYN-SFF-GP-U1-NF 3,8 CPU_SEL0 A37 E7 H_PW RGD 13,32
BSEL0 PWRGOOD
3,8 CPU_SEL1 C37 BSEL1 SLP# D10 H_CPUSLP# 7
3,8 CPU_SEL2 B38 BD10 PSI# 1
BSEL2 PSI# TP3 TPAD14-GP

1
PENRYN-SFF-GP-U1-NF C117

SC100P50V2JN-3GP
DY

2
Layout Note:
1D05V_S0 1 DY 2 TEST1 Comp0, 2 connect with Zo=27.4 ohm, make
R185 1KR2J-1-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
H_FERR# 1 2 1 DY 2 TEST2 trace length shorter than 0.5" .
H_STPCLK# C442 1DY 2 SC100P50V2JN-3GP XDP_TMS R140 1 2 51R2F-2-GP R173 1KR2J-1-GP make sure "TEST4" routing is
C425
H_IGNNE# C97 1DY 2 SC100P50V2JN-3GP reference to GND and away other
H_INTR C436 1DY 2 SC100P50V2JN-3GP XDP_TDI R141 1 2 51R2F-2-GP 2DY 1 TEST4
H_DPSLP# C439 SC100P50V2JN-3GP SCD1U10V2KX-4GP
noisy signals
1DY 2
H_PW RGD C437 1DY 2 SC100P50V2JN-3GP XDP_BPM#5 R143 1 2 51R2F-2-GP
H_A20M# C429 1DY 2 SC100P50V2JN-3GP
H_SMI# C435 1DY 2 SC100P50V2JN-3GP XDP_TDO R142 1 2 51R2F-2-GP
H_NMI C430 1DY 2 SC100P50V2JN-3GP DY
H_INIT# C431 1DY 2 SC100P50V2JN-3GP
C428 DY SC100P50V2JN-3GP
3D3V_S0 H_DPRSTP# 1 TP10 TPAD14-GP
1 DIS 1
H_DPSLP# 1 TP69 TPAD14-GP
H_DPW R# 1 TP62 TPAD14-GP
XDP_DBRESET# R37 2 1KR2J-1-GP H_PW RGD TP12 TPAD14-GP
1
H_CPUSLP#
1
1 TP68 TPAD14-GP Wistron Corporation
H_INIT# 1 TP13 TPAD14-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY H_CPURST# 1 TP9 TPAD14-GP Taipei Hsien 221, Taiwan, R.O.C.
XDP_TCK R145 1 2 51R2F-2-GP
Place these TP on button-side, Title
XDP_TRST# R144 1 2 51R2F-2-GP
easy to measure. CPU (1 of 3)
All place within 2" to CPU Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 4 of 48
A B C D E
 A B C D E

VCC_CORE

VCC_CORE CPU1D 4 OF 6
4 B42 VSS VSS AU35 4
F44 VSS VSS AV34
CPU1C 3 OF 6 D42 AW35
VSS VSS
F32 VCC VCC AB28 F42 VSS VSS AW33
G33 VCC VCC AD30 H42 VSS VSS AY34
H32 VCC VCC AD28 K42 VSS VSS AT36
J33 VCC VCC Y26 M42 VSS VSS AV36
K32 VCC VCC AB26 P42 VSS VSS BA33
L33 VCC VCC AD26 T42 VSS VSS BC33
M32 VCC VCC AF30 V42 VSS VSS BB36
N33 VCC VCC AF28 Y42 VSS VSS BD36
P32 VCC VCC AH30 AB42 VSS VSS C27
R33 VCC VCC AH28 AD42 VSS VSS C29
T32 VCC VCC AF26 AF42 VSS VSS C31
U33 VCC VCC AH26 AH42 VSS VSS E29
V32 VCC VCC AK30 AK42 VSS VSS E27
W33 VCC VCC AK28 AM42 VSS VSS G29
Y32 VCC VCC AM30 AP42 VSS VSS G27
AA33 VCC VCC AM28 AV44 VSS VSS E31
AB32 VCC VCC AP30 AT42 VSS VSS G31
AC33 VCC VCC AP28 AV42 VSS VSS J29
AD32 VCC VCC AK26 AY42 VSS VSS J27
AE33 VCC VCC AM26 BA43 VSS VSS L29
AF32 VCC VCC AP26 BB42 VSS VSS L27
AG33 VCC VCC AT30 C39 VSS VSS N29
AH32 VCC VCC AT28 E39 VSS VSS N27
AJ33 VCC VCC AV30 G37 VSS VSS J31
AK32 VCC VCC AV28 H38 VSS VSS L31
AL33 VCC VCC AY30 J39 VSS VSS N31
3 AM32 AY28 L39 R29 3
VCC VCC VSS VSS
AN33 VCC VCC AT26 M38 VSS VSS R27
AP32 VCC VCC AV26 N39 VSS VSS U29
AR33 VCC VCC AY26 R39 VSS VSS U27
AT34 VCC VCC BB30 T38 VSS VSS R31
AT32 VCC VCC BB28 U39 VSS VSS U31
AU33 BD30 1D05V_S0 W39 W29
VCC VCC VSS VSS
AV32 VCC Y38 VSS VSS W27
AY32 VCC VCCP J11 AA39 VSS VSS W31
BB32 VCC VCCP E11 layout note: "1D5V_VCCA_S0" AC39 VSS VSS AA29
BD32 VCC VCCP G11 as short as possible AD38 VSS VSS AA27
B28 VCC VCCP J37 AE39 VSS VSS AC29
B30 VCC VCCP K38 AG39 VSS VSS AC27
1

B26 L37 C36 C47 AH38 AA31

VCC VCCP VSS VSS
1

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

D28 N37 TC7 AJ39 AC31

VCC VCCP SE330U2D5VM-GP VSS VSS
D30 P38 AL39 AE29
2

VCC VCCP P_77.C3371.10L VSS VSS

F30 R37 AM38 AE27
2

VCC VCCP VSS VSS

F28 VCC VCCP U37 DY AN39 VSS VSS AG29
H30 VCC VCCP V38 AR39 VSS VSS AG27
H28 VCC VCCP W37 AR37 VSS VSS AJ29
D26 VCC VCCP AA37 AT38 VSS VSS AJ27
F26 VCC VCCP AB38 AU39 VSS VSS AE31
H26 AC37 1D5V_S0 AU37 AG31
VCC VCCP 1D5V_VCCA_S0 VSS VSS
K30 VCC VCCP AE37 R186 AW39 VSS VSS AJ31
K28 VCC AW37 VSS VSS AL29
M30 VCC VCCA B34 1 2 BA39 VSS VSS AL27
M28 VCC VCCA D34 BC41 VSS VSS AN29
1

K26 H_VID[6..0] 34 C453 C455 BD38 AN27

VCC H_VID0 0R0603-PAD VSS VSS
M26 BD8 B36 AL31
SC10U6D3V5MX-3GP
SCD01U16V2KX-3GP

2 VCC VID0 H_VID1 VSS VSS 2

P30 BC7 H34 AN31
2

VCC VID1 H_VID2 VSS VSS

P28 VCC VID2 BB10 D36 VSS VSS AR29
T30 BB8 H_VID3 K34 AR27
VCC VID3 H_VID4 VSS VSS
T28 VCC VID4 BC5 M34 VSS VSS AR31
V30 BB4 H_VID5 M36 AU29
VCC VID5 H_VID6 VSS VSS
V28 VCC VID6 AY4 P34 VSS VSS AU27
P26 VCC T34 VSS VSS AW29
T26 VCC V34 VSS VSS AW27
V26 VCC VCCSENSE BD12 VCORE_VCCSENSE 34 T36 VSS VSS AU31
Y30 VCC Y34 VSS VSS AW31
Y28 VCC AB34 VSS VSS BA29
AB30 VCC VSSSENSE BC13 VCORE_VSSSENSE 34 AD34 VSS VSS BA27
Y36 VSS VSS BC29
PENRYN-SFF-GP-U1-NF Layout Note: AD36 BC27
RN13 VSS VSS
AF34 VSS VSS BA31
2 3 VCCSENSE and VSSSENSE lines AH34 BC31
VCC_CORE VSS VSS
1 4 should be of equal length. AH36 C21
VSS VSS
AK34 VSS VSS C23
SRN100J-3-GP AM34 C25
Layout Note: VSS VSS
AM36 VSS VSS E25
Provide a test point (with AP34 E23
no stub) to connect a VSS VSS
AR35 VSS VSS E21
differential probe
between VCCSENSE and
VSSSENSE at the location PENRYN-SFF-GP-U1-NF
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (2 of 3)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 5 of 48
A B C D E
 5 4 3 2 1

VCC_CORE 1D05V_S0
CPU1E 5 OF 6 6 OF 6
Place these inside socket CPU1F
cavity on L8(North side Secondary) G25 AD10 BD28 AL37
VSS VSS VCC VCCP
G23 AH12 BB26 AN37
VSS VSS VCC VCCP
G21 AE15 BD26 AP38
VCC_CORE VCC_CORE VSS VSS VCC VCCP
J25 AG15 B22 B32
VSS VSS VCC VCCP
J23 AJ15 B24 C33
VSS VSS VCC VCCP
J21 AH10 D22 D32
VSS VSS VCC VCCP
D L25 AM12 D24 E35 D
VSS VSS VCC VCCP
L23 AL15 F24 E33
1

1
C410 C1S C5S C8S C409 C7S C25 C6S C19 C412 C32 C38 C46 C37 C29 C51 VSS VSS VCC VCCP
L21 AN15 F22 F34
VSS VSS VCC VCCP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
N25 AR15 H24 G35
C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP
VSS VSS VCC VCCP
N23 AM10 H22 F36
2

2
VSS VSS VCC VCCP
N21 AT12 K24 H36
VSS VSS VCC VCCP
R25 AV12 K22 J35
VSS VSS VCC VCCP
R23 AW13 M24 L35
VSS VSS VCC VCCP
R21 AW11 M22 N35
VSS VSS VCC VCCP
U25 AY12 P24 K36
VSS VSS VCC VCCP
U23 AU15 P22 R35
VSS VSS VCC VCCP
U21 AW15 T24 U35
VSS VSS VCC VCCP
W25 AT10 T22 P36
VSS VSS VCC VCCP
W23 BA13 V24 V36
VSS VSS VCC VCCP
W21 BA11 V22 W35
VSS VSS VCC VCCP
AA25 BB12 Y24 AA35
VCC_CORE VCC_CORE VSS VSS VCC VCCP
AA23 BC11 Y22 AC35
VSS VSS VCC VCCP
AA21 BA15 AB24 AB36
VSS VSS VCC VCCP
AC25 BC15 AB22 AE35
VSS VSS VCC VCCP
AC23 B6 AD24 AG35
VSS VSS VCC VCCP
AC21 D6 AD22 AJ35
1

1
C59 C53 C42 C4 C27 C23 C24 C66 C43 C48 C3 C34 C413 C411 C40 C2 VSS VSS VCC VCCP
AE25 E9 AF24 AF36
VSS VSS VCC VCCP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AE23 F6 AF22 AL35
VSS VSS VCC VCCP
AE21 G9 AH24 AN35
2

2
VSS VSS VCC VCCP
AG25 H6 AH22 AK36
VSS VSS VCC VCCP
AG23 K8 AK24 AP36
VSS VSS VCC VCCP
AG21 K6 AK22 B12
VSS VSS VCC VCCP
AJ25 M8 AM24 B14
VSS VSS VCC VCCP
AJ23 M6 AM22 C13
VSS VSS VCC VCCP
AJ21 P8 AP24 D12
VSS VSS VCC VCCP
AL25 P6 AP22 D14
VSS VSS VCC VCCP
AL23 T8 AT24 E13
VSS VSS VCC VCCP
AL21 T6 AT22 F14
VCC_CORE VCC_CORE VSS VSS VCC VCCP
AN25 V8 AV24 F12
VSS VSS VCC VCCP
AN23 V6 AV22 G13
VSS VSS VCC VCCP
AN21 U5 AY24 H14
VSS VSS VCC VCCP
AR25 Y8 AY22 H12
VSS VSS VCC VCCP
AR23 Y6 BB24 J13
1

1
C77 C91 C84 C102 C104 C112 C101 C83 C64 C58 C54 C45 C41 C100 C103 C107 VSS VSS VCC VCCP
AR21 AB8 BB22 K14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AU25 AB6 BD24 K12
VSS VSS VCC VCCP
AU23 AD8 BD22 L13
2

2
VSS VSS VCC VCCP
C AU21 AD6 B16 L11 C
VSS VSS VCC VCCP
AW25 AF8 B18 M14
VSS VSS VCC VCCP
AW23 AF6 B20 N13
VSS VSS VCC VCCP
AW21 AH8 D16 N11
VSS VSS VCC VCCP
BA25 AH6 D18 K10
VSS VSS VCC VCCP
BA23 AK8 F18 P14
VSS VSS VCC VCCP
BA21 AK6 F16 P12
VSS VSS VCC VCCP
BC25 AM8 H18 R13
VSS VSS VCC VCCP
BC23 AM6 H16 R11
VCC_CORE VCC_CORE VSS VSS VCC VCCP
BC21 AP8 D20 T14
VSS VSS VCC VCCP
C17 AP6 F20 U13
VSS VSS VCC VCCP
C19 AT8 H20 U11
VSS VSS VCC VCCP
E19 AT6 K18 V14
VSS VSS VCC VCCP
E17 AU9 K16 V12
1

1
C80 C72 C67 C60 C74 C79 C71 C85 C76 C69 C115 C56 C52 C33 C114 C99 VSS VSS VCC VCCP
G19 AV6 M18 W13
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP G17
VSS VSS
AU7 M16
VCC VCCP
W11
J19 AW9 K20 P10
2

VSS VSS VCC VCCP

J17 AY6 M20 V10
VSS VSS VCC VCCP
L19 BA9 P18 Y14
VSS VSS VCC VCCP
L17 BB6 P16 AA13
VSS VSS VCC VCCP
N19 BC9 T18 AA11
VSS VSS VCC VCCP
N17 BD6 T16 AB14
VSS VSS VCC VCCP
R19 B4 V18 AB12
VSS VSS VCC VCCP
R17 C3 V16 AC13
VSS VSS VCC VCCP
U19 E3 P20 AC11
VSS VSS VCC VCCP
U17 G3 T20 AD14
VSS VSS VCC VCCP
Place these inside socket W19
VSS VSS
J3 V20
VCC VCCP
AB10
cavity on L8(North side Secondary) W17 L3 Y18 AE13
VSS VSS VCC VCCP
AA19 N3 Y16 AE11
VSS VSS VCC VCCP
AA17 R3 AB18 AF14
VSS VSS VCC VCCP
AC19 U3 AB16 AF12
1D05V_S0 VSS VSS VCC VCCP
AC17 W3 AD18 AG13
VSS VSS VCC VCCP
AE19 AA3 AD16 AG11
VSS VSS VCC VCCP
AE17 AC3 Y20 AH14
VSS VSS VCC VCCP
AG19 AE3 AB20 AJ13
VSS VSS VCC VCCP
AG17 AG3 AD20 AJ11
VSS VSS VCC VCCP
AJ19 AJ3 AF18 AF10
1

C82 C63 C113 C81 C50 C57 VSS VSS VCC VCCP
AJ17 AL3 AF16 AK14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AL19 AN3 AH18 AK12

VSS VSS VCC VCCP
AL17 AR3 AH16 AL13
2

VSS VSS VCC VCCP

AN19 AU3 AF20 AL11
B VSS VSS VCC VCCP B
AN17 AW3 AH20 AN13
VSS VSS VCC VCCP
AR19 BA3 AK18 AN11
VSS VSS VCC VCCP
AR17 BC3 AK16 AP12
VSS VSS VCC VCCP
AU19 D2 AM18 AR13
VSS VSS VCC VCCP
AU17 G1 AM16 AR11
VSS VSS VCC VCCP
AW19 AW1 AP18 AK10
VSS VSS VCC VCCP
AW17 BB2 AP16 AP10
VSS VSS VCC VCCP
BA19 A39 AK20 AU13
VSS VSS VCC VCCP
BA17 A29 AM20 AU11
VSS VSS VCC VCCP
BC19 A27 AP20 L9
VSS VSS VCC VCCP
BC17 A31 AT18 L7
VSS VSS VCC VCCP
C11 A25 AT16 N9
VSS VSS VCC VCCP
C15 A23 AV18 N7
VSS VSS VCC VCCP
E15 A21 AV16 R9
VSS VSS VCC VCCP
G15 A19 AY18 R7
VSS VSS VCC VCCP
H10 A17 AY16 U9
VSS VSS VCC VCCP
M12 A11 AT20 U7
VSS VSS VCC VCCP
J15 A15 AV20 W9
VSS VSS VCC VCCP
L15 A7 AY20 W7
VSS VSS VCC VCCP
N15 A9 BB18 AA9
VSS VSS VCC VCCP
M10 BB16 AA7
VSS VCC VCCP
T12 BD18 AC9
VSS NCTF_VSS#A5 TP71 TPAD14-GP VCC VCCP
R15 A5 1 BD16 AC7
VSS NCTF_VSS#A5 VCC VCCP
U15 A41 NCTF_VSS#A41 1 TP61 TPAD14-GP BB20 AE9
VSS NCTF_VSS#A41 VCC VCCP
W15 AY44 NCTF_VSS#AY44 1 TP49 TPAD14-GP BD20 AE7
VSS NCTF_VSS#AY44 VCC VCCP
T10 BA1 NCTF_VSS#BA1 1 TP47 TPAD14-GP AM14 AG9
VSS NCTF_VSS#BA1 VCC VCCP
Y10 BD4 NCTF_VSS#BD4 1 TP46 TPAD14-GP AP14 AG7

A5,A41,AY44,BA1,BD4,BD40,D44,E1
VSS NCTF_VSS#BD4 VCC VCCP
Y12 BD40 NCTF_VSS#BD40 1 TP48 TPAD14-GP AT14 AJ9
VSS NCTF_VSS#BD40 VCC VCCP
AA15 D44 NCTF_VSS#D44 1 TP55 TPAD14-GP AV14 AJ7
VSS NCTF_VSS#D44 NCTF_VSS#E1 TP51 TPAD14-GP VCC VCCP
AC15 E1 1 AY14 AL9
VSS NCTF_VSS#E1 VCC VCCP
AD12 BB14 AL7
VSS VCC VCCP
BD14 AN9
1D05V_S0 VCC VCCP
AN7
PENRYN-SFF-GP-U1-NF VCCP
AF38 AR9
VCCP VCCP
AG37 AR7

NCTF TEST PIN:

VCCP VCCP
AJ37 A33
VCCP VCCP
AK38 A13
VCCP VCCP

PENRYN-SFF-GP-U1-NF
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (3 of 3)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 6 of 48
5 4 3 2 1
 5 4 3 2 1

NB1A 1 OF 10 H_A#[35..3]
H_A#[35..3] 4
H_D#[63..0] L15 H_A#3
4 H_D#[63..0] H_A#_3
H_D#0 J7 B14 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
H6 H_D#_1 H_A#_5 C15
H_D#2 L11 D12 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
J3 H_D#_3 H_A#_7 F14
1D05V_S0 H_D#4 H4 G17 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
D H_SWING routing Trace width and G3 H_D#_5 H_A#_9 B12 D
H_D#6 K10 J15 H_A#10
Spacing use 10 / 20 mil H_D#_6 H_A#_10

1
H_D#7 K12 D16 H_A#11
R196 H_D#8 H_D#_7 H_A#_11 H_A#12
L1 H_D#_8 H_A#_12 C17
221R2F-2-GP H_D#9 M10 D14 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
H_SWING Resistors and M6 H_D#_10 H_A#_14 K16
H_D#11 N11 F16 H_A#15
Capacitors close MCH

2
H_D#12 H_D#_11 H_A#_15 H_A#16
L7 H_D#_12 H_A#_16 B16
500 mil ( MAX ) H_SW ING H_D#13 K6 H_D#_13 H_A#_17 C21 H_A#17
H_D#14 M4 D18 H_A#18
H_D#_14 H_A#_18

1
H_D#15 K4 J19 H_A#19

SCD1U10V2KX-4GP
H_D#_15 H_A#_19
1

C499
R194 H_D#16 P6 J21 H_A#20
100R2F-L1-GP-U H_D#17 H_D#_16 H_A#_20 H_A#21
W9 H_D#_17 H_A#_21 B18
H_D#18 V6 D22 H_A#22
2

H_D#19 H_D#_18 H_A#_22 H_A#23

V2 G19

2
H_D#20 H_D#_19 H_A#_23 H_A#24
P10 H_D#_20 H_A#_24 J17
H_D#21 W7 L21 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
N9 H_D#_22 H_A#_26 L19
H_D#23 P4 G21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
U9 H_D#_24 H_A#_28 D20
H_D#25 V4 K22 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
U1 H_D#_26 H_A#_30 F18
H_D#27 W3 K20 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
V10 H_D#_28 H_A#_32 F20
H_D#29 U7 F22 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
W11 H_D#_30 H_A#_34 B20
H_D#31 U11 A19 H_A#35
H_D#32 H_D#_31 H_A#_35
AC11 H_D#_32
H_D#33 AC9 F10 H_ADS# 4
C H_D#34 H_D#_33 H_ADS# C
Y4 A15

HOST
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 C19 H_ADSTB#1 4
H_D#36 H_D#_35 H_ADSTB#_1
AB6 H_D#_36 H_BNR# C9 H_BNR# 4
H_D#37 AA9 B8 H_BPRI# 4
H_D#38 H_D#_37 H_BPRI#
AB10 H_D#_38 H_BREQ# C11 H_BREQ#0 4
H_D#39 AA1 E5 H_DEFER# 4
H_D#40 H_D#_39 H_DEFER#
AC3 H_D#_40 H_DBSY# D6 H_DBSY# 4
H_D#41 AC7 AH10 CLK_MCH_BCLK 3
H_D#42 H_D#_41 HPLL_CLK
AD12 H_D#_42 HPLL_CLK# AJ11 CLK_MCH_BCLK# 3
H_D#43 AB4 G11 H_DPW R# 4
H_D#44 H_D#_43 H_DPWR#
Y6 H_D#_44 H_DRDY# H2 H_DRDY# 4
H_RCOMP routing Trace width and H_D#45 AD10 C7 H_HIT# 4
H_D#46 H_D#_45 H_HIT#
AA11 F8 H_HITM# 4
Spacing use 10 / 20 mil H_D#47 AB2
H_D#_46 H_HITM#
A11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AD4 D8 H_TRDY# 4
H_D#49 H_D#_48 H_TRDY#
AE7 H_D#_49
1 2 H_RCOMP H_D#50 AD2 H_D#_50
R190 24D9R2F-L-GP H_D#51 AD6
H_D#52 H_D#_51 H_DINV#[3..0]
AE3 H_D#_52 H_DINV#[3..0] 4
H_D#53 AG9 L9 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AG7 H_D#_54 H_DINV#_1 N7
H_D#55 AE11 AA7 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#57
AK6
AF6
H_D#_56 H_DINV#_3 AG3
H_DSTBN#[3..0]
H_D#_57 H_DSTBN#[3..0] 4
H_D#58 AJ9 K2 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN_0 H_DSTBN#1
AH6 H_D#_59 H_DSTBN_1 N3
H_D#60 AF12 AA3 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN_2 H_DSTBN#3
AH4 H_D#_61 H_DSTBN_3 AF4
H_D#62 AJ7 H_DSTBP#[3..0]
B H_D#_62 H_DSTBP#[3..0] 4 B
H_D#63 AE9 L3 H_DSTBP#0
H_D#_63 H_DSTBP_0 H_DSTBP#1
H_DSTBP_1 M2
Y2 H_DSTBP#2
H_SW ING H_DSTBP_2 H_DSTBP#3
B6 H_SWING H_DSTBP_3 AF2
H_RCOMP D4 H_REQ#[4..0] 4
H_RCOMP H_REQ#0
H_REQ#_0 J13
1D05V_S0 L13 H_REQ#1
H_REQ#_1 H_REQ#2
H_REQ#_2 C13
G13 H_REQ#3
H_REQ#_3
2

4 H_CPURST# J11 G15 H_REQ#4

R48 H_CPURST# H_REQ#_4
4 H_CPUSLP# G9 H_CPUSLP# H_RS#[2..0] 4
1KR2F-3-GP F4 H_RS#0
H_RS#_0 H_RS#1
H_RS#_1 F2
G7 H_RS#2
1

H_AVREF H_RS#_2
L17 H_AVREF
K18 H_DVREF
CANTIGA-GS-GP-NF
1

1
SC1KP50V2KX-1GP

R49 C169
2KR2F-3-GP
2
2

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (1 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

NB1C 3 OF 10
NB1B 2 OF 10
1D05V_S0
J43
RSVD#J43
L43 BB32 D38
J41
RSVD#L43
RSVD#J41
SA_CK_0
SA_CK_1
BA25
M_CLK_DDR0
M_CLK_DDR1
18
18
19 GMCH_L_BKLTCTL
19 GMCH_BL_ON C37
L_BKLT_CTRL
L_BKLT_EN PEG_COMPI
U45 PEG_CMP 2 1
Close to GMCH as 500 mils.
L41 BA33 LCTLA_CLK K38 T44 R53 49D9R2F-GP
RSVD#L41 SB_CK_0 M_CLK_DDR2 17 L_CTRL_CLK PEG_COMPO
AN11

DDR CLK/ CONTROL/COMPENSATION

BA23 M_CLK_DDR3 17
RSVD#AN11 SB_CK_1 LCTLB_DATA
AM10 L37
RSVD#AM10 L_CTRL_DATA
AK10 BA31 M_CLK_DDR#0 18 41 GMCH_CLK_DDC_EDID J37 D52 PEG_RXN0 42
RSVD#AK10 SA_CK#_0 L_DDC_CLK PEG_RX#_0
AL11 BC25 M_CLK_DDR#1 18 41 GMCH_DAT_DDC_EDID L35 G49 PEG_RXN1 42
RSVD#AL11 SA_CK#_1 L_DDC_DATA PEG_RX#_1
F12 BC33 M_CLK_DDR#2 17 K54 PEG_RXN2 42
RSVD#F12 SB_CK#_0 PEG_RX#_2

RSVD
1D5V_S3 AN45 BB24 H50
RSVD#AN45 SB_CK#_1 M_CLK_DDR#3 17 PEG_RX#_3 PEG_RXN3 42
R218 1KR2F-3-GP AP44 19 GMCH_LCDVDD_ON GMCH_LCDVDD_ON B36 M52 PEG_RXN4 42
RSVD#AP44 LIBG L_VDD_EN PEG_RX#_4
2 1 AT44 BC35 M_CKE0 18 F50 N49 PEG_RXN5 42
RSVD#AT44 SA_CKE_0 LVDS_IBG PEG_RX#_5
AN47 BE33 M_CKE1 18 TPAD14-GP TP26 1 L_LVBG H46 P54 PEG_RXN6 42
SM_RCOMP_VOH RSVD#AN47 SA_CKE_1 LVDS_VBG PEG_RX#_6
C27 BE37 M_CKE2 17 P44 V46 PEG_RXN7 42
RSVD#C27 SB_CKE_0 LVDS_VREFH PEG_RX#_7

LVDS
D D30 BC37 M_CKE3 17 K46 Y50 PEG_RXN8 42 D
1

1
C513 C514 RSVD#D30 SB_CKE_1 LVDS_VREFL PEG_RX#_8
41 GMCH_TXACLK- D46 V52 PEG_RXN9 42
R216 LVDSA_CLK# PEG_RX#_9
J9 BK18 M_CS0# 18 41 GMCH_TXACLK+ B46 W49 PEG_RXN10 42
3K01R2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP RSVD#J9 SA_CS#_0 LVDSA_CLK PEG_RX#_10
BK16 M_CS1# 18 D44 AB54 PEG_RXN11 42

2
SA_CS#_1 LVDSB_CLK# PEG_RX#_11
BE23 M_CS2# 17 B44 AD46 PEG_RXN12 42
SB_CS#_0 LVDSB_CLK PEG_RX#_12
AW42 BC19 M_CS3# 17 AC55 PEG_RXN13 42
2

SM_RCOMP_VOL RSVD#AW42 SB_CS#_1 PEG_RX#_13

41 GMCH_TXAOUT0- G45 AE49 PEG_RXN14 42
LVDSA_DATA#_0 PEG_RX#_14
BJ17 M_ODT0 18 41 GMCH_TXAOUT1- F46 AF54 PEG_RXN15 42
2

1
SA_ODT_0 LVDSA_DATA#_1 PEG_RX#_15

GRAPHICS
C511 C510 BJ19 M_ODT1 18 41 GMCH_TXAOUT2- G41
R214 SA_ODT_1 LVDSA_DATA#_2
BB20 BC17 M_ODT2 17 C45 E51 PEG_RXP0 42
1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP RSVD#BB20 SB_ODT_0 LVDSA_DATA#_3 PEG_RX_0
BE19 BE17 M_ODT3 17 F48 PEG_RXP1 42
2

2
RSVD#BE19 SB_ODT_1 PEG_RX_1
BF20 41 GMCH_TXAOUT0+ F44 J55 PEG_RXP2 42
RSVD#BF20 M_RCOMPP LVDSA_DATA_0 PEG_RX_2
BF18 BL25 41 GMCH_TXAOUT1+ G47 J49 PEG_RXP3 42
1

RSVD#BF18 SM_RCOMP M_RCOMPN LVDSA_DATA_1 PEG_RX_3

BK26 SM_PWROK 32 41 GMCH_TXAOUT2+ F40 M54 PEG_RXP4 42
SM_RCOMP# LVDSA_DATA_2 PEG_RX_4
A45 M50 PEG_RXP5 42
SM_RCOMP_VOH LVDSA_DATA_3 PEG_RX_5
BK32 P52 PEG_RXP6 42
SM_RCOMP_VOH SM_RCOMP_VOL DDR_VREF_S3_1 PEG_RX_6
BL31 B40 U47 PEG_RXP7 42
SM_RCOMP_VOL LVDSB_DATA#_0 PEG_RX_7
layout take note 0.75V A41
LVDSB_DATA#_1 PEG_RX_8
AA49 PEG_RXP8 42
BC51 F42 V54 PEG_RXP9 42
SM_VREF DDR2 : connect to GND LVDSB_DATA#_2 PEG_RX_9
AY37 D48 V50 PEG_RXP10 42
SM_PWROK SM_REXT R2041 499R2F-2-GP LVDSB_DATA#_3 PEG_RX_10
BH20 2 AB52 PEG_RXP11 42

1
SM_REXT C238 RN8 PEG_RX_11
BA37 DDR3_DRAMRST# 17,18 D40 AC47 PEG_RXP12 42
SM_DRAMRST# LVDSB_DATA_0 PEG_RX_12

SCD1U10V2KX-4GP
DREFCLK 4 5 C41 AC53

PCI-EXPRESS
LVDSB_DATA_1 PEG_RX_13 PEG_RXP13 42
B42 DREFCLK# 3 6 G43 AD50 PEG_RXP14 42

2
DPLL_REF_CLK DREFCLK 3 DREFSSCLK LVDSB_DATA_2 PEG_RX_14
D42 2 7 B48 AF52 PEG_RXP15 42
DPLL_REF_CLK# DREFCLK# 3 DREFSSCLK# LVDSB_DATA_3 PEG_RX_15
B50 1 8
DPLL_REF_SSCLK DREFSSCLK 3
D50 L47 M_TXN0 C535 1 2 SCD1U6D3V1KX-GP PEG_TXN0 42
DPLL_REF_SSCLK# DREFSSCLK# 3 PEG_TX#_0
SRN0J-7-GP F52 M_TXN1 C539 1 2 SCD1U6D3V1KX-GP PEG_TXN1 42
TV_DACA PEG_TX#_1
R49 CLK_MCH_3GPLL 3 DY J27 P46 M_TXN2 C550 1 2 SCD1U6D3V1KX-GP PEG_TXN2 42
PEG_CLK TV_DACB TVA_DAC PEG_TX#_2
P50 CLK_MCH_3GPLL# 3 E27 H54 M_TXN3 C589 1 2 SCD1U6D3V1KX-GP PEG_TXN3 42
PEG_CLK# TVB_DAC PEG_TX#_3

TV
TV_DACC G27 L55 M_TXN4 C577 1 2 SCD1U6D3V1KX-GP
SB TVC_DAC PEG_TX#_4
PEG_TX#_5
T46 M_TXN5 C575 1 2 SCD1U6D3V1KX-GP
PEG_TXN4 42
PEG_TXN5 42
R53 M_TXN6 C573

CLK
F26 1 2 SCD1U6D3V1KX-GP PEG_TXN6 42
TVA_RTN PEG_TX#_6
AG55 U49 M_TXN7 C571 1 2 SCD1U6D3V1KX-GP PEG_TXN7 42
DMI_RXN_0 DMI_TXN0 14 PEG_TX#_7
AL49 T54 M_TXN8 C569 1 2 SCD1U6D3V1KX-GP PEG_TXN8 42
DMI_RXN_1 DMI_TXN1 14 PEG_TX#_8
AH54 Y46 M_TXN9 C567 1 2 SCD1U6D3V1KX-GP PEG_TXN9 42
DMI_RXN_2 DMI_TXN2 14 PEG_TX#_9
AL47 B34 AB46 M_TXN10C565 1 2 SCD1U6D3V1KX-GP PEG_TXN10 42
DMI_RXN_3 DMI_TXN3 14 TV_DCONSEL_0 PEG_TX#_10
D34 W53 M_TXN11C563 1 2 SCD1U6D3V1KX-GP PEG_TXN11 42
TV_DCONSEL_1 PEG_TX#_11
AG53 Y54 M_TXN12C561 1 2 SCD1U6D3V1KX-GP PEG_TXN12 42
DMI_RXP_0 DMI_TXP0 14 PEG_TX#_12
3,4 CPU_SEL0 K26 AK50 AC49 M_TXN13C559 1 2 SCD1U6D3V1KX-GP PEG_TXN13 42
CFG_0 DMI_RXP_1 DMI_TXP1 14 PEG_TX#_13
3,4 CPU_SEL1 G23 AH52 AF46 M_TXN14C557 1 2 SCD1U6D3V1KX-GP PEG_TXN14 42
CFG_1 DMI_RXP_2 DMI_TXP2 14 PEG_TX#_14
C
3,4 CPU_SEL2 G25 AL45 AD54 M_TXN15C555 1 2 SCD1U6D3V1KX-GP PEG_TXN15 42 C
CFG_2 DMI_RXP_3 DMI_TXP3 14 PEG_TX#_15
J25
CFG_3 GMCH_BLUE
3D3V_S0 L25 AG49 41 GMCH_BLUE J29 J47 M_TXP0 C530 1 2 SCD1U6D3V1KX-GP PEG_TXP0 42
CFG_4 DMI_TXN_0 DMI_RXN0 14 CRT_BLUE PEG_TX_0
L27 AJ49 F54 M_TXP1 C536 1 2 SCD1U6D3V1KX-GP PEG_TXP1 42
CFG_5 DMI_TXN_1 DMI_RXN1 14 GMCH_GREEN PEG_TX_1
F24 AJ47 41 GMCH_GREEN G29 N47 M_TXP2 C543 1 2 SCD1U6D3V1KX-GP PEG_TXP2 42
CFG_6 DMI_TXN_2 DMI_RXN2 14 CRT_GREEN PEG_TX_2
D24 AG47 H52 M_TXP3 C584 1 2 SCD1U6D3V1KX-GP PEG_TXP3 42
CFG_7 DMI_TXN_3 DMI_RXN3 14 PEG_TX_3

VGA
D26 GMCH_RED F30 L53 M_TXP4 C578 1 2 SCD1U6D3V1KX-GP
CFG_8 41 GMCH_RED CRT_RED PEG_TX_4 PEG_TXP4 42

CFG
CFG9 J23 AF50 R47 M_TXP5 C576 1 2 SCD1U6D3V1KX-GP
CFG_9 DMI_TXP_0 DMI_RXP0 14 PEG_TX_5 PEG_TXP5 42
R51 1 DY 2 4K02R2F-GP CFG20 B26 AH50 E29 R55 M_TXP6 C574 1 2 SCD1U6D3V1KX-GP
CFG_10 DMI_TXP_1 DMI_RXP1 14 CRT_IRTN PEG_TX_6 PEG_TXP6 42
A23 AJ45 T50 M_TXP7 C572 1 2 SCD1U6D3V1KX-GP PEG_TXP7 42
CFG_11 DMI_TXP_2 DMI_RXP2 14 PEG_TX_7

GRAPHICS VID DMI

C23 AG45 GMCH_DDCCLK D36 T52 M_TXP8 C570 1 2 SCD1U6D3V1KX-GP
CFG_12 DMI_TXP_3 DMI_RXP3 14 20 GMCH_DDCCLK CRT_DDC_CLK PEG_TX_8 PEG_TXP8 42
B24 GMCH_DDCDATA C35 W47 M_TXP9 C568 1 2 SCD1U6D3V1KX-GP
CFG_13 20 GMCH_DDCDATA CRT_DDC_DATA PEG_TX_9 PEG_TXP9 42
R50 1 DY 2 2K21R2F-GP CFG9 B22 J33 AA47 M_TXP10C566 1 2 SCD1U6D3V1KX-GP PEG_TXP10 42
CFG_14 CRT_HSYNC PEG_TX_10
K24 20 GMCH_HSYNC D32 W55 M_TXP11C564 1 2 SCD1U6D3V1KX-GP PEG_TXP11 42
CFG_15 CRT_TVO_IREF PEG_TX_11
TPAD14-GP TP77 1 CFG16 C25 20 GMCH_VSYNC G31 Y52 M_TXP12C562 1 2 SCD1U6D3V1KX-GP PEG_TXP12 42
CFG_16 CRT_VSYNC PEG_TX_12
L23 AB50 M_TXP13C560 1 2 SCD1U6D3V1KX-GP PEG_TXP13 42
CFG_17 PEG_TX_13
L33 AE47 M_TXP14C558 1 2 SCD1U6D3V1KX-GP PEG_TXP14 42
CFG_18 PEG_TX_14
K32 AD52 M_TXP15C556 1 2 SCD1U6D3V1KX-GP PEG_TXP15 42
CFG20 CFG_19 GFX_VID0 PEG_TX_15
K34 G33
1D5V_S3 CFG_20 GFX_VID_0 GFX_VID1 CRT_IREF
G37 1 2
GFX_VID_1 GFX_VID2 R211 976R2F-3-GP CANTIGA-GS-GP-NF
GFX_VID_2
F38
GFX_VID3
0201 CAPs
F36
GFX_VID_3 GFX_VID4
14 PM_SYNC# J35 G35 GFX_VID[4..0] 38
1

PM_SYNC# GFX_VID_4
4,13,34 H_DPRSTP# F6
PM_EXTTS#0 PM_DPRSTP#
R206 17,18 PM_EXTTS#0 J39 FOR Cantiga: 1.02k_1% ohm
PM_EXT_TS#_0
PM

80D6R2F-L-GP PM_EXTTS#1 L39 Teenah: 1.3k ohm

PM_EXT_TS#_1 GFXVR_EN
14,32 PWROK AY39 G39
PLT_RST1#_Cantiga PWROK GFX_VR_EN GFXVR_EN 38 1D05V_S0
BB18 CRT_IREF routing Trace
2

M_RCOMPP PM_THRMTRIP-A#_R RSTIN#

K28
width use 20 mil

2
THERMTRIP#
14,22,24,25,28,29,42 PLT_RST1# 2 1R47 K36
100R2J-2-GP DPRSLPVR R243
M_RCOMPN AK52 1KR2F-3-GP
CL_CLK0 14
1

C164 CL_CLK
AK54 CL_DATA0 14
1

SC100P50V2JN-3GP CL_DATA
A7 AW40 PWROK 14,32

1
NC#A7 CL_PWROK
ME

R207 DY A49 AL53

2

NC#A49 CL_RST# CL_RST#0 14

80D6R2F-L-GP A52 AL55 MCH_CLVREF
NC#A52 CL_VREF SRN100KJ-6-GP
R208 A54

1
NC#A54 GMCH_BL_ON
B54 2 3
2

1
NC#B54 C583 R244 GMCH_LCDVDD_ON
4,13,32 PM_THRMTRIP-A# 1 2 D55 1 4
NC#D55 511R2F-2-GP
G55 F34

SCD1U10V2KX-4GP
NC#G55 DDPC_CTRLCLK RN26
NC

14,34 PM_DPRSLPVR 0R0402-PAD BE55 F32

2
B NC#BE55 DDPC_CTRLDATA SDVO_CLK B
BH55 B38

2
NC#BH55 SDVO_CTRLCLK SDVO_DAT
BK55 A37
MISC

NC#BK55 SDVO_CTRLDATA
BK54 C31 CLK_MCH_OE# 3
NC#BK54 CLKREQ#
BL54 K42 MCH_ICH_SYNC# 14
NC#BL54 ICH_SYNC# LIBG
BL52 FOR Cantiga:500 ohm 1 2
NC#BL52 R221 2K4R2F-GP
BL49 Teenah: 392 ohm
NC#BL49 MCH_TSATN#
BL7 D10
NC#BL7 TSATN#
BL4 SRN150F-1-GP
NC#BL4 RN27
BL2
NC#BL2 GMCH_BLUE
BK2 1 8
NC#BK2 GMCH_GREEN 2
BK1
BH1
NC#BK1 for debug only 3D3V_S0 -1 GMCH_RED 3
7
6
NC#BH1
BE1 4 5
NC#BE1
G1 C29
NC#G1 HDA_BCLK RN46
B30
HDA_RST# SDVO_CLK
D28 3 2
HDA_SDI SDVO_DAT
A27 4 1
HDA_SDO SRN0J-10-GP-U
B28
HDA_SYNC
HDA

DY

CANTIGA-GS-GP-NF

1D05V_S0
RN23
1

3D3V_S0 1 8 TV_DACC
R198 2 7 TV_DACB
SRN10KJ-5-GP 56R2F-1-GP 3 6 TV_DACA
PM_EXTTS#0 3 2 4 5
PM_EXTTS#1 4 1
2

MCH_TSATN#
RN28 SRN75J-1-GP

3D3V_S0

SRN10KJ-5-GP
A LCTLA_CLK A
3 2
LCTLB_DATA 4 1
RN6

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (2 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 8 of 48
5 4 3 2 1
 5 4 3 2 1

M_A_DQ[63..0] NB1D 4 OF 10 M_B_DQ[63..0] NB1E 5 OF 10

18 M_A_DQ[63..0] 17 M_B_DQ[63..0]
M_A_DQ0 AP46 BC21 M_A_BS#0 18 M_B_DQ0 AP54 BJ13 M_B_BS#0 17
M_A_DQ1 SA_DQ_0 SA_BS_0 M_B_DQ1 SB_DQ_0 SB_BS_0
AU47 SA_DQ_1 SA_BS_1 BJ21 M_A_BS#1 18 AM52 SB_DQ_1 SB_BS_1 BK12 M_B_BS#1 17
M_A_DQ2 AT46 BJ41 M_A_BS#2 18 M_B_DQ2 AR55 BK38 M_B_BS#2 17
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AU49 SA_DQ_3 AV54 SB_DQ_3
M_A_DQ4 AR45 BH22 M_A_RAS# 18 M_B_DQ4 AM54
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AN49 SA_DQ_5 SA_CAS# BK20 M_A_CAS# 18 AN53 SB_DQ_5 SB_RAS# BE21 M_B_RAS# 17
M_A_DQ6 AV50 BL15 M_A_W E# 18 M_B_DQ6 AT52 BH14 M_B_CAS# 17
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AP50 SA_DQ_7 AU53 SB_DQ_7 SB_WE# BK14 M_B_W E# 17
D M_A_DQ8 AW47 M_B_DQ8 AW53 D
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
BD50 SA_DQ_9 AY52 SB_DQ_9
M_A_DQ10 AW49 M_A_DM[7..0] M_B_DQ10 BB52
SA_DQ_10 M_A_DM[7..0] 18 SB_DQ_10
M_A_DQ11 BA49 AT50 M_A_DM0 M_B_DQ11 BC53 M_B_DM[7..0]
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7..0] 17
M_A_DQ12 BC49 BB50 M_A_DM1 M_B_DQ12 AV52 AP52 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
M_A_DQ14 BA47 BE39 M_A_DM3 M_B_DQ14 BD52 BJ49 M_B_DM2
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43

A
M_A_DQ16 BF46 BE7 M_A_DM5 M_B_DQ16 BF54 BH12 M_B_DM4
M_A_DQ17 SA_DQ_16 SA_DM_5 M_A_DM6 M_B_DQ17 SB_DQ_16 SB_DM_4 M_B_DM5
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
M_A_DQ18 BF50 AR9 M_A_DM7 M_B_DQ18 BH48 AY2 M_B_DM6

B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_A_DQS[7..0] M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BF48 SA_DQ_19 M_A_DQS[7..0] 18 BK48 SB_DQ_19 SB_DM_7 AJ3
M_A_DQ20 BC43 AR47 M_A_DQS0 M_B_DQ20 BE53 M_B_DQS[7..0]
M_B_DQS[7..0] 17

MEMORY
M_A_DQ21 SA_DQ_20 SA_DQS_0 M_A_DQS1 M_B_DQ21 SB_DQ_20 M_B_DQS0
BE49 SA_DQ_21 SA_DQS_1 BA45 BH52 SB_DQ_21 SB_DQS_0 AR53
M_A_DQ22 BA43 BE45 M_A_DQS2 M_B_DQ22 BK46 BA53 M_B_DQS1
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2

MEMORY
BE47 SA_DQ_23 SA_DQS_3 BC41 BJ47 SB_DQ_23 SB_DQS_2 BH50
M_A_DQ24 BF42 BC13 M_A_DQS4 M_B_DQ24 BL45 BK42 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BC39 SA_DQ_25 SA_DQS_5 BB10 BJ45 SB_DQ_25 SB_DQS_4 BH8
M_A_DQ26 BF44 BA7 M_A_DQS6 M_B_DQ26 BL41 BB2 M_B_DQS5
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
BF40 SA_DQ_27 SA_DQS_7 AN7 BH44 SB_DQ_27 SB_DQS_6 AV2
M_A_DQ28 BB40 M_A_DQS#[7..0] M_B_DQ28 BH46 AM2 M_B_DQS7
SA_DQ_28 M_A_DQS#[7..0] 18 SB_DQ_28 SB_DQS_7
M_A_DQ29 BE43 AR49 M_A_DQS#0 M_B_DQ29 BK44 M_B_DQS#[7..0]
SA_DQ_29 SA_DQS#_0 SB_DQ_29 M_B_DQS#[7..0] 17
M_A_DQ30 BF38 AW45 M_A_DQS#1 M_B_DQ30 BK40 AT54 M_B_DQS#0
M_A_DQ31 SA_DQ_30 SA_DQS#_1 M_A_DQS#2 M_B_DQ31 SB_DQ_30 SB_DQS#_0 M_B_DQS#1
BE41 SA_DQ_31 SA_DQS#_2 BC45 BJ39 SB_DQ_31 SB_DQS#_1 BB54
M_A_DQ32 BA15 BA41 M_A_DQS#3 M_B_DQ32 BK10 BJ51 M_B_DQS#2
M_A_DQ33 SA_DQ_32 SA_DQS#_3 M_A_DQS#4 M_B_DQ33 SB_DQ_32 SB_DQS#_2 M_B_DQS#3
BE11 SA_DQ_33 SYSTEM SA_DQS#_4 BA13 BH10 SB_DQ_33 SB_DQS#_3 BH42
M_A_DQ34 BE15 BA11 M_A_DQS#5 M_B_DQ34 BK6 BK8 M_B_DQS#4
M_A_DQ35 SA_DQ_34 SA_DQS#_5 M_A_DQS#6 M_B_DQ35 SB_DQ_34 SB_DQS#_4 M_B_DQS#5
BF14 SA_DQ_35 SA_DQS#_6 BA9 BH6 SB_DQ_35 SB_DQS#_5 BC3
M_A_DQ36 M_A_DQS#7 M_B_DQ36 M_B_DQS#6

SYSTEM
BB14 SA_DQ_36 SA_DQS#_7 AN9 BJ9 SB_DQ_36 SB_DQS#_6 AW3
C M_A_DQ37 BC15 M_A_A[14..0] M_B_DQ37 BL11 AN3 M_B_DQS#7 C
SA_DQ_37 M_A_A[14..0] 18 SB_DQ_37 SB_DQS#_7
M_A_DQ38 BE13 BC23 M_A_A0 M_B_DQ38 BG5 M_B_A[14..0]
SA_DQ_38 SA_MA_0 SB_DQ_38 M_B_A[14..0] 17
M_A_DQ39 BF16 BF22 M_A_A1 M_B_DQ39 BJ5 BJ15 M_B_A0
M_A_DQ40 SA_DQ_39 SA_MA_1 M_A_A2 M_B_DQ40 SB_DQ_39 SB_MA_0 M_B_A1
BF10 SA_DQ_40 SA_MA_2 BE31 BG3 SB_DQ_40 SB_MA_1 BJ33
M_A_DQ41 BC11 BC31 M_A_A3 M_B_DQ41 BF4 BH24 M_B_A2
M_A_DQ42 SA_DQ_41 SA_MA_3 M_A_A4 M_B_DQ42 SB_DQ_41 SB_MA_2 M_B_A3
BF8 SA_DQ_42 SA_MA_4 BH26 BD4 SB_DQ_42 SB_MA_3 BA17
M_A_DQ43 BG7 BJ35 M_A_A5 M_B_DQ43 BA3 BF36 M_B_A4
M_A_DQ44 SA_DQ_43 SA_MA_5 M_A_A6 M_B_DQ44 SB_DQ_43 SB_MA_4 M_B_A5
BC7 SA_DQ_44 SA_MA_6 BB34 BE5 SB_DQ_44 SB_MA_5 BH36
M_A_DQ45 BC9 BH32 M_A_A7 M_B_DQ45 BF2 BF34 M_B_A6
M_A_DQ46 SA_DQ_45 SA_MA_7 M_A_A8 M_B_DQ46 SB_DQ_45 SB_MA_6 M_B_A7
DDR

BD6 SA_DQ_46 SA_MA_8 BB26 BB4 SB_DQ_46 SB_MA_7 BK34

M_A_DQ47 BF12 BF32 M_A_A9 M_B_DQ47 AY4 BJ37 M_B_A8
M_A_DQ48 SA_DQ_47 SA_MA_9 M_A_A10 M_B_DQ48 SB_DQ_47 SB_MA_8 M_B_A9
AV6 SA_DQ_48 SA_MA_10 BA21 BA1 SB_DQ_48 SB_MA_9 BH40

DDR
M_A_DQ49 BB6 BG25 M_A_A11 M_B_DQ49 AP2 BH16 M_B_A10
M_A_DQ50 SA_DQ_49 SA_MA_11 M_A_A12 M_B_DQ50 SB_DQ_49 SB_MA_10 M_B_A11
AW7 SA_DQ_50 SA_MA_12 BH34 AU1 SB_DQ_50 SB_MA_11 BK36
M_A_DQ51 AY6 BH18 M_A_A13 M_B_DQ51 AT2 BH38 M_B_A12
M_A_DQ52 SA_DQ_51 SA_MA_13 M_A_A14 M_B_DQ52 SB_DQ_51 SB_MA_12 M_B_A13
AT10 SA_DQ_52 SA_MA_14 BE25 AT4 SB_DQ_52 SB_MA_13 BJ11
M_A_DQ53 AW11 M_B_DQ53 AV4 BL37 M_B_A14
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53 SB_MA_14
AU11 SA_DQ_54 AU3 SB_DQ_54
M_A_DQ55 AW9 M_B_DQ55 AR3
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AR11 SA_DQ_56 AN1 SB_DQ_56
M_A_DQ57 AT6 M_B_DQ57 AP4
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AP6 SA_DQ_58 AL3 SB_DQ_58
M_A_DQ59 AL7 M_B_DQ59 AJ1
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AR7 SA_DQ_60 AK4 SB_DQ_60
M_A_DQ61 AT12 M_B_DQ61 AM4
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AM6 SA_DQ_62 AH2 SB_DQ_62
M_A_DQ63 AU7 M_B_DQ63 AK2
SA_DQ_63 SB_DQ_63
CANTIGA-GS-GP-NF CANTIGA-GS-GP-NF
B B

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (3 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1
NB1G 7 OF 10

VCC_GFXCORE
1D5V_S3

NB1F 6 OF 10
T32
VCC_AXG_NCTF
BB36 U31
VCC_SM VCC_AXG_NCTF
BE35 T31
VCC_SM VCC_AXG_NCTF 1D05V_S0
AW34 R31 FOR VCC CORE
VCC_SM VCC_AXG_NCTF
AW32 U29
VCC_SM VCC_AXG_NCTF
BK30 T29
VCC_SM VCC_AXG_NCTF
BH30 R29 AT41
VCC_SM VCC_AXG_NCTF VCC
BF30 U28 AR41
VCC_SM VCC_AXG_NCTF VCC
BD30 U27 AN41
VCC_SM VCC_AXG_NCTF C213 C221 C236 C204 C206 C212 C198 VCC
BB30 T27 AJ41

1
VCC_SM VCC_AXG_NCTF VCC

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AW30 R27 AH41
VCC_SM VCC_AXG_NCTF VCC
BL29 U25 AD41
VCC_SM VCC_AXG_NCTF VCC
BJ29 T25 AC41

2
VCC_SM VCC_AXG_NCTF VCC
BG29 R25 Y41
VCC_SM VCC_AXG_NCTF VCC
D BE29 U24 W41 D
VCC_SM VCC_AXG_NCTF VCC
BC29 U22 AT40
VCC_SM VCC_AXG_NCTF VCC

POWER
BA29 T22 AM40
VCC_SM VCC_AXG_NCTF VCC
AY29 R22 AL40
VCC_SM VCC_AXG_NCTF VCC
BK28 U21
VCC_SM VCC_AXG_NCTF Coupling CAP 370 mils from the Edge
BH28 T21 AJ40
VCC_SM VCC_AXG_NCTF VCC

VCC CORE
BF28 R21 AH40
VCC_SM VCC_AXG_NCTF VCC
BD28 AM19 AG40
VCC_SM VCC_AXG_NCTF VCC
BB28 AL19 AE40
VCC_SM VCC_AXG_NCTF VCC
BL27 AH19 AD40
VCC_SM VCC_AXG_NCTF VCC
BJ27 AG19 AC40
VCC_SM VCC_AXG_NCTF VCC
BG27 AE19 AA40
VCC_SM VCC_AXG_NCTF VCC

VCC SM
BE27 AD19 Y40
VCC_SM VCC_AXG_NCTF VCC_GFXCORE VCC
BC27 AC19 AN35

VCC GFX NCTF

VCC_SM VCC_AXG_NCTF VCC
BA27 W19 AM35

1
VCC_SM VCC_AXG_NCTF C218 C205 VCC
AY27 U19 AJ35
VCC_SM VCC_AXG_NCTF VCC
AW26 AM18 AH35
VCC_SM VCC_AXG_NCTF SCD1U10V2KX-4GP VCC
BF24 AL18 AD35

2
1

1
VCC_SM VCC_AXG_NCTF C174 C192 C163 C165 C178 C170 C184 C159 C162 BC1 C171 C172 VCC
BL19 AJ18 AC35

1
VCC_SM VCC_AXG_NCTF SC10U6D3V5MX-3GP VCC
BB16 AH18 W35

SC1U10V3KX-3GP
SC10U10V5KX-2GP

SC10U10V5KX-2GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
VCC_SM VCC_AXG_NCTF VCC
AG18 AM34

2
VCC_GFXCORE VCC_AXG_NCTF VCC
AE18 AL34

2
VCC_AXG_NCTF VCC
AD18 AJ34
VCC_AXG_NCTF VCC
AC18 AH34
VCC_AXG_NCTF VCC
W32
VCC_AXG VCC_AXG_NCTF
AA18 Coupling CAP AG34
VCC
AG31 Y18 AE34 1D05V_S0
VCC_AXG VCC_AXG_NCTF VCC

POWER
AE31 W18 AD34
VCC_AXG VCC_AXG_NCTF VCC
AD31 U18 AT38
VCC_AXG VCC_AXG_NCTF Coupling CAP VCC_NCTF
AC31 T18 AC34 AR38
VCC_AXG VCC_AXG_NCTF VCC VCC_NCTF
AA31 R18 DY DY AA34 AN38
VCC_AXG VCC_AXG_NCTF DY DY DY VCC VCC_NCTF
Y31 AM38
VCC_AXG VCC_NCTF
W31 Place on the Edge Y34 AL38
VCC_AXG VCC_GFXCORE VCC VCC_NCTF
AH29 W34 AG38
VCC_AXG VCC VCC_NCTF
AG29 AM32 AE38
VCC_AXG VCC VCC_NCTF
AE29 AL32 AA38
VCC_AXG VCC VCC_NCTF
AD29 AJ16 AJ32 Y38
VCC_AXG VCC_AXG VCC VCC_NCTF
AC29 AH16 AH32 W38
VCC_AXG VCC_AXG VCC VCC_NCTF
AA29 AD16 AE32 U38
VCC_AXG VCC_AXG VCC VCC_NCTF
Y29 AC16 AD32 T38
VCC_AXG VCC_AXG VCC VCC_NCTF
W29 AA16 AA32 R38
VCC_AXG VCC_AXG VCC VCC_NCTF
AH28 U16 AM31 AT37
VCC_AXG VCC_AXG VCC VCC_NCTF
C AG28 T16 AL31 AR37 C
VCC_AXG VCC_AXG VCC VCC_NCTF
VCC GFX

AE28 R16 AJ31 AN37

VCC_AXG VCC_AXG VCC VCC_NCTF
AA28 AM15 AH31 AM37
VCC_AXG VCC_AXG VCC VCC_NCTF
AH27 AL15 AM29 AL37
VCC_AXG VCC_AXG VCC VCC_NCTF
AG27
VCC_AXG VCC_AXG
AJ15 Place CAP where AL29
VCC VCC_NCTF
AJ37
AE27 AH15 LVDS and DDR3 taps AM28 AH37
VCC_AXG VCC_AXG VCC VCC_NCTF
AD27 AG15 AL28 AG37
VCC_AXG VCC_AXG VCC VCC_NCTF
AC27 AE15 AJ28 AE37
VCC_AXG VCC_AXG VCC VCC_NCTF
AA27 AA15 AM27 AD37
VCC_AXG VCC_AXG VCC VCC_NCTF
Y27 Y15 FOR VCC SM AL27 AC37
VCC_AXG VCC_AXG VCC VCC_NCTF

VCC NCTF
W27 W15 AM25 AA37
VCC_AXG VCC_AXG 1D5V_S3 VCC VCC_NCTF
AH25 U15 AL25 Y37
VCC_AXG VCC_AXG VCC VCC_NCTF
AD25 T15 AJ25 W37
VCC_AXG VCC_AXG VCC VCC_NCTF
AC25 AM24 U37
VCC_AXG C191 C187 R52 VCC_GMCH_35 N36 VCC VCC_NCTF
W25 1 2 T37

1
VCC_AXG VCC VCC_NCTF

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AJ24 C217 C216 C166 DY TC10 0R0402-PAD R37

1
VCC_AXG VCC_NCTF

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

ST330U2D5VBM-GP
AH24 AT35
VCC_AXG SCD1U10V2KX-4GP VCC_NCTF
AG24 AR35
2

2
VCC_AXG VCC_NCTF
AE24 U35

2
VCC_AXG VCC_NCTF
AD24 AT34
VCC_AXG VCC_NCTF
AC24 AR34
VCC_AXG VCC_NCTF
AA24 U34
VCC_AXG VCC_NCTF
Y24 T34
VCC_AXG VCC_NCTF
W24 R34
VCC_AXG VCC_NCTF
AM22
VCC_AXG
AL22
VCC_AXG
AJ22
VCC_AXG
Place on the Edge
VCC GFX

AH22
VCC_AXG
AG22
VCC_AXG
AE22
VCC_AXG
AD22
VCC_AXG
AC22
VCC_AXG
AA22 AU45 SM_LF1_GMCH
VCC_AXG VCC_SM_LF
VCC SM LF

AM21 BF52 SM_LF2_GMCH

VCC_AXG VCC_SM_LF
AL21 BB38 SM_LF3_GMCH
VCC_AXG VCC_SM_LF
AJ21 BA19 SM_LF4_GMCH
VCC_AXG VCC_SM_LF
AH21 BE9 SM_LF5_GMCH
VCC_AXG VCC_SM_LF
AD21 AU9 SM_LF6_GMCH
SCD47U10V3KX-3GP

VCC_AXG VCC_SM_LF
AC21 AL9 SM_LF7_GMCH CANTIGA-GS-GP-NF
VCC_AXG VCC_SM_LF
C211

C237

C229

AA21
SC1U10V3KX-3GP

SC1U10V3KX-3GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP
1

VCC_AXG
C146

C142

Y21 C147 C175

B VCC_AXG B
W21
VCC_AXG
AM16
2

VCC_AXG
AL16
VCC_AXG

VCC_AXG_SENSE AG13
38 VCC_AXG_SENSE VCC_AXG_SENSE
38 VSS_AXG_SENSE VSS_AXG_SENSE AE13
VSS_AXG_SENSE

place near Cantiga

U60(ISL6263ACRZ-T-GP) place near Cantiga
CANTIGA-GS-GP-NF

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (4 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 10 of 48
5 4 3 2 1
 5 4 3 2 1

5V_S0 Imax = 300 mA 3D3V_S0_DAC 1D05V_S0

3D3V_S0_DAC 852mA
U30 80mA NB1H 8 OF 10

SC2D2U6D3V3MX-1-GP
SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
C209 C210

ST220U2D5VDM-13GP
SCD47U6D3V2KX-GP

SC4D7U6D3V3KX-GP

SCD47U6D3V2KX-GP
1

1
1 1 TC8

C228

C220

C179

C193
1 VIN VOUT 5 VTT R13
2 GND VTT T12

1
3 4 J31 R11 2 2

2
EN NC#4 C509 VCCA_CRT_DAC VTT
VTT T10 DY
SC10U6D3V5MX-3GP R9

2
VTT
1

1
SC1U10V3KX-3GP

BC3 RT9198-33PBR-GP T8
BC2 VTT
74.09198.G7F L31 R7

CRT
3D3V_S0_DAC VCCA_DAC_BG VTT

SC1U10V3KX-3GP
74.09091.J3F M33 T6
2

2
VSSA_DAC_BG VTT
R5
D
10mA VTT
VTT T4
D

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
C202 C201 R3
VTT

1
M_VCCA_DPLLA J45 T2 3D3V_S0_DAC
1D05V_S0 VCCA_DPLLA VTT
R1

VTT
M_VCCA_DPLLB VTT
L49

2
VCCA_DPLLB
65mA

PLL

1
M_VCCA_DPLLA M_VCCA_HPLL AF10 180ohm 100MHz
VCCA_HPLL C197
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C520 C519 C518 M_VCCA_MPLL AE1 K30

2
VCCA_MPLL VCCA_TV_DAC SCD1U10V2KX-4GP

TV
1D8V_NB_S0
2

A PEG A LVDS
1
U43
C225 13.2mA U41
VCCA_LVDS
A31 SB

D TV/CRT HDA
SC1KP50V2KX-1GP VCCA_LVDS VCC_HDA
DY DY

2
V44
65mA M_VCCA_DPLLB 1D5V_S0 VSSA_LVDS
N34 1D5VRUN_TVDAC
VCCD_QDAC
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C528 C527 C529 AJ43 VCCA_PEG_BG 1D5VRUN_QDAC

VCCD_TVDAC N32

1
C227
50mA
2

SCD1U10V2KX-4GP I=300mA NB:180mA

1D05V_S0 1D05V_RUN_PEGPLL AG43

2
VCCA_PEG_PLL
3D3V_S0 U10
DY DY

2
AW24 VCCA_SM 1 VIN VOUT 5 1D8V_NB_S0
AU24 1D05V_S0 C222 2
VCCA_SM
POWER GND

2
SC1U10V2ZY-GP
C148 C160 C155 AW22 3 4
480mA 350mA

1
VCCA_SM EN/EN# NC#4

1
SC4D7U6D3V3KX-GP

SC1U10V3KX-3GP
C AU22 C234 C
VCCA_SM

SC10U6D3V5MX-3GP

SC1U10V2ZY-GP
AU21

1
1D05V_S0 VCCA_SM

SC10U6D3V5MX-3GP
AW20 RT9198-18PBR-GP

2
VCCA_SM

1
1D05V_SUS_MCH_PLL2

SC1U10V3KX-3GP

C231
AU19 C203 74.09198.C7F
VCCA_SM
AW18 74.09091.G3F

A SM
VCCA_SM
AU18 DY

2
VCCA_SM
AW16
FCM1608KF-1-GP 24mA AU16
VCCA_SM
VCCA_SM
1 2 M_VCCA_HPLL AT16 VCCA_SM
SC4D7U6D3V3KX-GP

L3 AR16 VCCA_SM
1

68.00217.161 C145 C153 AU15

SCD1U10V2KX-4GP VCCA_SM 1D5V_S3
2ND = 68.00248.061 AT15 VCCA_SM 200mA
AR15
2

VCCA_SM
AW14 VCCA_SM VCC_AXF M25
N24

AXF
VCC_AXF

SCD1U10V2KX-4GP
FCM1608KF-1-GP AT24 M23 C219 C180
139.2mA VCCA_SM_NCTF VCC_AXF

1
C503
1 2 M_VCCA_MPLL AR24 1 R205 2 1D5V_SM_CK_R 2 1
VCCA_SM_NCTF
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
L17 AT22 1R2F-GP DY
VCCA_SM_NCTF
1

68.00217.161 C466 C477 AR22

DY

2
SCD1U10V2KX-4GP VCCA_SM_NCTF SC10U6D3V5MX-3GP
2ND = 68.00248.061 AT21 VCCA_SM_NCTF
DY AR21 BK24
2

VCCA_SM_NCTF VCC_SM_CK
AT19 BL23

SM CK
VCCA_SM_NCTF VCC_SM_CK
120ohm 100MHz AR19 VCCA_SM_NCTF VCC_SM_CK BJ23
1D8V_NB_S0
AT18 VCCA_SM_NCTF VCC_SM_CK BK22
AR18
1D05V_S0 1D05V_S0 VCCA_SM_NCTF 100mA
C223

1
3D3V_HV_S0

C224
SC1KP50V2KX-1GP
L5 VCC_TX_LVDS T41

SC10U6D3V5MX-3GP
C186 AU27 VCCA_SM_CK 106mA
1

B B
SC2D2U6D3V3MX-1-GP

SCD1U10V2KX-4GP

1 2 1D05V_RUN_PEGPLL C181 C196 AU28 C33

24mA

2
VCCA_SM_CK VCC_HV
SC10U6D3V5MX-3GP

FCM1608CF-221T02-GP AU29 A33

VCCA_SM_CK VCC_HV
220ohm 100MHz AU31

HV
2

VCCA_SM_CK
1

C235 C233 DY AT31

68.00217.521 SCD1U10V2KX-4GP VCCA_SM_CK_NCTF 1D05V_S0
AR31
SC10U6D3V5MX-3GP

2ND = 68.00119.111 VCCA_SM_CK_NCTF

AT29 AB44
1782mA
2

VCCA_SM_CK_NCTF VCC_PEG
AR29 VCCA_SM_CK_NCTF VCC_PEG Y44

SC4D7U6D3V3KX-GP
AT28 AC43 C188 C208

PEG
VCCA_SM_CK_NCTF VCC_PEG

1
AR28 AA43 C189
VCCA_SM_CK_NCTF VCC_PEG

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
DY AT27 VCCA_SM_CK_NCTF
AR27

2
1D5V_S0 VCCA_SM_CK_NCTF

VCC_DMI AM44
1D05V_SUS_MCH_PLL2 AN43 DY 1D05V_S0
VCC_DMI
AL43
58.7mA 456mA

DMI
1D5VRUN_TVDAC VCC_DMI
AH12 VCCD_HPLL
SCD1U10V2KX-4GP

157.2mA
1

1
SCD1U10V2KX-4GP
C215 C214 1D05V_RUN_PEGPLL AE43 C185

ST150U6D3VBM-GP
VCCD_PEG_PLL
1
SCD022U16V2KX-3GP

SCD1U10V2KX-4GP

TC9
C154
1

C226 K14 VTTLF1

VTTLF
2

2
VTTLF
SCD1U10V2KX-4GP

M46 Y12 VTTLF2

50mA
2

VCCD_LVDS VTTLF
LVDS

L45 P2 VTTLF3
2

VCCD_LVDS VTTLF
DY

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP
1 1 1

C478

C152

C157
CANTIGA-GS-GP-NF
L4
1 2 1D5VRUN_QDAC 1D8V_NB_S0 2 2 2
A PBY160808T-181Y-GP A
68.00206.041
1

2ND = 68.00214.101 C194 C195 1D05V_S0

1
SCD01U16V2KX-3GP

SCD1U10V2KX-4GP

C232 D11
60.3mA 3D3V_S0 3D3V_HV_S0 Wistron Corporation
SCD1U10V2KX-4GP

1 BAT54-7-F-GP
R213 R212
2

180ohm 100MHz 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2

DY 2 1D05V_S0_SD 2 1 1 2 Taipei Hsien 221, Taiwan, R.O.C.

SCD1U10V2KX-4GP
1 Title

C505
3 10R2F-L-GP 0R0603-PAD
DY Cantiga (5 of 6)
2

Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 11 of 48
5 4 3 2 1
 5 4 3 2 1

NB1J 10 OF 10
NB1I 9 OF 10
AN25 VSS VSS AM8
BA55 VSS VSS C43 AG25 VSS VSS AK8
AU55 VSS VSS A43 AE25 VSS VSS AH8
AN55 VSS VSS BD42 AA25 VSS VSS AF8
AJ55 VSS VSS H42 Y25 VSS VSS AD8
AE55 VSS VSS BG41 E25 VSS VSS AB8
AA55 VSS VSS AY41 A25 VSS VSS Y8
U55 VSS VSS AU41 BD24 VSS VSS V8
N55 VSS VSS AM41 AN24 VSS VSS P8
BD54 VSS VSS AL41 AL24 VSS VSS M8
BG53 VSS VSS AG41 H24 VSS VSS K8
D AJ53 VSS VSS AE41 BG23 VSS VSS H8 D
AE53 VSS VSS AA41 AY23 VSS VSS BJ7
AA53 VSS VSS R41 E23 VSS VSS E7
U53 VSS VSS M41 BD22 VSS VSS BF6
N53 VSS VSS E41 BB22 VSS VSS BC5
J53 VSS VSS BD40 AN22 VSS VSS BA5
G53 VSS VSS AU40 Y22 VSS VSS AW5
E53 VSS VSS AR40 W22 VSS VSS AU5
K52 VSS VSS AN40 H22 VSS VSS AR5
BG51 VSS VSS W40 BL21 VSS VSS AN5
BA51 VSS VSS U40 BG21 VSS VSS AL5
AW51 VSS VSS T40 AY21 VSS VSS AJ5
AU51 VSS VSS R40 AN21 VSS VSS AG5
AR51 VSS VSS K40 AG21 VSS VSS AE5
AN51 VSS VSS H40 AE21 VSS VSS AC5
AL51 VSS VSS BL39 M21 VSS VSS AA5
AJ51 VSS VSS BG39 E21 VSS VSS W5
AG51 VSS VSS BA39 A21 VSS VSS U5
AE51 VSS VSS E39 BD20 VSS VSS N5
AC51 C39 H20 L5
AA51
W51
VSS
VSS
VSS
VSS
VSS
VSS
A39
BD38
BG19
AY19
VSS
VSS
VSS
VSS VSS
VSS
VSS
J5
G5
U51 AU38 M19 C5
R51
N51
VSS
VSS
VSS
VSS VSS
VSS
VSS
H38
BG37
E19
BD18
VSS
VSS
VSS
VSS
VSS
VSS
BH4
BE3
L51 VSS VSS AU37 N18 VSS VSS U3
J51 VSS VSS M37 H18 VSS VSS E3
G51 VSS VSS E37 BL17 VSS VSS BC1
C51 VSS VSS BD36 BG17 VSS VSS AW1
C BK50 AW36 AY17 AR1 C
VSS VSS VSS VSS
AM50 VSS VSS H36 M17 VSS VSS AL1
K50 VSS VSS BL35 E17 VSS VSS AG1
BG49 VSS VSS BG35 A17 VSS VSS AC1
E49 VSS VSS AY35 BD16 VSS VSS W1
C49 VSS VSS AU35 AN16 VSS VSS N1
BD48 VSS VSS AL35 AG16 VSS VSS J1
BB48 VSS VSS AG35 AE16 VSS VSS AU43
AY48 VSS VSS AE35 Y16 VSS VSS BB42
AV48 VSS VSS AA35 W16 VSS VSS AW38
AT48 VSS VSS Y35 N16 VSS VSS BA35
AP48 VSS VSS M35 H16 VSS VSS L29
AM48 VSS VSS E35 BG15 VSS VSS N28
AK48 VSS VSS A35 AY15 VSS VSS N22
AH48 VSS VSS BD34 AN15 VSS VSS N20
AF48 VSS VSS AU34 AD15 VSS VSS N14
AD48 VSS VSS AN34 AC15 VSS VSS AL13
AB48 VSS VSS H34 R15 VSS VSS B10
Y48 VSS VSS BL33 M15 VSS VSS AN13
V48 VSS VSS BG33 E15 VSS
T48 VSS VSS AY33 BD14 VSS VSS N42
P48 VSS VSS E33 H14 VSS VSS N40
M48 VSS VSS BD32 BL13 VSS VSS N38
K48 VSS VSS AU32 BG13 VSS VSS M39
H48 VSS VSS AN32 AY13 VSS
BL47 VSS VSS AG32 AU13 VSS
BG47 VSS VSS AC32 AR13 VSS VSS_NCTF AJ38
E47 VSS VSS Y32 AJ13 VSS VSS_NCTF AH38
C47 VSS VSS H32 AC13 VSS VSS_NCTF AD38
B B
A47 VSS VSS B32 AA13 VSS VSS_NCTF AC38
BD46 VSS VSS BJ31 W13 VSS VSS_NCTF T35
AY46 BG31 U13 R35

VSS NCTF
VSS VSS VSS VSS_NCTF
AM46 VSS VSS AY31 M13 VSS VSS_NCTF AT32
AK46 VSS VSS AN31 E13 VSS VSS_NCTF AR32
AH46 VSS VSS M31 A13 VSS VSS_NCTF U32
BG45 VSS VSS E31 BD12 VSS VSS_NCTF R32
AE45 VSS VSS N30 AV12 VSS VSS_NCTF T28
AC45 VSS VSS H30 AP12 VSS VSS_NCTF R28
AA45 VSS VSS AN29 AM12 VSS VSS_NCTF AT25
W45 VSS VSS AJ29 AK12 VSS VSS_NCTF AR25
R45 VSS VSS M29 AB12 VSS VSS_NCTF T24
N45 VSS VSS A29 V12 VSS VSS_NCTF R24
E45 VSS VSS AW28 P12 VSS VSS_NCTF AN19
BD44 VSS VSS AN28 H12 VSS VSS_NCTF AJ19
BB44 VSS VSS AD28 BG11 VSS VSS_NCTF AA19
AV44 VSS VSS AC28 AG11 VSS VSS_NCTF Y19
AK44 VSS VSS Y28 E11 VSS VSS_NCTF T19
AH44 VSS VSS W28 BD10 VSS VSS_NCTF R19
AF44 VSS VSS H28 AY10 VSS VSS_NCTF AN18
AD44 VSS VSS F28 AP10 VSS
K44 VSS VSS AN27 H10 VSS
H44 VSS VSS AJ27 BL9 VSS RSVD#B55 B55
BL43 M27 BG9 VSS SCB B2 VSS_SCB#B2 1 TP73 TPAD14-GP
VSS VSS VSS VSS_SCB
BG43 VSS VSS BF26 E9 VSS
BL55,BL1,A55,D1,A4

AY43 VSS VSS BD26 A9 VSS NCTF_VSS_SCB#BL55 TP78 TPAD14-GP

NCTF TEST PIN:

AR43 VSS VSS N26 BD8 VSS NCTF_VSS_SCB#BL55 BL55 1

W43 H26 BB8 BL1 NCTF_VSS_SCB#BL1 1 TP76 TPAD14-GP
VSS VSS VSS NCTF_VSS_SCB#BL1 NCTF_VSS_SCB#A55 TP79 TPAD14-GP
A R43 VSS VSS BJ25 AY8 VSS NCTF_VSS_SCB#A55 A55 1 A
M43 AY25 AV8 D1 NCTF_VSS_SCB#D1 1 TP72 TPAD14-GP
VSS VSS VSS NCTF_VSS_SCB#D1 NCTF_VSS_SCB#A4 TP75 TPAD14-GP
E43 VSS VSS AU25 AT8 VSS NCTF_VSS_SCB#A4 A4 1
AP8 VSS Wistron Corporation
CANTIGA-GS-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CANTIGA-GS-GP-NF Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (6 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 12 of 48
5 4 3 2 1
 5 4 3 2 1

C133 1 2 SC6P50V2CN-1GP RTC_X1

3D3V_AUX_S5

-1

4
D10
-1

1
BAS16-1-GP X1
83.00016.B11 D20 X-32D768KHZ-34GPU R45
2 RTC_AUX_S5 82.30001.661 10MR2J-L-GP
2ND = 83.00016.K11
82.30001.B21
3
3RD = 83.00016.F11

SC1U16V3ZY-GP
3

2
1
D D
1 C498
RTC_BAT_R

2
SB1A 1 OF 6
BAS40CW -GP C130 1 2 SC6P50V2CN-1GP
F25 RTCX1 FWH0/LAD0 H3 LPC_LAD0 28,29
RTC_X2 G25 J3
83.00040.E81 SRN20KJ-GP-U RTCX2 FWH1/LAD1 LPC_LAD1 28,29 1D05V_S0 1D05V_S0
FWH2/LAD2 K5 LPC_LAD2 28,29
1

2 3 RTC_RST# G24 L3
RTCRST# FWH3/LAD3 LPC_LAD3 28,29
R340 1 4 SRTC_RST# C24

RTC
LPC
SRTCRST#

1
1KR2J-1-GP R197 1 2 INTRUDER# C23 J2 LPC_LFRAME# 28,29
RN4 1MR2J-1-GP INTRUDER# FWH4/LFRAME# R36 R171

1
G75 C140 C149 INTVRMEN E25 H1 LDRQ0# 1 TP15 TPAD14-GP 56R2F-1-GP 56R2F-1-GP
2

INTVRMEN LDRQ0#

SC1U10V3KX-3GP

SC1U10V3KX-3GP
1 2 RTC_BAT_D D25 J1 3D3V_LDRQ1_S0 1 TP14 TPAD14-GP
24,28 RTC_BAT
R199 1KR2J-1-GP LAN100_SLP LDRQ1#/GPIO23 1D05V_S0 DY DY

GAP-OPEN

2
G22 GLAN_CLK A20GATE N3 KA20GATE 28
AB23 H_A20M# 4 H_DPRSTP#

1
TPAD14-GP TP19 A20M#
1ICH9_LAN_RSTSYNC D14 LAN_RSTSYNC
H_PW RGD
AE23 H_DPRSTP# H_DPRSTP# 4,8,34
DPRSTP#
A14 AE24 H_DPSLP# 4 RN14

LAN / GLAN
LAN_RXD0 DPSLP#
D12 LAN_RXD1 1 4
B14 AD25 H_FERR#_R 2 3 H_FERR# 4
LAN_RXD2 FERR#
GLAN_COMP place D13 LAN_TXD0 CPUPWRGD AE22 H_PW RGD H_PW RGD 4,32 SRN56J-4-GP
within 500 mil of ICH9M C13 LAN_TXD1
RTC_AUX_S5 A13 AD23 H_IGNNE# 4
LAN_TXD2 IGNNE#
integrated VccSus1_05,VccSus1_5,VccCL1_5

CPU
1D5V_S0 HDMI_EN D15 AE21
GPIO56 INIT# H_INIT# 4
1

INTVRMEN High=Enable Low=Disable INTR AD24 H_INTR 4

C R195 1 2 GLAN_COMP H22 L1 KBRCIN# 28
C
R189 24D9R2F-L-GP GLAN_COMPI RCIN#
330KR2F-L-GP integrated VccLan1_05VccCL1_05 H21 GLAN_COMPO
AD21 H_NMI 4 1D05V_S0
NMI R179
LAN100_SLP High=Enable Low=Disable ACZ_BIT_CLK AE7 AC21 H_SMI# 4
2

ACZ_SYNC_R HDA_BIT_CLK SMI#

AB7 HDA_SYNC 1 2
INTVRMEN AC25 H_STPCLK# 4
ACZ_RST#_R STPCLK#
AA7 HDA_RST# 56R2F-1-GP
AC23 H_THERMTRIP_R 1 2 PM_THRMTRIP-A# 4,8,32
THRMTRIP# R183 54D9R2F-L1-GP
22 ACZ_SDATAIN0 AB6 HDA_SDIN0
TPAD14-GP TP11 1 ACZ_SDIN1 AE6 AC22 ICH_TP11 1 TP57 TPAD14-GP
TPAD14-GP TP56 ACZ_SDIN2 HDA_SDIN1 TP11
1 AC6

IHDA
TPAD14-GP TP70 ACZ_SDIN3 HDA_SDIN2
1 AA5 HDA_SDIN3
AD12 SATA_RXN4_C SCD01U50V2KX-1GP 2 1 C93 SATA_RXN4 24
HDMI_EN ACZ_SDATAOUT_R SATA4RXN SATA_RXP4_C SCD01U50V2KX-1GP C92
AC7 AE12 2 1 SATA_RXP4 24
TPAD14-GP TP53 1 HDA_DOCK_EN# AD8
HDA_SDOUT

HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN
SATA4TXP
AB12
AA12
SATA_TXN4_C
SATA_TXP4_C
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
2
2
1
1
C94
C95
SATA_TXN4 24
SATA_TXP4 24
ODD
1

TPAD14-GP TP67 1 HDA_DOCK_RST# AB8

R200 HDA_DOCK_RST#/GPIO34
HDMI_DIS SATA5RXN AC11
10KR2J-3-GP 31 MEDIA_LED# AC9 SATALED# SATA5RXP AD11
SATA5TXN AB10
21 SATA_RXN0 C87 1 2 SCD01U50V2KX-1GP SATA_RXN0_C AE14 AA10
2

C88 SCD01U50V2KX-1GP SATA_RXP0_C SATA0RXN SATA5TXP

21 SATA_RXP0 1 2 AD14
SSD SATA0RXP

SATA
21 SATA_TXN0 C90 1 2 SCD01U50V2KX-1GP SATA_TXN0_C AC15 AC16 CLK_PCIE_SATA# 3
C89 SCD01U50V2KX-1GP SATA_TXP0_C SATA0TXN SATA_CLKN
21 SATA_TXP0 1 2 AD15 SATA0TXP SATA_CLKP AB16 CLK_PCIE_SATA 3

20 SATA_RXN1 C108 1 2 SCD01U50V2KX-1GP SATA_RXN1_C AD13 AD10 SATARBIAS

C109 SCD01U50V2KX-1GP SATA_RXP1_C SATA1RXN SATARBIAS#
20 SATA_RXP1 1 2 AC13 AE10 2 1

B
R172 HDD 20
20
SATA_TXN1
SATA_TXP1
C111
C110
1
1
2
2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_TXN1_C
SATA_TXP1_C
AA14
AB14
SATA1RXP
SATA1TXN
SATA1TXP
SATARBIAS 24D9R2F-L-GP R32
B
3D3V_S0 1 2 MEDIA_LED# Place within 500 mils of
ICH9 ball
10KR2J-3-GP ICH9M-1-GP

RN2
22 ACZ_RST# 1 8 ACZ_RST#_R
22 ACZ_SDATAOUT 2 7 ACZ_SDATAOUT_R
22 ACZ_SYNC 3 6 ACZ_SYNC_R
22 ACZ_BITCLK 4 5 ACZ_BIT_CLK

SRN0J-7-GP
1

C96
SCD1U10V2KX-4GP

DY
2

DIS
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH9-M (1 of 4)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 13 of 48

5 4 3 2 1
 5 4 3 2 1
SB1C 3 OF 6

SMB
SB1B 2 OF 6 3D3V_S5 C18 AE19 SATA0GP 2 3
16 SMB_CLK SMBCLK SATA0GP/GPIO21
C15 AA18 SATA1GP 1 4
RN19 16 SMB_DATA SMBDATA SATA1GP/GPIO19
A11 G4 PCI_REQ#0 SMB_LINK_ALERT# B21 AE20 DIS_EN 19,20,41

SATA
AD0 REQ0# LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

GPIO
SMLINK0
B12
A10
AD1 PCI GNT0# E1
A9 PCI_REQ#1
1
2
4
3 SMLINK1
E18
A24
SMLINK0 SATA5GP/GPIO37 AA20 G_VCORE_PGOOD 39,40,42 RN1
SRN10KJ-5-GP
AD2 REQ1#/GPIO50 SMLINK1
C12 AD3 GNT1#/GPIO51 E12 CLK14 K1 CLK_ICH14 3
A8 B11 PCI_REQ#2 1 PM_RI# C20 AB5 CLK48_ICH 3

Clocks
AD4 REQ2#/GPIO52 TP_GPIO1 SRN10KJ-5-GP RI# CLK48
A12 AD5 GNT2#/GPIO53 C10
E10 D6 PCI_REQ#3 TPAD14-GP T5 R3
AD6 REQ3#/GPIO54 DBRESET# SUS_STAT#/LPCPD# SUSCLK
C11 AD7 GNT3#/GPIO55 C6 C25 SYS_RESET#
B9 AD8
BOOT BIOS Strap SLP_S3# D18 PM_SLP_S3# 28,32,36,39,40
D8 AD9 C/BE0# D10 8 PM_SYNC# L2 PMSYNC#/GPIO0 SLP_S4# B20 PM_SLP_S4# 28,32,35,37
PCI_GNT#0 and SPI_CS1# A4 A5 PCI_GNT#0 SPI_CS#1 BOOT BIOS Location D16 PM_SLP_S5# 1 TP74
D AD10 C/BE1# SMB_ALERT# SLP_S5# TPAD14-GP D
have weak internal Pull up E8 AD11 C/BE2# E6 A23 SMBALERT#/GPIO11
A3 C9 0 1 SPI E14 S4_STATE# 1 TP17
AD12 C/BE3# S4_STATE#/GPIO26 TPAD14-GP
D9 AD13 1 0 PCI 3 PM_STPPCI# B15 STP_PCI#/GPIO15

SYS GPIO
C8 C3 PCI_IRDY# 1 1 LPC(Default) A20 D23
AD14 IRDY# 3 PM_STPCPU# STP_CPU#/GPIO25 PW ROK PWROK 8,32
C2 AD15 PAR B1 A16 swap override strap
D7 T3 M5 M1 PM_DPRSLPVR_1 R42 2 100R2J-2-GP
1
AD16 PCIRST# 28 PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR 8,34
B3 A7 PCI_DEVSEL# low = A16 swap override enable R39 1 2DY
AD17 DEVSEL#

Power MGT
D11 D4 PCI_PERR# PCI_GNT#3 high = default 25 PCIE_WAKE# C21 C16 PM_BATLOW#_R 100KR2J-1-GP
AD18 PERR# PCI_LOCK# W AKE# BATLOW #
B6 C5 28 INT_SERIRQ L4 D1
AD19 PLOCK# PCI_SERR# THRM# AD20 SERIRQ PWRBTN#_ICH BAS16-1-GP
D5 AD20 SERR# H5 1 THRM# PW RBTN# U4 1 PM_PWRBTN# 28
D3 A6 PCI_STOP# 3D3V_S0 TPAD14-GP TP58
AD21 STOP# PCI_TRDY# LAN_RST#_SB
F4 AD22 TRDY# A2 28,32,34 VR_PWRGD B24 VRMPW RGD LAN_RST# D22 3
E3 B8 PCI_FRAME# 83.00016.B11
AD23 FRAME# RSMRST#_SB 2ND = 83.00016.K11
E4 AD24 A19 TP12 RSMRST# D19 2

1
B2 A21 PLT_RST1# 3RD = 83.00016.F11
AD25 PLTRST# R167
C4 AD26 PCICLK B5 AE16 GPIO1 CK_PW RGD U1 CLK_PWRGD 3

10KR2J-3-GP
C1 T1 1 2DY AE18 3D3V_S0
AD27 PME# 28 EC_TMR GPIO6
D1 C501 SC100P50V2JN-3GP 28 ECSCI#_1 AD18 T4 PWROK 8,32
AD28 GPIO7 CLPW ROK
E2 28 ECSWI# B25

2
AD29 GPIO8 PM_SLP_M# 1 TP21
J4 AD30 PCLK_ICH 3 C14 GPIO12 SLP_M# B23

1
H2 D20 TPAD14-GP
AD31 PSW_CLR# GPIO13 R193
AE17 GPIO17 CL_CLK0 C22 CL_CLK0 8
TPAD14-GP TP89 3K24R2F-GP
INT_PIRQA# F1
Interrupt I/F G3 INT_PIRQE# TPAD14-GP TP60
1
1ICH9_GPIO20
K3
AC8
GPIO18 CL_CLK1 A18
INT_PIRQB# PIRQA# PIRQE#/GPIO2 INT_PIRQF# GPIO20
F5 G1 TPAD14-GP TP6 1CLK_SEL1 AC19 E22 CL_DATA0 8

2
PIRQB# PIRQF#/GPIO3 SCLOCK/GPIO22 CL_DATA0

2
INT_PIRQC# INT_PIRQG# MXM_RST#

Controller Link
F2 F3 G74 D17 B18

GPIO
PIRQC# PIRQG#/GPIO4 42 MXM_RST# GPIO27 CL_DATA1
INT_PIRQD# C7 H4 INT_PIRQH# ATI_PWR_ON# E20
PIRQD# PIRQH#/GPIO5 SATACLKREQ# GPIO28 CL_VREF0_ICH
3 SATACLKREQ# M4 SATACLKREQ#/GPIO35 CL_VREF0 F21

GAP-OPEN
1PCB_VER0_SB AB18 SLOAD/GPIO38 CL_VREF1 A17

1
ICH9M-1-GP TPAD14-GP TP65 1PCB_VER1_SB AC18

1
C TPAD14-GP TP5 MIC_SEL_1 SDATAOUT0/GPIO39 R192 C
AB19 SDATAOUT1/GPIO48 CL_RST0# C17 CL_RST#0 8

SCD1U10V2KX-4GP
RP3 RP2 AC20 B17 453R2F-1-GP
GPIO49 CL_RST1#

C488
1 10 PCI_REQ#3 1 10 NO_iTPM A16
3D3V_S0 3D3V_S0 GPIO57/CLGPIO5
PCI_STOP# 2 9 PCI_LOCK# PCI_PERR# 2 9 PCI_TRDY# A22 ICH_GPIO24 1 TP22

2
PCI_FRAME# PCI_DEVSEL# INT_PIRQB# PCI_IRDY# MEM_LED/GPIO24
3 8 3 8 22 ACZ_SPKR K4 E16 SUSPWRACK TPAD14-GP

2
PCI_REQ#1 INT_PIRQD# INT_PIRQG# PCI_SERR# SPKR GPIO10/SUS_PW R_ACK
4 7 4 7 GPIO49 should be pulled down to 8 MCH_ICH_SYNC# AB20 MCH_SYNC# GPIO14/AC_PRESENT A15 AC_PRESENT
5 6 PCI_REQ#2 5 6 PCI_REQ#0 GND only when using Teenah. When 1 ICH_TP3 C19 D21 ICH_GPIO91 TP23
3D3V_S0 3D3V_S0 TP3 W OL_EN/GPIO9

MISC
using Cantiga, this ball should TPAD14-GPTP20
TPAD14-GP TP20 1 ICH_TP8 AB17 TPAD14-GP
TP8

100KR2J-1-GP
SRN8K2J-2-GP-U SRN8K2J-2-GP-U TPAD14-GP TP66
TPAD14-GPTP66 1 ICH_TP9 AC17 R203
be left as No Connect. TPAD14-GP TP64
TPAD14-GPTP64 ICH_TP10 AD17 TP9
1 TP10
RP1 TPAD14-GP TP59
TPAD14-GPTP59
ECSCI#_1 1 10 3D3V_S0 3D3V_S0
INT_PIRQH# 2 9 INT_PIRQC# ICH9M-1-GP
-1

2
INT_PIRQF# 3 8 INT_PIRQE#
RN18
PM_CLKRUN# 4 7 INT_PIRQA# LAN_RST#_SB
5 6 INT_SERIRQ 1 4 MXM_RST# RP4 3D3V_S5
3D3V_S0 3D3V_S5

1
SB1D 4 OF 6 2 3 ATI_PWR_ON ECSWI# 1 10
SRN8K2J-2-GP-U
ATI_PWR_ON 39,40 PM_RI# 2 9 DBRESET# SB R343
100R2F-L1-GP-U
25 PCIE_RXN1 T25 V25 DMI_RXN0 8 3 8 SMB_ALERT#
PERN1 DMI0RXN SRN10KJ-5-GP PCIE_WAKE# SMB_LINK_ALERT#
Direct Media Interface

25 PCIE_RXP1 T24 PERP1 DMI0RXP V24 DMI_RXP0 8 4 7

C124 SCD1U10V2KX-5GP 2 1 TXN1 R24 U24 5 6 SUSPWRACK 3D3V_S0
25 PCIE_TXN1 DMI_TXN0 8 3D3V_S5

2
C123 SCD1U10V2KX-5GP 2 TXP1 PETN1 DMI0TXN
25 PCIE_TXP1 1 R23 PETP1 DMI0TXP U23 DMI_TXP0 8 R338
LAN P25 W 23
SRN10KJ-L3-GP
1 2 DIS_EN
25
25
PCIE_RXN2
PCIE_RXP2 P24
PERN2
PERP2
DMI1RXN
DMI1RXP W 24
DMI_RXN1
DMI_RXP1 8
8
-1 R187
CHANGE to GPO28(original is GPIO18)
C128 SCD1U10V2KX-5GP 2 1 TXN2 P21 V21
25 PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 8 3D3V_S5 10KR2J-3-GP
25 PCIE_TXP2 C126 SCD1U10V2KX-5GP 2 1 TXP2 P22 V22 DMI_TXP1 8 1 2 ATI_PWR_ON# ATI_PWR_ON# 40
PETP2 DMI1TXP
MINICARD1 N23 Y24 PM_BATLOW#_R 1 2
PERN3 DMI2RXN DMI_RXN2 8 10KR2J-3-GP
N24 Y25 R201 8K2R2J-3-GP
PCI-Express

PERP3 DMI2RXP DMI_RXP2 8

B M21 Y21 DMI_TXN2 8 DY PLT_RST1# 8,22,24,25,28,29,42
B
PETN3 DMI2TXN
M22 PETP3 DMI2TXP Y22 DMI_TXP2 8

1
No Reboot Strap
M25 AB24 DMI_RXN3 8 SPKR LOW = Defaule R202
3D3V_S5 PERN4 DMI3RXN 1D5V_S0 100KR2J-1-GP
RN3 M24 PERP4 DMI3RXP AB25 DMI_RXP3 8 High=No Reboot
L24 PETN4 DMI3TXN AA23 DMI_TXN3 8
5 4 USB_OC#0 L23 AA24 DMI_TXP3 8

2
PETP4 DMI3TXP
1

6 3
7 2 USB_OC#3~11 K24 T21 R35 3D3V_S0 3D3V_S5
PERN5 DMI_CLKN CLK_PCIE_ICH# 3
8 1 USB_OC#1 K25 T22 24D9R2F-L-GP
PERP5 DMI_CLKP CLK_PCIE_ICH 3
K21 MIC_SEL_1 1 2
PETN5 R170 10KR2J-3-GP
K22 AB21 RN21
2

SRN10KJ-6-GP PETP5 DMI_ZCOMP DMI_IRCOMP_R ACZ_SPKR AC_PRESENT

DMI_IRCOMP AB22 1 2 1 8
H24 R44 DY 1KR2J-1-GP 2 7
PERN6/GLAN_RXN THRM# NO_iTPM
H25 PERP6/GLAN_RXP USBP0N AE2 USBPN0 25 USB 1 2 3 6
J24 AD1 R169 10KR2J-3-GP 4 5 PWROK
PETN6/GLAN_TXN USBP0P USBPP0 25
J23 PETP6/GLAN_TXP USBP1N AD3 USBPN1 20 Pair Device
AD4 USBPP1 20 SRN10KJ-6-GP
USBP1P
E24 SPI_CLK USBP2N AC2 USBPN2 26 0 USB2
E23 AC3 USBPP2 26 D2
SPI_CS0# USBP2P RSMRST#_SB
F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AC5 USBPN3 25 1 USB3 1
USBP3P AB4 USBPP3 25
F22 SPI_MOSI USBP4N AB2 USBPN4 19 2 USB4 28 RSMRST#_KBC 3

1
SPI

G23 AB1 R46

SPI_MISO USBP4P USBPP4 19
USBP5N AA3 3 WiMAX 2

100KR2J-1-GP
25 USB_OC#0 USB_OC#0 P4 AA2
USB_OC#1 OC0#/GPIO59 USBP5P BAS16-1-GP
20 USB_OC#1 N4 OC1#/GPIO40 USBP6N Y1 4 WEBCAM
83.00016.B11
N1 USB Y2

2
OC2#/GPIO41 USBP6P 2ND = 83.00016.K11
P5 OC3#/GPIO42 USBP7N W2 USBPN7 24 5 NC
P1 W3 USBPP7 24 3RD = 83.00016.F11
A OC4#/GPIO43 USBP7P A
P2 OC5#/GPIO29 USBP8N V1 6 NC DIS
M3 OC6#/GPIO30 USBP8P V2
M2 OC7#/GPIO31 USBP9N Y5 USBPN9 20 7 BLUETOOTH
USB_OC#3~11 P3 Y4
R1
OC8#/GPIO44
OC9#/GPIO45
USBP9P
USBP10N U3
USBPP9 20
USBPN10 25 8 NC Wistron Corporation
R4 U2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
OC10#/GPIO46 USBP10P USBPP10 25
R2 V4 USBPN11 24 9 USB1 Taipei Hsien 221, Taiwan, R.O.C.
OC11#/GPIO47 USBP11N
These R need close SB USBP11P V5 USBPP11 24
within 600 mils USB_RBIAS_PN AE5 10 MINIC2 Title
USBRBIAS
2 1 AD5
R177 22D6R2F-L1-GP USBRBIAS#
11 Cardreader ICH9-M (2 of 4)
Size Document Number Rev
ICH9M-1-GP -1
JM41_Discrete
Date: Monday, April 06, 2009 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1
SB1F 6 OF 6
RTC_AUX_S5
6uA in G3 G17
VCCRTC VCC1_05
L11 Layout Note: Place near ICH9M
L12 1D05V_S0
V5REF_S0 G7
V5REF
VCC1_05
VCC1_05
L13 1.13A

1
C496 L14
VCC1_05

SCD1U10V2KX-4GP
V5REF_S5 U7 L15
V5REF_SUS VCC1_05

1
M11 C474 C462 C467 C473 C465

2
VCC1_05

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC39P50V2JN-1GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
J19 VCC1_5_B VCC1_05 M15 DY
K18 N11

2
VCC1_5_B VCC1_05
K19 N15
657mA L18
VCC1_5_B
VCC1_5_B
VCC1_05
VCC1_05 P11
1D5V_S0 L19 P15 DY
VCC1_5_B VCC1_05
M18 VCC1_5_B VCC1_05 R11
M19 VCC1_5_B VCC1_05 R12
D N18 R13 D
C470 VCC1_5_B VCC1_05
N19 R14
VCC1_5_B VCC1_05 23mA

1
C469 C468 TC4 P18 R15 L2 1D5V_S0
VCC1_5_B VCC1_05

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC1U10V3KX-3GP
R18 1D5V_DMIPLL_ICH_S0 1 2
VCC1_5_B

ST220U2D5VDM-13GP
T18 IND-1D2UH-7-GP

2
VCC1_5_B

1
T19 68.1R220.10B
VCC1_5_B C118 C120
U18 68.1R220.10D

CORE
VCC1_5_B SCD01U16V2KX-3GP SC10U6D3V5MX-3GP
DY U19

2
VCC1_5_B

1D05V_S0

C460 50mA

1
SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP
P19 C451
VCCDMIPLL
*Within a given well, 5VREF needs to be up before the
corresponding 3.3V rail T17

2
VCC_DMI 1D05V_S0
VCC_DMI U17

V16 1mA
47mA V_CPU_IO
V_CPU_IO U16
3D3V_S0 5V_S0 1D5V_S0 1D5V_APLL_S0 3D3V_S0
L1

1
V18 C449 C450
VCC3_3

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
1 2 C458 C445 C459
A

VCCA3GP
C68 AE9 SCD1U10V2KX-4GP SC1U10V2KX-1GP

2
VCC3_3

SC1U10V3KX-3GP
D9 R191 IND-10UH-66-GP SCD1U10V2KX-4GP

2
RB751V-40-2-GP 100R2J-2-GP 68.1001D.10E C65
2mA

SC10U6D3V5MX-3GP
83.R2004.B8F 3D3V_S0

2
83.R0304.A8F AA9
VCC3_3=278mA
K

V5REF_S0 VCC3_3
VCC3_3 V14

1
SCD1U16V2KX-3GP

C C491 W14 C441 C

VCC3_3
1

3D3V_S0
SCD1U10V2KX-4GP

2
G8 1D5V_S0

VCCP_CORE
2

VCC3_3

1
H7 C482 C489 C490
VCC3_3 32mA

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
VCC3_3 H8

1
Layout Note: C444

2
Place near ICH9 3D3V_S5 5V_S5 SCD1U10V2KX-4GP

2
A

D8 R184 AD7

PCI
RB751V-40-2-GP 100R2J-2-GP VCCHDA
2mA 83.R2004.B8F 1D5V_S0 W17 V10 VCCSUSHDA_ICH 32mA
83.R0304.A8F SATA+USB=1.56A VCCSATAPLL VCCSUSHDA
K

1
V5REF_S5 U13 T7 Vcc Sus 1_05 C461
VCC1_5_A VCCSUS1_05

1
SCD1U16V2KX-3GP

SCD1U10V2KX-4GP
C454 V13 H15 C479
VCC1_5_A VCCSUS1_05
1

W13 SCD1U10V2KX-4GP

2
VCC1_5_A

ARX
C447 C448 H16

2
SC1U10V2KX-1GP SC1U10V2KX-1GP VCCSUS1_5
2

V7
VCCSUS1_5

1
C452
SCD1U10V2KX-4GP
G14 3D3V_S5

2
VCCSUS3_3
U12 G15
VCC1_5_A VCCSUS3_3
V12 H14
VCC1_5_A VCCSUS3_3
W12
VCC1_5_A

1
ATX
C464 C476 C475

VCCPSUS

SCD1U10V2KX-4GP

SC39P50V2JN-1GP

SCD1U10V2KX-4GP
W8

2
VCCSUS3_3
B B
1D5V_S0 J7 DY DY
VCCSUS3_3
J8
VCCSUS3_3 3D3V_S5
W10 K7
VCC1_5_A VCCSUS3_3
SCD1U10V2KX-4GP

K8
VCCSUS3_3 177mA
1

C492 U15 L7
VCC1_5_A VCCSUS3_3
SCD1U10V2KX-4GP

C483 V15 L8
VCC1_5_A VCCSUS3_3

1
M7 C471 C472
2

VCCSUS3_3

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP
W18 M8 C463
VCC1_5_A VCCSUS3_3 SCD1U10V2KX-4GP
N7

2
VCCSUS3_3
G9 N8
VCC1_5_A VCCSUS3_3
H9 P7
VCCPUSB

VCC1_5_A VCCSUS3_3
P8
VCCSUS3_3
V11
VCC1_5_A
U11
1D5V_S0 VCC1_5_A

USBPLL=10mA U8
VCCUSBPLL VCCCL1_05
G18 VCCCL1D05V_INT_ICH
1

1
C427 C456 C457 T9 H17 VCCCL1D5V_INT_ICH C487
VCC1_5_A VCCCL1_5
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

USB CORE

DY U9
VCC1_5_A

SCD1U10V2KX-5GP
J14
2

2
VCCCL3_3

1
K14
3D3V_S0 VCCCL3_3 3D3V_S0 C494 C495
19mA in S0;78mA in S3/S4/S5 DY

2
SC1U10V2KX-1GP

SCD1U10V2KX-5GP
VCCLAN_1D05V_INT_ICH G11
VCCLAN1_05 18mA
1

C493 H11
VCCLAN1_05
1

C480 C481 SCD1U10V2KX-4GP DY

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY G12
2

1D5V_S0 VCCLAN3_3
H13
2

VCCLAN3_3
A 23mA J17 VCCGLANPLL
A

C485
1

1
SC10U6D3V5MX-3GP

GLAN POWER

C86 H19 VCCGLAN1_5

SC1U10V3KX-3GP

J18 VCCGLAN1_5 Wistron Corporation

2

1D5V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
80mA K16 VCCGLAN3_3 Title
1

3D3V_S0
C446 C484 1mA ICH9M-1-GP ICH9-M (3 of 4)
SC1U10V2KX-1GP SCD1U10V2KX-4GP Size Document Number Rev
2

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 15 of 48
5 4 3 2 1
 A B C D E

SB1E 5 OF 6

B4 VSS VSS U5
B7 VSS VSS U10
B10 VSS VSS W11
B13 VSS VSS U14
B16 VSS VSS W16
B19 VSS VSS U21
B22 VSS VSS U22
D2 VSS VSS U25
D24 VSS VSS V3
E5 VSS VSS V8
E7 VSS VSS V19
4 E9 VSS VSS V23 4
E11 VSS VSS W1
E13 VSS VSS W4
E15 VSS VSS W5
E17 VSS VSS W7
E19 VSS VSS W9
E21 VSS VSS W15
F24 VSS VSS W19
G2 VSS VSS W21
G5 VSS VSS W22
G10 VSS VSS W25
G13 VSS VSS Y3
G16 VSS VSS Y23
G19 VSS VSS AA1
G21 VSS VSS AA4
H10 VSS VSS AA6
H12 VSS VSS AA8
H18 VSS VSS AA11
H23 VSS VSS AA13
J5 VSS VSS AA15
J9 VSS VSS AA16
J10 VSS VSS AA17
J11 VSS VSS AA19
J12 VSS VSS AA21
J13 VSS VSS AA22
J15 VSS VSS AA25
J21 VSS VSS AB3
J22 VSS VSS AB9
J25 VSS VSS AB11
3 K2 AB13 3
VSS VSS
K9 VSS VSS AB15
K10 AC24 3D3V_S5 3D3V_S0
VSS VSS
K11 VSS VSS AC1
K12 VSS VSS AC4
K13 VSS VSS AC10
K15 VSS VSS AC12
K17 VSS VSS AC14

8
7
6
5
K23 VSS VSS AD2
L5 AD6 RN22
VSS VSS
L9 VSS VSS AD9 SRN2K2J-2-GP
L10 VSS VSS AD16
L16 VSS VSS AD19
L17 AD22

1
2
3
4
VSS VSS
L21 VSS VSS AE3
L22 VSS VSS AE4
L25 VSS VSS AE11
M9 VSS VSS AE13
M10 AE15 3D3V_S0
VSS VSS
M12 VSS VSS V17
M13 VSS VSS AE8
M14 VSS VSS V9
M16 VSS VSS J16
M17 VSS
M23 VSS Q10
N2 VSS
N5 VSS 14 SMB_CLK 3 4 SMBC_ICH 3,17,18
N9 VSS
N10 VSS 2 5
2 2
N12 VSS
N13 VSS 1 6
N14 VSS
N16 VSS
N17 2N7002EDW -GP
VSS 14 SMB_DATA
N21 VSS SMBD_ICH 3,17,18
N22 VSS 84.27002.G3F
N25 VSS
P9
P10
VSS
VSS
SMBUS
P12 VSS
P13 VSS
P14 VSS
P16 VSS
P17 VSS
P23 VSS
R5 VSS
R7 VSS
R8 VSS
R9 VSS
R10 VSS
R16 VSS
R17 VSS
R19 VSS
R21 A1 ICH0_NCTF#A1 1 TP18 TPAD14-GP
VSS VSS_NCTF ICH0_NCTF#A25 TP16 TPAD14-GP
R22 VSS VSS_NCTF A25 1
R25 AE1 ICH0_NCTF#AE1 1 TP8 TPAD14-GP
VSS VSS_NCTF ICH0_NCTF#AE25 TP7 TPAD14-GP
T2 VSS VSS_NCTF AE25 1
1 T8 VSS 1
T10 NCTF PIN
VSS
T11 VSS
T12
T13
VSS
VSS
Wistron Corporation
T14 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS Taipei Hsien 221, Taiwan, R.O.C.
T15 VSS
T16 VSS
T23 Title
VSS
ICH9-M (4 of 4)
ICH9M-1-GP Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 16 of 48
A B C D E
 A B C D E

DDR3 SOCKET_1
DM2
9 M_B_A[14..0] M_B_A0 98 NP1
M_B_A1 A0 NP1
4 97 NP2 4
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 9
M_B_A4 A3 RAS#
92 113 M_B_WE# 9
M_B_A5 A4 WE#
91 115 M_B_CAS# 9
M_B_A6 A5 CAS#
90
M_B_A7 A6
86 114 M_CS2# 8
M_B_A8 A7 CS0#
89 121 M_CS3# 8
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_CKE2 8
M_B_A11 A10/AP CKE0
84 74 M_CKE3 8
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_CLK_DDR2 8
M_B_A14 A13 CK0
80 103 M_CLK_DDR#2 8
A14 CK0#
TPAD14-GP TP25 1M_B_A15 78
A15
9 M_B_BS#2 79 102 M_CLK_DDR3 8
A16/BA2 CK1
104 M_CLK_DDR#3 8
CK1#
9 M_B_BS#0 109 M_B_DM[7..0] 9
BA0 M_B_DM0
9 M_B_BS#1 108 11
BA1 DM0 M_B_DM1
28
M_B_DQ0 DM1 M_B_DM2
5 46
M_B_DQ1 DQ0 DM2 M_B_DM3
9 M_B_DQ[63..0] 7 63
M_B_DQ2 DQ1 DM3 M_B_DM4
15 136
M_B_DQ3 DQ2 DM4 M_B_DM5
17 153
M_B_DQ4 DQ3 DM5 M_B_DM6
4 170
M_B_DQ5 DQ4 DM6 M_B_DM7
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6
18 200 SMBD_ICH 3,16,18
M_B_DQ8 DQ7 SDA
21 202 SMBC_ICH 3,16,18
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 3D3V_S0
33 198 PM_EXTTS#0 8,18
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
M_B_DQ14 DQ13
34 197

1
M_B_DQ15 DQ14 SA0 DDRB_SA1
36 201 2 1
M_B_DQ16 DQ15 SA1 R26 C73
39
DQ16

SCD1U16V2ZY-2GP
M_B_DQ17 41 77 10KR2J-3-GP

2
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
1D5V_S3 M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
3 42 75 3
M_B_DQ22 DQ21 VDD1
50
DQ22 VDD2
76 DY
M_B_DQ23 52 81
1

C200 C183 C173 C190 C161 C151 M_B_DQ24 DQ23 VDD3

57 82
DQ24 VDD4
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

M_B_DQ25 59 87
M_B_DQ26 DQ25 VDD5
67 88
2

M_B_DQ27 DQ26 VDD6

69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
DY 58
DQ29 VDD9
99
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
DY 129
DQ32 VDD12
106
M_B_DQ33 131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
130 118
1

DQ36 VDD16
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C506 C207 C143 C497 M_B_DQ37 132 123

M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
2

M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
DQ50 VSS
：Near Pin 126
Layout Note： M_B_DQ51
M_B_DQ52
177
164
DQ51 VSS
32
37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
DDR_VREF_S3_1 M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
C131 M_B_DQ59 DQ58 VSS
193 55
1

M_B_DQ60 DQ59 VSS

180 60
DQ60 VSS
SC1U10V3KX-3GP

C132 M_B_DQ61 182 61

2 SCD1U16V2ZY-2GP M_B_DQ62 DQ61 VSS 2
192 65
2

M_B_DQ63 DQ62 VSS

194 66
DQ63 VSS
71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
9 M_B_DQS#[7..0] 27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
DQS6# VSS
：Near Pin 1
Layout Note： M_B_DQS#7 186
DQS7# VSS
144
145
M_B_DQS0 VSS
12 150
DDR_VREF_S3_1 M_B_DQS1 DQS0 VSS
9 M_B_DQS[7..0] 29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
C298 M_B_DQS5 DQS4 VSS
154 162
1

M_B_DQS6 DQS5 VSS

171 167
DQS6 VSS
SC1U10V3KX-3GP

C309 M_B_DQS7 188 168

SCD1U16V2ZY-2GP DQS7 VSS
172
2

VSS
8 M_ODT2 116 173
ODT0 VSS
8 M_ODT3 120 178
ODT1 VSS
179
DDR_VREF_S3_1 VSS
126 184
DDR_VREF_S3_1 VREF_CA VSS
1 185
VREF_DQ VSS
189
VSS
8,18 DDR3_DRAMRST# 30 190
RESET# VSS
195
VSS
196
VSS
DDR_VREF_S3 203 205
VTT1 VSS
204 206
1

C98 C105 VTT2 VSS

SC1U10V3ZY-6GP

SC10U6D3V5MX-3GP
2

DDR3-204P-7-GP-U1
62.10017.F81
62.10017.P41
62.10017.N41

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3 Socket1
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 17 of 48

A B C D E
 A B C D E

DDR3 SOCKET_2

4 4

DM1
9 M_A_A[14..0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# 9
M_A_A4 A3 RAS#
92 113 M_A_WE# 9
M_A_A5 A4 WE#
91 115 M_A_CAS# 9
M_A_A6 A5 CAS#
90
M_A_A7 A6
86 114 M_CS0# 8
M_A_A8 A7 CS0#
89 121 M_CS1# 8
M_A_A9 A8 CS1#
85
M_A_A10 A9
107 73 M_CKE0 8
M_A_A11 A10/AP CKE0
84 74 M_CKE1 8
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_CLK_DDR0 8
M_A_A14 A13 CK0
80 103 M_CLK_DDR#0 8
A14 CK0#
TPAD14-GP TP24 1 M_A_A15 78
A15
9 M_A_BS#2 79 102 M_CLK_DDR1 8
A16/BA2 CK1
104 M_CLK_DDR#1 8
CK1#
9 M_A_BS#0 109 M_A_DM[7..0] 9
BA0 M_A_DM0
9 M_A_BS#1 108 11
BA1 DM0 M_A_DM1
28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
9 M_A_DQ[63..0] 7 63
M_A_DQ2 DQ1 DM3 M_A_DM4
15 136
M_A_DQ3 DQ2 DM4 M_A_DM5
17 153
M_A_DQ4 DQ3 DM5 M_A_DM6
4 170
M_A_DQ5 DQ4 DM6 M_A_DM7
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6 SMBD_ICH
18 200 SMBD_ICH 3,16,17
M_A_DQ8 DQ7 SDA SMBC_ICH
21 202 SMBC_ICH 3,16,17
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9
33 198 PM_EXTTS#0 8,17
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199 3D3V_S0
M_A_DQ13 DQ12 VDDSPD
24
M_A_DQ14 DQ13
3 34 197 3

1
M_A_DQ15 DQ14 SA0 C75
36 201
M_A_DQ16 DQ15 SA1
39
DQ16

SCD1U16V2ZY-2GP
M_A_DQ17 41 77

2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
67 88
M_A_DQ27 DQ26 VDD6 1D5V_S3
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ30 DQ29 VDD9
68 100

1
M_A_DQ31 DQ30 VDD10 C158 C176 C156 C168 C138 C144 TC11
70 105
DQ31 VDD11

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
M_A_DQ32 129 106
DQ32 VDD12

ST330U6VDM-2-GP
M_A_DQ33 131 111

2
M_A_DQ34 DQ33 VDD13
141 112
M_A_DQ35 DQ34 VDD14
143 117
M_A_DQ36 DQ35 VDD15
M_A_DQ37
130
DQ36 VDD16
118 DY DY DY
132 123
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
146 13

1
DQ44 VSS

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
M_A_DQ45 148 14 C141 C150 C177 C167
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS
160 20

2
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
M_A_DQ53 DQ52 VSS
166 38
M_A_DQ54 DQ53 VSS
174 43
DQ54 VSS
2
：Near Pin 126
Layout Note： M_A_DQ55
M_A_DQ56
176
181
DQ55 VSS
44
48
2

M_A_DQ57 DQ56 VSS

183 49
M_A_DQ58 DQ57 VSS
191 54
DDR_VREF_S3_1 M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS
192 65
C136 M_A_DQ63 DQ62 VSS
194 66
1

DQ63 VSS
71
VSS
SC1U10V3KX-3GP

C137 M_A_DQS#0 10 72
SCD1U16V2ZY-2GP M_A_DQS#1 DQS0# VSS
27 127
2

9 M_A_DQS#[7..0] DQS1# VSS

M_A_DQS#2 45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
9 M_A_DQS[7..0] 29 151
DQS1 VSS
：Near Pin 1
Layout Note： M_A_DQS2
M_A_DQS3
47
64
DQS2 VSS
155
156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
DDR_VREF_S3_1 M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
8 M_ODT0 116 173
C290 ODT0 VSS
8 M_ODT1 120 178
1

ODT1 VSS
179
VSS
SC1U10V3KX-3GP

C299 DDR_VREF_S3_1 126 184

SCD1U16V2ZY-2GP DDR_VREF_S3_1 VREF_CA VSS
1 185
2

VREF_DQ VSS
189
VSS
8,17 DDR3_DRAMRST# 30 190
RESET# VSS
195
VSS
196
VSS
DDR_VREF_S3 203 205
VTT1 VSS
204 206
1

C70 C78 VTT2 VSS

SC10U6D3V5MX-3GP

1 1
SC1U10V3ZY-6GP
2

DDR3-204P-46-GP
62.10017.P11
62.10017.N91
62.10017.P31

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3 Socket2
Size Document Number Rev

JM41_Discrete -1
Date: Thursday, April 09, 2009 Sheet 18 of 48
A B C D E
 5 4 3 2 1

LCD/CCD CONN Internal MIC

F1
2 1 DCBATOUT
POLYSW -1D1A24V-GP
DCBATOUT_LCD1 69.50007.A31
69.50007.A41
D LCD1 D

1
48 C61 C49

SCD1U16V2ZY-2GP

SC10U35V0ZY-GP
DY
41 50

2
1 F2
1 2 3D3V_S0
2

1
3 C443 C438 FUSE-1D1A6V-4GP-U

SC4D7U10V5ZY-3GP

SCD1U16V2ZY-2GP
4 DBC_EN 28 69.50007.691
5 BLON_OUT_R DY 69.50007.771

2
42 6 BRIGHTNESS_CN
7 CCD_PW R
8 USBPN4 14
9 USBPP4 14
10
11
12 EC37 EC36 3D3V_S0

1
43 13 DMIC_CLK 22
14

SC22P50V2JN-4GP

SC22P50V2JN-4GP
DMIC_DAT 22
15 3D3V_S0

2
16 DY DY
17

1
2
18
19
44 20 SRN2K2J-1-GP
21
22 RN16
23

4
3
24 LCD_TXAOUT0- LCD_TXAOUT0- 41
C 25 LCD_TXAOUT0+ LCD_TXAOUT0+ 41
C
26
45 27 LCD_TXAOUT1- LCD_TXAOUT1- 41 RN17
28 LCD_TXAOUT1+ LCD_TXAOUT1+ 41 LCD_EDID_DAT_C 3 2 LCD_EDID_DAT 41
29 LCD_EDID_CLK_C 4 1 LCD_EDID_CLK 41
30 LCD_TXAOUT2- LCD_TXAOUT2- 41 SRN0J-10-GP-U
31 LCD_TXAOUT2+ LCD_TXAOUT2+ 41
32
33 LCD_TXACLK- LCD_TXACLK- 41
46 34 LCD_TXACLK+
35
LCD_EDID_DAT_C
LCD_TXACLK+ 41
-1
36
37 LCD_EDID_CLK_C
38 LCDVDD 3D3V_S0
3D3V_S0
39 U33

SCD1U16V2ZY-2GP
40
47 51
8 GMCH_BL_ON 3 B0 A 4 KBC_BL_ON_IN 28
1

1
49 C486 C134 2 5
GND VCC

1
IPEX-CONN40-2R-GP
DY SC10U35V0ZY-GP 43 G_BL_ON 1 B1 S 6
R217
2

2
20.F1093.040 10KR2J-3-GP
20.F1289.040 NC7SB3157P6X-1GP
73.03157.C0H

2
14,20,41 DIS_EN

R347
B B
1 2
-1 0R2J-2-GP

Layout 40 mil 3D3V_S0

U51
LCDVDD 3D3V_S0 R33
3D3V_S0 8 GMCH_L_BKLTCTL 2 1 GMCH_L_BKLTCTL_R 3 4 BRIGHTNESS_CN
33R2J-2-GP B0 A
U8 2 GND VCC 5
U9 28 KBC_L_BKLTCTL 1 6
B1 S

1
C106
8 GMCH_LCDVDD_ON 3 4 LCDVDD_ON 1 5 SC100P50V2JN-3GP
B0 A EN VIN#5 NC7SB3157P6X-1GP
2 5 2 DY

2
GND VCC GND
42 G_LCDVDD_ON 1 B1 S 6 3 VOUT VIN#4 4 73.03157.C0H
1

DY C129 DY
1
SCD1U16V2ZY-2GP

NC7SB3157P6X-1GP C135 RT9724GB-GP 28 DIS_EN

2

73.03157.C0H 74.09724.09F
2

SC4D7U6D3V3KX-GP

74.05285.07F C139
SC4D7U6D3V3KX-GP
14,20,41 DIS_EN
2

R165
BLON_OUT_R 1 2 BLON_OUT 28
1KR2F-3-GP

1
C432

SC100P50V2JN-3GP
A DIS A

1
DY

2
R166
10KR2J-3-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD CONN
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 19 of 48
5 4 3 2 1
 A B C D E

3D3V_S0

5V_S0
Hsync & Vsync level shift

4
3
RN34
14,19,41 DIS_EN SRN10KJ-5-GP

1
2
U45
4 4
28 HDD_PW R_EN# CRT_DEC# 28
L=>B0 -UMA For UMA CRT 1 8 CN3
H=>B1 -MXM 2
1OE# VCC
7 21
8 GMCH_HSYNC 1A 2OE#
3 2Y 1Y 6 1
4 GND 2A 5
43 HDMI_DATA2+ 2
43 HDMI_DATA2- 3
SSLVC2G125DP-1GP 4
73.2G125.A07 43 HDMI_DATA1+ 5
8 GMCH_VSYNC 43 HDMI_DATA1- 6
7
43 HDMI_DATA0+ 8
CRT_VSYNC 2 3 RN38 43 HDMI_DATA0- 9
CRT_HSYNC 1 4 SRN0J-6-GP 10
43 HDMI_CLK+ 11
43 HDMI_CLK- 12
13
14
U44 13 SATA_TXP1 15
For DIS CRT 13 SATA_TXN1 16
1 1OE VCC 8 17
43,45 G_HSYNC 2 1A 2OE 7 13 SATA_RXP1 18
CRT_VSYNC_OT 3 6 CRT_HSYNC_OT 19
2Y 1Y 13 SATA_RXN1
4 GND 2A 5 20
22
SSHCT2G126DP-GP
73.2G126.ABB IPEX-CON20-1-GP

3 3
43,45 G_VSYNC 20.F1312.020

RN40
4 1 CRT_HSYNC_OT CN2
43,45 G_HSYNC CRT_VSYNC_OT
43,45 G_VSYNC 3 2 41
1
SRN0J-6-GP
14 USBPN9 2
DY 14 USBPP9 3
4
14 USBPN1 5
14 USBPP1 6
7
41 CRT_RED 8
9
DDC_CLK & DATA level shift 41 CRT_GREEN
41 CRT_BLUE 10
11
CRT_HSYNC 12
CRT_VSYNC 13
CRT_DDCCLK 14
CRT_DDCDATA 15
3D3V_S0 28 CRT_DEC# 16
VDDR3 3D3V_S0 3D3V_S0 17
43 G_HDMI_DATA
43 G_HDMI_CLK 18
43 HDMI_DETECT# 19
14 USB_OC#1 20
3D3V_S0 21
25,26,28 USB_PW R_EN#
4
3

3
4

2 2
28 MODEL_ID0 22
RN36 RN35 R296 28 MODEL_ID1 23
SRN2K2J-1-GP SRN2K2J-1-GP 10KR2J-3-GP 24
28 HDD_PW R_EN#
3
4

DY DY RN39 5V_S0 25
26
SRN4K7J-8-GP

27
1
2

2
1

5V_S5 28
U42 29
30
2
1

22 MIC1_JD# 31
8 GMCH_DDCDATA 3 B0 A 4 22 HP_JD# 32
2 GND VCC 5 Q17 33
43 G_DDCDATA 1 B1 S 6 34

1
SC33P50V2JN-3GP

SC33P50V2JN-3GP
DDCDATA 4 3 CRT_DDCDATA EC22 EC23 35
DY DY 22 HP_OUT_L 36
NC7SB3157P6X-1GP 5 2 37

2
22 HP_OUT_R
73.03157.C0H 22 SPDIF 38
6 1 22 MIC1_IN_L 39
22 MIC1_IN_R 40
2N7002EDW -GP 42
U43
84.27002.G3F
PTW O-CON40-2-GP
3 4 DDCCLK
8 GMCH_DDCCLK B0 A
2 5 CRT_DDCCLK 20.K0410.040
GND VCC
43 G_DDCCLK 1 B1 S 6 20.K0420.040

NC7SB3157P6X-1GP AGND
1 73.03157.C0H SB DIS 1

L=>B0 -UMA RN37 Wistron Corporation

H=>B1 -MXM 4 1 DDCDATA 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
43 G_DDCDATA Taipei Hsien 221, Taiwan, R.O.C.
3 2 DDCCLK
43 G_DDCCLK
Title
14,19,41 DIS_EN SRN0J-6-GP
DY CRT BD CONN
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 20 of 48
A B C D E
 SSD SATA Connector

SSD1
16

S1
S2 SATA_TXP0 13
13 SATA_TXN0 S3
S4
13 SATA_RXN0 S5
S6 SATA_RXP0 13
S7
3D3V_S0
3D3V_S0
P1
P2
P3

1
P4
P5 5V_S0 TC20 C665
5V_S0

SC10U10V5ZY-1GP

SCD1U16V2ZY-2GP
P6

2
P7
P8
P9
P10

1
P11
P12 C667 TC21

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP
P13

2
P14
P15

17

SKT-SATA7P+15P-30-GP

62.10065.911

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDD CONN
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 21 of 48
 5 4 3 2 1

5V_S0

U24

1 5 5VA_S0
EN NC#5
2 GND
3 VIN VOUT 4
1

1
D C397 Put C735 Close To CODEC D
SC1U10V3KX-3GP RT9198-4GPBG-GP C362
74.09198.A7F SC10U10V5KX-2GP 2 1 AUD_CPVEE
AGND
2

2
74.09091.F3F C634 SC2D2U6D3V3MX-1-GP

R327 5VA_S0 5VP_S0 MIC1_R 1 2 MIC1_IN_R 20

AGND AGND 1D5V_S0 1 2 DVDDIO MIC1_L C6381 2SC4D7U10V5ZY-3GP MIC1_IN_L 20
0R2J-2-GP C644 SC4D7U10V5ZY-3GP

1 2 3D3V_AUDIO_S0
SB 3D3V_S0
R132 0R0603-PAD

25
38

34
39
46

22

21
1
9
U47

AVDD1
AVDD2

PVDD1
PVDD2

MIC1_L
DVDD_IO
DVDD

MIC1_R
CPVEE
MIC2_R 17

20 HP_OUT_R 33 HP-OUT_R MIC2_L 16

20 HP_OUT_L 32 HP-OUT_L
LINE2-R 15
LINE2-L 14

20 SPDIF 48 SPDIFO RN41

30 MIC1_VREFO_R 4 1
C
SB SENSE_A
MIC1_VREFO_R
MIC1_VREFO_L 28 MIC1_VREFO_L 3 2
C
13 SENSE_A MIC2_VREFO 29

R311 2 SRN2K2J-1-GP
20 HP_JD# 1 18 SENSE_B
39K2R3F-GP Alnalog signal 24
LINEOUT1-R
20 MIC1_JD# 2 1 LINEOUT1-L 23
R309 20KR2F-L-GP

19 DMIC_CLK 2 3 DMIC_CLK_R 3
DMIC_DAT_R GPIO1/DMIC-CLK
19 DMIC_DAT 1 4 2 GPIO0/DMIC_DATA SPKL- 41 SPKR_L- 23
Digital signal SPKL+ 40 SPKR_L+ 23
EC56 EC61 RN43 44 SPKR_R- 23
SRN0J-6-GP AUD_EAPD SPKR-
47 SPDIFO2/EAPD SPKR+ 45 SPKR_R+ 23
1

1
SC22P50V2JN-4GP

SC22P50V2JN-4GP

DY DY
AUD_CBP 36
2

CBP

SDATA_OUT

MONO-OUT
2

SDATA_IN
C633 AUD_CBN 35

CPVREF
CBN

RESET#
BIT-CLK

AVSS1
AVSS2

PVSS1
PVSS2
JDREF
SYNC

DVSS
BEEP

VREF
SC2D2U10V3ZY-1GP

GND
1

PD#
Put C736 Close To CODEC
ALC269X-GR-GP

12

10
6
11
5
8

31
4
20
19

27

26
37

7
49

42
43
RN42
1 4 AUDIO_BEEP 1 2 PCBEEP
14 ACZ_SPKR C659 SCD1U10V2KX-4GP

ACZ_BITCLK_R

ACZ_SDATAIN0_R
28 EC_BEEP 2 3

AUD_PD#
SC100P50V2JN-3GP

SRN10KJ-5-GP
1

R316 C660
B 1KR2J-1-GP B
AGND
2

13 ACZ_SYNC
AGND AUD_VREF
-1
2

13 ACZ_BITCLK 2 R329 1 0R2J-2-GP AUD_JDREF

1
DY
-1 R295

1
1 2 2 R330 1 PLT_RST1# 8,14,24,25,28,29,42 R306 C631 C635

SC10U10V5KX-2GP

SCD1U10V2KX-4GP
AGND C666 SC22P50V2JN-4GP 0R2J-2-GP 20KR2F-L-GP 1 2
13 ACZ_RST# 1 2 ACZ_SDATAIN0 13

2
33R2F-3-GP R328

2
0R3J-0-U-GP AGND
1 2 ACZ_SDATAOUT 13
EC53 SC100P50V2JN-3GP DY
AGND AGND
-2
R348
AUD_EAPD 2 1 AUD_PD#

5V_S0 5VP_S0 3D3V_S0

0R2J-2-GP
R82
1 2
1

0R0603-PAD
C388 C369 C395 1 C394
SC10U10V5KX-2GP

SC10U10V5KX-2GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
2

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Close Pim.39 Close Pim.1 Title
and Pin.46 and Pin.9 AUDIO CODEC REALTEK ALC269
Size Document Number Rev

JM41_Discrete -1
Date: W ednesday, April 15, 2009 Sheet 22 of 48
5 4 3 2 1
 5 4 3 2 1

D D

Internal Speaker
C SPK1 C
5
22 SPKR_L- 1

22 SPKR_L+ 2
22 SPKR_R- 3
22 SPKR_R+ 4
6

EC31 SC100P50V2JN-3GP

EC32 SC100P50V2JN-3GP

EC33 SC100P50V2JN-3GP

EC34 SC100P50V2JN-3GP
ACES-CON4-5-GP

1
20.F0866.004
20.F1261.004

2
DY DY DY DY

B B

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

AUDIO JACK
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 23 of 48
5 4 3 2 1
 5 4 3 2 1

D D

20.K0289.032
ACES-CON32-GP-U
34
32
28 TP_LOCK_LED TP_LOCK_LED 31
13,28 RTC_BAT 30
28 DC_BATFULL DC_BATFULL 29
28 CHARGE_LED CHARGE_LED 28
3D3V_AUX_S5 27
26
14 USBPN7 25
C 24 C
14 USBPP7
23
8,14,22,25,28,29,42 PLT_RST1# 22
5V_ODD_S0 21
20
19
30 TP_BTN_L 18
30 TP_BTN_R 17
28 TP_LOCK_BTN# 16
15
28 BLUETOOTH_EN 14
3D3V_S0
13
28 LID_CLOSE# 12
1

1
SC33P50V2JN-3GP

SC33P50V2JN-3GP

EC54 EC55 EC52SC33P50V2JN-3GP

11
DY DY DY 13 SATA_RXP4 10
13 SATA_RXN4 9
2

8
13 SATA_TXN4 7
13 SATA_TXP4 6
5
14 USBPN11 4
14 USBPP11 3
2

1
33
CN1

B B

20.K0430.032

DIS
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CARDREADER BD CONN
Size Document Number Rev

JM41_Discrete -1
Date: Thursday, April 09, 2009 Sheet 24 of 48

5 4 3 2 1
 A B C D E

4 4

3D3V_S0

SC33P50V2JN-3GP
EC15
BTB1 DY
NP1

2
5V_S5 2 1

4 3

1
EC14 6 5
SC33P50V2JN-3GP DY 8 7
10 9 3D3V_AUX_S5

2
12 11 RUN_POW ER_ON
14 USBPN3 14 13 SMBC_THERM 27,28,43

1
16 15 EC12
14 USBPP3 SMBD_THERM 27,28,43
18 17 BAT_IN# 28 DY SC33P50V2JN-3GP
14 USBPN10
14 USBPP10 20 19 BAT_SDA 28

2
22 21 BAT_SCL 28
14 USBPN0 24 23 E51_RxD 28
14 USBPP0 26 25 E51_TxD 28
28 27 AD_IA 28
3 CLK_PCIE_MINI1# 30 29 AC_IN# 28
3 32 31 3
3 CLK_PCIE_MINI1 AD_ON 28
34 33 USB_OC#0 14
14 PCIE_TXN2 36 35 USB_PW R_EN# 20,26,28
14 PCIE_TXP2 38 37 PLT_RST1# 8,14,22,24,28,29,42
40 39 W LAN_CLKREQ# 3
14 PCIE_RXN2 42 41 ALL_LED_OFF# 28,31
14 PCIE_RXP2 44 43 MEDIA_INT# 28
46 45 W LAN_TEST_LED 28
14 PCIE_RXN1 48 47 W IRELESS_EN 28
14 PCIE_RXP1 50 49 3G_EN 28
52 51 EJECT_BTN 28
14 PCIE_TXN1 54 53 3V/5V_EN 28,32
14 PCIE_TXP1 56 55 PCIE_W AKE# 14
58 57
31 MEDIA_LED#_R 60 59 CLK_PCIE_LAN 3
3 LAN_CLKREQ# 62 61 CLK_PCIE_LAN# 3
64 63
66 65 3D3V_S5
68 67 1D5V_S0
DCBATOUT 70 69 DCBATOUT
NP2
1

1
SC33P50V2JN-3GP

SC33P50V2JN-3GP
EC5 STC-CONN70D-GP-U EC6 EC8
SC33P50V2JN-3GP DY DY DY
62.10080.031
2

2
2 2

1 DIS 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINI BD CONN
Size Document Number Rev
A3 JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 25 of 48
A B C D E
 5 4 3 2 1

D D

C BTB2 C
11
5V_S5 1

SC33P50V2JN-3GP
EC3 31 FRONT_PW RLED#_R 3
DY 28 KBC_PW RBTN#_L 4
5

2
14 USBPN2 6
14 USBPP2 7
8
31 STDBY_LED#_R 9
20,25,28 USB_PW R_EN# 10
12

SB ACES-CON10-7-GP

20.F0866.010
20.F1261.010

B B

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

POWER BUTTON CONN

Size Document Number Rev
A3 JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 26 of 48
5 4 3 2 1
 5 4 3 2 1
CPU TEMP:
5V_S0

H_THERMDA and H_THERMDC routing 10mil trace width

and spacing. Locate Capacity near thermal diode C500

1
for CPU thermal diode C502 C587 for EMI and
H_THERMDA C434 1 2 H_THERMDC SC4D7U10V5ZY-3GP
solve acoustic noise

SCD1U16V2ZY-2GP
SC100P50V2JN-3GP

2
4 H_THERMDA H_THERMDA
EMC2102_DP2 C440 1 2 EMC2102_DN2
SC100P50V2JN-3GP
4 H_THERMDC H_THERMDC
D CLOSE TO EMC2103 FAN1 D
5

1
84.03904.H11
3D3V_S0 3D3V_S0 EMC2102_DP2 84.03904.L06 FAN_PW M 2
84.T3904.C11 FAN_TACH 3

E
SC22P50V2JN-4GP MMBT3904-4-GP SC22P50V2JN-4GP 4
1

1
Q1 B B C182
Q2 C62 Q3 C199
MMBT3904-4-GP DY 6

SCD1U16V2ZY-2GP
R38 2N7002-11-GP DY DY
G
84.T3904.C11

2
C
E
10KR2J-3-GP 84.27002.Y31 PTW O-CON4-8-GP
84.03904.L06 EMC2102_DN2 20.F1396.004
2

PURE_HW _SHUTDOW N# S D RSMRST# 28,32 84.03904.H11

20.F0411.004
for T8 thermal diode for system thermal diode
R164
1 2 2103_VDD 5V_S0
3D3V_S0

1
49D9R2F-GP
C433 ps. FAN1 POWER TRACE WIDTH MAY BE IN 25 MIL
SCD1U16V2KX-3GP

2
1
U29 RN15
3D3V_S0 SRN10KJ-5-GP
3 4 2103_GPIO1 1 TP52 TPAD14-GP
VDD GPIO1 2103_GPIO2 1 TP54 TPAD14-GP
GPIO2 5
H_THERMDA 2

3
4
DP1
2

C R174 H_THERMDC 1 10 FAN_TACH C

10KR2J-3-GP EMC2102_DP2 DN1 TACH FAN_PW M
16 DP2/DN3 PWM 11
EMC2102_DN2 15 ND2/DP3 TRIP_SET R1751
TRIP_SET 14 2 787R2F-GP
PURE_HW _SHUTDOW N# 7 13
1

THERM_SCI# SYS_SHDN# SHDN_SEL SHDN_SEL

6 ALERT# 1 2
R181 22KR2F-GP
R180 2 1 0R0402-PAD SMBC_THERM_1 9 12
25,28,43 SMBC_THERM SMCLK GND
R176 2 1 0R0402-PAD SMBD_THERM_1 8 17
25,28,43 SMBD_THERM SMDATA GND

EMC2103-2-AP-GP
SA
74.02103.A73
Channel 1: CPU
Channel 2: Palmrest
Channel 3: T8

SHDN_SEL TRIP_SET
PULL UP Ttrip(degree) RSET(1%)
RESISTOR MODE OF OPERATION

<=4.7K OHM EXTERNAL DIODE 1 SIMPLE MODE-BETA 85 562

B COMPENSATION DISABLED,REC DISABLED B

86 604
6.8K OHM EXTERNAL DIODE 1 DIODE MODE-BETA 87 649
COMPENSATION DISABLED,REC ENABLED
88 698
10K OHM EXTERNAL DIODE 1 TRANSISTOR MODE-BETA 89 750
COMPENSATION ENABLED,REC ENABLED
90 787
15K OHM INTERNAL DIODE 91 845
92 909
22K OHM EXTERNAL DIODE 2 TRANSISTOR MODE-BETA 93 953
COMPENSATION ENABLED,REC ENABLED
94 1020
>=33K OHM EXTERNAL DIODE 1 TRANSISTOR MODE-BETA 95 1100
COMPENSATION ENABLED,REC ENABLED

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Fan Controllor
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 27 of 48
5 4 3 2 1
 A

3D3V_AUX_S5 3D3V_S0 3D3V_S0 3D3V_AUX_S5

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
1

1
EC21 C345 C354 C320 C609 C389 C387 C608

1
SRN4K7J-10-GP

SCD1U16V2ZY-2GP
8
7
6
5

2
RN9

2
DY

3D3V_AUX_S5
1
2
3
4
C555,C556 colse to Pin VDD R99
3D3V_AUX_S5_KBC 2 1
BAT_SCL SMBC_THERM

1
BAT_SDA SMBD_THERM 0R0402-PAD EC25

SCD1U16V2ZY-2GP
SC1U16V3ZY-GP
DY

SCD1U16V2ZY-2GP
1

1
4
C386 4

2
C391
DY

2
3D3V_S0 -1
R281
8,14,22,24,25,29,42 PLT_RST1# 1 2PLT_RST1#_1
100R2J-2-GP
3D3V_S0

SC27P50V2JN-2-GP
25 BAT_IN#

1
C616 3D3V_S0 X3

102

115
U16A

80

19
46
76
88
-1

1
1 OF 2 3 2

1
C332 C306

GPIO41

VDD

AVCC

VCC
VCC
VCC
VCC
VCC
10KR2J-3-GP 1 R94 2 E51_RxD R344 SC6P50V2CN-1GP SC6P50V2CN-1GP

1KBC_XO_R 2

2
DY 10KR2J-3-GP
4 1
124 104 2 R269 1 10KR2J-3-GP

2
10KR2J-3-GP R93 E51_TxD GPIO10/LPCPD# VREF
1 2 7
LRESET# X-32D768KHZ-34GPU
DY 3 PCLK_KBC
2
LCLK A/D GPI90/AD0
97 AD_IA 25 DY
13,29 LPC_LFRAME# 3 98 TP_LOCK_BTN# 24 82.30001.661

2
LFRAME# GPI91/AD1

33KR2J-3-GP
126 99 82.30001.B21 U16B 2 OF 2
13,29 LPC_LAD0 LAD0 GPI92/AD2
R77 127 100 VR_PWRGD 14,32,34 R72
13,29 LPC_LAD1 LAD1 GPI93/AD3
10KR2J-3-GP 1 R92 2 E51_TxD SC4D7P50V2CN-1GP DY 0R2J-2-GP 128 108 R71
13,29 LPC_LAD2 LAD2 GPIO05 MEDIA_INT# 25
KBC_XI KCOL1
1 LPC 96 S0_PWR_GOOD 32 1 2 77 53

2
C361 13,29 LPC_LAD3 LAD3 GPIO04 32KX1/32KCLKIN KBSOUT0/JENK#
125 52 KCOL2
14 INT_SERIRQ
1

SERIRQ KBSOUT1/TCK
1 2PCLK_KBC_RC 14 PM_CLKRUN# 8 20MR3-GP 51 KCOL3
GPIO11/CLKRUN# KBSOUT2/TMS KCOL4
DY 13 KBRCIN# 122
KBRST# KBSOUT3/TDI
50
121 101 KBC_XO 79 49 KCOL5
13 KA20GATE GA20 GPI94 32KX2 KBSOUT4/JEN0#
ECSCI#_KBC 29 105 PCB_VER0 30 48 KCOL6
ECSCI#/GPIO54 GPI95 PCB_VER1 GPIO55/CLKOUT KBSOUT5/TDO KCOL7
9 D/A 106 47
19 KBC_BL_ON_IN ECSWI#_KBC GPIO65/SMI# GPI96 KBSOUT6/RDY# KCOL8
123 107 CRT_DEC# 20 25,31 ALL_LED_OFF# 63 43
GPIO67/PWUREQ# GPI97 GPIO14/TB1 KBSOUT7 KCOL9
TP27 1
14 PM_PWRBTN#
CHG_ON#
117
31
GPIO20/TA2 KBC KBSOUT8
42
41 KCOL10
GPIO56/TA1 KBSOUT9 KCOL11
32 40
3D3V_S0 TPAD14-GP 22 EC_BEEP GPIO15/A_PWM KBSOUT10 KCOL12
THERMAL-----> 25,27,43 SMBD_THERM 68 64 PM_SLP_S3# 14,32,36,39,40 14 EC_TMR 118 39
GPIO74/SDA2 GPIO01/TB2 KBC_PWRBTN# GPIO21/B_PWM KBSOUT11 KCOL13
25,27,43 SMBC_THERM 67 SMB 95 19 KBC_L_BKLTCTL 62 38
GPIO73/SCL2 GPIO03 GPIO13/C_PWM KBSOUT12/GPIO64 KCOL14
69 93 AC_IN# 25 37

1
25 BAT_SDA GPIO22/SDA1 GPIO06 LID_CLOSE# KBSOUT13/GPIO63 KCOL15
BATTERY-----> 70 94 36
25 BAT_SCL GPIO17/SCL1 GPIO07
GPIO23
119 SB_ID LID_CLOSE# 24 SB R341 KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
35 KCOL16
6 HDMI_hotplug 43 10KR2J-3-GP TPAD14-GP TP29 1ENERGY_DET_KBC 13 34 KCOL17
GPIO24 GPIO12/PSDAT3 GPIO60/KBSOUT16 KCOL18
109 3G_EN 25 12 33
GPIO30 MODEL_ID0 GPIO25/PSCLK3 GPIO57/KBSOUT17
81 SP 120 MODEL_ID0 20 32 ODD_PWR_EN# 11

2
GPIO66/G_PWM GPIO31 GPIO27/PSDAT2
3 3

65 PWRLED 31 25 EJECT_BTN 10
GPIO32/D_PWM GPIO26/PSCLK2 KROW1
66 STDBY_LED 31 30 TPDATA 71 54
GPIO33/H_PWM GPIO35/PSDAT1 KBSIN0 KROW2
16 72 PS/2 55
R279
3D3V_S0
24 BLUETOOTH_EN 84
GPIO77
GPIO40/F_PWM
GPIO42/TCK
17 AD_OFF SB 30 TPCLK GPIO37/PSCLK1 KBSIN1
KBSIN2
56 KROW3
KROW4
DBC_EN 1 2 R188 19 DBC_EN
83
82
GPIO76/SHBM SPI GPIO43/TMS
20
21
RSMRST#_KBC 14 3D3V_S0 KBSIN3
57
58 KROW5
KA20GATE 1 2
25 WIRELESS_EN
91
GPIO75 GPIO GPIO44/TDI
22
PM_SLP_S4# 14,32,35,37
86
KBSIN4
59 KROW6
25 WLAN_TEST_LED GPIO81 GPIO45/E_PWM CHARGE_LED 24 29 SPIDI F_SDI KBSIN5
23 HDD_PWR_EN# 20 29 SPIDO 87 60 KROW7

1
10KR2J-3-GP 8K2R2J-3-GP GPIO46/TRST# MODEL_ID1 F_SDO KBSIN6 KROW8
24 MODEL_ID1 20 29 SPICS# 90 FIU 61
GPIO47 R278 F_CS0# KBSIN7
25 SPI_WP# 29 92
3D3V_AUX_S5 E51_TxD 111 GPIO50/TDO 29 SPICLK F_SCK
R95 26 TP_LOCK_LED 24 10KR2J-3-GP
25 E51_TxD E51_RxD 113 GPO83/SOUT_CR/BADDR1 GPIO51 ECRST#
27 BLON_OUT 19 85
SB_ID 25 E51_RxD GPIO87/SIN_CR GPIO52/RDY# UMA_DISCRETE# VCC_POR#
1 2 112 28

2
GPO84/BADDR0 GPIO53
73
GPIO70 BKLTCTL_SEL
114 74 BKLTCTL_SEL 19
10KR2J-3-GP BAT_IN# 24 DC_BATFULL GPIO16 GPIO71
1 R273 2 14 75 WPCE773LA0DG-GP
100KR2J-1-GP S5_ENABLE GPIO34 GPIO72
2 1 15 110 USB_PWR_EN# 20,25,26
25,32 3V/5V_EN R73 10KR2J-3-GP GPIO36 GPO82/TRIS#
UMA_DISCRETE# 1 R268 2
SER/IR
RN10
10KR2J-3-GP
VCORF 44 5 4 ECRST#
VCORF 3D3V_AUX_S5
S5_ENABLE 6 3
1

7 2 MEDIA_INT# C350

1
AGND 3D3V_AUX_S5 KBRCIN#
8 1

GND
GND
GND
GND
GND
GND
3D3V_S0

SC1U10V3KX-3GP
C604
2

SCD1U16V2ZY-2GP Q6

2
WPCE773LA0DG-GP SRN10KJ-6-GP MMBT3906-4-GP
D4
103

5
18
45
78
89
116
R79
27,32 RSMRST# B
6 1ECSCI#_KBC 71.00773.00G LID_CLOSE# 2 1
14 ECSCI#_1 84.T3906.A11

C
10KR2J-3-GP 2ND = 84.03906.F11
5 2 3RD = 84.03906.P11
3D3V_AUX_S5

14 ECSWI# 4 3ECSWI#_KBC

A
CH731UPT-GP D16
83.R0304.A8H RB751V-40-2-GP
2ND = 83.R2002.B8E 83.R2004.B8F
3RD = 83.R3004.A8E 3D3V_S0

K
2 2

83.R0304.A8F

AD_ON_R1
GREEN ADAPTER CIRCUIT

1
10KR2J-3-GP

10KR2J-3-GP
R325 R323
PlanarID
-1 DY
SA: 0,0

2
Q4 PCB_VER0 SB: 0,1
NDS0610-NL-GP 83.2R004.081 470R2J-2-GP PCB_VER1
84.00610.C31 SDM20E40C-7-F-GP R275 -1: 1,0
Internal KeyBoard R271

1
10KR2J-3-GP

10KR2J-3-GP
TP0610K-T1-GP 2 -1M: 1,1

1
3 AD_ON_R 1 2 AD_ON R326 R324
AD_ON 25
S D AD_ON_RD 1 DY
Connector 13,24 RTC_BAT

1
1

D19 470R2J-2-GP R256

2
1

R254 C598 Q5 100KR2J-1-GP

G

47KR2J-2-GP SC1U10V3KX-3GP .
84.2N702.D31
2

2
DY .
2

KB1 2N7002E-1-GP .
. . 2ND = 84.2N702.E31

K
ACES-CON26-3GP
20.K0256.026 D21

S
20.K0331.026 3D3V_AUX_S5 3D3V_AUX_S5 3D3V_AUX_S5
27

28

MMPZ5232BPT-GP-U
D14
R266

A
2

2 1 KBC_PWRBTN#_L1 K A
47KR2J-2-GP
1

R80 AD_OFF 1 2
1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

R87 47KR2J-2-GP RB751V-40-2-GP R277 0R2J-2-GP

47KR2J-2-GP 83.R2004.B8F
DY
1

Q7
83.R0304.A8F
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

1 6 KBC_PWRBTN#
2

3D3V_AUX_S5
2 5 KBC_PWRBTN#_L
KBC_PWRBTN#_L 26
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KCOL18

1
KCOL1

KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9

KBC_PWRBTN_L 3 4
1

R342
1

G64 10MR2J-L-GP
2N7002EDW-GP EC27 GAP-OPEN
84.27002.G3FSC1KP50V2KX-1GP
2

2
DY
1 1

-1
2

C671
MB PIN DEFINE 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
KB PIN DEFINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AD_OFF 1 2 DIS

SC1U10V2KX-1GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

K/B Title
Taipei Hsien 221, Taiwan, R.O.C.

24 1 KBC WPC775
Size Document Number Rev
A2 -1
JM41_Discrete
Date: Wednesday, April 15, 2009 Sheet 28 of 48
A
 A B C D E

3D3V_AUX_S5

SCD1U16V2ZY-2GP
1
EC43

8
7
6
5
DY
RN33

2
4 SRN3K3J-1-GP 3D3V_AUX_S5 4

-1

1
2
3
4
SPI_HOLD#

U36

28 SPICS# 1 CS# VCC 8

28 SPIDI 2 R258 1 SPI_DI 2 7 SPI_HOLD#
33R2F-3-GP SPI_WP# SO/SIO1 HOLD#
28 SPI_WP# 3 WP#/ACC SCLK 6 SPICLK 28
4 GND SI/SIO0 5 SPIDO 28

1
EC49
DY MX25L1605DM2I-12G-GP

1
SC4D7P50V2CN-1GP

72.25165.A01 EC50 EC51

2

2ND = 72.25X16.A01 DY DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP
3RD = 72.25016.A01

2
3 3

16M Bits
SPI FLASH ROM

GOLDEN FINGER FOR DEBUG BOARD

2 2

LPC_LAD0 1 TP41 TPAD30-1-GP

13,28 LPC_LAD0
LPC_LAD1 1 TP43 TPAD30-1-GP
13,28 LPC_LAD1
LPC_LAD2 1 TP42 TPAD30-1-GP
13,28 LPC_LAD2
LPC_LAD3 1 TP37 TPAD30-1-GP
13,28 LPC_LAD3
13,28 LPC_LFRAME# LPC_LFRAME# 1 TP32 TPAD30-1-GP
PLT_RST1# 1 TP44 TPAD30-1-GP
8,14,22,24,25,28,42 PLT_RST1# PCLK_FWH TP80 TPAD30-1-GP
3 PCLK_FWH 1

PCLK_FWH

DIS
1

1
DY EC47
SC5P50V2CN-2GP Wistron Corporation 1
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
BIOS
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 29 of 48
A B C D E
 5 4 3 2 1

TOUCH PAD
5V_S0 5V_S0

1
2
1
EC59 EC60

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
D RN45 DY DY D

2
SRN10KJ-5-GP

TP1

3
4
7

28 TPCLK 2 3 TP_CLK 2
28 TPDATA 1 4 TP_DATA 3
24 TP_BTN_L 4
RN44 24 TP_BTN_R 5
SRN33J-5-GP-U 6

ACES-CON6-12-GP

1
20.K0358.006
EC57 EC58 20.K0392.006

2
SC100P50V2JN-3GP

SC100P50V2JN-3GP
DY DY

C C

B B

DIS
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Touch PAD
Size Document Number Rev

JM41_Discrete -1
Date: Thursday, April 09, 2009 Sheet 30 of 48

5 4 3 2 1
 5 4 3 2 1

3
Q8
DTC143ZUB-GP

R2
84.00143.E1K

R1
84.00143.G1K
D D

1
1 2 FRONT_PW RLED#_R FRONT_PW RLED#_R 26
28 PW RLED R147
FRONT_PW RLED# 150R2F-1-GP

SB

3
Q23
DTC143ZUB-GP

R2
84.00143.E1K

R1
84.00143.G1K

1
1 2 STDBY_LED#_R STDBY_LED#_R 26
28 STDBY_LED R339
STDBY_LED# 150R2F-1-GP
C C

13 MEDIA_LED#

3D3V_S0
1

R168
10KR2J-3-GP
Q9
2

R2
2
25,28 ALL_LED_OFF# 1 R1
3 MEDIA_LED#_Q 1 2 MEDIA_LED#_R MEDIA_LED#_R 25
R163 100R2J-2-GP

DTC143ZUB-GP
B
84.00143.G1K B
84.00143.E1K

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LED
Size Document Number Rev
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 31 of 48
5 4 3 2 1
 ODD Power
Run Power
3D3V_AUX_S5 -1 DCBATOUT

Q20 5V_S0 5V_S5

U50
NDS0610-NL-GP
84.00610.C31 1 8

2
5V_ODD_S0
S D
TP0610K-T1-GP RUN_POW ER_ON 2 7
5V_S0
S D
R335 U49 R332 3 S D 6
100KR2J-1-GP 1 2 Z_12V S D 4 G D 5
1 GND VOUT 8

1
2 7 10KR2J-3-GP

K
VIN VOUT SI4800BDY-T1

1
3 6 R333 C669

G
VIN VOUT

SCD22U25V3KX-GP
R334 D18 84.04800.D37

10KR2J-3-GP
28 ODD_PW R_EN# 4 EN# FLG# 5
R336 PDZ9D1B-GP 84.08884.037

2
1

330KR2J-L1-GP
C504 C672 1 2 Z_12V_G3 83.9R103.C3F

2
SC4D7U16V5ZY-GP RT9715BGF-GP SC4D7U16V5ZY-GP 83.9R103.F3F

A
1
330KR2J-L1-GP

2
R337
74.09715.B79 100KR2J-1-GP
2ND = 74.00547.079 Z_12V_D4

2
Q21
1D5V_S3
4 3 1D5V_S0
U18

Z_12V_D3
1

3
Q21 5 2 1 8
2N7002KDW -GP PM_SLP_S3# 14,28,36,39,40 S D
2 S D 7
84.DM601.03F 6 1 3 S D 6
4 5

4
G D
2N7002EDW -GP
84.27002.G3F SI4800BDY-T1
84.04800.D37
84.08884.037

R96
SM_PW ROK_R 1 2 1D05V_S0

0R2J-2-GP

2
DY R237
56R2F-1-GP
3D3V_S5 U23
1

1
B S3_PW RGD 35
R88 5 VCC
A 2 PM_SLP_S4# 14,28,35,37 PM_THRMTRIP-A# 4,8,13
8 SM_PW ROK 1 2 SM_PW ROK_R 4 Y
GND 3
3D3V_AUX_S5
12KR2F-L-GP
2

74LVC1G08GW -1-GP

E
73.01G08.L04
R97 73.01G08.L03 1 2 H_PW RGD# B
10KR2J-3-GP 4,13 H_PW RGD Q14

3
R229 MMBT2222A-3-GP
1

C
1
1KR2J-1-GP 84.02222.V11 R234 D13
C547 2ND = 84.02222.R11 10KR2J-3-GP BAS16-1-GP
SC2D2U16V3KX-GP 3RD = 84.02222.S11 DY 2ND = 83.00016.K11

2
R115

2
3RD = 83.00016.F11

2
PW ROK 1 2 83.00016.B11

0R2J-2-GP 2
3D3V_S5 U26 DY 3 RSMRST# RSMRST# 27,28
B 1 S0_PW R_GOOD 28
5 VCC 25,28 3V/5V_EN 1

1
2 VR_PW RGD_R 2 1
A R98 VR_PW RGD 14,28,34 D12 BAS16-1-GP C554
8,14 PW ROK 4 Y DY
3 10KR2J-3-GP 83.00016.B11 SCD1U16V2ZY-2GP

2
GND 2ND = 83.00016.K11
D5
74LVC1G08GW -1-GP 1 BAS16-1-GP 3RD = 83.00016.F11
73.01G08.L04
73.01G08.L03 3 PM_SLP_S3# 14,28,36,39,40
2 83.00016.B11
2ND = 83.00016.K11
3RD = 83.00016.F11

DY

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
RUN & ODD POWER
Size Document Number Rev
JM41_Discrete -1
Date: W ednesday, April 15, 2009 Sheet 32 of 48
 5 4 3 2 1

CPU_CORE
ISL6261A RT8202 RT8202
1D05V_S0 1D5V_S3
VID Setting Output Signal
VID0
VID0(I / 3.3V) VR_PWROK DCBATOUT_8202_1D05V 1D05V_S0 (10A) DCBATOUT_8202_1D5V 1D5V_S3 (11A)
PGOOD VIN 1D5V(O) VIN 1D5V(O)
D
VID1 D
VID1(I / 3.3V)
VID2 PM_SLP_S3# CPUCORE_ON PM_SLP_S4# CPUCORE_ON
VID2(I / 3.3V) EN PGOOD EN PGOOD
VID3
VID3(I / 3.3V)
Output Power
VID4
VID4(I / 3.3V) VCC_CORE(Imax=18A)
VCC_CORE_PWR(O)
VID5
VID5(I / 3.3V)
VID6 GFX_CORE
VID6(I / 3.3V) RT9026 0D9V_S0
ISL6263A 5V_S5
Input Signal VIN
CPUCORE_ON VID Setting Output Signal 1D5V_S3 0D75V_S3 (1.2A)
EN (I / 3.3V) VID0 CPUCORE_ON VLDOIN VTT
VID0(I / 3.3V) PGOOD
C C
VID1 PM_SLP_S4#
Voltage Sense VID1(I / 3.3V) S3 0D75V_S3_1
VTTREF
VCC_SENSE VID2
VSEN(I / Vcore) VID2(I / 3.3V) S5
VSS_SENSE VID3
RGND(I / Vcore) VID3(I / 3.3V)
VID4
VID4(I / 3.3V)
Input Power
Input Power Output Power
DCBATOUT_6261A 5V_S0
VCC(I) VDD Charger MAX8731A
VCC_GFXCORE(7A)
5V_S0 DCBATOUT_6263A VGFXCORE (O)
VCC(I) VIN
Input Signal Output Signal
3D3V_S0
VCC(I) CHG_ON# AC_IN#
B Input Signal CHGEN# ACGOOD# B
PM_SLP_S3#
VR_ON AD_IA
24750_CELLS SRSET
GFXVR_EN CELLS

TPS51125 Voltage Sense

VCC_AXG_SENSE
5V/3D3V VSEN(I / Vcore) Input Power Output Power
VSS_AXG_SENSE
RGND(I / Vcore) AD+ BT+
Input Power Output Power ACN VOUT (O)
DCBATOUT_51125 5V_S5 (6A)
VIN 5V(O) VOUT (O) DCBATOUT
Adapter
Input Signal 3D3V_S5 (5A) Input Signal Output Signal
S5_ENABLE 3D3V(O) AD_IN# DIS
EN0 AD_OFF (I) (O)
A 5V_AUX_S5 A
5V(O) Wistron Corporation
Output Signal 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
ALW_PWRGD_3V_5V Input Power Output Power Taipei Hsien 221, Taiwan, R.O.C.
PGOOD 3D3V_AUX_S5
3D3V(O) AD_JK AD+ Title
VCC(I) VCC(O)
Power Sequence Logic
5V_AUX_S5 Size Document Number Rev
VCC(I) B
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 33 of 48
5 4 3 2 1
 5 4 3 2 1

3D3V_S0
D D
DCBATOUT DCBATOUT_6261A R23 1 0R0402-PAD
2 H_DPRSTP# 4,8,13
G8 1 R31 2 499R2F-2-GP PM_DPRSLPVR 8,14
1 2

1
R30 1 0R0402-PAD
2 CPUCORE_ON 36
GAP-CLOSE-PWR R24
G9 10R2F-L-GP
1 2

2
GAP-CLOSE-PWR
H_VID[6..0] 5

1
G10 6261A_VID0 0R0402-PAD2 1 R18 H_VID0
1 2 R25 6261A_VID1 0R0402-PAD2 1 R20 H_VID1
1

1
1K91R2F-1-GP C55 6261A_VID2 0R0402-PAD2 1 R22 H_VID2
TC18 GAP-CLOSE-PWR 6261A_VID3 0R0402-PAD2 1 R21 H_VID3
ST15U25VDM-1-GP

G11 6261A_VID4 0R0402-PAD2 1 R27 H_VID4 DCBATOUT_6261A

SCD1U10V2KX-5GP
2

6261A_PWRGOOD 2

2
1 2 6261A_VID5 0R0402-PAD2 1 R28 H_VID5
6261A_VID6 0R0402-PAD2 1 R29 H_VID6
GAP-CLOSE-PWR
G6

6261A_AGND

1
1 2 C421 C420 C28 C30

5
6
7
8
6261A_CORE_ON
6261A_DPRSTP#

6261A_DPRSLP
GAP-CLOSE-PWR U2

D
D
D
D
6261A_3V3

SC4D7U25V5MX-1GP

SC4D7U25V5MX-1GP

SC4D7U25V5MX-1GP
R19

SCD1U50V3KX-GP
FDMS8692-GP

6261A_VID6

6261A_VID5

6261A_VID4

6261A_VID3
14,28,32 VR_PWRGD 1 2 P_84.01426.037

0R0402-PAD

G
S
S
S
4
3
2
1
40

39

38

37

36

35

34

33

32

31
U4

PGOOD

DPRSLPVR

VR_ON
3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3
6261A_AGND 41 GND_T
C 30 6261A_VID2 C
VID2

5
6
7
8

5
6
7
8
6261A_DPRSLP 1 FDE

D
D
D
D

D
D
D
D
29 6261A_VID1 U6 U5
VID1

FDMS7672-GP

FDMS7672-GP
DY C44 R17
6261A_AGND 1 2 6261A_PMON_R 1 DY 2 6261A_PMON 2 PMON 6261A_VID0
VID0 28
SC1KP50V2KX-1GP 40K2R2F-GP

G
S
S
S

G
S
S
S
1 2 6261A_RBIAS 3 RBIAS 5V_S0
6261A_AGND R16 147KR2F-GP C39

4
3
2
1

4
3
2
1
VCCP 27 1 2
4 VR_TT# SC4D7U10V5KX-4GP Iomax=18A
26 6261A_LGATE
5 NTC
LGATE OCP>=27A
C35 25 P_84.01712.037 P_84.01712.037 VCC_CORE
6261A_SOFT VSSP
6261A_AGND 1 2 6 SOFT R146
L16
R15
SCD015U25V3KX-GP 24 6261A_PHASE 1 2 VCC_CORE_R 1 2
6261A_VO 6261A_OCSET PHASE IND-D36UH-9-GP
1 2 7 OCSET 68.R3610.20A
D003R3720F-1-GP-U

1
11K3R2F-2-GP
1 R14 2 6261A_VW 8 VW UGATE 23 6261A_UGATE TC1 TC3
R13 C31

2
P_77.C3371.051
SE330U2VDM-L-GP

P_77.C3371.051
SE330U2VDM-L-GP
6K81R2F-1-GP CYNTEC 1.5uH

2
C26 6261A_COMP 9 22 BOOT 1 2BOOT_R 1 2
COMP BOOT Idc=9A 6.5*6.9*3 G71 G72
1 2
0R3J-0-U-GP SCD22U50V5KX-3GP DCR=14mOhm

GAP-CLOSE-PWR

GAP-CLOSE-PWR
DROOP

SC1KP50V2KX-1GP 10 21 6261A_AGND

1
FB NC#21
VDIFF

VSUM
VSEN

VDD
RTN

DFB

VSS
VIN
VO

ISL6261ACRZ-T-GP
11

6261A_VSEN 12

13

14

15

16

17

18

19

20
B 6261A_FB R7 B
6261A_DROOP

5V_S0_ISL6261 1
6261A_RTN

6261A_DFB

1 2 2 5V_S0
6261A_VO

C16 R11 R12 C18 2D2R5F-2-GP

6261A_SUM_R
1 26261A_FB_R 1 2 1 2 SC1U10V3KX-3GP
U33_VDIFF_1

1
1KR2F-3-GP
SC120P50V3JN-GP 330KR2F-L-GP 1 2 6261A_AGND TC5 TC6

2
P_77.C3371.051
SE330U2VDM-L-GP

P_77.C3371.051
SE330U2VDM-L-GP
C22 R10 C17 C15 SCD1U25V3KX-GP
1 2 1 2U33_VDIFF_2 1 2 6261A_VIN 2 1 DCBATOUT_6261A
R8 10R3J-3-GP
SC82P50V2JN-3GP 1K58R3F-GP SC1200P50V2KX-1GP
R4
6261A_SUM 1 2
R3

5 VCORE_VCCSENSE 1 2 100R2F-L1-GP-U
1

C10
0R0603-PAD
1

SC180P50V2JN-1GP
R1
2

C20
SCD01U25V2KX-3GP 1 2 6261A_VO_R
R2
2

5 VCORE_VSSSENSE 1 2 0R2J-2-GP
R5
1
SCD01U25V2KX-3GP

1KR2F-3-GP
0R0603-PAD C9
2

SCD1U25V3KX-GP
2

2
1

R6 C13 C14 C12

1

100R2J-2-GP SCD01U25V2KX-3GP
SC330P50V2KX-3GP
2

G73
1

R9 1 2
330R2F-GP 6261A_AGND
GAP-CLOSE-PWR
6261A_AGND
2

A 6261A_AGND 6261A_AGND A

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
ISL6261A_CPU CORE
Document Number Rev
Custom
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 34 of 48
5 4 3 2 1
 5 4 3 2 1

DCBATOUT DCBATOUT_8202_1D5V

G68
1 2 1D5V_PW R 1D5V_S3
D
20090109 G54 D
GAP-CLOSE-PW R 1 2
G69
1 2 GAP-CLOSE-PW R
G53
GAP-CLOSE-PW R 1 2
G70
1 2 GAP-CLOSE-PW R
G55

1
TC22 GAP-CLOSE-PW R 1 2
G67
20090109
ST15U25VDM-1-GP
1 2 GAP-CLOSE-PW R
2 G56
GAP-CLOSE-PW R 1 2
G66 DCBATOUT_8202_1D5V
1 2 GAP-CLOSE-PW R
G51
GAP-CLOSE-PW R 1 2
G65
1 2 GAP-CLOSE-PW R

1
G49
GAP-CLOSE-PW R C402 C375 C383 1 2

5
6
7
8

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
1

2
U25 GAP-CLOSE-PW R

D
D
D
D
G48
FDMS8692-GP Iomax=11A 1 2
OCP>16A GAP-CLOSE-PW R

G
S
S
S
G47
C 5V_S5 1 2 C
20090109

4
3
2
1
GAP-CLOSE-PW R

1
G52
R139 RT8202_DH_1D5V Vout=1.5V 1D5V_PW R 1 2
10R2F-L-GP L26
20090109 RT8202_LX_1D5V 1 2 GAP-CLOSE-PW R
5V_S5 G50

2
IND-1D5UH-34-GP 1 2

1
RT8202_VDD_1D5V

DCBATOUT_8202_1D5V 68.1R510.10J C654 GAP-CLOSE-PW R

5
6
7
8

SCD1U10V2KX-4GP
C406 D6 68.1R51A.10G TC16

1
D
D
D
D
SC1U10V3KX-3GP CH521S-30-GP-U1 U20 68.1R51A.10E R135 SE330U2D5VM-GP
2

2
3D3V_S5 R138 FDMS7672-GP C403 21K5R3F-GP P_77.C3371.10L
1 2 RT8202_TON_1D5V 5V_S5 SC47P50V2JN-3GP

2
RT8202_BST_1D5V

2
1

820KR2F-GP C405

G
S
S
S
R118 SC1KP50V2KX-1GP RT8202_FB_1D5V
1
10KR2J-3-GP
2

4
3
2
1

1
C401
SC1U10V3KX-3GP RT8202_DL_1D5V R133
2

32 S3_PW RGD 2 R119 1 21K5R3F-GP

2

0R0402-PAD U27 1 2 RT8202_LX_1D5V

1

VDD

VDDP

2
C398 DY R136 C404
SC100P50V2JN-3GP 16 13 RT8202_BST_1D5V_L 1 2 SCD1U25V3KX-GP
20090109
2

RT8202_PGOOD_1D5V TON BOOT RT8202_DH_1D5V 1R2F-GP

4 PGOOD UGATE 12
11 RT8202_LX_1D5V
R137 PHASE
8 RT8202_DL_1D5V
B LGATE R134 B
1 2 RT8202_EN_1D5V 15
14,28,32,37 PM_SLP_S4# EN/DEM
OC 10 RT8202_OC_1D5V 1 2 RT8202_LX_1D5V Vout=0.75*(1+Rh/Rl)
1

3 RT8202_FB_1D5V
0R0603-PAD C407 FB
5 NC#5 4K32R2F-GP
SCD1U25V3KX-GP 14 1 1D5V_PW R
DY
2

NC#14 VOUT
PGND

GND
GND

20090109
RT8202APQW -GP
7

17
6

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8202_1D5V
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 13, 2009 Sheet 35 of 48
5 4 3 2 1
 5 4 3 2 1

20090109
20090109

DCBATOUT DCBATOUT_8202_1D05V 1D05V_PW R 1D05V_S0

G20
D G4 1 2 D
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R G19
G5 1 2
1 2
GAP-CLOSE-PW R
GAP-CLOSE-PW R
20090109 G15
G7 1 2
1 2
1 GAP-CLOSE-PW R
TC17 GAP-CLOSE-PW R G13
G1 DCBATOUT_8202_1D05V 1 2
ST15U25VDM-1-GP

1 2
2

GAP-CLOSE-PW R
GAP-CLOSE-PW R G12
G2 1 2
DY 1 2

1
GAP-CLOSE-PW R
GAP-CLOSE-PW R C408 C414 C21 G16

5
6
7
8

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
G3 1 2

2
U1

D
D
D
D
1 2
FDMS8692-GP GAP-CLOSE-PW R
GAP-CLOSE-PW R G17
Iomax=10A 1 2
OCP>15A

G
S
S
S
GAP-CLOSE-PW R
5V_S5 G18
20090109

4
3
2
1
1 2
C C

1
GAP-CLOSE-PW R
R148 RT8202_DH_1D05V Vout=1.0515V 1D05V_PW R G21
10R2F-L-GP L15
20090109 1 2
RT8202_LX_1D05V 1 2
5V_S5 GAP-CLOSE-PW R

2
G22
IND-1D5UH-34-GP
1 2

1
DCBATOUT_8202_1D05V 68.1R510.10J C11
RT8202_VDD_1D05V

5
6
7
8

SCD1U10V2KX-4GP
C416 D7 68.1R51A.10G TC2 GAP-CLOSE-PW R

1
D
D
D
D
SC1U10V3KX-3GP CH521S-30-GP-U1 U3 68.1R51A.10E R156 SE330U2D5VM-GP G14
2

2
3D3V_S5 R149 FDMS7672-GP C424 4K02R3F-GP P_77.C3371.10L 1 2
1 2 RT8202_TON_1D05V 5V_S5 SC47P50V2JN-3GP

2
GAP-CLOSE-PW R

RT8202_BST_1D05V

2
1

820KR2F-GP C418

G
S
S
S
R159 SC1KP50V2KX-1GP RT8202_FB_1D05V
10KR2J-3-GP 1
2

4
3
2
1

1
C423
SC1U10V3KX-3GP RT8202_DL_1D05V R155
2

2 R157 1 10KR3F-L-GP
34 CPUCORE_ON
2

0R0402-PAD U28 1 2 RT8202_LX_1D05V

1

VDD

VDDP

2
C426 DY R151 C419
SC100P50V2JN-3GP 16 13 RT8202_BST_1D05V_L1 2 SCD1U25V3KX-GP
20090109
2

RT8202_PGOOD_1D05V TON BOOT RT8202_DH_1D05V

4 PGOOD UGATE 12
11 RT8202_LX_1D05V 0R2J-2-GP
R150 PHASE
8 RT8202_DL_1D05V
RT8202_EN_1D05V LGATE R154
14,28,32,39,40 PM_SLP_S3# 1 2 15 EN/DEM
10 RT8202_OC_1D05V 1 2 RT8202_LX_1D05V
OC Vout=0.75*(1+Rh/Rl)
1

B RT8202_FB_1D05V B
FB 3
0R0603-PAD C415 5 4K53R2F-1-GP
DY SCD1U25V3KX-GP 14
NC#5
1 1D05V_PW R
2

NC#14 VOUT
PGND

GND
GND

20090109
RT8202APQW -GP
7

17
6

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8202_1D05V
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 13, 2009 Sheet 36 of 48
5 4 3 2 1
 5 4 3 2 1

Iomax=1.2A
OCP>2A

5V_S5 1D5V_S3 DDR_VREF_PW R DDR_VREF_S3

D D

2
C127 C122 DY C121 G23
SC1U10V2KX-1GP SC10U10V5KX-2GP SCD1U10V2KX-4GP 1 2

1
GAP-CLOSE-PW R
G24
U7 1 2

10 1 GAP-CLOSE-PW R
0R0603-PAD 1 R41 9026_S5 VIN VDDQSNS G25
14,28,32,35 PM_SLP_S4# 2 9 S5 VLDOIN 2
8 GND VTT 3 1 2
0R0603-PAD 1 R40 2 9026_S3 7 4
S3 PGND GAP-CLOSE-PW R
DDR_VREF_S3_1 6 VTTREF VTTSNS 5

GND
1

1
C125 C119 C116
SC1U10V2KX-1GP RT9026PFP-GP SC10U10V5KX-2GP SC10U10V5KX-2GP

11

2
C C

B B

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT9026_0D75V
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 37 of 48
5 4 3 2 1
 5 4 3 2 1

D
DCBATOUT_6263A DCBATOUT D

C618 GFX
1 R292 2 0R0402-PAD POWER_MONITOR 1 2 VGFXCORE VCC_GFXCORE
8 GFXVR_EN

1
SCD01U50V2KX-1GP GFX_VID[4..0] 8 G26
R289 1 2
G35 10KR2J-3-GP
1 2 1 2 GFX GAP-CLOSE-PWR
R291 100KR2J-1-GP G27

2
GAP-CLOSE-PWR 6236A_VID4 1 R288 2 0R0402-PAD GFX_VID4 1 2
G36

1
1 2 TC19 6236A_VID3 1 R287 2 0R0402-PAD GFX_VID3 GAP-CLOSE-PWR
G28

ST15U25VDM-1-GP
GAP-CLOSE-PWR 6236A_VID2 1 R286 2 0R0402-PAD GFX_VID2 1 2

2
G37
1 2 GFX 6236A_VID1 1 R285 2 0R0402-PAD GFX_VID1 GAP-CLOSE-PWR
1 2 G32
3D3V_S0
GAP-CLOSE-PWR DY R290 10KR2J-3-GP 6236A_VID0 1 R284 2 0R0402-PAD GFX_VID0 1 2
G38
1 2 GAP-CLOSE-PWR
TPAD14-GP TP81 1 G29
GAP-CLOSE-PWR 1 2

GAP-CLOSE-PWR
G33

6236A_VR_ON
6236A_AF_EN
6236A_GOOD

6236A_PMON
1 2

GAP-CLOSE-PWR
G30
1 2
5V_S0
DCBATOUT_6263A
GAP-CLOSE-PWR

2
C243 C239 G34

33

32

31

30

29

28

27

26

25

1
U37 C246 1 2
R272 SCD1U50V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
FDE

VID4

VID3

VID2
GND_T

PGOOD

AF_EN

VR_ON

PMON

1
5
6
7
8
150KR2F-L-GPGFX 0R0402-PAD GFX DY GAP-CLOSE-PWR
U12 G31

D
D
D
D
C R2761 2 6236A_RBIAS 1 24 FDMS8692-GP
VGFXCORE Iomax=7A 1 2 C

2
RBIAS VID1
GFX OCP>10.5A
R267
C6101 2GFX 6236A_SOFT 2 23 GFX GAP-CLOSE-PWR
SCD01U50V2KX-1GP SOFT VID0 C606
GFX Cyntec 7*7*3

G
S
S
S
6263A_VCC_PRM 1 2 6236A_OCSET 3 22 6236A_PVCC 1 2 Id=7A
C603 OCSET PVCC DCR=8mohm, Irating=13A
GFX

4
3
2
1
C601 Qg=8.7~13nC
1 2 GFX 6236A_VW 4 21 6236A_LGATE SC2D2U10V3KX-1GP Isat=24A
8K66R2F-GP VW LGATE
1 2 Rdson=23~30mohm
GFX SC1KP50V2KX-1GP 6236A_COMP 5 20
SC68P50V2JN-1GP COMP PGND
1 R259 2 L21
C597 6K98R3F-GP 6 19 6236A_PHASE 1 2
FB PHASE VGFXCORE
1 R252 2 6236A_COMP_R 1 2 GFX 6236A_FB
374KR3-GP 7 18 6236A_UGATE COIL-1UH-34-GP-U
SC180P50V2JN-1GP VDIFF UGATE
GFX GFX

DROOP
GFX 8 17 6236A_BOOT
1 2 1 2
VSEN BOOT

VSUM
68.1R01A.20B

6236A_BOOT_R
R255

VDD
RTN

DFB

VSS
VIN
VO
2D2R3J-2-GP C600 68.1R01B.10N

5
6
7
8
R2531 22K21R3F-L-GP 6236A_VDIFF SCD22U16V3KX-2-GP
GFX U13
GFX

D
D
D
D
9 GFX
10

11

12

13

14

15

16
C553 ISL6263ACRZ-T-GP FDMS7672-GP
1 R251
2 6236A_FB_R 6236A_VSEN 6236A_DROOP GFX

1
1

GFX 4K99R2F-L-GP

6236A_VSUM
6263A_VCC_PRM
SC560P50V2KX-2GP 6236A_DFB G77 G76

6236A_VIN
R247

6236A_VDD

G
S
S
S
GFX 6236A_RTN GAP-CLOSE-PWR GAP-CLOSE-PWR
1 2 5V_S0

4
3
2
1

2
GFX
10R2F-L-GP
GFX
R238
C594 Id=7.7A
C591 1 2 1 2 5V_S5 Qg=8.5~13nC
1 2 SC1U16V3KX-2GP 10R2F-L-GP Rdson=16.5~21mohm
2

DY
1

SC1KP50V2KX-1GP R249
C588 C587 GFX R245
GFX
SC1KP50V2KX-1GP GFX SC1KP50V2KX-1GP 1 2 DCBATOUT
2

2K32R2F-1-GP

DY DY
1

10R2F-L-GP
R274
1

1 2

1
B C546 C585 GFX TC12 B
1

GFX SCD01U25V2KX-3GP
SC330P50V2KX-3GP

0R0402-PAD

SE220U2VDM-8GP
P_80.2271V.A9L

2
1
2

G79 GAP-CLOSE-PWR R233 GFX

10 VCC_AXG_SENSE 1 2 GFX 1KR3F-GP

R224
2

G78 GAP-CLOSE-PWR C540

10 VSS_AXG_SENSE 1 2 1 2 GFX 1 2 6236A_VSUM_R
1

C534 GFX SCD033U25V3KX-GP

C552 7K68R2F-GP
SCD1U25V3KX-GP

1 2 GFX
2
1

1
R232 R231 GFX G40 G39
10R3F-GP 10R3F-GP SCD022U25V2KX-GP GAP-OPEN-PWR GAP-OPEN-PWR
1 R248 2GFX

2
2

GFX 4K53R2F-1-GP 6236A_VSUM_R_VCC_PRM

GFX GFX Close to choke 1 R226 2 1 R225 2

3K57R2F-GP
and on the same layer NTC-10K-27-GP
GFX

Parallel
VSS_AXG_SENSE_OUTCAP

VCC_AXG_SENSE_OUTCAP

A A

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ISL6263A_GFX CORE
Size Document Number Rev
A2
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 38 of 48
5 4 3 2 1
 5 4 3 2 1

DCBATOUT DCBATOUT_8202_VGA
G45
1 2

GAP-CLOSE-PW R
G44 5V_S0
1 2

1
GAP-CLOSE-PW R
G43 R319
1 2 10R2F-L-GP
1

TC14
D GAP-CLOSE-PW R 5V_S0 DCBATOUT_8202_VGA D

2
ST15U25VDM-1-GP

G42 RT8202_VDD_VGA
2

1 2

1
C663 D17
GAP-CLOSE-PW R SC1U10V3KX-4GP
DCBATOUT_8202_VGA C316 C338 C333 C341 Iomax=7.8A, OCP>12A

5
6
7
8

1
3D3V_S0 CH521S-30-GP-U1
VGA_CORE_PW R +VGA_CORE

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
1 R320 RT8202_TON_VGA 5V_S0 U22

D
D
D
D
2 20090220

2
1MR2F-GP

RT8202_BST_VGA
FDMS8692-GP

2
1

1
C662 P_84.01426.037 G63
R301 SC1KP50V2KX-1GP 1 2

1
10KR2F-2-GP C642

G
S
S
S
SC1U10V3KX-4GP GAP-CLOSE-PW R
R302
G62
2

4
3
2
1
2 1 C652 1 2
14,40,42 G_VCORE_PGOOD 20090220

9
U48 1 2RT8202_LX_VGA
1

0R0402-PAD-1-GP RT8202_DH_VGA VGA_CORE_PW R GAP-CLOSE-PW R

VDD

VDDP
L25
C643 R317 SCD1U25V3KX-GP G61
SC100P50V2JN-3GP 16 13 RT8202_BST_VGA_L
1 2 RT8202_LX_VGA 1 2 1 2
2

RT8202_PGOOD_VGA TON BOOT RT8202_DH_VGA 1R2F-GP

4 PGOOD UGATE 12
11 RT8202_LX_VGA IND-1D5UH-23-GP C653 GAP-CLOSE-PW R
R322 PHASE RT8202_DL_VGA G60
LGATE 8 R305

5
6
7
8
1 2 RT8202_EN_VGA 15 1 2
14,40 ATI_PW R_ON EN/DEM

1
D
D
D
D

SCD1U10V2KX-4GP
0R2J-2-GP
OC 10 RT8202_OC_VGA_L 1 2 RT8202_LX_VGA U21 68.1R510.10K
2

3 RT8202_FB_VGA FDMS7672-GP TC15 GAP-CLOSE-PW R

C664 FB 3KR2F-GP P_84.01712.037 G59
5

2
NC#5

P_77.C3371.051
SE330U2VDM-L-GP
14 1 VGA_CORE_PW R 68.1R510.10Y 1 2
DY
SCD1U25V3KX-GP
1

NC#14 VOUT

PGND

G
S
S
S
GAP-CLOSE-PW R
20090220

GND
GND
C R321 G58 C

4
3
2
1
14,28,32,36,40 PM_SLP_S3# 1 2 20090220 1 2
0R2J-2-GP RT8202APQW -GP

17
6
GAP-CLOSE-PW R
G57
DY
1 2
RT8202_DL_VGA
GAP-CLOSE-PW R
G46
1 2
RT8202_FB_VGA
GAP-CLOSE-PW R

Vout=0.75*(1+Rh/Rl)
1
1

R310
C651 12KR2F-L-GP RT8202_FB_VGA
SC47P50V2JN-3GP
2

1
2

R304 R303 R300

187KR2F-GP 30KR2F-GP 47KR2F-GP
1

M92_LP M92_XT
R307
2

2
59KR2F-GP
G_VID1_R

G_VID0_R
B B
2

D
Q19 Q18
R331 R308
2N7002-11-GP 2N7002-11-GP
G G_VID1 1 2 G G_VID0 1 2
84.27002.Y31 VCORE_VID1 43 84.27002.Y31 VCORE_VID0 43
1

1
S

S
C668 10KR2J-3-GP C649 10KR2J-3-GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2

2
M92_LP core power M92_XT core power
ALTV1 ALTV0 Vout ALTV1 ALTV0 Vout
0 0 0.90V 0 0 0.90V
0 1 1.09V 0 1 1.09V
1 0 0.95V 1 0 1.2V
A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8202A_VGA CORE
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 39 of 48
5 4 3 2 1
 5 4 3 2 1

SB ATI_PWR_ON ATI_PWR_ON 14,39

D D
+1.5V to +1.5VS_RUN Transfer

D
Q22
2N7002-11-GP
14 ATI_PWR_ON#
ATI_PWR_ON# G
84.27002.Y31
3D3V_S0 +3VS to 1.8V Transfer AO4468, SO-8
Id=11.6A, Qg=9~12nC

S
Rdson=17.4~22m ohm
1D5V_S3 +1.5V_RUN

2
SC1U10V2ZY-GP
C627
U17 1.5v (6A)
8 1

1
D S
7 D S 2
+1.8V_RUN 6 3

1
D S
2 U40 5 4 C622

1
D G
SCD1U16V2KX-3GP TC13
ATI_PWR_ON 3 1 5
I/O 1.8v = 1.9A C302 ST150U6D3VBM-2-GP

2
VIN VOUT C621 SI4800BDY-T1
2

2
GND

SC1U10V3KX-3GP
1 G_ENVCC18 3 4 SC10U10V5ZY-1GP 84.04800.D37
EN/EN# NC#4

1
84.08884.037
BAS16-1-GP D15 C611

2
1
83.00016.B11 C625 RT9198-18PBR-GP SC10U10V5ZY-1GP

2
2ND = 83.00016.K11 SC2D2U6D3V2MX-GP 74.09198.C7F RUN_POWER_ON
3RD = 83.00016.F11 74.09091.G3F

2
2ND = 84.00610.C31
R294 84.S0610.B31
14,28,32,36,39 PM_SLP_S3# 1 2 -1 Q16
NDS0610-NL-GP
0R2J-2-GP

S D RUNON_R
DY

G
R283
C R263 C
14,39,42 G_VCORE_PGOOD 1 2
1 2
0R2J-2-GP

1
330KR2J-L1-GP
R260 R345
100KR2J-1-GP 330KR2J-L1-GP

2
-1

DIS_EN_1D5_RUN
+3VS to 3.3V_DELAY Transfer
3.3v (115mA) VDDR3

Q13
R250 AO3413-GP

D
470R2J-2-GP
2 1 D S 3D3V_S0 Q15
R235 2N7002-11-GP
G_VCORE_PGOOD 1 2 G 84.27002.Y31
2

VDDR3discharge CKT 0R2J-2-GP

G

R228

S
100KR2J-1-GP
-1
D

Q12
1

2N7002-11-GP
G R236
84.27002.Y31 14,28,32,36,39 PM_SLP_S3# 1 2
0R2J-2-GP
S

B B
DY
D

Q11

G_ENVCC18 1 2 G
2N7002-11-GP +1.5v to PCIE 1.1V Transfer
R223 84.27002.Y31
1

51KR2F-L-GP
S

C533 5V_S5
2

+1.5V_RUN
SCD1U10V2KX-4GP

2
1

ATI_PWR_ON 3 C619
SC1U10V2KX-1GP SC10U6D3V3MX-GP
2

1 U15 1
C296
VCNTL

BAS16-1-GP D3 7 5 2 +1.1V_RUN
83.00016.B11 POK VIN
2ND = 83.00016.K11 R346 VIN
9
PCIE 1.1v (2.2A)
3RD = 83.00016.F11 G_ENVCC18 1 2 G_ENVCC11 8 3 SC47P50V2JN-3GP SC10U6D3V3MX-GP
0R2J-2-GP EN VOUT
4
VOUT

SC22U6D3V5MX-2GP
1

C304 R55 1
DY
1

1
2 10KR2F-2-GP C247 C245 1 C242
-1
GND

FB
L27 R1 DY
2

2
-1
2

2
G_ENVCC18 2 1 APL5913-KAC-1-GP
1

MLVG04025R0QV05BP-GP
EMI SCD1U10V2KX-4GP
1

R54
25K5R2F-GP Vout=0.8 x [1+(R1/R2)]
DY
A R2 A
2

L28 DIS
N76924178 2 1

MLVG04025R0QV05BP-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DY Title

M92S2 power
Size Document Number Rev
Custom
JM41_Discrete -1
Date: Monday, April 13, 2009 Sheet 40 of 48
5 4 3 2 1
 5 4 3 2 1

3D3V_S0
SB VDDR3
1D8V_NB_S0
U11

2
1
1
2
8 GMCH_TXAOUT0+ 38 ATMDS2+ VDD 2

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
37 8 C230 C240 C241 RN11
8 GMCH_TXAOUT0- ATMDS2- VDD SRN2K2J-1-GP
8 GMCH_TXAOUT1+ 36 ATMDS1+ VDD 16 SRN2K2J-1-GP
35 18 RN20

2
8 GMCH_TXAOUT1- ATMDS1- VDD
34 20

3
4
8 GMCH_TXAOUT2+ ATMDS0+ VDD
D 33 30 D

4
3
8 GMCH_TXAOUT2- ATMDS0- VDD
8 GMCH_TXACLK+ 32 ATMDSCLK+ VDD 40
8 GMCH_TXACLK- 31 ATMDSCLK- VDD 42
G_LCD_EDID_CLK GMCH_DAT_DDC_EDID
29 G_LCD_EDID_DAT GMCH_CLK_DDC_EDID
42 VGA_TXAOUT0+ BTMDS2+
42 VGA_TXAOUT0- 28 BTMDS2- TMDS2+ 3 LCD_TXAOUT0+ 19
42 VGA_TXAOUT1+ 27 BTMDS1+ TMDS2- 4 LCD_TXAOUT0- 19
26 6 LCD_TXAOUT1+ 19 3D3V_S0
42 VGA_TXAOUT1- BTMDS1- TMDS1+
42 VGA_TXAOUT2+ 25 BTMDS0+ TMDS1- 7 LCD_TXAOUT1- 19
42 VGA_TXAOUT2- 24 BTMDS0- TMDS0+ 11 LCD_TXAOUT2+ 19 U31
42 VGA_TXACLK+ 23 BTMDSCLK+ TMDS0- 12 LCD_TXAOUT2- 19
42 VGA_TXACLK- 22 BTMDSCLK- TMDSCLK+ 14 LCD_TXACLK+ 19
TMDSCLK- 15 LCD_TXACLK- 19 8 GMCH_DAT_DDC_EDID 3 B0 A 4 LCD_EDID_DAT 19
2 GND VCC 5
DIS_EN 9 1 6
SEL 43 G_LCD_EDID_DAT B1 S
VSS 1
VSS 5
10 NC7SB3157P6X-1GP
VSS
VSS 13 73.03157.C0H
VSS 17
VSS 19
VSS 21
VSS 39
41
GND

VSS

U32
TS3DV421RUAR-GP
43

71.03421.003
71.03412.B0G 8 GMCH_CLK_DDC_EDID 3 B0 A 4 LCD_EDID_CLK 19
C 71.03412.C0G 2 5 C
GND VCC
43 G_LCD_EDID_CLK 1 B1 S 6

NC7SB3157P6X-1GP
73.03157.C0H

14,19,20 DIS_EN

RN5

43 G_LCD_EDID_DAT 4 1 LCD_EDID_DAT 19
43 G_LCD_EDID_CLK 3 2 LCD_EDID_CLK 19

SRN0J-6-GP
DY

B B

5V_S0
SCD1U10V2KX-4GP C521 U34
2 1 16 VCC
14,19,20 DIS_EN DIS_EN DIS_EN 1 4
S YA CRT_BLUE 20
8 GMCH_BLUE 2 IA0
43 G_BLUE 3 IA1 YB 7 CRT_GREEN 20
8 GMCH_GREEN 5 IB0
RN29 43 G_GREEN 6 IB1 YC 9 CRT_RED 20
8 GMCH_RED 11 IC0
42 VGA_TXAOUT0+ 1 8 LCD_TXAOUT0+ 19 43 G_RED 10 IC1 YD 12
42 VGA_TXAOUT0- 2 7 LCD_TXAOUT0- 19 14 ID0
42 VGA_TXAOUT1+ 3 6 LCD_TXAOUT1+ 19 13 ID1 OE# 15
42 VGA_TXAOUT1- 4 5 LCD_TXAOUT1- 19 8 GND
PI5C3257QE-GP
SRN0J-7-GP
73.53257.B0C
DY 2ND = 73.03257.C0B

RN30

A 42 VGA_TXAOUT2+ 1 8 LCD_TXAOUT2+ 19 DIS A

42 VGA_TXAOUT2- 2 7 LCD_TXAOUT2- 19
42 VGA_TXACLK+ 3 6 LCD_TXACLK+ 19
42 VGA_TXACLK- 4 5 LCD_TXACLK- 19 RN7 Wistron Corporation
1 8 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SRN0J-7-GP 43 G_BLUE CRT_BLUE 20 Taipei Hsien 221, Taiwan, R.O.C.
43 G_GREEN 2 7 CRT_GREEN 20
DY 3 6
4 5 Title
43 G_RED CRT_RED 20

SRN0J-7-GP
PX_SWITCH
Size Document Number Rev
DY A3 -1
Date: Monday, April 06, 2009 Sheet 41 of 48
5 4 3 2 1
 5 4 3 2 1

U113A 1 OF 7

D D

SSID = VIDEO
8 PEG_TXP0 AF30 AH30 RXP0 2 1 C248 SCD1U6D3V1KX-GP PEG_RXP0 8
PCIE_RX0P PCIE_TX0P
8 PEG_TXN0 AE31 AG31 RXN0 2 1 C249 SCD1U6D3V1KX-GP PEG_RXN0 8
PCIE_RX0N PCIE_TX0N

8 PEG_TXP1 AE29 AG29 RXP1 2 1 C250 SCD1U6D3V1KX-GP PEG_RXP1 8

PCIE_RX1P PCIE_TX1P RXN1
8 PEG_TXN1 AD28 AF28 2 1 C251 SCD1U6D3V1KX-GP PEG_RXN1 8
PCIE_RX1N PCIE_TX1N

AD30 AF27 RXP2 2 1 C277 SCD1U6D3V1KX-GP U113F 6 OF 7

8 PEG_TXP2 PCIE_RX2P PCIE_TX2P PEG_RXP2 8
8 PEG_TXN2 AC31 AF26 RXN2 2 1 C278 SCD1U6D3V1KX-GP PEG_RXN2 8
PCIE_RX2N PCIE_TX2N

AC29 AD27 RXP3 2 1 C279 SCD1U6D3V1KX-GP LVDS CONTROL AB11 G_L_BKLTCTL 43

8 PEG_TXP3 PCIE_RX3P PCIE_TX3P PEG_RXP3 8 VARY_BL
8 PEG_TXN3 AB28 AD26 RXN3 2 1 C280 SCD1U6D3V1KX-GP PEG_RXN3 8 AB12
PCIE_RX3N PCIE_TX3N DIGON G_LCDVDD_ON 19

8 PEG_TXP4 AB30 PCIE_RX4P PCIE_TX4P AC25 RXP4 2 1 C252 SCD1U6D3V1KX-GP PEG_RXP4 8

1
PCI EXPRESS INTERFACE
8 PEG_TXN4 AA31 AB25 RXN4 2 1 C253 SCD1U6D3V1KX-GP PEG_RXN4 8
PCIE_RX4N PCIE_TX4N R78 R75
TXCLK_UP_DPF3P AH20

10KR2J-3-GP

10KR2J-3-GP
TXCLK_UN_DPF3N AJ19
8 PEG_TXP5 AA29 Y23 RXP5 2 1 C254 SCD1U6D3V1KX-GP PEG_RXP5 8
PCIE_RX5P PCIE_TX5P
8 PEG_TXN5 Y28 Y24 RXN5 2 1 C255 SCD1U6D3V1KX-GP PEG_RXN5 8 AL21

2
PCIE_RX5N PCIE_TX5N TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N AK20

8 PEG_TXP6 Y30 PCIE_RX6P PCIE_TX6P AB27 RXP6 2 1 C256 SCD1U6D3V1KX-GP PEG_RXP6 8 TXOUT_U1P_DPF1P AH22
8 PEG_TXN6 W31 AB26 RXN6 2 1 C257 SCD1U6D3V1KX-GP PEG_RXN6 8 AJ21
PCIE_RX6N PCIE_TX6N TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P AL23
8 PEG_TXP7 W29 Y27 RXP7 2 1 C258 SCD1U6D3V1KX-GP PEG_RXP7 8 AK22
C PCIE_RX7P PCIE_TX7P TXOUT_U2N_DPF0N C
8 PEG_TXN7 V28 PCIE_RX7N PCIE_TX7N Y26 RXN7 2 1 C259 SCD1U6D3V1KX-GP PEG_RXN7 8
TXOUT_U3P AK24
TXOUT_U3N AJ23
8 PEG_TXP8 V30 W24 RXP8 2 1 C260 SCD1U6D3V1KX-GP PEG_RXP8 8
PCIE_RX8P PCIE_TX8P RXN8
8 PEG_TXN8 U31 W23 2 1 C261 SCD1U6D3V1KX-GP PEG_RXN8 8
PCIE_RX8N PCIE_TX8N LVTMDP

8 PEG_TXP9 U29 V27 RXP9 2 1 C262 SCD1U6D3V1KX-GP PEG_RXP9 8 AL15 VGA_TXACLK+ 41

PCIE_RX9P PCIE_TX9P RXN9 TXCLK_LP_DPE3P
8 PEG_TXN9 T28 U26 2 1 C263 SCD1U6D3V1KX-GP PEG_RXN9 8 AK14 VGA_TXACLK- 41
PCIE_RX9N PCIE_TX9N TXCLK_LN_DPE3N
AH16 VGA_TXAOUT0+ 41
RXP10 TXOUT_L0P_DPE2P
8 PEG_TXP10 T30
PCIE_RX10P PCIE_TX10P
U24 2 1 C264 SCD1U6D3V1KX-GP PEG_RXP10 8 TXOUT_L0N_DPE2N
AJ15 VGA_TXAOUT0- 41
8 PEG_TXN10 R31 U23 RXN10 2 1 C265 SCD1U6D3V1KX-GP PEG_RXN10 8
PCIE_RX10N PCIE_TX10N
AL17 VGA_TXAOUT1+ 41
TXOUT_L1P_DPE1P
AK16 VGA_TXAOUT1- 41
TXOUT_L1N_DPE1N
8 PEG_TXP11 R29 T26 RXP11 2 1 C266 SCD1U6D3V1KX-GP PEG_RXP11 8
PCIE_RX11P PCIE_TX11P RXN11
8 PEG_TXN11 P28 T27 2 1 C267 SCD1U6D3V1KX-GP PEG_RXN11 8 AH18 VGA_TXAOUT2+ 41
PCIE_RX11N PCIE_TX11N TXOUT_L2P_DPE0P
AJ17 VGA_TXAOUT2- 41
TXOUT_L2N_DPE0N
8 PEG_TXP12 P30 T24 RXP12 2 1 C268 SCD1U6D3V1KX-GP PEG_RXP12 8 AL19
PCIE_RX12P PCIE_TX12P TXOUT_L3P
8 PEG_TXN12 N31 T23 RXN12 2 1 C269 SCD1U6D3V1KX-GP PEG_RXN12 8 AK18
PCIE_RX12N PCIE_TX12N TXOUT_L3N

8 PEG_TXP13 N29 P27 RXP13 2 1 C270 SCD1U6D3V1KX-GP PEG_RXP13 8

PCIE_RX13P PCIE_TX13P RXN13
8 PEG_TXN13 M28
PCIE_RX13N PCIE_TX13N
P26 2 1 C271 SCD1U6D3V1KX-GP PEG_RXN13 8
M92-S2-GP

8 PEG_TXP14 M30 P24 RXP14 2 1 C272 SCD1U6D3V1KX-GP PEG_RXP14 8

PCIE_RX14P PCIE_TX14P RXN14
8 PEG_TXN14 L31 P23 2 1 C273 SCD1U6D3V1KX-GP PEG_RXN14 8
PCIE_RX14N PCIE_TX14N

8 PEG_TXP15 L29 M27 RXP15 2 1 C274 SCD1U6D3V1KX-GP PEG_RXP15 8

PCIE_RX15P PCIE_TX15P
8 PEG_TXN15 K30 N26 RXN15 2 1 C275 SCD1U6D3V1KX-GP PEG_RXN15 8
PCIE_RX15N PCIE_TX15N
B B

CLOCK
0201 CAPs
R293
3 CLK_PCIE_VGA AK30
PCIE_REFCLKP
14,39,40 G_VCORE_PGOOD 2 1 3 CLK_PCIE_VGA# AK32
PCIE_REFCLKN

0R2J-2-GP CALIBRATION
DY L9 Y22 PCIE_CALRP R68 1 2 1K27R2F-L-GP
U41 3D3V_S5 NC#L9 PCIE_CALRP
N9
NC#N9 PCIE_CALRN R67
14 MXM_RST# 1 N10 AA22 1 2 2KR2F-3-GP +1.1V_RUN
B NC_PWRGOOD PCIE_CALRN
5
VCC
8,14,22,24,25,28,29 PLT_RST1# 2
A MXM_RST2#
4 AL27
Y PERSTB
3
GND
74LVC1G08GW-1-GP M92-S2-GP
73.01G08.L04
73.01G08.L03

A A

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-PCIE/LVDS(1/4)
Size Document Number Rev
Custom
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 42 of 48
5 4 3 2 1
 5 4 3 2 1

U113B 2 OF 7
SSID = VIDEO PLACE THESE CAPACITOR CLOSE TO CONNECTOR HDMI(DPA)
DVPDATA [3:0]
AF2 G_HDMI_D_CLK+ C376 1 2 SCD1U10V2KX-4GP HDMI_CLK+ 20
0100 64Mx16 Hynix TXCAP_DPA3P
AF4 G_HDMI_D_CLK- C372 1 2 SCD1U10V2KX-4GP
TXCAM_DPA3N HDMI_CLK- 20
1000 64Mx16 Samsung
AG3 G_HDMI_TX2+ C390 1 2 SCD1U10V2KX-4GP HDMI_DATA0+ 20
+1.8V_RUN MUTI GFX TX0P_DPA2P G_HDMI_TX2- C384 1
AG5 2 SCD1U10V2KX-4GP HDMI_DATA0- 20
DPA TX0M_DPA2N
AH3 G_HDMI_TX1+ C396 1 2 SCD1U10V2KX-4GP HDMI_DATA1+ 20
TX1P_DPA1P G_HDMI_TX1- C392 1
AH1 2 SCD1U10V2KX-4GP HDMI_DATA1- 20
TX1M_DPA1N
AA1 AK3 G_HDMI_TX0+ C400 1 2 SCD1U10V2KX-4GP HDMI_DATA2+ 20
2 DVPCNTL_MVP_0 TX2P_DPA0P

2
Y4 AK1 G_HDMI_TX0- C399 1 2 SCD1U10V2KX-4GP HDMI_DATA2- 20
R120 R101 R121 R100 DVPCNTL_MVP_1 TX2M_DPA0N
AC7
DVPCNTL_0
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP Y2 AK5
D DVPCNTL_1 TXCBP_DPB3P D
Samsung Hynix DY DY U5
DVPCNTL_2 TXCBM_DPB3N
AM3
U1
1

1
DVPDATA20 DVPCLK
Y7
DVPDATA_0 TX3P_DPB2P
AK6 PLACE THESE RESISTORS CLOSE TO
DVPDATA23 DVPDATA22 DVPDATA21 DVPDATA20 DVPDATA21 V2 AM5 DIFF. PAIRS AND AVOID STUBS TO ALL
DVPDATA22 DVPDATA_1 DPB TX3M_DPB2N
Y8
DVPDATA23 V4
DVPDATA_2
AJ7
DIFF. TRACES.
DVPDATA_3 TX4P_DPB1P
AB7 AH6
DVPDATA_4 TX4M_DPB1N
W1
2

2
DVPDATA_5
AB8
DVPDATA_6 TX5P_DPB0P
AK8 MINIMIZE THE DISTANCE
R116 R102 R117 R86 W3 AL7 BETWEEN THESE RES. AND
DVPDATA_7 TX5M_DPB0N
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP AB9
Hynix Samsung W5
DVPDATA_8 100nF AC CAPS
DVPDATA_9
AC6
1

1
DVPDATA_10
W6
DVPDATA_11
AD7
DVPDATA_12
AA3
DVPDATA_13
AC8
DVPDATA_14
AA5
DVPDATA_15
AE8
DVPDATA_16
AA6
DVPDATA_17
AE9
DVPDATA_18
STRAPS PIN DESCRIPTION AB4
DVPDATA_19
AD9
DVPDATA_20
AB2
DVPDATA_21
MEM_TYPE DVPDATA(23:20) MEMORY TYPE,MAKE AND SIZE INFO AC10
DVPDATA_22
0000 - GDDR3 16Mx32 Qimonda AC5
DVPDATA_23
(Internal PD) 0001 - GDDR3 32Mx32 Hynix
0010 - GDDR3 32Mx32 Qimonda
0011 - GDDR3 32Mx32 Samsung
V
+DAC1_AVDD +1.8V_RUN
I2C
L18 1 2

C297

C545

C538

C531
R1 BLM15BD121SN1D-GP

SC1U10V2KX-1GP
41 G_LCD_EDID_CLK

SCD1U16V2KX-3GP
SCD01U16V2KX-3GP

SC4D7U6D3V5KX-3GP
1

1
SCL
R3
41 G_LCD_EDID_DAT SDA
G_RED
CRT 68.00217.611
C AM26 G_RED 41 C

2
GENERAL PURPOSE I/O R R63
AK26 1 2 150R2F-1-GP
R89 RB
45 G_GPIO_0 U6
0R2J-2-GP GPIO_0 G_GREEN
42 G_L_BKLTCTL 1 2 45 G_GPIO_1 U10 AL25 G_GREEN 41
GPIO_1 G R64
45 G_GPIO_2 T10 AJ25 1 2 150R2F-1-GP
GPIO_2 GB
U8
VDDR3 GPIO_3_SMBDATA G_BLUE +DAC1_VDD1DI +1.8V_RUN
U7 AH24 G_BLUE 41
GPIO_4_SMBCLK B R69
45 G_GPIO_5 T9 AG25 1 2 150R2F-1-GP
R90 GPIO_5_AC_BATT DAC1 BB L19
TP38 1 T8 1 2
0R2J-2-GP G_BL_ON_R GPIO_6

C544

C303

C537
1 2 T7 AH26 BLM15BD121SN1D-GP

SC1U10V2KX-1GP
G_HSYNC 20,45

SCD1U16V2KX-3GP
SCD01U16V2KX-3GP
19 G_BL_ON GPIO_7_BLON HSYNC

1
P10 AJ27 G_VSYNC 20,45 68.00217.611
DY 45 G_GPIO_8
1

GPIO_8_ROMSO VSYNC
45 G_GPIO_9 P4
G_TEMP_FAIL R124 GPIO_9_ROMSI
1 P2 (Placed between this pin and AVSSQ)

2
TP86 GPIO_10_ROMSCK VGA_RSET
10KR2J-3-GP 45 G_GPIO_11 N6 AD22 1 2
GPIO_11 RSET R70 499R2F-2-GP
45 G_GPIO_12 N5
GPIO_12 GAP-CLOSE
N3 70mA AG24 +DAC1_AVDD
2

45 G_GPIO_13 GPIO_13 AVDD

1 VGA_THERM# 1 Y9 AE22 M92_AVSSQ 1 2
TP36 GPIO_14_HPD2 AVSSQ
TP45 N1
39 VCORE_VID0 GPIO_15_PWRCNTL_0 G41
1 CLK_VGA_27M_SS M4 AE23 +DAC1_VDD1DI
TP87
VGA_THERM# GPIO_16_SSIN 45mA VDD1DI
R6 AD23
GPIO_17_THERMAL_INT VSS1DI
2 1 R128 VGA_CLK_REQ# 3 TP33 1 W10
10KR2J-3-GP G_TEMP_FAIL GPIO_18_HPD3
M2
GPIO_19_CTF
39 VCORE_VID1 P8 AM12
R109 1 GPIO_20_PWRCNTL_1 R2
R81 2 P7 AK12
10KR2J-3-GP GPIO_21_BB_EN R2B VDDR3
45 G_GPIO_22 N8
G_HDMI_DETECT# VGA_CLK_REQ# GPIO_22_ROMCSB
20 HDMI_DETECT# 2 1 N7 AL11
GPIO_23_CLKREQB G2
T11 AJ11
GPIO_29_DRM_0 G2B
1

R11

1
4K99R2F-L-GP R84 GPIO_30_DRM_1
AK10
JTAG_TRSTB B2 C614
10KR2J-3-GP L6 AL9
JTAG_TRSTB B2B SCD1U16V2KX-3GP
1 L5

2
TP85 JTAG_TDI
1 L3 U38
1KR2J-1-GP
2

JTAG_TCK
1

TP83 1 L1 AH12 G83

JTAG_TMS C
1GAP-CLOSE2 KBC_THERM_G781_CLK
R131

TP84 1 K4 AM10 8 1
JTAG_TDO Y 25,27,28 SMBC_THERM SMBCLK VCC
JTAG_TESTEN TP82 AF24 AJ9 1 2 KBC_THERM_G781_DAT 7 2 GPU_TEMP+
TESTEN COMP 25,27,28 SMBD_THERM SMBDATA DXP
GAP-CLOSE G781_ALERT# 6 3

1
TP30 DAC2 G82 ALERT# DXN GPU_THERM#
1 AB13 5 4
1KR2J-1-GP
2

GENERICA GND THERM#

1

TP40 1 W8 AL13 C607

B GENERICB H2SYNC B
R66

TP35 1 W9 AJ13 SC2200P50V2KX-2GP

2
+DPLL_PVDD +1.8V_RUN TP39 GENERICC V2SYNC
1 W7 G781P8F-GP
GENERICD GPU_TEMP-
L24 1 AD10
GENERICE_HPD4 40mA
TP34 AD19 +1.8V_RUN
40mA
2

VDD2DI
1

1
1 2 G_HDMI_DETECT# AC14 AC19
SC10U6D3V3MX-GP

+1.8V_RUN
SCD1U16V2KX-3GP

HPD1 VSS2DI
C648

C647

C357

R299 R262 R264 GPU DIE TEMP:

SC1U10V2KX-1GP

BLM15BD121SN1D-GP 1 499R2F-2-GP 65mA 2K2R2F-GP 2K2R2F-GP

VREFG VOLTAGE DIVIDER IS AE20
REMOTE2+ and REMOTE2- routing 10mil
65mA A2VDD VDDR3
2 (VREFG = VDDR4,5(1.8V) / 3 = .6V) trace width and 10 mil spacing.
2

2
68.00217.611 2mA AE17 +1.8V_RUN
VGA_VREFG A2VDDQ
AC16
VREFG 2mA
AE19
A2VSSQ
1

VDDR3
C331
+DPLL_VDDC R74 SCD1U16V2KX-3GP AG13 VGA_R2SET 1 2
L23 -1
2

249R2F-GP R2SET R76 715R2F-GP 3D3V_S0

+1.1V_RUN 1 2
2
SC10U6D3V3MX-GP

SCD1U16V2KX-3GP

+DPLL_PVDD DDC/AUX
C640

C639

C344

BLM15BD121SN1D-GP AE6
SC1U10V2KX-1GP

DDC1CLK G_DDCCLK 20
1

1
1 PLL/CLOCK AE5
DDC1DATA G_DDCDATA 20
AF14 R219
DPLL_PVDD 120mA
68.00217.611 2 AE14 AD2 10KR2J-3-GP
2

+DPLL_VDDC DPLL_PVSS AUX1P

AD4
AUX1N

2
AD14 300mA AC11 G_HDMI_CLK 20 HDMI_hotplug 28
DPLL_VDDC DDC2CLK
C612 AC13 G_HDMI_DATA 20
SC22P50V2JN-4GP DDC2DATA
2 1 G_27M_XTALIN AM28 AD13 VDDR3

D
G_27M_XTALOUT XTALIN AUX2P
AK28 AD11
XTALOUT AUX2N Q24
2N7002-11-GP
4

4
3
82.30034.611 AB22 HDMI_DETECT# G
X4 NC#AB22 RN12
2ND = 82.30034.421 1MR2F-GP NC#AC22
AC22 84.27002.Y31
SRN1K5J-GP

S
XTAL-27MHZ-74-GP R282 GPU_TEMP+ T4
GPU_TEMP- DPLUS THERMAL
T2
1

SC27P50V2JN-2-GP C624 DMINUS

AE16
H:UMA MODE HDMI PLUG_OUT
1
2

L22 DDCAUX5P
A 2 1 AD16 A
TP88 DDCAUX5N
1 R5
TS_FDO
+1.8V_RUN 1 2 +TSVDD AD17
AC17
TSVDD 20mA DDC6CLK
AC1
AC3
G_HDMI_CLK
G_HDMI_DATA
L:UMA MODE HDMI PLUG_IN
BLM15BD121SN1D-GP TSVSS DDC6DATA
SCD1U16V2KX-3GP

DIS
C329

C330

AD20
SC1U10V2KX-1GP

NC_DDCAUX7P
AC20
NC_DDCAUX7N
68.00217.611 Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

M92-S2-GP Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-TV/CRT/DP PORT(2/4)
Size Document Number Rev
C
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO U113E 5 OF 7

+1.5V_RUN

AA27 A3
PCIE_VSS GND
AB24 A30
PCIE_VSS GND
AB32 AA13

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
PCIE_VSS GND
AC24 AA16

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

1
PCIE_VSS GND

C368

C301

C380

C340

C356

C371

C288

C325

C349

C326
AC26 AB10
PCIE_VSS GND 1 1 1
AC27 AB15
PCIE_VSS GND +1.8V_RUN
AD25 AB6

2
PCIE_VSS GND 2 2 2
AD32 AC9
PCIE_VSS GND L7
AE27 AD6
PCIE_VSS GND
AF32 AD8 1 2
PCIE_VSS GND BLM21PG221SN1D-1GP
AG27 AE7
PCIE_VSS GND
AH32 AG12 220R_2000mA

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP
SCD1U16V2KX-3GP
PCIE_VSS GND

C285

C286

C292

C310

C276
K28 AH10

SCD01U16V2KX-3GP
1

1
PCIE_VSS GND U113D 4 OF 7 1
K32 AH28

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
PCIE_VSS GND
D L27 B10 D

1
PCIE_VSS GND

C305

C289

C374
M32 B12 MEM I/O 2

2
PCIE_VSS GND PCIE
N25 B14
PCIE_VSS GND
N27 B16 H13 AB23

2
PCIE_VSS GND VDDR1 PCIE_VDDR
P25 B18 H16 AC23
PCIE_VSS GND VDDR1 PCIE_VDDR
P32 B20 H19 AD24
PCIE_VSS GND VDDR1 PCIE_VDDR
R27 B22 J10 AE24

500mA
PCIE_VSS GND VDDR1 PCIE_VDDR
T25 B24 J23 AE25
PCIE_VSS GND VDDR1 PCIE_VDDR
T32 B26 J24 AE26
PCIE_VSS GND VDDR1 PCIE_VDDR
U25 B6 J9 AF25
PCIE_VSS GND VDDR1 PCIE_VDDR +1.1V_RUN
U27 B8 K10 AG26

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
PCIE_VSS GND VDDR1 PCIE_VDDR
V32 C1 K23 2.2A

1
PCIE_VSS GND VDDR1

C315

C360
W25 C32 K24
PCIE_VSS GND VDDR1
W26 E28 K9 L23
PCIE_VSS GND VDDR1 PCIE_VDDC
W27 F10 L11 L24

2
PCIE_VSS GND VDDR1 PCIE_VDDC
Y25 F12 L12 L25

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP
PCIE_VSS GND VDDR1 PCIE_VDDC

C293

C294

C295

C291

C287

C300
Y32 F14 L13 L26

1
PCIE_VSS GND VDDR1 PCIE_VDDC 1
F16 L20 M22
GND VDDR1 PCIE_VDDC
F18 L21 N22
GND VDDR1 PCIE_VDDC
F2 L22 2A N23 2

2
GND +1.8V_RUN VDDR1 PCIE_VDDC
F20 L6 N24
GND PCIE_VDDC
M6 F22 R22
GND GND +VDD_CT PCIE_VDDC
N11 F24 1 2 T22
GND GND BLM15BD121SN1D-GP LEVEL PCIE_VDDC
N12 F26 U22

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
GND GND PCIE_VDDC

C244
N13 F6 300mA TRANSLATION V22

SC10U6D3V3MX-GP

1
GND GND PCIE_VDDC

C312

C311
N16 F8 1 AA20 +VGA_CORE
N18
GND
GND GND
G10 68.00217.611 AA21
VDD_CT

110mA
GND GND 2 VDD_CT
N21 G27 AB20 AA15

2
GND GND VDD_CT CORE VDDC
P6 G31 AB21 N15
GND GND VDD_CT VDDC
P9 G8 N17

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
GND GND VDDC

C355

C337

C336
R12 H14 R13
GND GND I/O VDDC 1 1 1
R15 H17 R16
GND GND VDDC
R17 H2 AA17 R18
GND GND VDDR3 VDDR3 VDDC 2 2 2
R20 H20 AA18 R21

50mA
GND GND VDDR3 VDDC
T13 H6 AB17 T12
GND GND VDDR3 VDDC
T16 J27 AB18 T15
GND GND VDDR3 VDDC
T18 J31 T17

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
GND GND VDDC +VGA_CORE
T21 K11 T20

1
GND GND VDDC

C321

C327
T6 K2 U11 U13
GND GND VDDR5 VDDC
U15 K22 U12 U16

170mA
GND GND VDDR5 VDDC
U17 K6 V11 U18

2
GND GND VDDR5 VDDC
C U20 V12 U21 C
GND VDDR5 VDDC

POWER
U3 V15

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
GND VDDC

C351

C358

C359

C348

C318

C328

C334

C313

C335

C347
U9 V17

1
GND VDDC
V13 AA11 V20
GND +1.8V_RUN VDDR4 VDDC
V16 AA12 V21

170mA
GND VDDR4 VDDC
V18 Y11 Y13

2
GND VDDR4 VDDC
V6 Y12 Y16
GND VDDR4 VDDC
Y10 A32 SC1U6D3V2KX-GP Y18

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
GND VSS_MECH +1.5V_RUN VDDC
Y15 AM1 Y21
1

1
GND VSS_MECH VDDC
C366

C363

C364

C365
Y17 AM32 L10 MEM CLK
GND VSS_MECH SC1U6D3V2KX-GP +VDDRHA
Y20 1 2 L17
GND BLM15BD121SN1D-GP VDDRHA
Y6
2

2
GND C339 ISOLATED
300mA L16

1
VSSRHA CORE I/O
68.00217.611
M13
M92-S2-GP +PCIE_PVDD PLL VDDCI
M15

2
VDDCI
AM30 40mA M16
PCIE_PVDD VDDCI
M17
VDDCI
M18
VDDCI
L8 M20
+1.8V_RUN NC_MPV18 VDDCI +VGA_CORE
L20 M21
VDDCI
N20
+VGA_CORE +SPV10 VDDCI
1 2 L13 H7
BLM15BD121SN1D-GP NC_SPV18
300mA 1 2 H8
SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
SPV10 35mA
C551

C590

C593 BLM15BD121SN1D-GP

SC10U6D3V3MX-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

68.00217.611 1

C352

C317

C353

C319
1 300mA J7

1
SPVSS 1

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
68.00217.611

C382

C381
2
2

1
+VGA_CORE 2

2
BACK BIAS
M11

2
BBP#1
M12 120mA
BBP#2

M92-S2-GP

B B

U113G 7 of 7

+1.8V_RUN +DPE_VDD18 DP E/F POWER DP A/B POWER

L11
1 2 SC10U6D3V3MX-GP SCD1U16V2KX-3GP AG15 AE11
200mA

BLM15BD121SN1D-GP DPE_VDD18 NC_DPA_VDD18

AG16 AF11
1

C346 1 C342 C343 DPE_VDD18 NC_DPA_VDD18

300mA
+DPA_VDD10 +1.1V_RUN
68.00217.611 2 +DPE_VDD10 L14
2

AG20 AF6 SC1U6D3V2KX-GP SC10U6D3V3MX-GP 2 1

170mA

200mA

+1.1V_RUN SC1U6D3V2KX-GP DPE_VDD10 DPA_VDD10 BLM18PG300SN-GP

AG21 AF7

1
L8 DPE_VDD10 DPA_VDD10 C379 C373 1 C385
2 1 SC10U6D3V3MX-GP
BLM18PG300SN-GP AG14 AE1 2 68.00214.081

2
1

C314 1 C307 C308 SCD1U16V2KX-3GP DPE_VSSR DPA_VSSR

1A AH14
DPE_VSSR DPA_VSSR
AE3
AM14 AG1 SC1U6D3V2KX-GP
68.00214.081 2 AM16
DPE_VSSR DPA_VSSR
AG6
2

DPE_VSSR DPA_VSSR
AM18 AH5
SC1U6D3V2KX-GP DPE_VSSR DPA_VSSR

+DPE_VDD18
AF16 AE13
200mA

DPF_VDD18 NC_DPB_VDD18
AG17 AF13
DPF_VDD18 NC_DPB_VDD18
+1.1V_RUN +1.1V_RUN

AF22 AF8
170mA

200mA

DPF_VDD10 DPB_VDD10
AG22 AF9
DPF_VDD10 DPB_VDD10

AF23 AF10
DPF_VSSR DPB_VSSR
AG23 AG9
DPF_VSSR DPB_VSSR
AM20 AH8
DPF_VSSR DPB_VSSR
AM22 AM6
DPF_VSSR DPB_VSSR
AM24 AM8
DPF_VSSR DPB_VSSR

+1.8V_RUN
A L12 A

2 R297 1 AF17 AE10 1 R83 2 SCD1U16V2KX-3GP SC1U6D3V2KX-GP 2 1

DPEF_CALR DPAB_CALR BLM18PG300SN-GP
1

+1.8V_RUN 150R2F-1-GP 150R2F-1-GP C377 C378 C370

L9
20mA 20mA 68.00214.081 DIS
1 2 SC10U6D3V3MX-GP SCD1U16V2KX-3GP +DPE_PVDD AG18 DP PLL POWER AG8 +DPA_PVDD
2

BLM15BD121SN1D-GP DPE_PVDD DPA_PVDD

AF19 AG7
1

C322 1 C323 C324 DPE_PVSS DPA_PVSS SC1U6D3V2KX-GP

300mA
+1.8V_RUN
+1.8V_RUN Wistron Corporation
68.00217.611 2 20mA 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

AG19 AG10 Taipei Hsien 221, Taiwan, R.O.C.

SC1U6D3V2KX-GP NC_DPF_PVDD DPB_PVDD
AF20 AG11
NC_DPF_PVSS DPB_PVSS Title

M92-S2-GP
VGA-POWER/GND(3/4)
Size Document Number Rev
A2
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 44 of 48

5 4 3 2 1
 5 4 3 2 1

U113C 3 OF 7 VDDR3
SSID = VIDEO 46 MDA[0..63]
MAA[0..12] 46
ATI RESERVED CONFIGURATION STRAPS
MDA0 K27 K17 MAA0 R122 1 2 10KR2J-3-GP ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
DQA_0 MAA_0 43 G_GPIO_0
MDA1 J29 J20 MAA1 THEY MUST NOT CONFLICT DURING RESE
MDA2 DQA_1 MAA_1 MAA2
H30 H23
MDA3 DQA_2 MAA_2 MAA3 R103 1
H32 G23 2 10KR2J-3-GP
MDA4 DQA_3 MAA_3 MAA4 43 G_GPIO_1
GPIO3 , H2SYNC , V2SYNC

MEMORY INTERFACE
G29 G24
MDA5 DQA_4 MAA_4 MAA5
F28 H24
MDA6 DQA_5 MAA_5 MAA6
F32 J19 43 G_GPIO_2
R104 1 2 10KR2J-3-GP PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
MDA7 DQA_6 MAA_6 MAA7
F30 K19
MDA8 C30
DQA_7 MAA_7
J14 MAA8 M92_XT THEY MUST NOT CONFLICT DURING RESET
MDA9 DQA_8 MAA_8 MAA9 R123 1
F27 K14 43 G_GPIO_5 2 10KR2J-3-GP
MDA10 DQA_9 MAA_9 MAA10
A28 J11
MDA11 DQA_10 MAA_10 MAA11
C28
DQA_11 MAA_11
J13 If BIOS_ROM_EN (GPIO22) = 0 If BIOS_ROM_EN (GPIO22) = 1
MDA12 E27 H11 MAA12 R105 1 2 10KR2J-3-GP
DQA_12 MAA_12 43 G_GPIO_8
MDA13 G26 G11 BA2 Size of the primary
MDA14 DQA_13 MAA_13/BA2 BA0 BA2 46
MDA15
D26
DQA_14 MAA_14/BA0
J16
BA1 BA0 46
R125
memory apertures GPIO[9,13,12,11] Manufacturer Part Number GPIO[13,12,11]
F25 L15 1 2 10KR2J-3-GP
D
MDA16 A25
DQA_15 MAA_15/BA1 BA1 46 43 G_GPIO_9 DY D

MDA17 DQA_16 DQMA#0

C25
DQA_17 DQMA_0
E32 128MB x000 M25P05A 0100
MDA18 E25 E30 DQMA#1 R126 1 2 10KR2J-3-GP ST
MDA19 D24
DQA_18 DQMA_1
A21 DQMA#2
43 G_GPIO_13 DY V
256MB x001 M25P10A 0101
MDA20 DQA_19 DQMA_2 DQMA#3 64MB x010 Microelectronics M25P20 0101
E23 C21
MDA21 DQA_20 DQMA_3 DQMA#4 R127
F23 E13 1 2 10KR2J-3-GP 32MB x M25P40 0101
MDA22 D22
DQA_21 DQMA_4
D12 DQMA#5 43 G_GPIO_12 DY
MDA23 F21
DQA_22 DQMA_5
E3 DQMA#6 512MB x M25P80 0101
MDA24 DQA_23 DQMA_6 DQMA#7 R106 1GB x
E21 F4 43 G_GPIO_11 1 2 10KR2J-3-GP
MDA25 DQA_24 DQMA_7 Chingis
D20 DQMA#[0..7] 46 2GB x Pm25LV512A 0100
MDA26 DQA_25 RDQSA0
MVDDQ=1.5V FOR DDR3 MEMORY F19 H28 (formerly PMC)
MDA27 A19
DQA_26 RDQSA_0
C27 RDQSA1 R107 1 2 10KR2J-3-GP
4GB x Pm25LV010A 0101
MDA28 D18
DQA_27 RDQSA_1
A23 RDQSA2
43 G_GPIO_22 DY
MDA29 DQA_28 RDQSA_2 RDQSA3
DIVIDER RESISTORS DDR2/DDR3 GDDR3 F17
DQA_29 RDQSA_3
E19
MDA30 A17 E15 RDQSA4
MDA31 DQA_30 RDQSA_4 RDQSA5
C17 D10
MDA32 DQA_31 RDQSA_5 RDQSA6
MVREF TO 1.8V 100R 40.2R E17
DQA_32 RDQSA_6
D6
MDA33 D16 G5 RDQSA7 STRAPS PIN DESCRIPTION
MDA34 DQA_33 RDQSA_7
F15 RDQSA[0..7] 46
MDA35 DQA_34 WDQSA0
MVREF TO GND 100R 100R A15
DQA_35 WDQSA_0
H27 Tansmitter Power Savings Enable
MDA36 D14 A27 WDQSA1 TX_PWRS_ENB GPIO0 0= 50% Tx output swing
MDA37 DQA_36 WDQSA_1 WDQSA2
F13 C23 1= Full Tx output swing
MDA38 DQA_37 WDQSA_2 WDQSA3
A13
DQA_38 WDQSA_3
C19 (Internal PD) V
MDA39 C13 C15 WDQSA4
MDA40 DQA_39 WDQSA_4 WDQSA5
E11
DQA_40 WDQSA_5
E9 Transmitter De-emphasis Enable
MDA41 A11 C5 WDQSA6 TX_DEEMPH_EN GPIO1 0= Tx de-emphasis disabled
MDA42 DQA_41 WDQSA_6 WDQSA7
C11 H4 1= Tx de-emphasis enabled
MDA43 DQA_42 WDQSA_7 VDDR3
F11
DQA_43 WDQSA[0..7] 46 (Internal PD) V
MDA44 A9 L18
MDA45 DQA_44 ODTA0 ODTA0 46
C9
DQA_45 ODTA1
K16
ODTA1 46 V 0 = Advertises the PCI-E device
MDA46 F9 R56 1 2 10KR2J-3-GP BIF_GEN2_EN_A GPIO2 as 2.5GT/s
+1.5V_RUN MDA47 DQA_46 CLKA0 20,43 G_VSYNC
D8 H26 CLKA0 46 1 = Advertises the PCI-E device
MDA48 DQA_47 CLKA0 CLKA0#
PLCAE MVREF DIVIDERS AND E7 H25 CLKA0# 46 20,43 G_HSYNC
R62 1 2 10KR2J-3-GP
MDA49 DQA_48 CLKA0B as 5GT/s
CAPS CLOSE TO ASIC A7
MDA50 DQA_49 CLKA1
C7 G9 CLKA1 46
1

R57 MDA51 DQA_50 CLKA1 CLKA1#

F7 H9 CLKA1# 46
100R2F-L1-GP-U MDA52 DQA_51 CLKA1B
A5
MDA53 DQA_52 RASA0#
E5
DQA_53 RASA0B
G22 RASA0# 46 BIF_CLK_PM_EN GPIO8 0= Disable CLKREQ#power management capability
MDA54 C3 G17 RASA1# 1= Enable CLKREQ# power management capability
MDA55 DQA_54 RASA1B RASA1# 46
E1 V
2

MDA56 DQA_55 CASA0#

C G7 G19 CASA0# 46
C
MDA57 DQA_56 CASA0B CASA1#
G6 G16 CASA1# 46
DQA_57 CASA1B
C281

C282

MDA58 G1 ROMIDCFG[3:0] if BIOS_ROM_EN=1,then Config[3:0]

SCD1U16V2KX-3GP
SCD01U16V2KX-3GP

MDA59 DQA_58 CSA0_0#

G3 H22 CSA0_0# 46 GPIO[13,12,11] defines the ROM type
1

MDA60 DQA_59 CSA0B_0 CSA0_1#

+1.5V_RUN
R58 J6
DQA_60 CSA0B_1
J22 1 TP28 (Internal PD) if BIOS_ROM_EN=0,then Config[3:0]
100R2F-L1-GP-U MDA61 J1 TPAD14-GP
MDA62 DQA_61 CSA1_0# defines the primary memory apeture size
J3 G13
2

DQA_62 CSA1B_0 CSA1_0# 46

MDA63 J5 K13 CSA1_1# 1 TP31
DQA_63 CSA1B_1 TPAD14-GP
2
1

MVREFD K26 K20 CKEA0 Enable external BIOS ROM device

MVREFDA CKEA0 CKEA0 46
R61 MVREFS J26 J17 CKEA1 BIOS_ROM_EN GPIO_22_ROMCSB V 0= Disable external BIOS ROM device
MVREFSA CKEA1 CKEA1 46
100R2F-L1-GP-U
+1.5V_RUN WEA0#
1= Enable external BIOS ROM device
R65 1
DY 2 243R2F-2-GP J25
NC_MEM_CALRN0 WEA0B
G25 WEA0# 46 (Internal PD)
R110 1 2 243R2F-2-GP K7 H10 WEA1#
DY WEA1# 46
2

NC_MEM_CALRN1 WEA1B
AUD[1:0]
R129 1 2 243R2F-2-GP J8
MEM_CALRP1 RSVD#1
AB16 AUD[1] VGA_HSYNC 00:No audio function
C283

C284

R59 1 2 243R2F-2-GP K25 G14

DY
SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

AUD[0] 01:Audio for DisplayPort and HDMI

1

NC_MEM_CALRP0 RSVD#2
RSVD#3
G20 VGA_VSYNC
R60 L10 ( if adapter is detected)
+1.5V_RUN DRAM_RST 10:Audio for DisplayPort only
100R2F-L1-GP-U (Internal PD)
2

K8 11:Audio for both DisplayPort and HDMI

CLKTESTA
L7 V
2

CLKTESTB
R91
M92-S2-GP
2KR2F-3-GP
2

46 MEM_RST
1

R85 C367
4K7R2F-GP SC1U6D3V2KX-GP
1

DY
2

R130 R108
2

4K7R2F-GP 4K7R2F-GP
2

B B

A A

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VGA-MEMORY/STRAPS(4/4)
Size Document Number Rev
A2
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 45 of 48

5 4 3 2 1
 5 4 3 2 1

512MB DDR3
U14 U39 U46 U19
MDA[0..63] 45 MDA[0..63] 45 MDA[0..63] 45 MDA[0..63] 45
VREFC_U0 M8 E3 MDA17 VREFC_U0 M8 E3 MDA24 VREFC_U2 M8 E3 MDA51 VREFC_U2 M8 E3 MDA39
VREFD_U0 VREFCA DQL0 MDA18 VREFD_U0 VREFCA DQL0 MDA28 VREFD_U2 VREFCA DQL0 MDA54 VREFD_U2 VREFCA DQL0 MDA34
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDA20 VREFDQ DQL1 MDA26 VREFDQ DQL1 MDA48 VREFDQ DQL1 MDA36
45 MAA[0..12] F2 45 MAA[0..12] F2 45 MAA[0..12] F2 45 MAA[0..12] F2
MAA0 DQL2 MDA21 MAA0 DQL2 MDA27 MAA0 DQL2 MDA52 MAA0 DQL2 MDA32
N3 F8 N3 F8 N3 F8 N3 F8
MAA1 A0 DQL3 MDA22 MAA1 A0 DQL3 MDA31 MAA1 A0 DQL3 MDA50 MAA1 A0 DQL3 MDA38
P7 H3 P7 H3 P7 H3 P7 H3
MAA2 A1 DQL4 MDA19 MAA2 A1 DQL4 MDA30 MAA2 A1 DQL4 MDA55 MAA2 A1 DQL4 MDA33
P3 H8 P3 H8 P3 H8 P3 H8
MAA3 A2 DQL5 MDA23 MAA3 A2 DQL5 MDA25 MAA3 A2 DQL5 MDA49 MAA3 A2 DQL5 MDA37
N2 G2 N2 G2 N2 G2 N2 G2
MAA4 A3 DQL6 MDA16 MAA4 A3 DQL6 MDA29 MAA4 A3 DQL6 MDA53 MAA4 A3 DQL6 MDA35
P8 H7 P8 H7 P8 H7 P8 H7
MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
P2 P2 P2 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 R8 R8 R8
MAA7 A6 MDA3 MAA7 A6 MDA13 MAA7 A6 MDA44 MAA7 A6 MDA57
D R2 D7 R2 D7 R2 D7 R2 D7 D
MAA8 A7 DQU0 MDA2 MAA8 A7 DQU0 MDA10 MAA8 A7 DQU0 MDA42 MAA8 A7 DQU0 MDA61
T8 C3 T8 C3 T8 C3 T8 C3
DQMA#[0..7] MAA9 A8 DQU1 MDA0 MAA9 A8 DQU1 MDA14 MAA9 A8 DQU1 MDA47 MAA9 A8 DQU1 MDA56
45 DQMA#[0..7] R3 C8 R3 C8 R3 C8 R3 C8
MAA10 A9 DQU2 MDA4 MAA10 A9 DQU2 MDA9 MAA10 A9 DQU2 MDA43 MAA10 A9 DQU2 MDA62
L7 C2 L7 C2 L7 C2 L7 C2
MAA11 A10/AP DQU3 MDA6 MAA11 A10/AP DQU3 MDA12 MAA11 A10/AP DQU3 MDA45 MAA11 A10/AP DQU3 MDA60
R7 A7 R7 A7 R7 A7 R7 A7
QSA#[0..7] MAA12 A11 DQU4 MDA5 MAA12 A11 DQU4 MDA8 MAA12 A11 DQU4 MDA40 MAA12 A11 DQU4 MDA59
45 WDQSA[0..7] N7 A2 N7 A2 N7 A2 N7 A2
A12/BC# DQU5 MDA1 A12/BC# DQU5 MDA15 A12/BC# DQU5 MDA46 A12/BC# DQU5 MDA63
T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 MDA7 A13 DQU6 MDA11 A13 DQU6 MDA41 A13 DQU6 MDA58
T7 A3 T7 A3 T7 A3 T7 A3
QSA[0..7] A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
45 RDQSA[0..7] M7 M7 M7 M7
A15 A15 A15 A15
CASA0#
45 CASA0# CASA1#
45 BA0 M2 B2 +1.5V_RUN 45 BA0 M2 B2 +1.5V_RUN 45 BA0 M2 B2 +1.5V_RUN 45 BA0 M2 B2 +1.5V_RUN
45 CASA1# BA0 VDD BA0 VDD BA0 VDD BA0 VDD
45 BA1 N8 D9 45 BA1 N8 D9 45 BA1 N8 D9 45 BA1 N8 D9
CSA0_0# BA1 VDD BA1 VDD BA1 VDD BA1 VDD
45 BA2 M3 G7 45 BA2 M3 G7 45 BA2 M3 G7 45 BA2 M3 G7
45 CSA0_0# CSA1_0# BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
45 CSA1_0# VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD VDD VDD VDD
45 CLKA0 J7 N9 45 CLKA0 J7 N9 45 CLKA1 J7 N9 45 CLKA1 J7 N9
CK VDD CK VDD CK VDD CK VDD
45 CLKA0# K7 R1 45 CLKA0# K7 R1 45 CLKA1# K7 R1 45 CLKA1# K7 R1
CK# VDD CK# VDD CK# VDD CK# VDD
45 CKEA0 K9 R9 45 CKEA0 K9 R9 45 CKEA1 K9 R9 45 CKEA1 K9 R9
CKE VDD CKE VDD CKE VDD CKE VDD

VRAM_ODTA0 K1 A1 VRAM_ODTA0 K1 A1 VRAM_ODTA1 K1 A1 VRAM_ODTA1 K1 A1

ODT VDDQ +1.5V_RUN ODT VDDQ +1.5V_RUN ODT VDDQ +1.5V_RUN ODT VDDQ +1.5V_RUN
45 CSA0_0# L2 A8 45 CSA0_0# L2 A8 45 CSA1_0# L2 A8 45 CSA1_0# L2 A8
CS# VDDQ CS# VDDQ CS# VDDQ CS# VDDQ
45 RASA0# J3 C1 45 RASA0# J3 C1 45 RASA1# J3 C1 45 RASA1# J3 C1
RAS# VDDQ RAS# VDDQ RAS# VDDQ RAS# VDDQ
45 CASA0# K3 C9 45 CASA0# K3 C9 45 CASA1# K3 C9 45 CASA1# K3 C9
CAS# VDDQ CAS# VDDQ CAS# VDDQ CAS# VDDQ
45 WEA0# L3 D2 45 WEA0# L3 D2 45 WEA1# L3 D2 45 WEA1# L3 D2
WE# VDDQ WE# VDDQ WE# VDDQ WE# VDDQ
E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSA2 VDDQ QSA3 VDDQ QSA6 VDDQ QSA4 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#6 E7 A9 DQMA#4 E7 A9

DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSA#2 VSS QSA#3 VSS QSA#6 VSS QSA#4 VSS
G3 J2 G3 J2 G3 J2 G3 J2
QSA#0 DQSL# VSS QSA#1 DQSL# VSS QSA#5 DQSL# VSS QSA#7 DQSL# VSS
B7 J8 B7 J8 B7 J8 B7 J8
DQSU# VSS DQSU# VSS DQSU# VSS DQSU# VSS
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
C P1 P1 P1 P1 C
VSS VSS VSS VSS
45 MEM_RST T2 P9 45 MEM_RST T2 P9 45 MEM_RST T2 P9 45 MEM_RST T2 P9
RESET# VSS RESET# VSS RESET# VSS RESET# VSS
T1 T1 T1 T1
VSS VSS VSS VSS
1 2 L8 T9 1 2 L8 T9 1 2 L8 T9 1 2 L8 T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
R246 243R3F-GP R280 243R3F-GP R318 243R3F-GP R298 243R3F-GP
B1 B1 B1 B1
VSSQ VSSQ VSSQ VSSQ
B9 B9 B9 B9
VSSQ VSSQ VSSQ VSSQ
D1 D1 D1 D1
VSSQ VSSQ VSSQ VSSQ
D8 D8 D8 D8
VSSQ VSSQ VSSQ VSSQ
E2 E2 E2 E2
VSSQ VSSQ VSSQ VSSQ
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ NC#J1 VSSQ NC#J1 VSSQ NC#J1 VSSQ
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ NC#L1 VSSQ NC#L1 VSSQ NC#L1 VSSQ
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ NC#J9 VSSQ NC#J9 VSSQ NC#J9 VSSQ
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ NC#L9 VSSQ NC#L9 VSSQ NC#L9 VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ1G63AFR-14C-GP H5TQ1G63AFR-14C-GP H5TQ1G63AFR-14C-GP H5TQ1G63AFR-14C-GP
H_72.51G63.C0U H_72.51G63.C0U H_72.51G63.C0U H_72.51G63.C0U

+1.5V_RUN +1.5V_RUN
+1.5V_RUN +1.5V_RUN
1

R257 R261

1
R265 R242
4K99R2F-L-GP 4K99R2F-L-GP
45 ODTA0 1 2 VRAM_ODTA0 2 1 +1.5V_RUN R312 R112
4K99R2F-L-GP 4K99R2F-L-GP
2

VREFC_U0 VREFD_U0 0R2J-2-GP 56R2J-4-GP

2
DY VREFC_U2 VREFD_U2
1

1
R270 C613 R241 C581
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP R114 R113
4K99R2F-L-GP 4K99R2F-L-GP R313 C656 R111 C393
2

1 2 VRAM_ODTA1 2 1 4K99R2F-L-GP SCD1U16V2ZY-2GP 4K99R2F-L-GP SCD1U16V2ZY-2GP

45 ODTA1 +1.5V_RUN

2
2

2
B 0R2J-2-GP 56R2J-4-GP B
DY

Samsung : K4W1G1646E-EC12

Hynix : H5TQ1G63BFR-12C

+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN

1

45 CLKA0
R240
56R2F-1-GP
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C580
1

1
C602

C620

C599

C596

C641

C605

C628

C617

C615

C646

C636

C658

C582

C645

C637

C655

C632
1 2

1 2
2

2
R239 SCD01U16V2KX-3GP
56R2F-1-GP
2

45 CLKA0#

+1.5V_RUN
A +1.5V_RUN A
1

45 CLKA1
R315
56R2F-1-GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C657 DIS
C626

C623

C592

C586

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1 2

C661

C629

C595

1 2 1 1 1 1 C650
1 1 1 1
SCD01U16V2KX-3GP
2 2 2 2 Wistron Corporation
R314 2 2 2 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
56R2F-1-GP Taipei Hsien 221, Taiwan, R.O.C.
2

45 CLKA1# Title

VRAM
Size Document Number Rev
A2
JM41_Discrete -1
Date: Tuesday, April 07, 2009 Sheet 46 of 48

5 4 3 2 1
 5 4 3 2 1

DCBATOUT
1

1
EC30 EC1 EC2

1
EC20 EC24
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
DY DY DY
2

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
DY DY

2
D D

VCC_GFXCORE
3D3V_S0
1

EC16

1
SCD1U16V2ZY-2GP

DY EC40 EC39

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DY DY
2

2
1D5V_S0 VGA_CORE_PW R VGFXCORE 1D05V_S0
1

1
EC26 EC28 EC17 EC38 EC11 EC4 EC7
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DY DY DY DY DY DY DY
2

2
C C

1D5V_S3 5V_S5

1
EC29 EC42 EC35
1

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
EC9 EC18 EC19 EC10 EC41 EC13 EC63 EC62 EC64 DY DY DY
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DY DY DY DY DY DY DY DY DY

2
2

B B

SP1 SP2 SP3 SP5 SP6

34.41Y01.001

34.41Y01.001

34.39S07.003

34.41Y01.001
SPRING-5-GP

SPRING-5-GP

SPRING-5-GP
SPRING-62-GP

SPRING-9-GP
34.49U23.001
DY
1

H1 H2 H3 H4 H9 H10
A DIS A
H5 H6 H7 H8 H11
HOLE389X394R166-S-GP
HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP
HOLET237B315X315R91-S-GP
ZZ.00PAD.571

ZZ.00PAD.571

ZZ.00PAD.571

ZZ.00PAD.571

ZZ.00PAD.591

ZZ.00PAD.571
W AIT_STFT256BR75H81-GP W AIT_STFT256BR75H81-GP W AIT_STFT256BR75H81-GP W AIT_STFT256BR75H81-GP W AIT_STFT256BR75H81-GP
34.4CQ05.001 34.4CQ05.001 34.4CQ05.001 34.4CQ05.001 34.4CQ05.001 Wistron Corporation
1

1
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

Title

EMI/Spring/Boss
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 47 of 48
5 4 3 2 1
 5 4 3 2 1

JM41/JM51 DIS Schematic EC Tracking Record

EC #/ Page / Description / Part Affected

EC SC01/11/connect NB1.A31 to GND(For power save)

EC SC02/14/net DIS_EN pull high 10K to 3D3V_S0
EC SC03/20/CN2.pin35 change to AGND
EC SC04/22/R311 change to 39.2K
EC SC05/22/U24.pin2 change to AGND
EC SC06/26/BTB2.pin9 add stand by led control signal
D EC SC07/28/U16.pin66 add stand by led control signal D

EC SC08/28/add circuit to support green adapter

EC SC09/28/net EJECT_BTN pull high 10K to 3D3V_S0
EC SC10/31/add circuit to stand by led control
EC SC11/40/change GPU power enable signal to ATI_PWR_ON#(low active)
EC SC12/41/change U11 power plane to 1D8V_NB_S0

C C

B B

A A

DIS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HISTORY
Size Document Number Rev
A2
JM41_Discrete -1
Date: Wednesday, April 15, 2009 Sheet 48 of 48
5 4 3 2 1
www.s-manuals.com