Compal La-6801p r1.0 Schematics

A B C D E
MODEL NAME : PALB0

PCB NO : LA-6801P ( DAB00000410 )
BOM P/N : 46198531L01 -->R3
1 46198531L02 -->R1 1
46198531L03 -->R3
46198531L04 -->R1
Dell/Compal Confidential
Schematic Document
2
Specter (Huron River) 2
Sandy Bridge(PGA) + Cougar Point(standard)

DISCRETE VGA N12E-GE-B (optimus)
3
2011-01-25 3
Rev: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
LA-6801P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 25, 2011 Sheet 1 of 61
A B C D E
A B C D E
Compal Confidential CPU XDP

FFS Fan Control
Project Code : PALB0 P.28 P.30 Conn. P.6
File Name : LA-6801P
HDMI HDMI Intel
Sandy Bridge
1 1
Conn. P.39
DisplayPort GPU
PEG x16 (DIS) Processor Memory Bus (DDRIII) 204pin DDRIII SO-DIMM x2
Dual Channel
DP Conn.
P.38
N12E-GE 4C 45W SV 1.5V DDRIII 1066/1333 MHz
BANK 0, 1, 2, 3 P.11,12
DisplayPort
P.40~45
rPGA 989 Socket
P.5~10
DP (DIS)
DP MUX FDI x8 DMI x4
(UMA) 100MHz
P.37
DP 100MHz 5GB/s Port 0
2.7GT/s SATA HDD Conn.
P.28
LVDS LVDS Port 2

SATA2.0
Conn. SATA ODD Conn.
2
P.21 P.28 2
CRT Port 0 USB 2.0

CRT Conn. ( USB Charger ) P.26
P.21
DisplayPort Intel Port 2

Cougar Point Digital Camera P.21 DMC/Daughter Board
PCI-E x1
PCH Port 4
Port 3 Port 2 Port 1 Port 4 Port 6 Mini Card-1 (WLAN)
( Half ) P.32
USB2.0
Mini Card-1 Mini Card-2 LAN(GbE) Card Reader USB 3.0/2.0
Port 5 Mini Card-2 (WWAN)
WLAN (Half) WWAN (Full) AR8151-BL1A RTS5209 Host Ctrl. BGA 989 Balls ( Full ) P.32 SIM Card P.32
P.22 P.23 P.27
Port 6
3 USB[x] USB[x] USB 3.0/2.0 AlienFX/ELC P.34~36 3
port4 port5 RJ45 9 in 1 Combo Conns x2 HD Audio
P.22 Socket P.23 P.27 Port 8
DMC/Daughter Board P13~20 BT 2.1 /BT 3.0 P.32
P.32
TPA6211A P.25
SPI LPC Bus
RTC CKT. Audio Codec
P.13 ALC665-GR P.24
sub-woofer conn. P.25
Power On/Off CKT.
P.29 SPI ROM ENE 3810 ENE KB930 TI TPA6017A2 P.25
Audio Jack x3
( HeadPhone x2, MIC) P.25
P.13 P.31 P.31
DC/DC Interface CKT.
P.33
Int. Speaker P.25
Digital MIC P.24
4 Power Circuit DC/DC Touch Pad Int.KBD BIOS ROM 4
P.49~59 P.35 P.29 P.31

Block Diagram
LA-6801P
A B C D E
A B C D E
Compal Confidential
Project Code : PALB0
File Name : LA-6801P
1 LA-6801P M/B 1
Camera
40 pin LCD Panel

Wire
Blue Tooth
Wire
LS-6801P 12 pin
80 pin
BTB conn.
LS-6803P
INDICATOR/B HDD
Wire Wire
2
Led-Wireless
6 pin WLAN WWAN/DMC 2
20 pin
Led-CapsLock
DMC/B
14 pin ODD
LF-6801P
FPC
FFC Wire FFC
20 pin
6 pin 12 pin
LS-6802P
LS-6809P LS-6806P
TP LED/B
Touch Pad FFC Led x 6
LOGO LIGHT GUIDE/B POWER BUTTON/B
4 pin on/off SW
Lid Led x 6 Led x 3
3 3
4 pin 4 pin
Wire Wire
LS-6807P LS-6808P
FRONT LIGHT L/B FRONT LIGHT R/B
Led x 2 Led x 2
4 4

Block Diagram
A B C D E
A
Board ID Table for AD channel

Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 None
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 1 JUSB1 (2.0 Ext Left Side)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 2 Bluetooth
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 1.0
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 3 CAMERA
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 4 JMINI1 (WLAN)
PCH
SMBUS Control Table
5 JMINI2 (WWAN/DMC)
Thermal Thermal VGA Thermal
SOURCE MINI1 MINI2 BATT SODIMM Sensor 1 Sensor 2 FFS Sensor VGA DMC XDP Charger
6 ELC 8051
EC_SMB_CK1
EC_SMB_DA1
KB930 V 7 None
EC_SMB_CK2
EC_SMB_DA2
KB930 V V V 8 None
PCH_SML0CLK PCH Link 9 None
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
PCH V 10 None
MEM_SMBCLK
MEM_SMBDATA
PCH V V V V V V V 11 None
12 None
CLKOUT DESTINATION 13 None

1 1
PCI0 PCH_LOOPBACK
PCI1 EC LPC
PCI2 None
SATA DESTINATION PCI EXPRESS DESTINATION
PCI3 None
SATA0 HDD Lane 1 10/100/1G LAN
PCI4 None
SATA1 None Lane 2 MINI CARD-2 WWAN/DMC
SATA2 ODD Lane 3 MINI CARD-1 WLAN

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION
SATA3 None Lane 4 CARD READER
CLKOUT_PCIE0 None CLKOUTFLEX0 None
SATA4 None Lane 5 None
CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 None
SATA5 None Lane 6 USB 3.0
CLKOUT_PCIE2 MINI CARD-2 WWAN CLKOUTFLEX2 None
Lane 7 None
Symbol Note :
CLK CLKOUT_PCIE3 MINI CARD-1 WLAN CLKOUTFLEX3 None
Lane 8 None
CLKOUT_PCIE4 CARD READER : means Digital Ground
CLKOUT_PCIE5 None
: means Analog Ground
CLKOUT_PCIE6 USB 3.0
CLKOUT_PCIE7 None Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
Notes List
CLKOUT_PEG_B None AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-6801P
A
5 4 3 2 1
+VCCP
PEG_ICOMPI and RCOMPO signals should be shorted and routed
1
with - max length = 500 mils - typical impedance = 43 mohms JCPU1I
RC2 PEG_ICOMPO signals should be routed with - max length = 500 mils
24.9_0402_1% - typical impedance = 14.5 mohms
T35 F22
VSS161 VSS234
2
JCPU1A T34 F19
D PEG_COMP VSS162 VSS235 D
J22 T33 E30
PEG_ICOMPI VSS163 VSS236
J21 T32 E27
PEG_ICOMPO VSS164 VSS237
<15> DMI_CRX_PTX_N0 B27 H22 T31 E24
DMI_RX#[0] PEG_RCOMPO VSS165 VSS238
<15> DMI_CRX_PTX_N1 B25 T30 E21
DMI_RX#[1] VSS166 VSS239
<15> DMI_CRX_PTX_N2 A25 T29 E18
DMI_RX#[2] PEG_GTX_C_HRX_N15 VSS167 VSS240
<15> DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15 <40> T28 E15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14 VSS168 VSS241
M35 PEG_GTX_C_HRX_N14 <40> T27 E13
PEG_RX#[1] PEG_GTX_C_HRX_N13 VSS169 VSS242
<15> DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13 <40> T26 E10
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12 VSS170 VSS243
<15> DMI_CRX_PTX_P1 B26 J35 PEG_GTX_C_HRX_N12 <40> P9 E9
DMI_RX[1] PEG_RX#[3] VSS171 VSS244
DMI
<15> DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N11 <40> P8 E8
<15> DMI_CRX_PTX_P3 B23 H34 PEG_GTX_C_HRX_N10 <40> P6 E7
H31 PEG_GTX_C_HRX_N9 <40> P5 E6
<15> DMI_CTX_PRX_N0 G21 G33 PEG_GTX_C_HRX_N8 <40> P3 E5
DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7 VSS175 VSS248
<15> DMI_CTX_PRX_N1 E22 G30 PEG_GTX_C_HRX_N7 <40> P2 E4
<15> DMI_CTX_PRX_N2 F21 F35 PEG_GTX_C_HRX_N6 <40> N35 E3
<15> DMI_CTX_PRX_N3 D21 E34 PEG_GTX_C_HRX_N5 <40> N34 E2
E32 PEG_GTX_C_HRX_N4 <40> N33 E1
<15> DMI_CTX_PRX_P0 G22 D33 PEG_GTX_C_HRX_N3 <40> N32 D35
DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 VSS180 VSS253
<15> DMI_CTX_PRX_P1 D22 D31 PEG_GTX_C_HRX_N2 <40> N31 D32
<15> DMI_CTX_PRX_P2 F20 B33 PEG_GTX_C_HRX_N1 <40> N30 D29
PCI EXPRESS* - GRAPHICS

<15> DMI_CTX_PRX_P3 C21 C32 PEG_GTX_C_HRX_N0 <40> N29 D26
DMI_TX[3] PEG_RX#[15] VSS183 VSS256
N28 D20
PEG_GTX_C_HRX_P15 VSS184 VSS257
J33 PEG_GTX_C_HRX_P15 <40> N27 D17
PEG_RX[0] PEG_GTX_C_HRX_P14 VSS185 VSS258
L35 PEG_GTX_C_HRX_P14 <40> N26 C34
K34 PEG_GTX_C_HRX_P13 <40> M34 C31
FDI_CTX_PRX_N0 PEG_RX[2] PEG_GTX_C_HRX_P12 VSS187 VSS260
<15> FDI_CTX_PRX_N0 A21 H35 PEG_GTX_C_HRX_P12 <40> L33 C28
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PEG_GTX_C_HRX_P11 VSS188 VSS261
<15> FDI_CTX_PRX_N1 H19 H32 PEG_GTX_C_HRX_P11 <40> L30 C27
<15> FDI_CTX_PRX_N2 E19 G34 PEG_GTX_C_HRX_P10 <40> L27 C25
F18 G31 L9 C23
<15>
<15>
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI0_TX#[3]
FDI1_TX#[0] Intel(R) FDI PEG_RX[6]
PEG_RX[7]
F33
F30
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P9 <40>
L8
L6
VSS191
VSS192
VSS264
VSS265
C10
C1
<15> FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PEG_GTX_C_HRX_P6 VSS193 VSS266
<15> FDI_CTX_PRX_N6 D18 E35 PEG_GTX_C_HRX_P6 <40> L5 B22
FDI1_TX#[2] PEG_RX[9] VSS194 VSS267
VSS
C FDI_CTX_PRX_N7 E17 E33 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P5 <40> L4 B19 C
<15> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] VSS195 VSS268
F32 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P4 <40> L3 B17
D34 PEG_GTX_C_HRX_P3 <40> L2 B15
FDI_CTX_PRX_P0 PEG_RX[12] PEG_GTX_C_HRX_P2 VSS197 VSS270
<15> FDI_CTX_PRX_P0 A22 E31 PEG_GTX_C_HRX_P2 <40> L1 B13
FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1 VSS198 VSS271
<15> FDI_CTX_PRX_P1 G19 C33 PEG_GTX_C_HRX_P1 <40> K35 B11
FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 VSS199 VSS272
<15> FDI_CTX_PRX_P2 E20 B32 PEG_GTX_C_HRX_P0 <40> K32 B9
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
<15> FDI_CTX_PRX_P3 G18 K29 B8
FDI_CTX_PRX_P4 FDI0_TX[3] PEG_HTX_GRX_N15 CC200 220nF_0402_16V7K VSS201 VSS274
<15> FDI_CTX_PRX_P4 B20 M29 1 2 PEG_HTX_C_GRX_N15 <40> K26 B7
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] PEG_HTX_GRX_N14 CC199 220nF_0402_16V7K VSS202 VSS275
<15> FDI_CTX_PRX_P5 C19 M32 1 2 PEG_HTX_C_GRX_N14 <40> J34 B5
<15> FDI_CTX_PRX_P6 D19 M31 1 2 PEG_HTX_C_GRX_N13 <40> J31 B3
<15> FDI_CTX_PRX_P7 F17 L32 1 2 PEG_HTX_C_GRX_N12 <40> H33 B2
FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 CC196 220nF_0402_16V7K VSS205 VSS278
L29 1 2 PEG_HTX_C_GRX_N11 <40> H30 A35
FDI_FSYNC0 PEG_TX#[4] PEG_HTX_GRX_N10 CC195 220nF_0402_16V7K VSS206 VSS279
<15> FDI_FSYNC0 J18 K31 1 2 PEG_HTX_C_GRX_N10 <40> H27 A32
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 CC194 220nF_0402_16V7K VSS207 VSS280
<15> FDI_FSYNC1 J17 K28 1 2 PEG_HTX_C_GRX_N9 <40> H24 A29
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 CC193 220nF_0402_16V7K VSS208 VSS281
J30 1 2 PEG_HTX_C_GRX_N8 <40> H21 A26
FDI_INT PEG_TX#[7] PEG_HTX_GRX_N7 CC192 220nF_0402_16V7K VSS209 VSS282
<15> FDI_INT H20 J28 1 2 PEG_HTX_C_GRX_N7 <40> H18 A23
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 CC191 220nF_0402_16V7K VSS210 VSS283
H29 1 2 PEG_HTX_C_GRX_N6 <40> H15 A20
FDI_LSYNC0 PEG_TX#[9] PEG_HTX_GRX_N5 CC190 220nF_0402_16V7K VSS211 VSS284
<15> FDI_LSYNC0 J19 G27 1 2 PEG_HTX_C_GRX_N5 <40> H13 A3
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PEG_HTX_GRX_N4 CC189 220nF_0402_16V7K VSS212 VSS285
<15> FDI_LSYNC1 H17 E29 1 2 PEG_HTX_C_GRX_N4 <40> H10
FDI1_LSYNC PEG_TX#[11] PEG_HTX_GRX_N3 CC188 220nF_0402_16V7K VSS213
F27 1 2 PEG_HTX_C_GRX_N3 <40> H9
PEG_TX#[12] PEG_HTX_GRX_N2 CC187 220nF_0402_16V7K VSS214
D28 1 2 PEG_HTX_C_GRX_N2 <40> H8
+VCCP PEG_TX#[13] PEG_HTX_GRX_N1 CC186 220nF_0402_16V7K VSS215
F26 1 2 PEG_HTX_C_GRX_N1 <40> H7
PEG_TX#[14] PEG_HTX_GRX_N0 CC185 220nF_0402_16V7K VSS216
E25 1 2 PEG_HTX_C_GRX_N0 <40> H6
+EDP_COM PEG_TX#[15] VSS217
1 2 A18 H5
RC36 24.9_0402_1% eDP_COMPIO PEG_HTX_GRX_P15 CC216 220nF_0402_16V7K VSS218
A17 M28 1 2 PEG_HTX_C_GRX_P15 <40> H4
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 CC215 220nF_0402_16V7K VSS219
2 1 B16 M33 1 2 PEG_HTX_C_GRX_P14 <40> H3
eDP_HPD PEG_TX[1] PEG_HTX_GRX_P13 CC214 220nF_0402_16V7K VSS220
M30 1 2 PEG_HTX_C_GRX_P13 <40> H2
R1942 10K_0402_5%~D PEG_TX[2] PEG_HTX_GRX_P12 CC213 220nF_0402_16V7K VSS221
L31 1 2 PEG_HTX_C_GRX_P12 <40> H1
PEG_TX[3] PEG_HTX_GRX_P11 CC212 220nF_0402_16V7K VSS222
C15 L28 1 2 PEG_HTX_C_GRX_P11 <40> G35
eDP_AUX PEG_TX[4] PEG_HTX_GRX_P10 CC211 220nF_0402_16V7K VSS223
D15 K30 1 2 PEG_HTX_C_GRX_P10 <40> G32
eDP_AUX# PEG_TX[5] VSS224
eDP
K27 PEG_HTX_GRX_P9 CC210 1 2 220nF_0402_16V7K PEG_HTX_C_GRX_P9 <40> G29

J29 1 2 PEG_HTX_C_GRX_P8 <40> G26
B PEG_TX[7] PEG_HTX_GRX_P7 CC208 220nF_0402_16V7K VSS226 B
C17 J27 1 2 PEG_HTX_C_GRX_P7 <40> G23
eDP_TX[0] PEG_TX[8] PEG_HTX_GRX_P6 CC207 220nF_0402_16V7K VSS227
F16 H28 1 2 PEG_HTX_C_GRX_P6 <40> G20
C16 G28 1 2 PEG_HTX_C_GRX_P5 <40> G17
G15 E28 1 2 PEG_HTX_C_GRX_P4 <40> G11
F28 1 2 PEG_HTX_C_GRX_P3 <40> F34
C18 D27 1 2 PEG_HTX_C_GRX_P2 <40> F31
eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 CC202 220nF_0402_16V7K VSS232
E16 E26 1 2 PEG_HTX_C_GRX_P1 <40> F29
eDP_TX#[1] PEG_TX[14] PEG_HTX_GRX_P0 CC201 220nF_0402_16V7K VSS233
D16 D25 1 2 PEG_HTX_C_GRX_P0 <40>
eDP_TX#[2] PEG_TX[15]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
A A

PROCESSOR(1/6) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
LA-6801P
5 4 3 2 1
5 4 3 2 1
+VCCP +VCCP
<15,31> PCH_PWROK +3VALW

JXDP1
1 2 +3VS
XDP_PREQ#_R GND0 GND1 CFG16_R RC3 @ 0_0402_5%~D RC128
0.1U_0402_16V7K~D
3 4 1 2 CFG16 <8> <15> SYS_PWROK
XDP_PRDY#_R OBSFN_A0 OBSFN_C0 CFG17_R RC5 @ 0_0402_5%~D +1.5V_CPU_VDDQ
5 6 1 2 CFG17 <8>
OBSFN_A1 OBSFN_C1
1
7 8 @ 1
XDP_BPM#0 GND2 GND3 CFG0_R RC7 @ 0_0402_5%~D RC127 @ RC6
CC65
0_0402_5%~D
9 10 1 2 CFG0 <8>
OBSDATA_A0 OBSDATA_C0
1
XDP_BPM#1 11 12 CFG1_R RC9 1 @ 2 0_0402_5%~D 0_0402_5%~D 10K_0402_5%~D
OBSDATA_A1 OBSDATA_C1 CFG1 <8>
13 14 RC8
XDP_BPM#2 GND4 GND5 CFG2_R RC10 1 @ 0_0402_5%~D 2
15 16 2 CFG2 <8> 200_0402_1%
OBSDATA_A2 OBSDATA_C2
2
XDP_BPM#3 17 18 CFG3_R RC12 1 @ 2 0_0402_5%~D UC1
OBSDATA_A3 OBSDATA_C3 CFG3 <8>
19 20 1 5
GND6 GND7 B VCC
2
0_0402_5%~D 2 @ 1 RC13 CFG10_R 21 22 CFG8_R RC14 1 @ 2 0_0402_5%~D 1 2D_PWG 2
<8> CFG10 OBSFN_B0 OBSFN_D0 CFG8 <8> <15> PM_DRAM_PWRGD A
D 0_0402_5%~D 2 @ 1 RC15 CFG11_R 23 24 CFG9_R RC16 1 @ 2 0_0402_5%~D RC11 0_0402_5%~D3 4 VDDPWRGOOD D
<8> CFG11 OBSFN_B1 OBSFN_D1 CFG9 <8> GND Y
25 26
XDP_BPM#4 GND8 GND9 CFG4_R RC17 1 @ 0_0402_5%~D RC4 74AHC1G09GW TSSOP 5P
27 28 2 CFG4 <8> RC8
XDP_BPM#5 OBSDATA_B0 OBSDATA_D0 CFG5_R RC18 1 @ 0_0402_5%~D
29 30 2 CFG5 <8> +3V_PCH 1 2 CRB 1.1K
OBSDATA_B1 OBSDATA_D1
2
31 32 200_0402_1% CHECK LIST 0.7 --> 4.75K
XDP_BPM#6 GND10 GND11 CFG6_R RC20 1 @ 0_0402_5%~D RC19
33 34 2 CFG6 <8>
XDP_BPM#7 OBSDATA_B2 OBSDATA_D2 CFG7_R RC21 1 @ 0_0402_5%~D INTEL recommand 1.1K
35 36 2 CFG7 <8> 39_0402_1%
OBSDATA_B3 OBSDATA_D3 PDG 0.71 rev -->200
37 38
H_CPUPWRGD 1K_0402_5%~D 1 H_CPUPWRGD_XDP GND12 GND13 CLK_CPU_ITP
2 RC22 39 40 CLK_CPU_ITP <14>
PWRGOOD/HOOK0 ITPCLK/HOOK4
1
<15,31> PBTN_OUT# 0_0402_5%~D 1 2 RC23 CFD_PWRBTN#_XDP 41 42 CLK_CPU_ITP# CLK_CPU_ITP# <14>
HOOK1 ITPCLK#/HOOK5
43 44
1K_0402_5%~D 1 XDP_HOOK2 VCC_OBS_AB VCC_OBS_CD XDP_RST#_R PLT_RST#
<8> CFG0 2 RC24 45 46 1 2
HOOK2 RESET#/HOOK6 D
1
0_0402_5%~D 1 2 RC26 SYS_PWROK_XDP 47 48 XDP_DBRESET# RC25 1K_0402_5%~D
<15,31,57> VGATE HOOK3 DBR#/HOOK7
49 50 RUN_ON_CPU1.5VS3# 2 QC1
GND14 GND15 <10,33> RUN_ON_CPU1.5VS3#
51 52 XDP_TDO RC28 1 @ 2 0_0402_5%~D PCH_JTAG_TDO <13> G SSM3K7002F_SC59-3
<11,12,14,28,32> PCH_SMBDATA SDA TD0 XDP_TRST#_R
<11,12,14,28,32> PCH_SMBCLK 53 54 S
SCL TRST#
3
<13> PCH_JTAG_TCK 1 2 RC30 XDP_TCK1 55 56 XDP_TDI RC31 1 @ 2 0_0402_5%~D PCH_JTAG_TDI <13>
0_0402_5%~D @ XDP_TCK_R TCK1 TDI XDP_TMS_R RC29 1 @
57 58 2 0_0402_5%~D PCH_JTAG_TMS <13>
TCK0 TMS
59 60
GND16 GND17
The resistor SAMTE_BSH-030-01-L-D-A
for HOOK2 should be CONN@ +3VALW
+VCCP
placed such that the +3VALW +VCCP
0.1U_0402_16V7K~D
stub is very small
on CFG0 net 1
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1
CC68
1 1
1
@ RC32
RC27 2
CC67
CC66
75_0402_5%
1K_0402_5%~D
2 2
2
UC2
2
C 1 5 C
SYS_PWROK_XDP NC VCC RC33
<16,22,23,27,31,32> PLT_RST# 2
A BUFO_CPU_RST# BUF_CPU_RST#
3 4 1 2
GND Y 43_0402_1%
Place near JXDP1 SN74LVC1G07DCKR_SC70-5~D
1
@
RC34
0_0402_5%~D
JCPU1B
2
A28 CLK_CPU_DMI_R RC37 1 2 0_0402_5%~D
BCLK CLK_CPU_DMI <14>
MISC
CLOCKS
C26 A27 CLK_CPU_DMI#_R RC38 1 2 0_0402_5%~D
<17> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <14>
AN34
SKTOCC# CLK_CPU_DPLL_R RC39 1
A16 2 0_0402_5%~D CLK_CPU_DPLL <14>
+VCCP DPLL_REF_CLK CLK_CPU_DPLL#_R RC40 1
A15 2 0_0402_5%~D CLK_CPU_DPLL# <14> PU/PD for JTAG signals
DPLL_REF_CLK#
+VCCP
PAD~D T1 @ H_CATERR# AL33
CATERR#
2
THERMAL
RC43 XDP_TMS_R 51_0402_5% 1 2 RC45
62_0402_5% AN33 R8 H_DRAMRST#
<17,31> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
XDP_TDI_R 51_0402_5% 1 2 RC46
DDR3
MISC
1
RC41 XDP_PREQ# 51_0402_5% 1 @ 2 RC47

<31> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 140_0402_1%1
140_0402_1% 2 RC55
56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP1 25.5_0402_1%1 XDP_TDO
A5 2 RC58 51_0402_5% 1 2 RC48
B SM_RCOMP[1] SM_RCOMP2 200_0402_1%1
200_0402_1% B
A4 2 RC60
SM_RCOMP[2]
H_THERMTRIP# AN32 DDR3 Compensation Signals
<17> H_THERMTRIP# THERMTRIP# XDP_TCK_R 51_0402_5% 1 2 RC52
for EMC request, close to CPU 7/26 XDP_TRST#_R 51_0402_5% 1 2 RC54
AP29 XDP_PRDY# RC1211 2 0_0402_5%~D XDP_PRDY#_R

PRDY# XDP_PREQ# RC1221 XDP_PREQ#_R
AP27 2 0_0402_5%~D
PREQ#
AR26 XDP_TCK RC1231 2 0_0402_5%~D XDP_TCK_R
TCK
PWR MANAGEMENT
RC49 AR27 XDP_TMS RC1241 2 0_0402_5%~D XDP_TMS_R

JTAG & BPM
H_PM_SYNC_R TMS XDP_TRST# RC1251 XDP_TRST#_R

<15> H_PM_SYNC 1 2 AM34 AP30 2 0_0402_5%~D
0_0402_5%~D PM_SYNC TRST#
AR28 XDP_TDI_R RC50 1 XDP_TDI
2 0_0402_5%~D
RC53 TDI XDP_TDO_R RC51 1 XDP_TDO
AP26 2 0_0402_5%~D
TDO +3VS
<17> H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33
0_0402_5%~D UNCOREPWRGOOD
close to CPU 7/26
RC56 XDP_DBRESET# 1K_0402_5%~D
1 2 RC42
RC57 AL35 XDP_DBRESET#_R 1 XDP_DBRESET#
2 0_0402_5%~D XDP_DBRESET# <15>
VDDPWRGOOD DBR#
1 2 VDDPWRGOOD_R V8
130_0402_1%~D SM_DRAMPWROK
AT28 XDP_BPM#0_R RC59 1 2 XDP_BPM#0
0_0402_5%~D H_CPUPWRGD_R 10K_0402_5%~D
1 2 RC44
BPM#[0] XDP_BPM#1_R RC61 XDP_BPM#1
0_0402_5%~D
AR29 1 2
0_0402_5%~D
AR30 1 2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R RC63 XDP_BPM#3
0_0402_5%~D
AR33 AT30 1 2
RESET# BPM#[3] XDP_BPM#4_R RC64 XDP_BPM#4
0_0402_5%~D
AP32 1 2
0_0402_5%~D
AR31 1 2
0_0402_5%~D
AT31 1 2
0_0402_5%~D
AR32 1 2
BPM#[7]
XDP_BPM#4 RC68 1 2 0_0402_5%~D
A XDP_BPM#5 CFG12 <8> A
RC69 1 2 0_0402_5%~D
CFG13 <8>
XDP_BPM#6 RC70 1 2 0_0402_5%~D
XDP_BPM#7 CFG14 <8>
Sandy Bridge_rPGA_Rev1p0 RC71 1 2 0_0402_5%~D
CFG15 <8>
CONN@

PROCESSOR(2/6) PM,XDP,CLK
LA-6801P
5 4 3 2 1
5 4 3 2 1
JCPU1C
JCPU1D
AB6 M_CLK_DDR0
<11> DDR_A_D[0..63] SA_CLK[0] M_CLK_DDR0 <11>
AA6 M_CLK_DDR#0
SA_CLK#[0] M_CLK_DDR#0 <11>
D DDR_A_D0 C5 V9 DDR_CKE0_DIMMA AE2 M_CLK_DDR2 D
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <11> <12> DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR2 <12>
DDR_A_D1 D5 AD2 M_CLK_DDR#2
SA_DQ[1] SB_CLK#[0] M_CLK_DDR#2 <12>
DDR_A_D2 D3 DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
SA_DQ[2] SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <12>
DDR_A_D3 D2 DDR_B_D1 A7
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D2 SB_DQ[1]
D6 AA5 M_CLK_DDR1 <11> D10
DDR_A_D5 SA_DQ[4] SA_CLK[1] M_CLK_DDR#1 DDR_B_D3 SB_DQ[2]
C6 AB5 M_CLK_DDR#1 <11> C8
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D4 SB_DQ[3] M_CLK_DDR3
C2 V10 DDR_CKE1_DIMMA <11> A9 AE1 M_CLK_DDR3 <12>
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] M_CLK_DDR#3
C3 A8 AD1 M_CLK_DDR#3 <12>
DDR_A_D8 SA_DQ[7] DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
F10 D9 R10 DDR_CKE3_DIMMB <12>
DDR_A_D9 SA_DQ[8] DDR_B_D7 SB_DQ[6] SB_CKE[1]
F8 D8
DDR_A_D10 SA_DQ[9] DDR_B_D8 SB_DQ[7]
G10 AB4 G4
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D9 SB_DQ[8]
G9 AA4 F4
F9 W9 F1 AB2
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D11 SB_DQ[10] RSVD_TP[11]
F7 G1 AA2
DDR_A_D14 SA_DQ[13] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G8 G5 T9
G7 F5
K4 AB3 F2
K5 AA3 G2
K1 W10 J7 AA1
DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
J1 J8 AB1
J5 K10 T10
J4 K9
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D20 SB_DQ[19]
J2 AK3 DDR_CS0_DIMMA# <11> J9
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_CS1_DIMMA# DDR_B_D21 SB_DQ[20]
K2 AL3 DDR_CS1_DIMMA# <11> J10
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
M8 AG1 K8 AD3 DDR_CS2_DIMMB# <12>
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D23 SB_DQ[22] SB_CS#[0] DDR_CS3_DIMMB#
N10 AH1 K7 AE3 DDR_CS3_DIMMB# <12>
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D24 SB_DQ[23] SB_CS#[1]
N8 M5 AD6
N7 N4 AE6
M10 N2
DDR_A_D29 SA_DQ[28] M_ODT0 DDR_B_D27 SB_DQ[26]
M9 AH3 M_ODT0 <11> N1
DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 DDR_B_D28 SB_DQ[27]
N9 AG3 M_ODT1 <11> M4
SA_DQ[30] SA_ODT[1] SB_DQ[28]
DDR SYSTEM MEMORY A
DDR_A_D31 M7 AG2 DDR_B_D29 N5 AE4 M_ODT2

SA_DQ[31] RSVD_TP[9] SB_DQ[29] SB_ODT[0] M_ODT2 <12>
DDR_A_D32 DDR_B_D30 M_ODT3
DDR SYSTEM MEMORY B

AG6 AH2 M2 AD4 M_ODT3 <12>
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D31 SB_DQ[30] SB_ODT[1]
AG5 M1 AD5
AK6 AM5 AE5
C
DDR_A_D35 SA_DQ[34] DDR_B_D33 SB_DQ[32] RSVD_TP[20] C
AK5 AM6
AH5 DDR_A_DQS#[0..7] <11> AR3
DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D35 SB_DQ[34]
AH6 C4 AP3
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35]
AJ5 G6 AN3 DDR_B_DQS#[0..7] <12>
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0
AJ6 J3 AN2 D7
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ8 M6 AN1 F3
AK8 AL6 AP2 K6
AJ9 AM8 AP5 N3
AK9 AR12 AN9 AN5
AH8 AM15 AT5 AP9
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AH9 AT6 AK12
DDR_A_D46 SA_DQ[45] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AL9 AP6 AP15
DDR_A_D47 SA_DQ[46] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AL8 AN8
AP11 DDR_A_DQS[0..7] <11> AR6
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D47 SB_DQ[46]
AN11 D4 AR5
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D48 SB_DQ[47]
AL12 F6 AR9 DDR_B_DQS[0..7] <12>
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AM12 K3 AJ11 C7
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM11 N6 AT8 G3
AL11 AL5 AT9 J6
AP12 AM9 AH11 M3
AN12 AR11 AR8 AN6
AJ14 AM14 AJ12 AP8
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AH14 AH12 AK11
DDR_A_D58 SA_DQ[57] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AL15 AT11 AP14
DDR_A_D59 SA_DQ[58] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AK15 AN14
AL14 DDR_A_MA[0..15] <11> AR14
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AK14 AD10 AT14
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AJ15 W1 AT12 DDR_B_MA[0..15] <12>
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AH15 W2 AN15 AA8
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
W7 AR15 T7
SA_MA[3] DDR_A_MA4 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
V3 AT15 R7
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
V2 T6
SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
W3 T2
<11> DDR_A_BS0 AE10 W6 T4
SA_BS[0] SA_MA[7] DDR_A_MA8 SB_MA[5] DDR_B_MA6
B
<11> DDR_A_BS1 AF10 V1 T3 B
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS2 V6 W5 <12> DDR_B_BS0 AA9 R2
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[0] SB_MA[7] DDR_B_MA8
AD8 <12> DDR_B_BS1 AA7 T5
SA_MA[10] DDR_A_MA11 SB_BS[1] SB_MA[8] DDR_B_MA9
V4 <12> DDR_B_BS2 R6 R3
SA_MA[11] DDR_A_MA12 SB_BS[2] SB_MA[9] DDR_B_MA10
W4 AB7
<11> DDR_A_CAS# AE8 AF8 R1
SA_CAS# SA_MA[13] DDR_A_MA14 SB_MA[11] DDR_B_MA12
<11> DDR_A_RAS# AD9 V5 T1
SA_RAS# SA_MA[14] DDR_A_MA15 SB_MA[12] DDR_B_MA13
<11> DDR_A_WE# AF9 V7 <12> DDR_B_CAS# AA10 AB10
SA_WE# SA_MA[15] SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_B_RAS# AB8 R5
SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_B_WE# AB9 R4
SB_WE# SB_MA[15]
CONN@
CONN@
+1.5V
1
1 @ 2 RC75
RC74 0_0402_5%~D 1K_0402_5%~D
QC2
BSS138_SOT23
2
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
S
<6> H_DRAMRST# DDR3_DRAMRST# <11,12>

RC76 1K_0402_5%~D
DG 1.0 Figure 61 RC76=1K
G
1
RC77 1 2 DRAMRST_CNTRL_PCH <14>

4.99K_0402_1%~D RC72 0_0402_5%~D
A A
DRAMRST_CNTRL
2
1 @ 2 DRAMRST_CNTRL_EC <31>
RC73 0_0402_5%~D
1
CC69
.047U_0402_16V7K~D
2 Security Classification Compal Secret Data Compal Electronics, Inc.
PROCESSOR(3/6) DDRIII
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

D D
CFG2
1
JCPU1E RC78
1K_0402_1%~D
L7 @ T2 PAD~D
RSVD28
2
AG7 @ T3 PAD~D
CFG0 RSVD29 @ T4 PAD~D
<6> CFG0 AK28 AE7
CFG1 CFG[0] RSVD30 @ T5 PAD~D
<6> CFG1 AK29 AK2
<6> CFG2 AL26 W8
CFG3 CFG[2] RSVD32
<6> CFG3 AL27
CFG4 CFG[3]
<6> CFG4 AK26
CFG[4]
<6> CFG5 CFG5 AL29
CFG[5] RSVD33
AT26 @ T7 PAD~D PEG Static Lane Reversal - CFG2 is for the 16x
<6> CFG6 CFG6 AL30 AM33 @ T8 PAD~D
<6> CFG7 AM31 AJ27
CFG8 CFG[7] RSVD35
<6> CFG8 AM32
CFG[8] 1:(Default) Normal Operation; Lane #
CFG9 AM30 CFG2
<6> CFG9
CFG10 AM28
CFG[9] definition matches socket pin map definition
+VCC_GFXCORE_AXG <6> CFG10 CFG[10]
<6> CFG11 CFG11 AM26
CFG[11]
+VCC_CORE <6> CFG12 CFG12
CFG13
AN28
AN31
CFG[12]
T8 @ T10 PAD~D
* 0:Lane Reversed
<6> CFG13 CFG[13] RSVD37
<6> CFG14 CFG14 AN26 J16 @ T11 PAD~D
CFG[14] RSVD38
2
@ <6> CFG15 CFG15 AM27 H16 @ T12 PAD~D CFG4

RC79 CFG16 CFG[15] RSVD39 @ T13 PAD~D
<6> CFG16 AK31 G16
CFG[16] RSVD40
1
50_0402_1% <6> CFG17 CFG17 AN29
CFG[17]
2
@ @ RC81
RC80 1K_0402_1%~D
1
50_0402_1%
AR35 @ T14 PAD~D
RSVD41
2
VCC_AXG_VAL_SENSE AJ31 AT34 @ T15 PAD~D
VAXG_VAL_SENSE RSVD42
1
VSS_AXG_VAL_SENSE AH31 AT33 @ T16 PAD~D

VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD43 @ T17 PAD~D
AJ33 AP35
VSS_VAL_SENSE VCC_VAL_SENSE RSVD44 @ T18 PAD~D
AH33 AR34
C VSS_VAL_SENSE RSVD45 C
PAD~D T19 @ AJ26

RSVD5 Display Port Presence Strap
+V_DDR_REFA
RESERVED
+V_DDR_REFB
RC82 1 @ 2 0_0402_5%~D +V_DDR_REFA_R B4
RSVD46
B34
A33
@ T20
@ T21
PAD~D
PAD~D CFG4
* 1 : Disabled; No Physical Display Port
RC83 1 @ 2 0_0402_5%~D +V_DDR_REFB_R D1
RSVD6 RSVD47
A34 @ T22 PAD~D attached to Embedded Display Port
RSVD7 RSVD48 @ T23 PAD~D
B35
RSVD49 @ T24 PAD~D
RSVD50
C35 0 : Enabled; An external Display Port device is
1
PAD~D T25 @ F25

connected to the Embedded Display Port
RC84 RC85 PAD~D T26 @ RSVD8
F24
1K_0402_1%~D 1K_0402_1%~D PAD~D T27 @ RSVD9
F23
PAD~D T28 @ RSVD10 @ T29 PAD~D
D24 AJ32
RSVD11 RSVD51
2
PAD~D T30 @ G25 AK32 @ T31 PAD~D CFG6

PAD~D T32 @ RSVD12 RSVD52
G24
PAD~D T33 @ RSVD13 CFG5
E23
RSVD14
INTEL 12/28 recommand PAD~D T34 @ D23
RSVD15
1
PAD~D T35 @ C30 AH27 @ T36 PAD~D
to add 1k pull down PAD~D T37 @ A31
RSVD16 VCC_DIE_SENSE @ RC87 @ RC86
PAD~D T38 @ RSVD17 1K_0402_1%~D 1K_0402_1%~D
B30
PAD~D T39 @ RSVD18
B29
PAD~D T40 @ RSVD19
D30 AN35 CLK_RES_ITP <14>
RSVD20 RSVD54
2
PAD~D T41 @ B31 AM35 CLK_RES_ITP# <14>
PAD~D T42 @ RSVD21 RSVD55
A30
PAD~D T43 @ RSVD22
C29
RSVD23
PAD~D T44 @ J20

PAD~D T45 @ RSVD24 @ T46 PAD~D
B18 AT2
RSVD25 RSVD56
<54> VCCP_PWRCTRL 1 2 H_VCCP_SEL A19 AT1 @ T47 PAD~D
VCCIO_SEL RSVD57
RC88 0_0402_5%~D
RSVD58
AR1 @ T48 PAD~D PCIE Port Bifurcation Straps
B PAD~D T49 @ J15 B
RSVD27
* 11: (Default) x16 - Device 1 functions 1 and 2 disabled
Need PWR add new circuit on 1.05V(refer CRB) B1 @ T50 PAD~D CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
KEY
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CONN@
CFG7
1
@ RC89
1K_0402_1%~D
2
VSS_AXG_VAL_SENSE
VSS_VAL_SENSE PEG DEFER TRAINING

2
@
RC90
@
RC91 CFG7
* 1: (Default) PEG Train immediately
50_0402_1% following xxRESETB de assertion
50_0402_1%
A 0: PEG Wait for BIOS for training A

1
INTEL 12/28 recommand

to add RC120, RC121, RC122, RC123
Please place as close as JCPU1 Security Classification Compal Secret Data Compal Electronics, Inc.
PROCESSOR(4/6) RSVD,CFG
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
JCPU1F POWER
+VCC_CORE QC=94A
+VCC_CORE
DC=53A +VCCP
1 1 1 1 1 AG35
8.5A PDDG 0.7@P12
VCC1
D AG34 AH13 D
CC85 CC70 CC87 CC71 VCC2 VCCIO1
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC86 AG33 AH10 1 1 1 1 1 1 1 1 1 1 1
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC3 VCCIO2
AG32 AG10
2 2 2 2 2 VCC4 VCCIO3
CC72
CC73
CC74
CC75
CC76
CC77
CC88
CC78
CC79
CC80
CC81
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2 2
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
1 1 1 1 1 1 AF35 J13
VCC11 VCCIO10
AF34 J12
CC82 CC89 CC90 CC91 CC83 VCC12 VCCIO11
CC84 AF33 J11
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC13 VCCIO12
AF32 H14
2 2 2 2 2 2 VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
AF30 H11 1 1 1 1 1 1 1 1 1 1 1
VCC16 VCCIO15
AF29 G14
VCC17 VCCIO16
CC92
CC93
CC94
CC95
CC96
CC97
CC98
CC99
CC100
CC101
CC102
AF28 G13
VCC18 VCCIO17
PEG AND DDR

AF27 G12
VCC19 VCCIO18 2 2 2 2 2 2 2 2 2 2 2
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20
AD34 F12
VCC22 VCCIO21
AD33 F11
VCC23 VCCIO22
AD32 E14
VCC24 VCCIO23
AD31 E12
VCC25 VCCIO24
AD30
VCC26
AD29 E11
VCC27 VCCIO25
AD28 D14
VCC28 VCCIO26
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
AD27 D13 1 1 1 1 1 1 1 1 1
+VCC_CORE VCC29 VCCIO27 @
AD26 D12
VCC30 VCCIO28 + +
CC103
CC104
CC105
CC106
CC107
CC108
CC109
CC110
CC111
AC35 D11
VCC31 VCCIO29
AC34 C14
VCC32 VCCIO30 2 2 2 2 2 2 2
AC33 C13
VCC33 VCCIO31 2 2
1 1 1 1 1 AC32 C12
VCC34 VCCIO32
AC31 C11
CC113 CC114 CC115 CC116 CC117 VCC35 VCCIO33
AC30 B14
C
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC36 VCCIO34 C
AC29 B12
2 2 2 2 2 VCC37 VCCIO35
AC28 A14
VCC38 VCCIO36
AC27 A13
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38
AA35 A11
VCC41 VCCIO39
AA34
VCC42
AA33 J23
VCC43 VCCIO40
1 1 1 1 1 AA32
VCC44
AA31
CC118 CC119 CC120 CC121 VCC45
CC122 AA30
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC46
AA29
2 2 2 2 2 VCC47
AA28
VCC48
AA27
VCC49 +VCCP
AA26
VCC50
CORE SUPPLY
Y35
VCC51
Y34
VCC52
Y33
VCC53
1 1 1 1 1 Y32
VCC54
Y31
VCC55
1
CC123 CC124 CC125 CC126 CC127 Y30
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC56
2 2
22U_0805_6.3VAM~D
2 2
22U_0805_6.3VAM~D
2
Y29
VCC57
RC95 RC93 Place the PU
Y28
VCC58 RC95 close to CPU 75_0402_5% resistors close to CPU
Y27 130_0402_1%~D
VCC59
Y26
VCC60
2
V35
VCC61
SVID
V34 AJ29 H_CPU_SVIDALRT# RC94 1 2 43_0402_1%
VCC62 VIDALERT# VR_SVID_ALRT# <57>
V33 AJ30 H_CPU_SVIDCLK RC92 1 2 0_0402_5%~D
VCC63 VIDSCLK VR_SVID_CLK <57>
1 1 1 1 V32 AJ28 H_CPU_SVIDDAT RC96 1 2 0_0402_5%~D
VCC64 VIDSOUT VR_SVID_DAT <57>
V31
CC128 CC129 CC130 CC131 VCC65
V30
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC66
V29
2 2 2 2 VCC67
V28
VCC68
V27
VCC69
V26
VCC70
B U35 B
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80 +VCC_CORE
R35
+VCC_CORE VCC81
R34
VCC82
R33
VCC83
1
R32
VCC84 RC97
R31
VCC85
R30 100_0402_1%~D
VCC86
1 1 1 1 R29
VCC87
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
SENSE LINES
R28
VCC88
2
+ CC132 + CC133 + CC134 + CC135 R27 AJ35 VCCSENSE_R RC98 1 2 0_0402_5%~D
VCC89 VCC_SENSE VCCSENSE <57>
R26 AJ34 VSSSENSE_R RC99 1 2 0_0402_5%~D VSSSENSE <57>
VCC90 VSS_SENSE
P35
2 2 2 2 VCC91
P34
VCC92
1
P33
VCC93 RC100
P32 B10 VCCIO_SENSE <54>
VCC94 VCCIO_SENSE
P31 A10 VSSIO_SENSE <54> 100_0402_1%~D
VCC95 VSSIO_SENSE
P30
VCC96
P29
VCC97
2
P28
VCC98
P27
VCC99
1 P26
VCC100
470U_D2_2VM_R4.5M~D
+ CC136
2
A A
CONN@

PROCESSOR(5/6) PWR,BYPASS
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+1.5V QC3 +1.5V_CPU_VDDQ
+3VALW B+_BIAS AO4728L_SO8~D
8 1
7 2
1
6 3 1
20K_0402_5%~D
5
1
RC101
10U_0805_10V4Z~D
CC138
RC103
RC102 100K_0402_5%~D
4
100K_0402_5%~D 2
2
RUN_ON_CPU1.5VS3 JCPU1H
0.1U_0603_50V_X7R
AT35 AJ22
VSS1 VSS81
1
QC5B 1 AT32 AJ19
VSS2 VSS82
330K_0402_1%
D RUN_ON_CPU1.5VS3# 5 AT29 AJ16 D
VSS3 VSS83
CC139
AT27 AJ13
RC105
2N7002DW-7-F_SOT363-6~D AT25 VSS4 VSS84 AJ10
VSS5 VSS85
4
2 AT22 AJ7
VSS6 VSS86
2
6
AT19 AJ4
QC5A AT16 VSS7 VSS87 AJ3
@ RC104 2N7002DW-7-F_SOT363-6~D AT13 VSS8 VSS88 AJ2
1 2 2 AT10 VSS9 VSS89 AJ1
<18,31,33,53,54> SUSP# VSS10 VSS90
0_0402_5%~D AT7 AH35
RC107 AT4 VSS11 VSS91 AH34
VSS12 VSS92
1
<31> CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# <6,33>
AT3 AH32
0_0402_5%~D AR25 VSS13 VSS93 AH30
AR22 VSS14 VSS94 AH29
1 VSS15 VSS95
AR19 AH28
CC217 @ VSS16 VSS96
AR16 AH26
0.1U_0402_10V7K~D
2 AR10 VSS18 VSS98 AH22
VSS22 VSS102
POWER
AP34 AH4
AP31 VSS23 VSS103 AG9
AP28 VSS24 VSS104 AG8
+VCC_GFXCORE_AXG JCPU1G AP25 VSS25 VSS105 AG4
VSS26 VSS106
AP22 AF6
VSS27 VSS107
33A AP19
VSS28 VSS108
AF5
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE AP16 AF3
VAXG1 VAXG_SENSE VSS_AXG_SENSE VCC_AXG_SENSE <57> VSS29 VSS109
AT23 AK34 VSS_AXG_SENSE <57> AP13 AF2
VAXG2 VSSAXG_SENSE +1.5V_CPU_VDDQ VSS30 VSS110
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1 AT21 AP10 AE35

VAXG3 VSS31 VSS111
CC140
CC141
CC142
CC143
CC144
CC145
CC146
CC147
AT20 AP7 AE34

AT18 VAXG4 AP4 VSS32 VSS112 AE33
AT17 VAXG5 AP1 VSS33 VSS113 AE32
VAXG6 VSS34 VSS114
1
2 2 2 2 2 2 2 2 AR24 AN30 AE31
AR23 VAXG7 1 2 AN27 VSS35 VSS115 AE30
VAXG8 1K_0402_5%~D VSS36 VSS116
VSS
AR21 +V_SM_VREF should @ RC106 0_0402_5%~D AN25 AE29
AR20 VAXG9 RC112 AN22 VSS37 VSS117 AE28
VAXG10 have 10 mil trace width VSS38 VSS118
VREF
AR18 AN19 AE27
VAXG11 VSS39 VSS119
2
AR17 AN16 AE26
AP24 VAXG12 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF AN13 VSS40 VSS120 AE9
AP23 VAXG13 SM_VREF AN10 VSS41 VSS121 AD7
VAXG14 VSS42 VSS122
1
AP21 AN7 AC9
VAXG15 VSS43 VSS123
1
C C
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1 AP20 AN4 AC8

VAXG16 1K_0402_5%~D VSS44 VSS124
CC148
CC149
CC150
CC151
CC152
CC153
CC154
CC155
AP18 RC126 QC4 AM29 AC6

AP17 VAXG17 2 NTR4503NT1G_SOT23-3~D RC116 AM25 VSS45 VSS125 AC5
VAXG18 100K_0402_5%~D VSS46 VSS126
AN24 AM22 AC3
VAXG19 VSS47 VSS127
2
2 2 2 2 2 2 @ 2 2 @ AN23 RUN_ON_CPU1.5VS3 AM19 AC2
VAXG20 VSS48 VSS128
2
AN21
AN20 VAXG21 5A AM16
AM13 VSS49 VSS129
AB35
AB34
AN18 VAXG22 +1.5V_CPU_VDDQ @ AM10 VSS50 VSS130 AB33
DDR3 -1.5V RAILS
AN17 VAXG23 J8 AM7 VSS51 VSS131 AB32

AM24 VAXG24 AF7 1 2 AM4 VSS52 VSS132 AB31
GRAPHICS
VAXG25 VDDQ1 +1.5V VSS53 VSS133

AM23 AF4 AM3 AB30
AM21 VAXG26 VDDQ2 AF1 PAD-OPEN 4x4m AM2 VSS54 VSS134 AB29
VAXG27 VDDQ3 J8 OPEN VSS55 VSS135
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1 1 AM20 AC7 1 1 1 1 1 1 1 AM1 AB28
VAXG28 VDDQ4 VSS56 VSS136
AM18 AC4 AL34 AB27
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
CC160
CC161
CC162
CC163
CC164
CC165
+ CC156 + CC157 AM17 AC1 + CC166 AL31 AB26
AL24 VAXG30 VDDQ6 Y7 330U_D2_2VM_R6M~D AL28 VSS58 VSS138 Y9
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 AL25 VSS59 VSS139 Y8
2 2 AL21 VAXG32 VDDQ8 Y1 2 AL22 VSS60 VSS140 Y6
AL20 VAXG33 VDDQ9 U7 AL19 VSS61 VSS141 Y5
AK24 VAXG36 VDDQ12 P7 AL10 VSS64 VSS144 W35
AK23 VAXG37 VDDQ13 P4 AL7 VSS65 VSS145 W34
AK21 P1 AL4 W33
AK20 VAXG39 VDDQ15 AL2 VSS67 VSS147 W32
AK18 VAXG40 AK33 VSS68 VSS148 W31
AK17 VAXG41 AK30 VSS69 VSS149 W30
AJ24 VAXG42 AK27 VSS70 VSS150 W29
VAXG46 +VCCSA VSS74 VSS154
AJ18 AK16 U9
AJ17 VAXG47 AK13 VSS75 VSS155 U8
VAXG48 1 VSS76 VSS156
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0603_6.3V6M~D
AH24 1 1 1 1 @ AK10 U6
SA RAIL
VAXG49 VSS77 VSS157

AH23
VAXG50 6A + CC171
330U_D2_2VM_R6M~D
AK7
VSS78 VSS158
U5
CC167
CC168
CC169
CC170
AH21 M27 AK4 U3
AH20 VAXG51 VCCSA1 M26 AJ25 VSS79 VSS159 U2
AH18 VAXG52 VCCSA2 L26 2 2 2 2 2 VSS80 VSS160
AH17 VAXG53 VCCSA3 J26
VAXG54 VCCSA4 J25
VCCSA5 J24
B VCCSA6 H26 Sandy Bridge_rPGA_Rev1p0
B
VCCSA7 H25 CONN@
+1.8VS VCCSA8 RC120 1 2 0_0402_5%~D VSSSA_SENSE <55>
1.8V RAIL
TBD
RC109 1 2 0_0805_5%~D +1.8VS_VCCPLL B6 H23 +1.5V_CPU_VDDQ +1.5V
VCCPLL1 VCCSA_SENSE VCCSA_SENSE <55>
MISC
A6
VCCPLL2
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
330U_D2_2.5VM_R6M~D
1 1 1 1 A2
VCCPLL3 CC182 2 1 0.1U_0402_10V7K~D
H_FC_C22
CC172
CC174
CC175
CC176
+ C22
FC_C22
C24 VCCSA_SEL <55>
2 2 2 VCCSA_VID1 CC184 2 1 0.1U_0402_10V7K~D
1
2
RC111 @ RC110
Sandy Bridge_rPGA_Rev1p0 10K_0402_5%~D 0_0402_5%~D CC181 2 1 0.1U_0402_10V7K~D
CONN@
2
CC183 2 1 0.1U_0402_10V7K~D
add CC181 , CC182, 4 caps are all pop.

follow checklist 1.0 5/24
A A

PROCESSOR(6/6) PWR,VSS
Size Docum ent Num ber Rev
LA-6801P 1.0
Date: Tues day, January 25, 2011 Sheet 10 of 61

5 4 3 2 1
5 4 3 2 1
+1.5V RD2 0_0402_5%~D +1.5V +1.5V

+V_DDR_REFA 1 2 JDIMM1
1
+DIMM0_VREF 1 2
<7> DDR_A_DQS#[0..7] VREF_DQ VSS
RD1 3 4 DDR_A_D4
DDR_A_D0 VSS DQ4 DDR_A_D5
2.2U_0603_6.3V6K~D
0.1U_0402_16V7K~D
1K_0402_1%~D 5 6
<7> DDR_A_DQS[0..7] DQ0 DQ5
DDR_A_D1 7 8
+V_DDR_REFA DQ1 VSS DDR_A_DQS#0
<7> DDR_A_D[0..63] 1 1 9 10
VSS DQS0#
2
11 12 DDR_A_DQS0
DM0 DQS0
CD1
CD2
<7> DDR_A_MA[0..15]
13 14
DDR_A_D2 VSS VSS DDR_A_D6
15 16
2 2 DQ2 DQ6
1
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
RD3 DDR_A_D8 VSS VSS DDR_A_D12
21 22
1K_0402_1%~D DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
DQ9 DQ13
25 26
VSS VSS
2
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# <7,12>
D DQS1 RESET# D
31 32
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
VSS VSS
Layout Note: All VREF traces should DDR_A_D16 39
DQ16 DQ20
40 DDR_A_D20
have 10 mil trace width DDR_A_D17 41 42 DDR_A_D21
Place near JDIMM1 43 DQ17 DQ21 44
DDR_A_DQS#2 VSS VSS
45 46
DDR_A_DQS2 47 DQS2# DM2 48
DQS2 VSS DDR_A_D22
49 50
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 54
+1.5V DQ19 VSS DDR_A_D28
55 56
DDR_A_D25 59 DQ24 DQ29 60
DQ25 VSS DDR_A_DQS#3
61 62
VSS DQS3# DDR_A_DQS3
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
63 64
65 DM3 DQS3 66
1 1 1 1 VSS VSS
DDR_A_D26 DDR_A_D30
CD3
CD4
CD5
CD6
67 68
69 70
71 DQ27 DQ31 72
2 2 2 2 VSS VSS
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
VDD VDD DDR_A_MA15
77 78
DDR_A_BS2 NC A15 DDR_A_MA14
<7> DDR_A_BS2 79 80
BA2 A14
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 86
+1.5V A9 A7
87 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
93 A5 A4 94
DDR_A_MA3 VDD VDD DDR_A_MA2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
330U_SX_2VY~D
@ 1 99 100
C M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1 C
1 1 1 1 1 1 1 <7> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <7>
M_CLK_DDR#0 M_CLK_DDR#1
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
+ 103 104
<7> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <7> +1.5V
105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 108 DDR_A_BS1 <7>
2 2 2 2 2 2 2 2 DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<7> DDR_A_BS0 109 110 DDR_A_RAS# <7>
BA0 RAS#
111 112
VDD VDD
1
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<7> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
DDR_A_CAS# 115 116 M_ODT0 RD4
<7> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
117 118 1K_0402_1%~D
DDR_A_MA13 VDD VDD M_ODT1
119 120 M_ODT1 <7>
DDR_CS1_DIMMA# A13 ODT1
<7> DDR_CS1_DIMMA# 121 122
S1# NC
2
123 124
VDD VDD +VREF_CA
125 126
TEST VREF_CA
127 128
VSS VSS
Layout Note: DDR_A_D32 DDR_A_D36
2.2U_0603_6.3V6K~D
0.1U_0402_16V7K~D
129 130
DQ32 DQ36
1
DDR_A_D33 131 132 DDR_A_D37
Place near JDIMM1.203,204 133
DQ33 DQ37
134 1 1 RD5
DDR_A_DQS#4 VSS VSS 1K_0402_1%~D
135 136
DQS4# DM4
CD15
CD16
DDR_A_DQS4 137 138
139 DQS4 VSS 140 DDR_A_D38
VSS DQ38 2 2
2
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_A_D44
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
+0.75VS DDR_A_D41 149 DQ40 DQ45 150
151 152
153 154
DM5 DQS5
155 156
157 158
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
159 160
DQ43 DQ47
1 1 1 1 161 162
163 164
DQ48 DQ52
CD17
CD18
CD19
CD20
DDR_A_D49 165 166 DDR_A_D53

DQ49 DQ53
167 168
2 2 2 2 DDR_A_DQS#6 VSS VSS
169 170
DDR_A_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_A_D54
173 174
B
DDR_A_D51 DQ50 DQ55 B
177 178
179 DQ51 VSS 180 DDR_A_D60
<BOM Structure> DDR_A_D57 DQ56 DQ61
183 184
185 186
187 188
DM7 DQS7
189 190
191 192
193 194
DQ59 DQ63
195 196
VSS VSS
1 2 197 198
RD6 10K_0402_5%~D 199 SA0 EVENT# PCH_SMBDATA
+3VS 200 PCH_SMBDATA <6,12,14,28,32>
VDDSPD SDA PCH_SMBCLK
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
1 2 201 202 PCH_SMBCLK <6,12,14,28,32>

RD7 10K_0402_5%~D 203 SA1 SCL
1 1 204 +0.75VS
VTT VTT
CD21
CD22
+0.75VS
205 206
GND1 GND2
207 208
2 2 BOSS1 BOSS2
FOX_AS0A626-U2SN-7F
A A

DDRIII DIMMA
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
RD14 0_0402_5%~D
1 2 +1.5V +1.5V
+V_DDR_REFB
JDIMM2
+1.5V +DIMM1_VREF 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
2.2U_0603_6.3V6K~D
0.1U_0402_16V7K~D
5 6
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
1
1 1 9 10 DDR_B_DQS#0
11 VSS4 DQS#0 12 DDR_B_DQS0
DM0 DQS0
CD27
CD26
RD15 13 14
1K_0402_1%~D DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 16
+V_DDR_REFB 2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
DQ3 DQ7
2
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
<7> DDR_B_DQS#[0..7] 21 22
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13
<7> DDR_B_DQS[0..7] 25 26
VSS9 VSS10
1
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
<7> DDR_B_D[0..63] 29 30 DDR3_DRAMRST# <7,11>
D DQS1 RESET# D
RD16 Note: 31
VSS11 VSS12
32
1K_0402_1%~D DDR_B_D10 33 34 DDR_B_D14
<7> DDR_B_MA[0..15] Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
2
VREF_DQ at the DIMM socket 37
VSS13 VSS14
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
43 DQ17 DQ21 44
DDR_B_DQS#2 VSS15 VSS16
45 46
DDR_B_DQS2 47 DQS#2 DM2 48
DQS2 VSS17 DDR_B_D22
49 50
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS19 DDR_B_D28
All VREF traces should 55 56
have 10 mil trace width DQ24 DQ29
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 62
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
VSS23 VSS24
Layout Note: DDR_B_D26 67
DQ26 DQ30
68 DDR_B_D30
DDR_B_D27 69 70 DDR_B_D31
Place near JDIMMB 71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
VDD1 VDD2 DDR_B_MA15
77 78
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 80
+1.5V BA2 A14
81 82
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
83 84
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
87 A9 A7 88
VDD5 VDD6
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
1 1 1 1 A5 A4
CD28
CD29
CD30
CD31
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
95 96
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
C 2 2 2 2 99 A1 A0 100 C
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<7> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <7> +1.5V
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <7>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<7> DDR_B_BS0 109 110 DDR_B_RAS# <7>
BA0 RAS#
111 112
VDD13 VDD14
1
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
+1.5V <7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <7> RD17
CAS# ODT0 1K_0402_1%~D
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3
119 120 M_ODT3 <7>
DDR_CS3_DIMMB# A13 ODT1
<7> DDR_CS3_DIMMB# 121 122
S1# NC2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@ 123 124
VDD17 VDD18 +VREF_CB
125 126
NCTEST VREF_CA
330U_SX_2VY~D
@ 1 127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_16V7K~D
1 1 1 1 1 1 1 DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
+ DDR_B_D33 DDR_B_D37
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
131 132
DQ33 DQ37 RD18
133 134 1 1
DDR_B_DQS#4 VSS29 VSS30 1K_0402_1%~D
135 136
2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS#4 DM4
CD40
CD41
137 138
DQS4 VSS31 DDR_B_D38
139 140
VSS32 DQ38 2 2
2
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44
145 146
DDR_B_D41 DQ40 DQ45
149 150
151 152
VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
157 158
DQ42 DQ46
Layout Note: DDR_B_D43 159
DQ43 DQ47
160 DDR_B_D47
161 162
Place near JDIMMB.203,204 DDR_B_D48 163
VSS39 VSS40
164 DDR_B_D52
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42
169 170
DDR_B_DQS6 DQS#6 DM6
171 172
173 DQS6 VSS43 174 DDR_B_D54
B
B
175 176
DDR_B_D51 177 DQ50 DQ55 178
+0.75VS 179 DQ51 VSS45 180 DDR_B_D60
181 182
DDR_B_D57 DQ56 DQ61
183 184
185 186
VSS48 DQS#7 DDR_B_DQS7
187 188
DM7 DQS7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
189 190
1 1 1 1 191 192
193 194
DQ59 DQ63
CD42
CD43
CD44
CD45
195 196
+3VS VSS51 VSS52
197 198
2 2 2 2 SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA <6,11,14,28,32>
VDDSPD SDA PCH_SMBCLK
2 1 201 202 PCH_SMBCLK <6,11,14,28,32>
SA1 SCL
+0.75VS 203 204 +0.75VS
VTT1 VTT2
1
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
RD19
10K_0402_5%~D
10K_0402_5%~D 205 206

G1 G2
RD20
1 1
CD46
CD47
LCN_DAN06-K4926-0100
2
2 2 CONN@
A A

DDRIII DIMMB
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2
RH2 10M_0402_5%
@
2 1 HDA_SDOUT
CH103 10P_0402_50V8J~D
32.768KHZ_12.5PF_Q13MC14610002
@
2 1 HDA_BIT_CLK
1
CH97 10P_0402_50V8J~D UH1 R1@

18P_0402_50V8J~D
1 1
OSC
OSC
CH2 CH3
18P_0402_50V8J~D
+RTCVCC
2 YH1 2
Reserve for RF please close to UH1
NC
NC
D D
RH11 1 2 SM_INTRUDER# BD82HM67 SLH9C B2
1M_0402_5%~D
2
SA00004ED2L
R3@ SA00004ED3L
UH1A
far away hot spot
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <31>
1
CMOS A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <31>
LPC
CH4 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <31>
1U_0603_10V4Z SHORT PADS C37 LPC_AD3
2 FWH3 / LAD3 LPC_AD3 <31>
2
1 2 PCH_RTCRST# D20
RH25 20K_0402_5%~D RTCRST# LPC_FRAME#
D36 LPC_FRAME# <31>
PCH_SRTCRST# FWH4 / LFRAME#
1 2 G22
RH23 20K_0402_5%~D1 SRTCRST#
E36
LDRQ0#
RTC
1
SM_INTRUDER# K22 K36
CH5 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <31>
2 INTVRMEN SERIRQ
2
ME CMOS
CLP1 & CLP2 place near DIMM
AM3 SATA_PRX_DTX_N1 <28>
HDA_BIT_CLK HDA_BIT_CLK SATA0RXN
<24> HDA_BITCLK_AUDIO 1 2 N34 AM1 SATA_PRX_DTX_P1 <28>
HDA_BCLK SATA0RXP
RH27 33_0402_5% AP7 SATA_PTX_DRX_N1 CH91 1 2 0.01U_0402_16V7K~D HDD1
SATA 6G
+5VS HDA_SYNC SATA0TXN SATA_PTX_DRX_N1_C <28>
L34 AP5 SATA_PTX_DRX_P1 CH90 1 2 0.01U_0402_16V7K~D
HDA_RST# HDA_SYNC SATA0TXP SATA_PTX_DRX_P1_C <28>
<24> HDA_RST_AUDIO# 1 2
RH28 33_0402_5% HDA_SPKR T10 AM10
<24> HDA_SPKR SPKR SATA1RXN
2
G
AM8
HDA_RST# SATA1RXP
K34 AP11
HDA_SYNC_R HDA_SYNC HDA_RST# SATA1TXN
<24> HDA_SYNC_AUDIO 1 2 3 1 AP10
RH33 33_0402_5% SATA1TXP
S
<24> HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 <28>

QH1 BSS138_SOT23 HDA_SDIN0 SATA2RXN AD5
SATA2RXP SATA_PRX_DTX_P2 <28> +3VS
1 2 1 @ 2 G34
HDA_SDIN1 SATA2TXN
AH5 SATA_PTX_DRX_N2 CH92 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_RP <28> ODD
RH275 1M_0402_5%~D RH36 0_0402_5%~D AH4 SATA_PTX_DRX_P2 CH93 1 2 0.01U_0402_16V7K~D
SATA2TXP SATA_PTX_DRX_P2_RP <28>
C34
HDA_SDIN2
IHDA
C AB8 SERIRQ RH29 2 1 10K_0402_5%~D C
SATA3RXN +RTCVCC
A34 AB10
@ HDA_SDOUT HDA_SDIN3 SATA3RXP PCH_GPIO21 RH32
<31> HDA_SDO 1 2 AF3 2 1 10K_0402_5%~D
RH24 0_0402_5%~D SATA3TXN
AF1
HDA_SDOUT SATA3TXP PCH_INTVRMEN RH31
A36 2 1 330K_0402_5% PCH_SATALED#RH35 2 1 10K_0402_5%~D
HDA_SDO
SATA
<24> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT Y7
RH30 33_0402_5% SATA4RXN PCH_INTVRMEN RH34 @
Y5 2 1 330K_0402_5%
SATA4RXP
C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN +3VS
AD1
DP_PCH_HPD SATA4TXP
<38> DP_PCH_HPD N32 INTVRMEN
HDA_DOCK_RST# / GPIO13
SATA5RXN
Y3
Y1
* HL Integrated
Integrated
VRM enable
VRM disable HDA_SPKR RH37 2 @ 1 1K_0402_5%~D
SATA5RXP
AB3
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK SATA5TXN
<6> PCH_JTAG_TCK J3 AB1 LOW=Default
JTAG_TCK SATA5TXP
<6> PCH_JTAG_TMS
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA *HIGH=No Reboot
JTAG_TMS SATAICOMPO
JTAG
1
@ RH38 @ RH39 @ RH40

@RH40 PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
<6> PCH_JTAG_TDI JTAG_TDI SATAICOMPI
200_0402_5% 200_0402_5% 200_0402_5% RH41 37.4_0402_1%
PCH_JTAG_TDO
<6> PCH_JTAG_TDO H1
JTAG_TDO
AB12 +1.05VS_SATA3 HDA_SDO +3V_PCH
SATA3RCOMPO
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI ME debug mode , this signal has a weak internal PD
AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH43 49.9_0402_1% L=>security measures defined in the Flash HDA_SDOUT RH42 2 @ 1 1K_0402_5%~D
RH44 RH45 RH46 RH255 0_0402_5%~D
Descriptor will be in effect (default)
100_0402_1%~D 100_0402_1%~D 100_0402_1%~D PCH_SPI_CLK_R 2 1 PCH_SPI_CLK T3
SPI_CLK SATA3RBIAS
AH1 RBIAS_SATA3 1
RH48
2
750_0402_1%~D *Low = Disabled
High = Enabled
PCH_SPI_CS# Y14 H=>Flash Descriptor Security will be overridden
SPI_CS0#
2
close to UH1
T1
SPI_CS1#
SPI
P3 PCH_SATALED#
SATALED# PCH_SATALED# <35>
PCH_SPI_SI V4 V14 PCH_GPIO21
+3V_PCH SPI_MOSI SATA0GP / GPIO21
PCH_SPI_SO U3 P1 BBS_BIT0_R 2 1 10K_0402_5%~D HDA_SYNC
SPI_MISO SATA1GP / GPIO19 +3VS
RH276
1
@ This signal has a weak internal pull-down

B RH267 CougarPoint_Rev_1p0
On Die PLL VR is supplied by B
10K_0402_5%~D
1.5V when smapled high
RTC Battery 1.8V when sampled low
2
DP_PCH_HPD SPI ROM FOR ME ( 4MByte ) Needs to be pulled High for Huron River platfrom
+3V_PCH
2
RH268
100K_0402_5%~D
+3V_PCH +RTCBATT HDA_SYNC RH52 2 1 1K_0402_5%~D
@
SPI ROM FOR ME
1
( 4MByte )
2
@ RH57
3.3K_0402_5% +CHGRTC RH259
+3V_PCH 1K_0402_5%~D
1
U48
1
PCH_JTAG_TCK 1 2 PCH_SPI_CS# 1 2 PCH_SPI_CS#_R 1 8 W=20mils
RH53 51_0402_5% RH58 0_0402_5%~D /CS VCC
1 W=20mils
+3V_PCH
2
PCH_SPI_SO 1 2 PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# CH6
RH60 33_0402_5% DO /HOLD 0.1U_0402_16V7K~D DH4
PCH_SPI_WP# 3 6 PCH_SPI_CLK_R BAT54CW_SOT323-3
/WP CLK 2
1 2 PCH_SPI_WP# 4 5 PCH_SPI_SI_R 1 2 PCH_SPI_SI
RH54 3.3K_0402_5% GND DIO RH63 33_0402_5%
1
+RTCVCC
1 2 PCH_SPI_HOLD# W25Q32BVSSIG_SO8
RH56 3.3K_0402_5% W=20mils 1
SPI BIOS Pinout CH95
1U_0603_10V4Z
(1)CS# (5)DIO 2
@ @ (2)DO (6)CLK
CH94 RH256
2 1 1 2 PCH_SPI_CLK_R
(3)WP# (7)HOLD#
22P_0402_50V8J~D 33_0402_5% (4)GND (8)VCC
A A
Reserve for EMI please close to U48 RH260 RH261
W25X32 0_0603_5%~D 0_0603_5%~D
+CHGRTC 2 1 2 1
+3VLP
CH98
2 1 PCH_SPI_CLK
@
10P_0402_50V8J~D
Reserve for RF please close to UH1 Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
PCH (1/8) SATA,HDA,SPI, LPC
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
1 2 EC_LID_OUT# SMBCLK 1 2 +3V_PCH

EC_LID_OUT# <31>
0_0402_5%~D RH68 RH67 2.2K_0402_5%~D
UH1B SMBDATA 1 2
RH69 2.2K_0402_5%~D
<22> PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_N3 BG34 @ SML0CLK 1 2
PCIE_PRX_GLANTX_P3 PERN1 PCH_LID_SW_IN# RH70 2.2K_0402_5%~D
<22> PCIE_PRX_GLANTX_P3 BJ34 E12 1 2 LID_SW_IN# <31,34,35>
PERP1 SMBALERT# / GPIO11
10/100/1G LAN ---> <22> PCIE_PTX_GLANRX_N3
CH9 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_N3_C AV32
PETN1
0_0402_5%~D RH71 SML0DATA 1 2
CH14 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_P3_C AU32 H14 SMBCLK RH72 2.2K_0402_5%~D
<22> PCIE_PTX_GLANRX_P3 PETP1 SMBCLK
MEMORY SML1CLK 1 2
<32> PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_N2 BE34 C9 SMBDATA RH73 2.2K_0402_5%~D
PCIE_PRX_WANTX_P2 PERN2 SMBDATA SML1DATA
<32> PCIE_PRX_WANTX_P2 BF34 1 2
PERP2
MiniDMC (Mini Card 2)---> <32> PCIE_PTX_WANRX_N2
CH10 1 2 0.1U_0402_10V7K~D PCIE_PTX_WANRX_N2_C BB32
PETN2
RH74 2.2K_0402_5%~D
CH15 1 2 0.1U_0402_10V7K~D PCIE_PTX_WANRX_P2_C AY32 LID_SW_IN# 1 2
<32> PCIE_PTX_WANRX_P2 PETP2
SMBUS
D DRAMRST_CNTRL_PCH R1790 10K_0402_5%~D D
A12 DRAMRST_CNTRL_PCH <7>
PCIE_PRX_WLANTX_N1 SML0ALERT# / GPIO60 @
<32> PCIE_PRX_WLANTX_N1 BG36
PCIE_PRX_WLANTX_P1 PERN3 SML0CLK
<32> PCIE_PRX_WLANTX_P1 BJ36 C8
PERP3 SML0CLK
MiniWLAN (Mini Card 1)---> <32> PCIE_PTX_WLANRX_N1
CH11 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N1_C AV34
PETN3
DRAMRST_CNTRL_PCH 1 2
CH16 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P1_C AU34 G12 SML0DATA RH75 1K_0402_5%~D
<32> PCIE_PTX_WLANRX_P1 PETP3 SML0DATA
<23> PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_N4 BF36
PCIE_PRX_CARDTX_P4 PERN4
<23> PCIE_PRX_CARDTX_P4 BE36
PERP4
CARD_READER ---> <23> PCIE_PTX_CARDRX_N4
CH12 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_N4_C AY34
PETN4 SML1ALERT# / PCHHOT# / GPIO74
C13
CH13 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_P4_C BB34 CLKIN_DMI2# RH76 1 2 10K_0402_5%~D
<23> PCIE_PTX_CARDRX_P4 PETP4
E14 SML1CLK CLKIN_DMI2 RH78 1 2 10K_0402_5%~D
SML1CLK / GPIO58
PCI-E*
BG37 CLKIN_DMI# RH77 1 2 10K_0402_5%~D
PERN5 SML1DATA CLKIN_DMI RH79 10K_0402_5%~D
BH37 M16 1 2
PERP5 SML1DATA / GPIO75 CLKIN_DOT96# RH80 10K_0402_5%~D
AY36 1 2
PETN5
BB36
PETP5 Total device 20090512 CLKIN_DOT96 RH81 1 2 10K_0402_5%~D
CLKIN_SATA# RH82 1 2 10K_0402_5%~D
PCIE_PRX_USB3TX_N6 BJ38
add double mosfet prevent CLKIN_SATA RH83 1 2 10K_0402_5%~D
<27> PCIE_PRX_USB3TX_N6 PERN6
<27> PCIE_PRX_USB3TX_P6 PCIE_PRX_USB3TX_P6 BG38 ATI M92 electric leakage CLK_PCH_14M RH84 1 2 10K_0402_5%~D
PERP6
USB 3.0 ---> CH19 1 2 0.1U_0402_10V7K~D PCIE_PTX_USB3RX_N6_C
Controller
<27> PCIE_PTX_USB3RX_N6 AU36 M7
CH20 1 PETN6 CL_CLK1
<27> PCIE_PTX_USB3RX_P6 2 0.1U_0402_10V7K~D PCIE_PTX_USB3RX_P6_C AV36
PETP6 If use extenal CLK gen, please place close to CLK gen
Link
BG40 T11 +3V_PCH else, please place close to PCH
PERN7 CL_DATA1
BJ40
PERP7 No support iAMT
@ @ AY40
RH86 CH21 PETN7
BB40 P10
PETP7 CL_RST1#
2
CLK_PCH_14M 2 1 1 2
33_0402_5% 22P_0402_50V8J~D BE38 RH141
PERN8
BC38 10K_0402_5%~D
PERP8
Reserve for EMI please close to UH1 AW38
PETN8
AY38
PETP8
1
M10 PEG_A_CLKRQ# PEG_A_CLKRQ# <40>
C @ @ PAD~D T81 @ PEG_A_CLKRQ# / GPIO47 C
Y40
RH89 CH22 PAD~D T82 @ CLKOUT_PCIE0N
Y39
CLK_PCI_LPBACK 2 CLKOUT_PCIE0P CLK_PEG_VGA#
1 1 2 AB37 CLK_PEG_VGA# <40>
CLKOUT_PEG_A_N +3VS +3VS
CLOCKS
33_0402_5% 22P_0402_50V8J~D +3V_PCH RH91 1 2 10K_0402_5%~D PCIECLKREQ0# J2 AB38 CLK_PEG_VGA CLK_PEG_VGA <40>
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
Reserve for EMI please close to
UH1
RH93 1 2 0_0402_5%~D PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
<22> CLK_PCIE_LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6>
10/100/1G LAN ---> <22> CLK_PCIE_LAN
RH94 1 2 0_0402_5%~D PCIE_LAN AB47
CLKOUT_PCIE1P CLKOUT_DMI_P
AU22 CLK_CPU_DMI
CLK_CPU_DMI <6>
+3VS RH95 2 @ 1 10K_0402_5%~D
<22> LANCLK_REQ# LANCLK_REQ# M1
PCIECLKRQ1# / GPIO18 CLK_CPU_DPLL#
AM12 CLK_CPU_DPLL# <6>
CLKOUT_DP_N
2
AM13 CLK_CPU_DPLL
CLKOUT_DP_P CLK_CPU_DPLL <6>
RH96 2 1 0_0402_5%~D PCIE_MINI2# AA48 RH98 RH99
<32> CLK_PCIE_MINI2# CLKOUT_PCIE2N
RH97 2 1 0_0402_5%~D PCIE_MINI2 AA47 2.2K_0402_5%~D 2.2K_0402_5%~D
<32> CLK_PCIE_MINI2 CLKOUT_PCIE2P
MiniDMC (Mini Card 2)---> +3VS RH100 2 1 10K_0402_5%~D
CLKIN_DMI_N
BF18 CLKIN_DMI#
2
<32> MINI2CLK_REQ# MINI2CLK_REQ# V10 BE18 CLKIN_DMI
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
1
SMBCLK 6 1 PCH_SMBCLK <6,11,12,28,32>
RH101 2 1 0_0402_5%~D PCIE_MINI1# Y37 BJ30 CLKIN_DMI2#
<32> CLK_PCIE_MINI1# CLKOUT_PCIE3N CLKIN_GND1_N
RH102 2 1 0_0402_5%~D PCIE_MINI1 Y36 BG30 CLKIN_DMI2 DMN66D0LDW-7_SOT363-6~D
<32> CLK_PCIE_MINI1 CLKOUT_PCIE3P CLKIN_GND1_P
MiniWLAN (Mini Card 1)---> +3V_PCH RH103 2 1 10K_0402_5%~D QH3A
<32> MINI1CLK_REQ# MINI1CLK_REQ# A8 RH105
PCIECLKRQ3# / GPIO25 CLKIN_DOT96#
G24 1 @ 2
CLKIN_DOT_96N
5
E24 CLKIN_DOT96 0_0402_5%~D
RH104 PCIE_CD# CLKIN_DOT_96P
<23> CLK_PCIE_CD# 2 1 0_0402_5%~D Y43
RH106 CLKOUT_PCIE4N
<23> CLK_PCIE_CD 2 1 0_0402_5%~D PCIE_CD Y45 SMBDATA 3 4 PCH_SMBDATA <6,11,12,28,32>
CLKOUT_PCIE4P
Card Reader ---> +3V_PCH RH107 2 1 10K_0402_5%~D
CLKIN_SATA_N
AK7 CLKIN_SATA#
CDCLK_REQ# L12 AK5 CLKIN_SATA DMN66D0LDW-7_SOT363-6~D
<23> CDCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
QH3B
RH111
V45 K45 CLK_PCH_14M 1 @ 2
CLKOUT_PCIE5N REFCLK14IN 0_0402_5%~D
V46
B CLKOUT_PCIE5P B
+3V_PCH RH110 1 2 10K_0402_5%~D L14 H45 CLK_PCI_LPBACK

PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <16>
AB42 V47 XTAL25_IN

CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT +3VS
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
+3V_PCH RH112 1 2 10K_0402_5%~D PEG_B_CLKREQ# E6
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
RH114 2 XCLK_RCOMP
<27> CLK_PCIE_USB30# 1 0_0402_5%~D PCIE_USB30# V40 RH113 90.9_0402_1%
CLKOUT_PCIE6N
2
USB 3.0 ---> <27> CLK_PCIE_USB30
RH115 2 1 0_0402_5%~D PCIE_USB30 V42
CLKOUT_PCIE6P
+3V_PCH RH116 1 2 10K_0402_5%~D
<27> USB30_CLKREQ# USB30_CLKREQ# T13 SML1CLK 6 1 PCH_SMLCLK <31,51>
PCIECLKRQ6# / GPIO45
XTAL25_IN V38 K43 KB_DET# DMN66D0LDW-7_SOT363-6~D
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 KB_DET# <29>
FLEX CLOCKS
V37 QH4A
XTAL25_OUT CLKOUT_PCIE7P DMC_PCH_DET#
2 1 F47 DMC_PCH_DET# <37>
CLKOUTFLEX1 / GPIO65
5
1M_0402_5%~D RH117 +3V_PCH RH118 1 2 10K_0402_5%~D GPIO46 K12
YH2 PCIECLKRQ7# / GPIO46 BT_DET#
H47 BT_DET# <32>
25MHZ_18PF_1Y725000CE1A~D CLK_CPU_ITP# RH119 CLKOUTFLEX2 / GPIO66
<6> CLK_CPU_ITP# 2 1 0_0402_5%~D CLK_BCLK_ITP# AK14 SML1DATA 3 4 PCH_SMLDATA <31,51>
CLK_CPU_ITP RH120 CLKOUT_ITPXDP_N
1 2 <6> CLK_CPU_ITP 2 1 0_0402_5%~D CLK_BCLK_ITP AK13 K49 CAM_DET#
CAM_DET# <21>
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 DMN66D0LDW-7_SOT363-6~D
QH4B
1 1 RH121 2 @ 1 0_0402_5%~D CougarPoint_Rev_1p0
<8> CLK_RES_ITP#
22P_0402_50V8J~D
22P_0402_50V8J~D
RH122 2 @ 1 0_0402_5%~D R3@ +3VS

<8> CLK_RES_ITP
CH23 CH24
CAM_DET# 1 2
2 2 RH166 10K_0402_5%~D
DMC_PCH_DET# 1 2
RH109 10K_0402_5%~D
BT_DET# 1 2
A RH108 10K_0402_5%~D A
KB_DET# 2 1
R1791 100K_0402_5%~D

PCH (2/8) PCIE, SMBUS, CLK
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UH1C
<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 <5>

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 <5>
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3 UH1D
<5> DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 <5>
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4 ENBKL
BC12 FDI_CTX_PRX_N4 <5> <31> ENBKL J47 AP43
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 L_BKLTEN SDVO_TVCLKINN
<5> DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 <5> <21,31> VGA_LVDDEN M45 AP45
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6 L_VDD_EN SDVO_TVCLKINP
<5> DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 <5> <21> VGA_PWM P45 AM42
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 L_BKLTCTL SDVO_STALLN
<5> DMI_CTX_PRX_P3 BJ20 AM40
DMI3RXP FDI_CTX_PRX_P0 LVDS_DDC_CLK SDVO_STALLP
BG14 FDI_CTX_PRX_P0 <5> <21> LVDS_DDC_CLK T40
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 LVDS_DDC_DATA L_DDC_CLK
<5> DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 <5> <21> LVDS_DDC_DATA K47 AP39
DMI_CRX_PTX_N1 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P2 L_DDC_DATA SDVO_INTN
<5> DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 <5> AP40
D DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 CTRL_CLK SDVO_INTP D
<5> DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 <5> T45
DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4 CTRL_DATA L_CTRL_CLK
<5> DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 <5> P39
DMI3TXN FDI_RXP4 L_CTRL_DATA
DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 <5> LVDS_IBG AF37 P38
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <5> PAD~D T203 AF36 M39
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 LVD_VBG SDVO_CTRLDATA
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18 AE48
<5> DMI_CRX_PTX_P3 DMI3TXP LVD_VREFH
AW16 FDI_INT AE47 AT49
FDI_INT FDI_INT <5> LVD_VREFL DDPB_AUXN
AT47
+1.05VS FDI_FSYNC0 DDPB_AUXP
BJ24 AV12 FDI_FSYNC0 <5> AT40
DMI_ZCOMP FDI_FSYNC0 LVDS_ACLK- DDPB_HPD
<21> LVDS_ACLK- AK39
LVDSA_CLK#
LVDS
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 LVDS_ACLK+ AK40 AV42
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5> <21> LVDS_ACLK+ LVDSA_CLK DDPB_0N
RH124 49.9_0402_1% AV40
RBIAS_CPY FDI_LSYNC0 LVDS_A0- DDPB_0P
RH125
1 2
750_0402_1%~D
BH21
DMI2RBIAS FDI_LSYNC0
AV14 FDI_LSYNC0 <5> <21> LVDS_A0-
LVDS_A1-
AN48
AM47
LVDSA_DATA#0 HDMI DDPB_1N AV45
AV46
<21> LVDS_A1- LVDSA_DATA#1 DDPB_1P
FDI_LSYNC1 LVDS_A2-
Digital Display Interface

4mil width and place FDI_LSYNC1
BB10 FDI_LSYNC1 <5> <21> LVDS_A2- AK47
LVDSA_DATA#2 DDPB_2N
AU48
AJ48 AU47
within 500mil of the PCH LVDSA_DATA#3 DDPB_2P
AV47
LVDS_A0+ DDPB_3N
<21> LVDS_A0+ AN47 AV49
DSWODVREN LVDS_A1+ LVDSA_DATA0 DDPB_3P
A18 <21> LVDS_A1+ AM49
DSWVRMEN @ LVDS_A2+ LVDSA_DATA1
<21> LVDS_A2+ AK49
LVDSA_DATA2
1 RH126 2 0_0402_5%~D PCH_RSMRST#_R AJ47 P46
System Power Management

SUSACK#_R PCH_DPWROK LVDSA_DATA3 DDPC_CTRLCLK
<31> SUSACK# 1 2 C12 E22 PCH_DPWROK <31> P42
RH127 0_0402_5%~D SUSACK# DPWROK DDPC_CTRLDATA
LVDS_BCLK- AF40
<21> LVDS_BCLK- LVDSB_CLK#
XDP_DBRESET# K3 B9 WAKE# 1 2 LVDS_BCLK+ AF39 AP47
<6> XDP_DBRESET# SYS_RESET# WAKE# PCIE_WAKE# <22,31,32> <21> LVDS_BCLK+ LVDSB_CLK DDPC_AUXN
RH128 0_0402_5%~D AP49
@ LVDS_B0- DDPC_AUXP
<21> LVDS_B0- AH45 AT38
SYS_PWROK PM_CLKRUN# LVDS_B1- LVDSB_DATA#0 DDPC_HPD
1 2 P12 N3 <21> LVDS_B1- AH47
RH273 0_0402_5%~D SYS_PWROK CLKRUN# / GPIO32 LVDS_B2- AF49 LVDSB_DATA#1 AY47
<21> LVDS_B2- LVDSB_DATA#2 DDPC_0N
AF45 AY49
PCH_PWROK PM_PWROK_R SUS_STAT# T76 PAD~D LVDSB_DATA#3 DDPC_0P
1 2 L22 G8 AY43
C RH130 0_0402_5%~D PWROK SUS_STAT# / GPIO61 LVDS_B0+ DDPC_1N C
<21> LVDS_B0+ AH43 AY45
LVDS_B1+ LVDSB_DATA0 DDPC_1P
1 2 L10 N14 SUSCLK 2 1
<21> LVDS_B1+
LVDS_B2+
AH49
AF47
LVDSB_DATA1 mDP DDPC_2N
BA47
BA48
<31> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK_R <31> <21> LVDS_B2+ LVDSB_DATA2 DDPC_2P
RH131 0_0402_5%~D RH132 0_0402_5%~D AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
PM_DRAM_PWRGD PM_SLP_S5# DDPC_3P
<6> PM_DRAM_PWRGD B13 D10 PM_SLP_S5# <31,34>
DRAMPWROK SLP_S5# / GPIO63
CRT_B N48 M43 PCH_DPD_CLK
<21> CRT_B CRT_BLUE DDPD_CTRLCLK PCH_DPD_CLK <37>
<31> PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4#
PM_SLP_S4# <31> <21> CRT_G
CRT_G P49 M36 PCH_DPD_DAT PCH_DPD_DAT <37>
RH133 0_0402_5%~D RSMRST# SLP_S4# CRT_R CRT_GREEN DDPD_CTRLDATA
<21> CRT_R T49
CRT_RED
<31> SUSWARN# 1 2 SUSWARN#_R K16 F4 PM_SLP_S3#

PM_SLP_S3# <31,34> AT45
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# DDPD_AUXN
CRT
RH134 0_0402_5%~D CRT_DDC_CLK T39 AT43
<21> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41 PCH_DMC_HPD
<21> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD PCH_DMC_HPD <37>
<6,31> PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10
RH135 0_0402_5%~D PWRBTN# SLP_A# RH136 33_0402_5% PCH_DPD_N0
BB43 PCH_DPD_N0 <37>
DDPD_0N
2 HSYNC PCH_DPD_P0
<31> AC_PRESENT 1 2 AC_PRESENT_R H20
ACPRESENT / GPIO31 SLP_SUS#
G16 PM_SLP_SUS#
PM_SLP_SUS# <31>
<21> CRT_HSYNC
<21> CRT_VSYNC
1
1 2 VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC DMC
DDPD_0P
DDPD_1N
BB45
BF44 PCH_DPD_N1
PCH_DPD_P0
PCH_DPD_N1
<37>
<37>
DMC
RH137 0_0402_5%~D RH138 33_0402_5% BE44 PCH_DPD_P1
GPIO72 H_PM_SYNC CRT_IREF

DDPD_1P
DDPD_2N
BF42 PCH_DPD_N2
PCH_DPD_P2
PCH_DPD_P1
PCH_DPD_N2
<37>
<37> ( HDMI )
E10 AP14 H_PM_SYNC <6> T43 BE42 PCH_DPD_P2 <37>
BATLOW# / GPIO72 PMSYNCH DAC_IREF DDPD_2P PCH_DPD_N3
T42 BJ42 PCH_DPD_N3 <37>
Can be left NC when IAMT is CRT_IRTN DDPD_3N PCH_DPD_P3
BG42 PCH_DPD_P3 <37>
DDPD_3P
1
SUSWARN# 1 2 SUSACK#_R RI# A10 K14 not support on the platfrom
RH139 0_0402_5%~D RI# SLP_LAN# / GPIO29 If not using integrated CougarPoint_Rev_1p0
LAN,signal may be left as NC. RH140
CougarPoint_Rev_1p0 1K_0402_0.5%~D
Check EC for S3 S4 LED R3@
2
R3@
+3V_PCH CH102
SUSCLK 2 1
B GPIO72 RH143 1 2 10K_0402_5%~D @ B
+RTCVCC 10P_0402_50V8J~D
RI# RH145 1 2 10K_0402_5%~D
WAKE# RH146 1 2 10K_0402_5%~D DSWODVREN RH147 2 1 330K_0402_5% Reserve for RF please close to UH1 1 2 PM_CLKRUN#
RH167 10K_0402_5%~D
AC_PRESENT RH150 1 @ 2 10K_0402_5%~D DSWODVREN RH151 2 @ 1 330K_0402_5% 1 2 LVDS_IBG
RH144 2.37K_0402_1%~D
SUSWARN# RH154 1 2 10K_0402_5%~D +3VS 1 2 CRT_B
DSWODVREN - On Die DSW VR Enable RH149 150_0402_1%~D
PCH_RSMRST# RH159 1 2 10K_0402_5%~D

* HL Enable
Disable 1 @ 2 CRT_DDC_CLK RH153
1 2
150_0402_1%~D
CRT_G
RH148 2.2K_0402_5%~D 1 2 CRT_R

SYS_PWROK RH272 1 2 10K_0402_5%~D 1 @ 2 CRT_DDC_DATA RH156 150_0402_1%~D
RH152 2.2K_0402_5%~D 1 2 VGA_LVDDEN
1 2 CTRL_CLK RH158 100K_0402_5%~D
RH155 2.2K_0402_5%~D 1 2 ENBKL
+3VS 1 2 CTRL_DATA RH123 100K_0402_5%~D
RH157 2.2K_0402_5%~D
1 2 PM_CLKRUN#
1 RH248 @ 8.2K_0402_5%~D
CH96
0.1U_0402_16V7K~D
2 +3VS
5
UH7 RV169 1 2 2.2K_0402_5%~D LVDS_DDC_CLK

RV170 1 2 2.2K_0402_5%~D LVDS_DDC_DATA
VCC
PCH_PWROK 1
<6,31> PCH_PWROK IN1
4 SYS_PWROK
OUT SYS_PWROK <6>
<6,31,57> VGATE 2
GND
IN2
A A
MC74VHC1G08DFT2G_SC70-5
3

PCH (3/8) DMI,FDI,PM,GFX,DP
LA-6801P
5 4 3 2 1
Compal Electronics, Inc.

5 4 3 2 1
UH1E
AY7
RSVD1
AV7
RSVD2
BG26 AU3
TP1 RSVD3
BJ26 BG4
TP2 RSVD4
BH25
TP3
BJ16 AT10
TP4 RSVD5
BG16 BC8
TP5 RSVD6
AH38
TP6
AH37 AU2
TP7 RSVD7
AK43 AT4
TP8 RSVD8
AK45 AT3
TP9 RSVD9
C18 AT1
TP10 RSVD10
N30 AY3
TP11 RSVD11
H3 AT5
D TP12 RSVD12 D
AH12 AV3
TP13 RSVD13
AM4 AV1
TP14 RSVD14
AM5 BB1
TP15 RSVD15
Y13 BA3
TP16 RSVD16
K24 BB5
TP17 RSVD17
L24 BB3
TP18 RSVD18
AB46 BB7
TP19 RSVD19
AB45 BE8
TP20 RSVD20
RSVD
BD4
RSVD21
BF6
RSVD22
B21 AV5 NV_ALE
TP21 RSVD23
M20 AV10
TP22 RSVD24
AY16
TP23
Intel Anti-Theft Techonlogy
BG46 AT8
TP24 RSVD25
High=Endabled
AY5 NV_ALE
RSVD26
BE28
TP25
RSVD27
BA2 Low=Disable(floating)
*
BC30 AT12
TP26 RSVD28 +1.8VS
BE32 BF3
TP27 RSVD29
BJ32
TP28 NV_ALE @ RH160 1
BC28 2 1K_0402_5%~D
TP29
BE30
TP30
BF32
TP31
BG32 C24
TP32 USBP0N
AV26 A24
TP33 USBP0P USB20_N9
BB26 C25 USB20_N9 <26>
TP34 USBP1N
AU28
TP35 USBP1P
B25 USB20_P9
USB20_P9 <26> USB/B
AY30 C26 USB20_N8
TP36 USBP2N USB20_N8 <32>
+3V_PCH
AU26
TP37 USBP2P
A26 USB20_P8
USB20_P8 <32> Bluetooth
AY26 K28 USB20_N3
C TP38 USBP3N USB20_N3 <21> C
AV28
TP39 USBP3P
H28 USB20_P3
USB20_P3 <21> Camera
AW30 E28 USB20_N4
TP40 USBP4N USB20_N4 <32>
1
@
USBP4P
D28 USB20_P4
USB20_P4 <32> Mini Card(WLAN)
RH269 C28 USB20_N5
USBP5N USB20_N5 <32>
10K_0402_5%~D A28 USB20_P5 Mini Card(Mini2)
USBP5P USB20_P5 <32>
C29 USB20_N6
USBP6N USB20_N6 <34>
USBP6P
B29 USB20_P6
USB20_P6 <34> ELC LED
2
PCI_PIRQA# K40 N28

CARD_HPLUG PCI_PIRQB# PIRQA# USBP7N
K38 M28
PIRQB# USBP7P
PCI
PCI_PIRQC# H38 L30
PIRQC# USBP8N
2
PCI_PIRQD# G38 K30

RH264 PIRQD# USBP8P
G30
DGPU_HOLD_RST#C46 USBP9N
100K_0402_5%~D E30
REQ1# / GPIO50 USBP9P
USB
@ DGPU_SELECT# C44 C30
<37> DGPU_SELECT# REQ2# / GPIO52 USBP10N
DGPU_PWR_EN E40 A30
<33,43,55,56> DGPU_PWR_EN REQ3# / GPIO54 USBP10P
1
L32
DMC_RADIO_OFF# USBP11N
<32> DMC_RADIO_OFF# D47 K32
GNT1# / GPIO51 USBP11P +3V_PCH
E42 G32
WL_OFF# GNT2# / GPIO53 USBP12N
<32> WL_OFF# F46 E32
GNT3# / GPIO55 USBP12P RPH1
C32
USBP13N USB_OC0#
A32 4 5
FFS_INT1 USBP13P USB_OC2#
<28> FFS_INT1 G42 3 6
PIRQE# / GPIO2
<28> ODD_DA# ODD_DA# G40
PIRQF# / GPIO3 Within 500 mils GPIO10 2 7
DP_CBL_DET C42 C33 USBRBIAS 1 2 USB_OC5# 1 8
<38> DP_CBL_DET PIRQG# / GPIO4 USBRBIAS#
<23> CARD_HPLUG CARD_HPLUG D44 RH163 22.6_0402_1%
PIRQH# / GPIO5 10K_1206_8P4R_5%~D
B33 RPH2
PAD~D T123 @ USBRBIAS USB_OC1#
K10 4 5
PME# 1.5VDDR_VID0 3 6
PCH_PLTRST# C6 A14 USB_OC2# 1.5VDDR_VID1 2 7
PLTRST# OC0# / GPIO59 USB_OC2# <26>
K20 USB_OC1# GPIO14 1 8
OC1# / GPIO40 1.5VDDR_VID0
B17 1.5VDDR_VID0 <53>
B CLK_PCI_LPBACK RH164 OC2# / GPIO41 B
<14> CLK_PCI_LPBACK 2 1 22_0402_5% CLK_PCI0 H49 C16 1.5VDDR_VID1
1.5VDDR_VID1 <53>
10K_1206_8P4R_5%~D
CLK_PCI_LPC RH165 CLKOUT_PCI0 OC3# / GPIO42
<31> CLK_PCI_LPC 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC0#
PAD~D T165 @ CLK_PCI2 CLKOUT_PCI1 OC4# / GPIO43 USB_OC5# (For USB Port 9)
J48 A16
PAD~D T166 @ CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 GPIO10
K42 D14 1 2 USB3_SMI# USB3_SMI# <27>
PAD~D T204 @ CLK_PCI4 CLKOUT_PCI3 OC6# / GPIO10 GPIO14 @ RH277 0_0402_5%~D
H40 C14
CLKOUT_PCI4 OC7# / GPIO14
1 2 USB3_SMI#
CougarPoint_Rev_1p0 RH278 0_0402_5%~D
R3@ 1 2
+3VS @ RH254 0_0402_5%~D
+3VS 1 @ 2
RPH3 RH168 0_0402_5%~D
WL_OFF# 1 8
2
PCI_PIRQB# 2 7 @ +3VS +3VS

PCI_PIRQD# 3 6 RH169
PCI_PIRQC# 4 5 10K_0402_5%~D 1 2 DGPU_PWROK
DGPU_PWROK <17,38,39,55,56>
5
UH6 @ RH265 0_0402_5%~D
5
8.2K_0804_8P4R_5% UH5 2 1 2 PCH_PLTRST#
P
B
1
1 PCH_PLTRST# 2 1 RH170 4 RH266 0_0402_5%~D

P
IN1 <40> PLTRST_VGA# Y

RPH4 4 100_0402_5%~D 1 DGPU_HOLD_RST#
<6,22,23,27,31,32> PLT_RST# O A
G
DMC_RADIO_OFF# 1 8 2
IN2
1
G
DGPU_SELECT# 2 7 SN74AHC1G08DCKR_SC70-5
1
2
DGPU_PWR_EN 3 6 SN74AHC1G08DCKR_SC70-5 RH172
3
FFS_INT1 4 5 100K_0402_5%~D RH179

2
RH171 @ 10K_0402_5%~D
8.2K_0804_8P4R_5% 100K_0402_5%~D RH183
2
@ 10K_0402_5%~D
2
1
RPH5
1 8
1
PCI_PIRQA# 2 7
3 6
ODD_DA# 4 5
A A
8.2K_0804_8P4R_5%
DGPU_HOLD_RST# 1 RH173 2 10K_0402_5%~D
CH99 Security Classification Compal Secret Data Compal Electronics, Inc.

2 1 CLK_PCI1 2011/01/25 2012/01/25 Title
Issued Date Deciphered Date
@
10P_0402_50V8J~D
PCH (4/8) PCI, USB, NVRAM
Reserve for RF please close to UH1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+3V_PCH
UH1F
1
RH270
10K_0402_5%~D CRT_DET T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <28>
<37> DGPU_EDIDSEL# DGPU_EDIDSEL# A42 B41 GPIO69 @ T126 PAD~D

TACH1 / GPIO1 TACH5 / GPIO69
2
HDMI_PCH_HPD# GPIO6 H36 C41 +3VS
<31> EC_SCI# EC_SCI# E38 A40

2
D D
DMI Termination Voltage
<31> EC_SMI# EC_SMI# C10 RH174
GPIO8
10K_0402_5%~D Set to Vcc when HIGH
<32> BT_RADIO_DIS# BT_RADIO_DIS# C4 NV_CLE
LAN_PHY_PWR_CTRL / GPIO12
Set to Vss when LOW
1
<39> HDMI_PCH_HPD# HDMI_PCH_HPD# G2 P4
GPIO15 A20GATE GATEA20 <31>
AU16 PCH_PECI_R 1 @ 2
PECI H_PECI <6,31>
GPIO16 U2 0_0402_5%~D RH175
SATA4GP / GPIO16 KB_RST#
P5 KB_RST# <31>
RCIN# +1.8VS
GPIO
GPIO28 <16,38,39,55,56> DGPU_PWROK DGPU_PWROK D40 AY11
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
CPU/MISC
On-Die PLL Voltage Regulator Weak internal
1
This signal has a weak internal pull up PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THERMTRIP# H_THERMTRIP# <6> PU,Do not pull low
SCLOCK / GPIO22 THRMTRIP# 390_0402_5% RH176 RH161
* HOn-Die voltage regulator enable
LOn-Die PLL Voltage Regulator disable
E8
GPIO24 / MEM_LED INIT3_3V#
T14 INIT3_3V# 2.2K_0402_5%~D
PCH_GPIO27 E16 AY1 NV_CLE

GPIO27 DF_TVS
2
1 2 PCH_GPIO28 NV_CLE 2 1 H_SNB_IVB# <6>
1
PCH_GPIO28 P8 @ 1K_0402_5%~D RH162
@ RH177 1K_0402_5%~D GPIO28 RH178
AH8
BT_ON# TS_VSS1
<32> BT_ON# K1 10K_0402_5%~D
STP_PCI# / GPIO34
AK11
GPIO35 TS_VSS2
K4
GPIO35
2
TS_VSS3
AH10 INIT3_3V CLOSE TO THE BRANCHING POINT
ODD_DETECT# V8
<28> ODD_DETECT# SATA2GP / GPIO36
PCH_GPIO37 M5
TS_VSS4
AK10 This signal has weak internal RH161 and RH162
SATA3GP / GPIO37 PU, can't pull low
PCH_GPIO37 PCH_GPIO38
Follow CRB FAB2 setting
N2 P37
SLOAD / GPIO38 NC_1
FDI TERMINATION VOLTAGE OVERRIDE
PCH_GPIO39 M3
C SDATAOUT0 / GPIO39 C
* LOW - Tx, Rx terminated
to same voltage <28> FFS_INT2
FFS_INT2 V13
SDATAOUT1 / GPIO48 VSS_NCTF_15
BG2 +3VS
(DC Coupling Mode)
GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
+3VS HDD_DETECT# D6 BH3
<28> HDD_DETECT# GPIO57 VSS_NCTF_17
BH47 DGPU_EDIDSEL# 1 RH180 2 10K_0402_5%~D
RH181 @ VSS_NCTF_18
2 1 1K_0402_5%~D PCH_GPIO37
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
RH182 1 2 PCH_GPIO37 A44 BJ44
10K_0402_5%~D VSS_NCTF_2 VSS_NCTF_20
A45 BJ45
NCTF
A46 BJ46
A5 BJ5
GPIO27
A6 BJ6 +3V_PCH
PCH_GPIO27 (Have internal Pull-High)
B3 C2
*High: VCCVRM VR Enable
Low: VCCVRM VR Disable
B47 C48
1 2 PCH_GPIO27 BD1 D1 ODD_EN# 1 2 10K_0402_5%~D
@ RH186 10K_0402_5%~D VSS_NCTF_9 VSS_NCTF_27 RH187
BD49 D49 HDD_DETECT# 1 2 10K_0402_5%~D
VSS_NCTF_10 VSS_NCTF_28 RH188
BE1 E1
BE49 E49
B VSS_NCTF_12 VSS_NCTF_30 B
BF1 F1 EC_SMI# 1 2 10K_0402_5%~D
VSS_NCTF_13 VSS_NCTF_31 RH190
BF49 F49
+3VS
CougarPoint_Rev_1p0
CRT_DET# 1 @ 2 10K_0402_5%~D
R3@ RH192
ODD_DETECT# 1 2 200K_0402_5%
RH193
GPIO16 1 2 10K_0402_5%~D
RH274
BT_ON# 1 2 8.2K_0402_5%~D
RH195
KB_RST# 1 2 10K_0402_5%~D
RH196
PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO22 1 2 10K_0402_5%~D
PCH_GPIO15 needs to be connected to XDP_FN16 RH197
+3VS GPIO35 1 2 10K_0402_5%~D
Please refer to Huron River Debug Board DG 0.5 RH257
2
GPIO49 1 2 10K_0402_5%~D
High: CRT Plugged RH198 RH258
10K_0402_5%~D PCH_GPIO38 1 2 10K_0402_5%~D
RH262
PCH_GPIO39 1 2 10K_0402_5%~D
1
CRT_DET RH263
A A
D
1
GPIO6 1 2 10K_0402_5%~D
2 RH271
<21> CRT_DET#
QH5 G
SSM3K7002F_SC59-3 S
3

PCH (5/8) GPIO, CPU, MISC
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+1.05VS PCH Power Rail Table

UH1G POWER +3VS S0 Iccmax
J10
@ Voltage Rail Voltage Current (A)
1300mA LH1
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
VCCCORE[1] 1mA VCCADAC
AC23 1 1 1 BLM18PG181SN1_0603~D V_PROC_IO 1.05 0.001
VCCCORE[2]
10U_0805_4VAM~D
AD21
CRT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
PAD-OPEN 4x4m 1 1 1 1 VCCCORE[3]
AD23 U47 CH31
CH29
CH30
VCCCORE[4] VSSADAC 10U_0805_4VAM~D V5REF 5 0.001
AF21
CH27
CH28
CH25
CH26
VCC CORE
VCCCORE[5] 2 2 2
AF23
D 2 2 2 2 VCCCORE[6] +3VS D
AG21
VCCCORE[7] V5REF_Sus
AG23 5 0.001
VCCCORE[8] +VCCA_LVDS RH199
AG24 1mA VCCALVDS AK36 1 2 0_0805_5%
VCCCORE[9]
AG26
VCCCORE[10] +1.8VS
AG27 AK37 Vcc3_3 3.3 0.266
VCCCORE[11] VSSALVDS
AG29
VCCCORE[12] LH2
AJ23
VCCCORE[13] Near AP43
LVDS
AJ26 AM37 +VCCTX_LVDS CH34 2 1 VccADAC 3.3 0.001
VCCCORE[14] VCCTX_LVDS[1] CH32 1 0.1UH_MLF1608DR10KT_10%_1608
AJ27 1 1
+1.05VS VCCCORE[15] 0.01U_0402_16V7K~D 22U_0805_6.3V6M~D
AJ29 AM38 0.1uH inductor, 200mA
VCCCORE[16] VCCTX_LVDS[2]
AJ31 CH33 VccADPLLA 1.05 0.08
VCCCORE[17] 0.01U_0402_16V7K~D
60mA VCCTX_LVDS[3] AP36
2 2 2
AP37 VccADPLLB 1.05 0.08
VCCTX_LVDS[4]
+1.05VS RH200 2 1 0_0603_5%~D +1.05VS_VCCDPLLEXP AN19
VCCIO[28]
@ LH3 VccCore 1.05 1.3
2 @ 1+VCCAPLLEXP_R1 2 +VCCAPLLEXP BJ22
RH201 0_0603_5%~D 1UH_LB2012T1R0M_20%~D VCCAPLLEXP RH202
+3VS_VCC3_3_6 VccDMI 1.05 0.042
10U_0805_4VAM~D
1 V33 1 2 +3VS
VCC3_3[6]
HVCMOS
AN16 0_0805_5%~D
VCCIO[15]
Place CH40 Near BJ22 pin
CH35
1
AN17 VccIO 1.05 2.925
2 @ VCCIO[16] CH36
V34
+1.05VS VCC3_3[7]
0.1U_0402_10V7K~D
AN21 2 VccASW 1.05 1.01
VCCIO[17]
AN26
VCCIO[18]
1
VccSPI 3.3 0.02

RH203 AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
0_0805_5%~D
AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.003
C VCCIO[20] RH204 C
2
+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2

VCCIO[21] VCCDMI[1]
1 VccpNAND 1.8 0.19
DMI
0_0805_5%~D
10U_0805_4VAM~D
AP24
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 VCCIO[22]
VCCIO
+3VS RH205 CH42
AP26 AB36 +1.05VS_VCC_DMI_CCI 1 2 VccRTC 3.3 6 uA
CH37
CH38
CH39
CH40
CH41
VCCIO[23] 20mA VCCCLKDMI +1.05VS 2 1U_0402_6.3V6K~D

1 0_0805_5%~D
2 2 2 2 2 AT24
VCCIO[24] CH43 VccSus3_3 3.3 0.119
1U_0402_6.3V6K~D
2
1
AN33
RH206 VCCIO[25] VccSusHDA 3.3 / 1.5 0.01
0_0805_5%~D AN34 AG16
VCCIO[26] VCCDFTERM[1] +VCCPNAND
VccVRM 1.8 / 1.5 0.16
2
+3VS_VCCA3GBG BH29 AG17 1 2 +1.8VS

VCC3_3[3] 190mA VCCDFTERM[2] RH207 0_0805_5%~D
DFT / SPI
1
CH44 VccCLKDMI 1.05 0.02
0.1U_0402_10V7K~D
+1.05VS AJ16 1
0.1U_0402_10V7K~D VCCDFTERM[3]
2 +VCCAFDI_VRM AP16 VccSSC 1.05 0.095
CH45
VCCVRM[2]
AJ17
VCCDFTERM[4] 2
Place CH53 Near BG6 pin
2 @ 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
RH208 0_0603_5%~D VccAFDIPLL
RH209
1U_0402_6.3V6K~D
1
+1.05VS 1 2+1.05VS_VCCDPLL_FDI AP17 RH210 VccALVDS 3.3 0.001
0_0805_5%~D VCCIO[27] +3V_VCCPSPI
V1 1 2
FDI
CH46
20mA VCCSPI +3V_PCH

0_0805_5%~D
2 @ AU20 VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] 1
CH47
B CougarPoint_Rev_1p0 1U_0402_6.3V6K~D B
2
R3@
VCCVRM = 160mA detal waiting for newest spec

+3VALW +1.5VS +VCCAFDI_VRM
RH211 @
2 1 +VCCAFDI_VRM
1
0_0603_5%~D
C432
1U_0402_6.3V6K~D U47
2 1 5 2 1
VIN VOUT RH212
4
SUSP# NC 0_0603_5%~D
<10,31,33,53,54> SUSP# 3 2
EN GND
RT9013-15GB_SOT23-5
A A

PCH (6/8) PWR
LA-6801P
5 4 3 2 1
5 4 3 2 1
+1.05VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
2 @ 1 +VCCACLK
+3V_PCH RH213 0_0603_5%~D
UH1J POWER QH7
1 2
+3V_DSW RH214 0_0603_5%~D AD49 N26 +1.05VS_VCCUSBCORE 2 1 +5VALW RH215 AO3419L_SOT23-3 +5V_PCH
1 VCCACLK VCCIO[29] +1.05VS
RH220 0_0603_5%~D 0_0603_5%~D
CH48 P26 2 1 3 1
D
VCCIO[30] 1
1 2 0.1U_0402_10V7K~D +VCCPDSW T16
0.1U_0402_10V7K~D
D 2 VCCDSW3_3 3mA D
RH221 @ 0_0603_5%~D CH50
20K_0402_5%~D
P28
VCCIO[31]
1
1U_0402_6.3V6K~D 1
G
2
2
+PCH_VCCDSW V12 T27
R22
+1.05VS @ LH4 DCPSUSBYP VCCIO[32]
C8
1
@ RH216 10UH_LBR2012T100M_20%~D T29
VCCIO[33] <33> PCH_PWR_EN# 2
1 2 +VCCAPLL_CPY 1 2 @ CH51 +3VS_VCC_CLKF33 T38
VCC3_3[5]
2
0.1U_0402_10V7K~D
0_0805_5%~D @ 2 +3V_VCCPUSB
10U_0805_10V4Z~D
1 T23 2 1 +3V_PCH
+1.05VS +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7] RH217 0_0603_5%~D
0.1U_0402_10V7K~D
VCCAPLLDMI2 +3V_VCCAUBG
CH49
T24 1 2 1 +3V_PCH
+VCCDPLL_CPY VCCSUS3_3[8] RH218 0_0603_5%~D +5V_PCH +3V_PCH
1 2 AL29
0.1U_0402_10V7K~D
2 RH219 0_0603_5%~D VCCIO[14]
V23
CH52
VCCSUS3_3[9] 1
USB
2
2
+VCCSUS1 AL24 V24 +VCCA_USBSUS
CH53
DCPSUS[3] VCCSUS3_3[10] RH222 DH2
1U_0402_6.3V6K~D
1 2
@ P24 1 100_0402_5%~D RB751S40T1_SOD523-2~D
+3VALW QH6 +3V_DSW CH54 VCCSUS3_3[6]
AO3419L_SOT23-3 1U_0402_6.3V6K~D AA19
@CH55
2 VCCASW[1]
1
T26 +1.05VS_VCCAUPLL 2 1 +PCH_V5REF_SUS
VCCIO[34] +1.05VS 2
3 1 AA21 1010mA RH223 0_0603_5%~D
S
VCCASW[2] 1
+1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS CH56
VCCASW[3] 1mA V5REF_SUS
2 1 0.1U_0603_25V7K
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1
G
+3V_PCH 2
2
AA26 RH224 0_0603_5%~D
0.1U_0402_10V7K~D
Clock and Miscellaneous
VCCASW[4] +VCCA_USBSUS
AN23
CH57
CH58
DCPSUS[4] 1
AA27
2 2 VCCASW[5] +3V_VCCPSUS_1
AN24
CH59
VCCSUS3_3[1]
AA29
VCCASW[6] 2
<31> PCH_VREG_EN# +1.05VS +5VS +3VS
AA31
VCCASW[7]
1 2 AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF
2
C RH225 0_0805_5%~D RH226 C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1
AC27 0_0603_5%~D RH227 DH3
VCCASW[9] +3V_VCCPSUS 100_0402_5%~D
N20 2 1
CH60
CH61
CH62
VCCSUS3_3[2] +3V_PCH RB751S40T1_SOD523-2~D
AC29
PCI/GPIO/LPC
VCCASW[10] 1
2 2 2 N22
VCCSUS3_3[3]
1
AC31 CH63 +PCH_V5REF_RUN
VCCASW[11] 1U_0402_6.3V +3VS
P20 1
VCCSUS3_3[4] 2
AD29
+3VS VCCASW[12] +3VS_VCCPCORE CH64
P22 2 1
VCCSUS3_3[5] RH228 0_0805_5%~D 1U_0603_10V6K~D
5/18 delete RH229 AD31
VCCASW[13] 1 2
W21 AA16 CH65
LH5 VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
10UH_LBR2012T100M_20%~D W23 W16 2 +3VS
VCCASW[15] VCC3_3[8]
1 2+3VS_VCC_CLKF33_R 1 2 +3VS_VCC_CLKF33
0_0805_5%~D RH230 W24 T34 +3VS_VCCPPCI 2 1
10U_0805_10V4Z~D
1U_0402_6.3V6K~D
1 1 VCCASW[16] VCC3_3[4]
1 RH231 0_0603_5%~D
W26
CH66
CH67
VCCASW[17] CH68
2 2 W29 +3VS 0.1U_0402_10V7K~D
VCCASW[18] RH232 2
W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3
1
W33 0_0603_5%~D RH233
VCCASW[20] CH69
AF13 2 1 +1.05VS
VCCIO[5] 0.1U_0402_10V7K~D 1
+1.05VS +VCCRTCEXT N16 2 0_0805_5%~D
DCPRTC CH70
1 AH13
@ +1.05VM_VCCSUS VCCIO[12] 1U_0402_6.3V6K~D
2 1
RH234 0_0603_5%~D CH71 +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
0.1U_0402_10V7K~D VCCVRM[4] VCCIO[13]
2
B +1.05VS AF14 @ LH6 @ B
+1.05VS_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D RH236
BD47
VCCADPLLA 80mA
SATA
2 1 +VCCDIFFCLK AK1 +VCCSATAPLL 1 2 +VCCSATAPLL_R 2 1
VCCAPLLSATA +1.05VS
RH235 0_0603_5%~D +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
VCCADPLLB 80mA 0_0805_5%~D
1 1
CH72 AF11 +VCCAFDI_VRM @ CH73
VCCVRM[1] +1.05VS_VCC_SATA 10U_0805_10V4Z~D
AF17
+1.05VS 1U_0402_6.3V6K~D +1.05VS_VCCDIFFCLKN VCCIO[7] RH238
AF33
VCCDIFFCLKN[1]
Place CH80 Near AK1 pin
2 AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
VCCDIFFCLKN[2] VCCIO[2] +1.05VS
2 1 +1.05VS_VCCDIFFCLKN AG34
RH237 0_0603_5%~D VCCDIFFCLKN[3] 0_0805_5%~D
AC17
1U_0402_6.3V6K~D
1 VCCIO[3] 1
CH74 +1.05VS_SSCVCC AG33 AD17
CH75
1U_0402_6.3V6K~D VCCSSC 95mA VCCIO[4]
+1.05VS 2 2
+VCCSST V16 +1.05VS
DCPSST
2 1
RH239 0_0603_5%~D 1 1 +1.05VM_VCCSUS
CH78 1 T17 T21 +VCCME_22 RH240 2 1 0_0603_5%~D
CH77 0.1U_0402_10V7K~D @ DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC
1U_0402_6.3V6K~D CH76
+1.05VS 2 2 1U_0402_6.3V6K~D V21 +VCCME_23 RH241 2 1 0_0603_5%~D
2 VCCASW[23]
CPU
1 2 +V_CPU_IO BJ8
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
RH242 0_0603_5%~D V_PROC_IO 1mA +VCCME_21 RH243

1 1 1 T19 2 1 0_0603_5%~D
VCCASW[21]
CH79 +RTCVCC
CH80
CH81
4.7U_0603_6.3V6K~D
2 2 2 A22 P32 +VCCSUSHDA 2 1
RTC
VCCRTC 10mA VCCSUSHDA +3V_PCH

HDA
RH244 0_0603_5%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1 1 1 1 1 2 +3V_PCH
LH7 CougarPoint_Rev_1p0 @ RH245 180_0402_1% If it support 3.3V audio signals
150_0402_1%~D
1
A 10UH_LBR2012T100M_20%~D 0.1U_0402_10V7K~D CH85 POP:RH228 A
CH82
CH83
CH84
1 2 +1.05VS_VCCA_A_DPL Depop RH233/RH234

+1.05VS 2 2 2 R3@ 2 @
RH246 If it support 1.5V audio signals
1 2 +VCCA_DPLL_L 1 2 +1.05VS_VCCA_B_DPL POP:RH233/RH234
220U_B2_2.5VM_R35M~D
RH247 LH8 2 Depop R228

220U_B2_2.5VM_R35M~D
10UH_LBR2012T100M_20%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0_0805_5%~D 1 1
+
1
+
1 Security Classification Compal Secret Data Compal Electronics, Inc.
CH86
CH88
2011/01/25 2012/01/25 Title

CH87
CH89

2 2 2 2
PCH (7/8) PWR
LA-6801P
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 H46
VSS[159] VSS[259]
AY42 K18
VSS[160] VSS[260]
AY46 K26
VSS[161] VSS[261]
AY8 K39
D UH1H VSS[162] VSS[262] D
B11 K46
VSS[163] VSS[263]
H5 B15 K7
VSS[0] VSS[164] VSS[264]
B19 L18
VSS[165] VSS[265]
AA17 AK38 B23 L2
VSS[1] VSS[80] VSS[166] VSS[266]
AA2 AK4 B27 L20
VSS[2] VSS[81] VSS[167] VSS[267]
AA3 AK42 B31 L26
VSS[3] VSS[82] VSS[168] VSS[268]
AA33 AK46 B35 L28
VSS[4] VSS[83] VSS[169] VSS[269]
AA34 AK8 B39 L36
VSS[5] VSS[84] VSS[170] VSS[270]
AB11 AL16 B7 L48
VSS[6] VSS[85] VSS[171] VSS[271]
AB14 AL17 F45 M12
VSS[7] VSS[86] VSS[172] VSS[272]
AB39 AL19 BB12 P16
VSS[8] VSS[87] VSS[173] VSS[273]
AB4 AL2 BB16 M18
VSS[9] VSS[88] VSS[174] VSS[274]
AB43 AL21 BB20 M22
VSS[10] VSS[89] VSS[175] VSS[275]
AB5 AL23 BB22 M24
VSS[11] VSS[90] VSS[176] VSS[276]
AB7 AL26 BB24 M30
VSS[12] VSS[91] VSS[177] VSS[277]
AC19 AL27 BB28 M32
VSS[13] VSS[92] VSS[178] VSS[278]
AC2 AL31 BB30 M34
VSS[14] VSS[93] VSS[179] VSS[279]
AC21 AL33 BB38 M38
VSS[15] VSS[94] VSS[180] VSS[280]
AC24 AL34 BB4 M4
VSS[16] VSS[95] VSS[181] VSS[281]
AC33 AL48 BB46 M42
VSS[17] VSS[96] VSS[182] VSS[282]
AC34 AM11 BC14 M46
VSS[18] VSS[97] VSS[183] VSS[283]
AC48 AM14 BC18 M8
VSS[19] VSS[98] VSS[184] VSS[284]
AD10 AM36 BC2 N18
VSS[20] VSS[99] VSS[185] VSS[285]
AD11 AM39 BC22 P30
VSS[21] VSS[100] VSS[186] VSS[286]
AD12 AM43 BC26 N47
VSS[22] VSS[101] VSS[187] VSS[287]
AD13 AM45 BC32 P11
VSS[23] VSS[102] VSS[188] VSS[288]
AD19 AM46 BC34 P18
VSS[24] VSS[103] VSS[189] VSS[289]
AD24 AM7 BC36 T33
VSS[25] VSS[104] VSS[190] VSS[290]
AD26 AN2 BC40 P40
VSS[26] VSS[105] VSS[191] VSS[291]
AD27 AN29 BC42 P43
VSS[27] VSS[106] VSS[192] VSS[292]
AD33 AN3 BC48 P47
VSS[28] VSS[107] VSS[193] VSS[293]
AD34 AN31 BD46 P7
C VSS[29] VSS[108] VSS[194] VSS[294] C
AD36 AP12 BD5 R2
VSS[30] VSS[109] VSS[195] VSS[295]
AD37 AP19 BE22 R48
VSS[31] VSS[110] VSS[196] VSS[296]
AD38 AP28 BE26 T12
VSS[32] VSS[111] VSS[197] VSS[297]
AD39 AP30 BE40 T31
VSS[33] VSS[112] VSS[198] VSS[298]
AD4 AP32 BF10 T37
VSS[34] VSS[113] VSS[199] VSS[299]
AD40 AP38 BF12 T4
VSS[35] VSS[114] VSS[200] VSS[300]
AD42 AP4 BF16 W34
VSS[36] VSS[115] VSS[201] VSS[301]
AD43 AP42 BF20 T46
VSS[37] VSS[116] VSS[202] VSS[302]
AD45 AP46 BF22 T47
VSS[38] VSS[117] VSS[203] VSS[303]
AD46 AP8 BF24 T8
VSS[39] VSS[118] VSS[204] VSS[304]
AD8 AR2 BF26 V11
VSS[40] VSS[119] VSS[205] VSS[305]
AE2 AR48 BF28 V17
VSS[41] VSS[120] VSS[206] VSS[306]
AE3 AT11 BD3 V26
VSS[42] VSS[121] VSS[207] VSS[307]
AF10 AT13 BF30 V27
VSS[43] VSS[122] VSS[208] VSS[308]
AF12 AT18 BF38 V29
VSS[44] VSS[123] VSS[209] VSS[309]
AD14 AT22 BF40 V31
VSS[45] VSS[124] VSS[210] VSS[310]
AD16 AT26 BF8 V36
VSS[46] VSS[125] VSS[211] VSS[311]
AF16 AT28 BG17 V39
VSS[47] VSS[126] VSS[212] VSS[312]
AF19 AT30 BG21 V43
VSS[48] VSS[127] VSS[213] VSS[313]
AF24 AT32 BG33 V7
VSS[49] VSS[128] VSS[214] VSS[314]
AF26 AT34 BG44 W17
VSS[50] VSS[129] VSS[215] VSS[315]
AF27 AT39 BG8 W19
VSS[51] VSS[130] VSS[216] VSS[316]
AF29 AT42 BH11 W2
VSS[52] VSS[131] VSS[217] VSS[317]
AF31 AT46 BH15 W27
VSS[53] VSS[132] VSS[218] VSS[318]
AF38 AT7 BH17 W48
VSS[54] VSS[133] VSS[219] VSS[319]
AF4 AU24 BH19 Y12
VSS[55] VSS[134] VSS[220] VSS[320]
AF42 AU30 H10 Y38
VSS[56] VSS[135] VSS[221] VSS[321]
AF46 AV16 BH27 Y4
VSS[57] VSS[136] VSS[222] VSS[322]
AF5 AV20 BH31 Y42
VSS[58] VSS[137] VSS[223] VSS[323]
AF7 AV24 BH33 Y46
VSS[59] VSS[138] VSS[224] VSS[324]
AF8 AV30 BH35 Y8
VSS[60] VSS[139] VSS[225] VSS[325]
AG19 AV38 BH39 BG29
B VSS[61] VSS[140] VSS[226] VSS[328] B
AG2 AV4 BH43 N24
VSS[62] VSS[141] VSS[227] VSS[329]
AG31 AV43 BH7 AJ3
VSS[63] VSS[142] VSS[228] VSS[330]
AG48 AV8 D3 AD47
VSS[64] VSS[143] VSS[229] VSS[331]
AH11 AW14 D12 B43
VSS[65] VSS[144] VSS[230] VSS[333]
AH3 AW18 D16 BE10
VSS[66] VSS[145] VSS[231] VSS[334]
AH36 AW2 D18 BG41
VSS[67] VSS[146] VSS[232] VSS[335]
AH39 AW22 D22 G14
VSS[68] VSS[147] VSS[233] VSS[337]
AH40 AW26 D24 H16
VSS[69] VSS[148] VSS[234] VSS[338]
AH42 AW28 D26 T36
VSS[70] VSS[149] VSS[235] VSS[340]
AH46 AW32 D30 BG22
VSS[71] VSS[150] VSS[236] VSS[342]
AH7 AW34 D32 BG24
VSS[72] VSS[151] VSS[237] VSS[343]
AJ19 AW36 D34 C22
VSS[73] VSS[152] VSS[238] VSS[344]
AJ21 AW40 D38 AP13
VSS[74] VSS[153] VSS[239] VSS[345]
AJ24 AW48 D42 M14
VSS[75] VSS[154] VSS[240] VSS[346]
AJ33 AV11 D8 AP3
VSS[76] VSS[155] VSS[241] VSS[347]
AJ34 AY12 E18 AP1
VSS[77] VSS[156] VSS[242] VSS[348]
AK12 AY22 E26 BE16
VSS[78] VSS[157] VSS[243] VSS[349]
AK3 AY28 G18 BC16
VSS[79] VSS[158] VSS[244] VSS[350]
G20 BG28
CougarPoint_Rev_1p0 VSS[245] VSS[351]
G26 BJ28
VSS[246] VSS[352]
G28
VSS[247]
G36
R3@ VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
A VSS[258] A
CougarPoint_Rev_1p0
R3@

PCH (8/8) VSS
LA-6801P
5 4 3 2 1
5 4 3 2 1
CRT
D66 D15 D67
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59-3 DAN217_SC59-3 DAN217_SC59-3
1
D68 FV3 W=40mils
2 1 1 2
W=40mils 3 NC
1
1.1A_6VDC_FUSE 1
BAT1000-7-F_SOT23-3~D R1857 C535
+3VS 2 0_1206_5%~D
1 0.1U_0402_16V7K~D
3
0.1U_0402_16V7K~D CU55 R2012 @ 100K_0402_5%~D
2 1 2
2
<17> CRT_DET#
JCRT1
LU6 0_0603_5%~D L31 BLM18BB750SN1D_2P~D 6
1 2 CRT_R_C 1 2 CRT_R_L PAD~D T83 @ 11
<15> CRT_R
CRT_R_L 1
LU7 0_0603_5%~D L32 BLM18BB750SN1D_2P~D 7
1 2 CRT_G_C 1 2 CRT_G_L CRT_DDC_DATA_C 12
D <15> CRT_G D
CRT_G_L 2
LU8 0_0603_5%~D L103 BLM18BB750SN1D_2P~D 8 G 16
1 2 CRT_B_C 1 2 CRT_B_L HSYNC_L 13 17
<15> CRT_B G
CRT_B_L 3
10P_0402_50V8J~D
CU56
10P_0402_50V8J~D
CU57
10P_0402_50V8J~D
CU58
150_0402_1%~D
R366
150_0402_1%~D
R1832
150_0402_1%~D
R1833
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
10P_0402_50V8J~D
C540
10P_0402_50V8J~D
C541
10P_0402_50V8J~D
C542
1 1 1 9
C537
C538
C539
VSYNC_L 14
1
1
For EMI 4
@ @ @ 10
2 2 2 CRT_DDC_CLK_C 15
2
2
1 5
100P_0402_50V8J~D
C543
SUYIN_070546HR015M25CZR
CONN@
2
C545 +CRT_VCC
+3VS +3VS +3VS +CRT_VCC +CRT_VCC 0.1U_0402_16V7K~D
1 2
2
5
1
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
R1834
R370
2.2K_0402_5%~D
R371
R372
R1160
P
OE#
CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 0_0603_5%~D HSYNC_L
<15> CRT_HSYNC A Y
G
U625
1
1
74AHCT1G125GW_SOT353-5 R1161 +INV_PWR_SRC
3
D_CRT_VSYNC 1 2 0_0603_5%~D VSYNC_L
2
+5VALW
G
1
1 1 @
CRT_DDC_DATA_C +CRT_VCC
15P_0402_50V8J~D
C547
15P_0402_50V8J~D
C548
3 1 C546 R373 R2013
<15> CRT_DDC_DATA
1
0.1U_0402_16V7K~D 10K_0402_5%~D 820_0805_1%
S
D
2
G
Q286 1 2 1 2 R2014
2 2
2N7002DW-7-F_SOT363-6
PMF3800SN_SC70-3 100K_0402_5%
3 2
3 1 CRT_DDC_CLK_C @
<15> CRT_DDC_CLK
5
1
@
S
2
Q287 Q305B
P
OE#
2N7002DW-7-F_SOT363-6
C PMF3800SN_SC70-3 CRT_VSYNC 2 4 C
<15> CRT_VSYNC A Y 5
G
U626
6
74AHCT1G125GW_SOT353-5 @
4
Q305A
+LCDVDD_R 2
1
B+ @R1835
@ R1835 1 2 0_0805_5%~D +INV_PWR_SRC
+LCDVDD +5VALW
W=60mils Discharg Circuit
2
+3VS
R1847
R377
47K_0402_5% 60mil Q70
100_0402_5%~D
B+ SI3457BDV-T1-E3_TSOP6~D 60mil
1 1
R378 +INV_PWR_SRC_R R2015 1 2 0_0805_5%~D +INV_PWR_SRC
D
D
3
LVDS Conn.
56K_0402_5% AO3419L_SOT23-3 6
S
G
Q288 2 2 1 2 Q289 4 5
SSM3K7002FU_SC70-3~D G W=60mils 2
1000P_0402_50V7K~D
C1126
100K_0402_5%~D
R1242
S 1
3
1
4.14 +LCDVDD
G
1 1 1
0.47U_0402_16V4Z~D
C549
D37
D
1
3
VGA_LVDDEN 2 +LCDVDD C1127 JLVDS
<15,31> VGA_LVDDEN
1
D 0.1U_0603_50V_X7R LVDS_A0-
<15> LVDS_A0- 1
Q290 2 2 2 LVDS_A0+ 1
1 2 1 1 <15> LVDS_A0+ 2
2
2
G BSS138_SOT23~D C551 3
3
1
EC_ENVDD 3 S C1869 0.1U_0402_16V7K~D PWR_SRC_ON LVDS_A1- 4

<31> EC_ENVDD <15> LVDS_A1- 4
3
4.7U_0805_10V4Z~D LVDS_A1+ 5
2 2 <15> LVDS_A1+ 5
1
BAT54C-7-F_SOT23~D R380 6
10K_0402_5%~D R1243 5P_0402_50V8C LVDS_A2- 6
C1133 <15> LVDS_A2- 7
@ LVDS_A2+ 7
100K_0402_5%~D <15> LVDS_A2+ 8
8
2
1 2 9
LVDS_ACLK- 9
C1132 <15> LVDS_ACLK- 10 C1134
10
2
5P_0402_50V8C @ LVDS_ACLK+ 11 5P_0402_50V8C
B <15> LVDS_ACLK+ 11 B
R2005 1 2 12 1 @2 LVDS_BCLK-
12
1
+3VS 0_0402_5%~D D LVDS_B0-

<15> LVDS_B0- 13
2 1 +LCDVDD_R 2 Q71 LVDS_B0+ 14 13
<31> EN_INVPWR <15> LVDS_B0+ 14 C1135
G SSM3K7002FU_SC70-3~D 15 5P_0402_50V8C
15
1
R2006 S LVDS_B1- 16 1 @2 LVDS_BCLK+

<15> LVDS_B1- 16
3
@ R382 0_0402_5%~D LVDS_B1+ 17

<15> LVDS_B1+ 17
+LCDVDD 2 1 18
@ 4.7K_0402_5%~D LVDS_B2- 18
<15> LVDS_B2- 19
D69 @ LVDS_B2+ 19
<15> LVDS_B2+ 20
20
2
BKOFF# 1 2 DISPOFF# 21
<31> BKOFF# 21
<15> LVDS_BCLK- LVDS_BCLK- 22
22
1
LVDS_BCLK+ 23
<15> LVDS_BCLK+ 23
CH751H-40PT_SOD323-2~D LCD_TEST 24
10K_0402_5%~D <31> LCD_TEST 24
D72 2 1 EDID_CLK_LCD 25
R2021 <15> LVDS_DDC_CLK 25
2 1 D50 R3790_0402_5%~D
2 1 EDID_DATA_LCD 26
<15> LVDS_DDC_DATA 26
DMIC_CLK 6 1 USB20_N3 INV_PWM_R R1836 0_0402_5%~D 27
+3VS +3VS V I/O V I/O 27
2
DISPOFF# 28
CH751H-40PT_SOD323-2~D USB20_P3 28
+5VS 5 2 <16> USB20_P3 29
V BUS Ground USB20_N3 30 29 41
<16> USB20_N3 30 G1
1
DMIC0 4 3 USB20_P3 CAM_DET# 31 42

V I/O V I/O <14> CAM_DET# 31 G2
DMIC_CLK_R 32 43
@R394
@ R394 IP4223CZ6_SO6-6 32 G3
33 44
33 G4
5
U54 10K_0402_5%~D DMIC0 34 45

<24> DMIC0 34 G5
1 +3VS_CAM 35 46
P
<15> VGA_PWM IN1 35 G6

2
4 INV_PWM 36 47
O +3VS 36 G7
<31> EC_INV_PWM 2
IN2 W=60mils +LCDVDD 37
37 G8
48
G
38 49
SN74AHC1G08DCKR_SC70-5 38 G9
39 50
39 G10
3
+3VS +3VS_CAM
Q47 W=60mils +INV_PWR_SRC 40
40 G11
51
SI2301CDS-T1-GE3_SOT23-3 JAE_FI-G40SB-VF25-R2000-DT~D
@R944
@ R944
0_0402_5%~D 3 1
S
CONN@
2 1 R1948
0_0402_5%~D
1
@ R1837
@R1837 2 INV_PWM 2 1 INV_PWM_R R1949
G
2
0_0402_5%~D R1653 0_0402_5%~D

A 2 1 C1748 100K_0402_5%~D DMIC_CLK 2 1 DMIC_CLK_R A
<24> DMIC_CLK
0.1U_0402_16V7K~D 1 1
1 @CU64
@ CU64
2
CU63
680P_0402_50V7K~D 470P_0402_50V7K~D
2 2
+LCDVDD
+3VS
1
D
close to JLVDS
0.1U_0402_16V7K~D
10U_0805_10V4Z~D
1
CV367 1 1 2
<31> EN_CAM
CV368
CV369
G Q42
0.1U_0402_16V7K~D
2
S SSM3K7002F_SC59-3
3
2 2 2011/01/25 2012/01/25 Title

EN_CAM# control circuit THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA / LVDS /camera conn.
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UL1
Atheros +LAN_IO
2 1 PCIE_PRX_GLANTX_P3_C 30 11 LAN_MDIP0 RL2 2 1 49.9_0402_1% +LAN0 CL3 1 2 1000P_0402_50V7K~D
<14> PCIE_PRX_GLANTX_P3 TX_P AR8151 AL1A TRXP0 LAN_MDIN0
CL2 0.1U_0402_16V7K~D 12 RL1 2 1 49.9_0402_1% CL4 1 2 0.1U_0402_16V7K~D
2 1 PCIE_PRX_GLANTX_N3_C 29 TRXN0 14 LAN_MDIP1 RL3 2 1 49.9_0402_1% +LAN1 CL5 1 2 1000P_0402_50V7K~D
<14> PCIE_PRX_GLANTX_N3 TX_N TRXP1
1
0_0402_5%~D
CL1 0.1U_0402_16V7K~D 15 LAN_MDIN1 RL4 2 1 49.9_0402_1% CL6 1 2 0.1U_0402_16V7K~D
PCIE_PTX_GLANRX_P3 TRXN1 LAN_MDIP2 RL5 49.9_0402_1% +LAN2 CL7 1000P_0402_50V7K~D RL6
<14> PCIE_PTX_GLANRX_P3 35 17 2 1 1 2
RX_P TRXP2 18 LAN_MDIN2 RL7 2 1 49.9_0402_1% CL8 1 2 0.1U_0402_16V7K~D
PCIE_PTX_GLANRX_N3 36 TRXN2 20 LAN_MDIP3 RL8 2 1 49.9_0402_1% +LAN3 CL9 1 2 1000P_0402_50V7K~D
<14> PCIE_PTX_GLANRX_N3 RX_N TRXP3
21 LAN_MDIN3 RL9 2 1 49.9_0402_1% CL10 1 2 0.1U_0402_16V7K~D
TRXN3
2
CLK_PCIE_LAN 33
<14> CLK_PCIE_LAN REFCLK_P
close to Lan chip 1000p reserved for EMI PLT_RST# 1 @ 2 4.7K_0402_5%~D
CLK_PCIE_LAN# 32 RL10
<14> CLK_PCIE_LAN# REFCLK_N 13 +AVDDL PCIE_WAKE# 1 @ 2 4.7K_0402_5%~D
CLKREQ_LAN#_R AVDDL RL11 +LAN_IO
<14> LANCLK_REQ# 2 1 4 19
RL12 0_0402_5%~D CLKREQ# AVDDL
31
PLT_RST# AVDDL CLKREQ_LAN#_R
<6,16,23,27,31,32> PLT_RST# 2 34 1 2 4.7K_0402_5%~D
D PERST# AVDDL RL13
D
6
PCIE_WAKE# AVDDL_REG
<15,31,32> PCIE_WAKE# 3
WAKE#
16 +AVDDH W=40mils
AVDDH
25
SMCLK AVDDH
22 2.2UH +-20% 1225AS-H-2R2M-P2 1.3A W=20mils
26 9
SMDATA AVDDH_REG LL1
28 +LX 1 2 +VDDCT +DVDDL
TEST_RST
1000P_0402_50V7K~D
10U_0603_6.3V6M~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
27 24 +DVDDL
TESTMODE DVDDL
1U_0603_10V6K~D
41 37
GND DVDDL_REG
LAN_X1
W=40mils 1 1 1 1 1 1 1
7
XTLO W=40mils
LAN_X2_R 8 1 +LAN_IO CL11 CL12 CL13 CL14 CL15 CL16 CL17
XTLI VDD33
2 2 2 2 2 2 2
40 +LX
LX
RL15
LAN_ACTIVITY VDDCT
5 +VDDCT close to Lan pin40
38
LED_0
2
LAN_LINK#_R 39 10 +RBIAS 1 RL14 2

LED_1 RBIAS
LAN_LED2#_R 23
LED_2
2.37K_0402_1%~D close to Lan pin5
2
close to Lan pin37 close to Lan pin24

0_0402_5%~D RL16
25MHz_12P_X5H025000FC1H-H 5.1K_0402_1%~D AR8151-BL1A
1
YL1
Version A will be fail on 802.3a
1
1 2 LAN_X2
1
CL18
1
CL19
need to update to Version B
15P_0402_50V8J~D 15P_0402_50V8J~D
2 2
W=40mils
W=40mils
C +3VALW C
QL1 W=20mils W=20mils
+LAN_IO close to Lan pin19
D
6 1A
S
1 5 4 +LAN_IO_R R2016 1 2 close to Lan pin9 close to Lan pin16 close to Lan pin6 close to Lan pin31
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CL20 2
1U_0603_10V6K~D
1U_0402_6.3V6K~D 1 0_0805_5%~D +AVDDH +AVDDL
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
SI3456BDV-T1-E3 1N TSOP6
G
1U_0603_10V6K~D
1U_0603_10V6K~D
B+_BIAS 1 1 1 1 1
3
+3VALW 1 1 1 1 1 1 1 1 1 1
CL31 CL32 CL33 CL34 CL35
CL21 CL22 CL23 CL24 CL25 CL26 CL27 CL28 CL29 CL30
2 2 2 2 2
2
RL18 2 2 2 2 2 2 2 2 2 2
2
470K_0402_5%~D
RL28
10K_0402_5%~D
1
EN_WOL close to Pin 1

1
D
2
1.5M_0402_5%~D
1 close to Lan pin22

<31> EN_WOL# 2 QL2 close to Lan pin34 close to Lan pin13
G SSM3K7002FU_SC70-3 RL19 CL36
S 0.1U_0402_25V6
2
3
2 1 LAN_LED2#_R
RL26 470_0402_5%~D
TS1 2 1 LAN_LINK#_R
LL2 RL21 RL27 130_0402_1%~D
+VDDCT 2 1 +VDDCT_L 1 24 RJ45_CT3 1 2
MURATA_BLM18AG601SN1D_0603 LAN_MDIP3 TCT1 MCT1 RJ45_MDI3+ 75_0402_1%~D JLAN1
2 23
LAN_MDIN3 TD1+ MX1+ RJ45_MDI3- RJ45_MDI0+ CL49 470P_0402_50V7K
3 22 1
TD1- MX1- RL22 PR1+ LAN_LED2#
9 1 2
4 21 RJ45_CT2 1 2 RJ45_MDI0- 2 LDE_ORANGE- CL38 470P_0402_50V7K
B
LAN_MDIP2 TCT2 MCT2 RJ45_MDI2+ 75_0402_1%~D PR1- LAN_LINK#
B
5 20 10 2 1
LAN_MDIN2 6 TD2+ MX2+ 19 RJ45_MDI2- RJ45_MDI1+ 3 LDE_GREEN-
TD2- MX2- RL23 PR2+ 11 LAN_LED_VCC1 2 RL20 1
A2 +LAN_IO
7 18 RJ45_CT1 1 2 RJ45_MDI2+ 4 0_0402_5%~D
LAN_MDIP1 TCT3 MCT3 RJ45_MDI1+ 75_0402_1%~D PR3+ LAN_ACTIVITY_R
8 17 12 2 1LAN_ACTIVITY
LAN_MDIN1 TD3+ MX3+ RJ45_MDI1- RJ45_MDI2- LED_YELLOW+ RL25 330_0402_5%
9 16 5
TD3- MX3- RL24 PR3-
13
RJ45_CT0 RJ45_MDI1- LED_YELLOW-
10 15 1 2 6
LAN_MDIP0 TCT4 MCT4 RJ45_MDI0+ 75_0402_1%~D PR2-
11 14 14
LAN_MDIN0 TD4+ MX4+ RJ45_MDI0- RJ45_MDI3+ NC
12 13 7
SHLD1
SHLD2
TD4- MX4- PR4+
RJ45_MDI3- 8
PR4-
2
350UH_GST5009-CLF FOX_JM36113-P2651-9F~D
15
16
TIMAG: S X'FORM_ IH-160 LAN , SP050006F00 CL39
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 1000P_1808_3KV7K~D
1
CONN@
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1U_0603_10V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
CL40
CL41
CL42
CL43
CL44
CL45
CL46
CL47
CL48
1 2 1 2 1 2 1 2 1
close to LL2
@ @ @ @
2 1 2 1 2 1 2 1 2
close to TS1
A A

GLAN AR8151 AL1A/ RJ45
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+3VS_CR
Zdiff = 100 ohm U135 +ODR_PWR

R1563
PCIE_PTX_CARDRX_P4 1 48 RREF 2 1
<14> PCIE_PTX_CARDRX_P4 HSIP RREF CR27
6.2K_0402_1%~D
<14> PCIE_PTX_CARDRX_N4 PCIE_PTX_CARDRX_N4 2 47 2 1
HSIN 3V3_IN
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CLK_PCIE_CD 3 46 CDCLK_REQ# CR5 CR6
<14> CLK_PCIE_CD REFCLKP CLK_REQ# CDCLK_REQ# <14> 0.1U_0402_10V7K~D
10K_0402_5%~D
1 CR4 1 1
1
CLK_PCIE_CD# 4 45 PLT_RST# RR3 CR3
<14> CLK_PCIE_CD# REFCLKN PERST# PLT_RST# <6,16,22,27,31,32>
CR24 4.7U_0603_6.3V6K~D
1 2 AV12 5 44
AV12 EEDO 2 2 2
2
D D
2
PCIE_PRX_CARDTX_P4 1 2 PCIE_PRX_CARDTX_P4_C 6 43 CARD_HPLUG_R 1 @ 2 CARD_HPLUG
<14> PCIE_PRX_CARDTX_P4 HSOP EECS CARD_HPLUG <16>
CR15 0.1U_0402_10V7K~D RR25 0_0402_5%~D For ver:ES2-B0
PCIE_PRX_CARDTX_N4 1 2 PCIE_PRX_CARDTX_N4_C 7 42
<14> PCIE_PRX_CARDTX_N4 HSON EESK
CR16 0.1U_0402_10V7K~D
8 41
GND GPIO/EEDI
+ODR_PWR 1 2 DV12 9 40 MS_INS#
CR22 0.1U_0402_10V7K~D DV12 MS_INS#
+3VS_CR
10
Card1_3V3 SD_CD#
39 SD_CD#
RR22 change to 0Ω Place CR3 close to socket pin 22
11 38 SP15_SDWP_XDD7 Place CR4 close to socket pin 11
3V3_IN SP15
1 12
Card2_3V3 SP14
37 SP14_MSCLK_XDD6 1 2 SP14_MSCLK_XDD6_R
2 Place CR5 close to socket pin 11
1
CR28 CR19 RR22 0_0402_5%~D

XD_CD# 13 36 SP13_MSD7_XDD5 CR26 Place CR6 close to socket pin 18
10U_0603_6.3V6M~D 0.1U_0402_10V7K~D XD_CD# SP13
22P_0402_50V8J~D
2 1
2
DV33_18 14 35 SP12_MSD3_XDD4
DV33_18 SP12 @
1
CR23 15 34 SP11_MSD6_XDD3
GND SP11
0.1U_0402_10V7K~DSP1_SDD7_XDRDY 16 33 SP10_MSD2_XDD2
2 SP1 SP10
Removed CR17 SP2_SDD6_XDRE# 17 32 SP9_MSD0_XDD1
SP2 SP9
SP3_SDD5_XDCE# 18 31 SP8_MSD4_XDD0
SP3 SP8
SP4_SDD4_XDWE# 19 30 SP7_MSD1_XDWP#
SP4 SP7
CR20
SD_D1_R 1 2 SD_D1 20 29 SP6_MSD5_XDALE
RR20 0_0402_5%~D SD_D1 SP6
1 2
SD_D0_R 1 2 SD_D0 21 28 SP5_MSBS_XDCLE
CR25 RR19 0_0402_5%~D SD_D0 SP5 4.7U_0603_6.3V6K~D
1 2SD_CLK_R 1 2 SD_CLK 22 27 DV12_S 1 2
RR23 33_0402_1% SD_CLK DV12_S CR21
22P_0402_50V8J~D SD_CMD_R 1 2 SD_CMD 23 26 0.1U_0402_10V7K~D
@ RR24 0_0402_5%~D SD_CMD GND
Reserved SD_D3_R 1 2 SD_D3 24
SD_D3 SD_D2
25 SD_D2 1 2 SD_D2_R
C RR21 0_0402_5%~D RR12 0_0402_5%~D C
RTS5209-GR_LQFP48_7X7
+3VS R2017 1 2 +3VS_CR

0_0805_5%~D
+ODR_PWR +ODR_PWR Reserve for EMI please close to JREAD1

JREAD CONN@ Co-lay connector for 2nd. 2010/11/26
22 11
XD-VCC SD4-VDD
18
SP8_MSD4_XDD0 MS9-VCC @ @ +ODR_PWR +ODR_PWR
30
SP9_MSD0_XDD1 XD10-D0 SD_CLK_R
29 9 1 RR8 2 2 1 CR14
SP10_MSD2_XDD2 28 XD11-D1 SD5-CLK 4 SD_D0_R 33_0402_5% 22P_0402_50V8J~D JREAD1 CONN@
B
SP11_MSD6_XDD3 XD12-D2 SD7-DAT0 SD_D1_R
B
27 3 24 12
SP12_MSD3_XDD4 26 XD13-D3 SD8-DAT1 21 SD_D2_R XD-VCC SD-VDD/MMC-VDD 19
SP13_MSD7_XDD5 25 XD14-D4 SD9-DAT2 19 SD_D3_R SP8_MSD4_XDD0 32 MS-VCC
SP14_MSCLK_XDD6 XD15-D5 SD1-DAT3 SD_CMD_R SP9_MSD0_XDD1 XD-D0 SD_CLK_R
24 16 31 10
SP15_SDWP_XDD7 XD16-D6 SD2-CMD SD_CD# SP10_MSD2_XDD2 XD-D1 MMC-CLK/SD-CLK SD_D0_R
23 1 30 4
XD17-D7 SD-CD SP15_SDWP_XDD7 SP11_MSD6_XDD3 XD-D2 MMC-DAT/SD-DAT0 SD_D1_R
2 29 3
SP4_SDD4_XDWE# SD-WP SP12_MSD3_XDD4 XD-D3 SD-DAT1 SD_D2_R
33 28 22
SP7_MSD1_XDWP# XD07-WE Reserve for EMI SP13_MSD7_XDD5 XD-D4 SD-DAT2 SD_D3_R
32 6 27 20
SP6_MSD5_XDALE XD08-WP SD6-VSS SP14_MSCLK_XDD6 XD-D5 MMC-RSV/SD-DAT3 SD_CMD_R
34 13 please close to JREAD1 26 17
XD_CD# XD06-ALE SD3-VSS SP15_SDWP_XDD7 XD-D6 SD-CMD/MMC-CMD SD_CD#
39 25 1
SP1_SDD7_XDRDY XD01-CD XD-D7 SD-CD SP15_SDWP_XDD7
38 2
SP2_SDD6_XDRE# XD02-R/B @ SP4_SDD4_XDWE# SD-WP
37 35 5
SP3_SDD5_XDCE# XD03-RE SP14_MSCLK_XDD6_R 1 RR11 SP7_MSD1_XDWP# XD-WE SD-CD
36 17 2 34
SP5_MSBS_XDCLE XD04-CE MS8-SCLK SP9_MSD0_XDD1 33_0402_5% SP6_MSD5_XDALE XD-WP SP14_MSCLK_XDD6_R
35 10 36 18
XD05-CLE MS4-DATA0 SP7_MSD1_XDWP# XD_CD# XD-ALE MS-SCLK SP9_MSD0_XDD1
8 41 11
31 MS3-DATA1 12 SP10_MSD2_XDD2 SP1_SDD7_XDRDY 40 XD-CD MS-SDIO/DATA0 9 SP7_MSD1_XDWP#
XD GND MS5-DATA2 SP12_MSD3_XDD4 SP2_SDD6_XDRE# XD-R/-B MS-DATA1 SP10_MSD2_XDD2
40 15 1 39 13
XD GND MS7-DATA3 MS_INS# SP3_SDD5_XDCE# XD-RE MS-DATA2 SP12_MSD3_XDD4
14 38 16
MS6-INS 7 SP5_MSBS_XDCLE CR18 SP5_MSBS_XDCLE 37 XD-CE MS-DATA3 15 MS_INS#
MS2-BS 5 @ 22P_0402_50V8J~D XD-CLE MS-INS 8 SP5_MSBS_XDCLE
MS1-VSS 2 MS-BS
41 20 6
SD CD/WP GND MS10-VSS MS-VSS
42 33 21
SD CD/WP GND XD-GND MS-VSS
42
T-SOL_144-1300002600_NR XD-GND
14
SD-VSS/MMC-VSS1
43 23
GND SD-VSS/MMC-VSS2
44 7
GND SD-VSS/MMC-VSS2
ALPS_SCDG4B0102_NR
A A

Card Reader RTS5209
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+VDDA
1
R1
+5VAMP
10K_0402_5%~D
60mil U1 (output = 300 mA)
+5VS L1 1 2 1
IN 40mil
2
FBMA-L11-201209-221LMA30T_0805 5 +VDDA
OUT
1 2 1 1 2
C2 C3 GND
1 4.75V
1
C1 1U_0402_6.3V6K~D L2 1 2 3 4 C4
R2 FBMA-L11-201209-221LMA30T_080510U_0805_10V4Z~D
0.1U_0402_16V7K~D SHDN BYP
D 10K_0402_5%~D 2 2 RT9198-4GGBR_SOT23-5 4.7U_0805_10V4Z~D D
1 2
C5
2
C6
1 2 MONO_IN 2
HD Audio Codec
1U_0402_6.3V6K~D 0.01U_0402_16V7K~D
1
C7 C 1 2
R4 Q1 R3 1.3K_0402_1%
<31> BEEP# 1 2 1 2 2
B
1U_0402_6.3V6K~D 560_0402_5% E 2SC2411K_SOT23
3
C1870
20mil +1.5VS_DVDD
1
L14 @
2
R5 +1.5VS
1 2 1 2 1 1 FBMA-L11-160808-800LMT_0603
<13> HDA_SPKR
2
C47 C48
1
1U_0402_6.3V6K~D 560_0402_5% R2003
D1 +AVDD_HDA 0.1U_0402_16V7K~D 0_0402_5%~D
R6 2 2
SDMK0340L-7-F_SOD323-2~D
10K_0402_5%~D L4
40mil 20mil 10U_0805_10V4Z~D L5
1
1 2 +3VS_DVDD1 2
+VDDA +3VS
2
FBMA-L11-160808-800LMT_0603
1 1 1 1 FBMA-L11-160808-800LMT_0603
C11 C12
C9 C10
10U_0805_10V4Z~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D
25
38
2 2 2 2
9
U2
10U_0805_10V4Z~D
DVDD
DVDD_IO
AVDD1
AVDD2
+3VS close to U2, 7/26
14

LINE2-L
1
39 AMP_LEFT
C SURR_L AMP_LEFT <25> C
R1792 15
4.7K_0402_1%~D LINE2-R AMP_RIGHT
5/30 change +1.5vs to +3vs 16
MIC2_L
SURR_R
41 AMP_RIGHT <25>
35 MIC2-OUT_L <25>
MIC2-OUT-L
2
HDA_RST_AUDIO# 17
MIC2_R
33 MIC2-OUT_R <25>
MIC2-OUT-R
1 2 1 29
2.2U_0603_6.3V6K~D
C13 CBP
C46
32 LINE2-OUT_R <25>
0.1U_0402_16V7K~D LINE2-OUT-R
30
CBN
Close to codec LINE2-OUT-L
34 LINE2-OUT_L <25>
2 2 1 31
2.2U_0603_6.3V6K~DC14 CPVEE
For EMI 1 2 1 2 C15
MIC1_L 1 2 21 43 R7 0_0402_5%~D 22P_0402_50V8J~D
<25> MIC1_L MIC1_L NC
C16 4.7U_0603_6.3V6M
MIC1_R 1 2 22 6
<25> MIC1_R MIC1_R BITCLK HDA_BITCLK_AUDIO <13>
C17 4.7U_0603_6.3V6M
MONO_IN 12 8 HDA_SDIN0_AUDIO 1 2
PCBEEP SDATA_IN HDA_SDIN0 <13>
R8 33_0402_5%
<13> HDA_RST_AUDIO# 11
RESET#
23
LINE1-L
<13> HDA_SYNC_AUDIO 10
SYNC
24
LINE1-R
<13> HDA_SDOUT_AUDIO 5
SDATA_OUT
Place close to Codec 45

SPDIFO2 MIC2-VREFO
19
R9 1 2 20K_0402_1%~D 13 20
<25> MIC1_PLUG# SENSE A LINE2-VREFO
R10 2 1 39.2K_0402_1% 36
<25> LINE2_PLUG# SENSE B
R11 1 2 20K_0402_1%~D 18
<25> MIC2_PLUG# LINE1-VREFO
<31> EC_EAPD# 47
48
EAPD
28
10mil
SPDIFO1 MIC1-VREFO MIC1_VREFO
B L102 FBMA-10-100505-301T 0402 CODEC_VREF
10mil B
44 27
DMIC-CLK3/4 VREF
<21> DMIC_CLK 1 2 46 1 1
DMIC_CLK1/2
Reserve for EMI 40 C20
JDREF C19
3
GPIO1/DMIC-3/4
1
1 2 2 37 0.1U_0402_16V7K~D 10U_0805_10V4Z~D
<21> DMIC0 GPIO0/DMIC-1/2 MONO-OUT 2 2 @
R110 0_0402_5%~D R12
20K_0402_1%~D
@ C119
@ C120
4 26
DVSS AVSS1
7 42
DVSS AVSS2
1 1 Close to codec
2
ALC665-GR_LQFP48_7X7
15P_0402_50V8J~D
15P_0402_50V8J~D
2 2
MONO_OUT <25>
1 2 1 2
R13 0_0805_5%~D R14 0_0805_5%~D
1 2 1 2
R15 0_0805_5%~D R16 0_0805_5%~D
1 2 1 2
R17 0_0805_5%~D R18 0_0805_5%~D
GND GNDA GND GNDA
A A

Codec ALC665
LA-6801P
5 4 3 2 1
5 4 3 2 1
+5VAMP LINE Out/Headphone Out

W=40mil JHP1
+5VAMP +5VAMP 1 1 3
C21 C27
<24> LINE2-OUT_L 1 2 LINE2_OUT_L_1 1 2 LINE2_L 1
0.1U_0402_16V7K~D 4.7U_0805_10V4Z R30 56.2_0603_1% L6 BLM15AG121SN1D_L0402_2P
2 2
2
GAIN0 GAIN1 <24> LINE2-OUT_R 1 2 LINE2_OUT_R_1 1 2 LIEN2_R 2
R31 56.2_0603_1% L7 BLM15AG121SN1D_L0402_2P 5
0 0 6dB R23 R24
+3VS
0 1 10dB 100K_0402_1% 100K_0402_1%
<24> LINE2_PLUG# 6
@
1 0 15.6dB
2 1
2 1
GAIN0 GAIN1
W=20mil
1 1 21.6dB 4 SHLD1
3
U3
PJDLC05C_SOT23-3
R26 R27 R25
100K_0402_1% 100K_0402_1% 16 12 47K_0402_1% D5 SINGA_2SJ2285-112252
@ VDD NC
6 1 1
D PVDD D
1
15 @ C33 @ C34 CONN@
PVDD
2
19 SPK_MUTE# <31>
SHUTDOWN
10P_0402_50V8J
10P_0402_50V8J
GAIN0 2 2 2
GAIN0 SPKL- @
8
LOUT-
1
GAIN1 3
GAIN1
FFC=153HZ ROUT-
14 SPKR-
LINE Out/Headphone Out

C26 4 SPKL+
0.47U_0603_16V4Z LOUT+
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C 5 18 SPKR+
<24> AMP_LEFT LIN- ROUT+
C29 0.1U_0402_16V7K~D
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C 17
<24> AMP_RIGHT RIN-
C28 C32 0.1U_0402_16V7K~D 1 JHP2
GND
1
0.47U_0603_16V4Z 9 11 3
R28 R29 LIN+ GND R33 75_0402_1%
13
7 GND 20 1 2 MIC2_OUT_L_11 2 MIC2_OUT_L_R 1
RIN+ GND <24> MIC2-OUT_L
390_0402_5% 390_0402_5% 21 R32 75_0402_1% L8 BLM15AG121SN1D_L0402_2P
GND MIC2_OUT_R_1 MIC2_OUT_R_R
1 1 1 2 1 2 2
<24> MIC2-OUT_R
2
10 L9 BLM15AG121SN1D_L0402_2P 5
C30 C31 BYPASS
1
0.1U_0603_25V7K 0.1U_0603_25V7K 6
2 2 <24> MIC2_PLUG#
C41
TPA6017A2PWPR_TSSOP20 2.2U_0603_10V7K~D
2 4 SHLD1
3
220P_0402_50V8J
1 1 SINGA_2SJ2285-112252
@ C35 @ C36 D6
CONN@
1 2 1 2 220P_0402_50V8J PJDLC05C_SOT23-3
C1926 0.015U_0402_16V7K C1927 0.015U_0402_16V7K 2 2
For ESD @
R1980 1 2 12K_0402_5%~D R1981 1 2 12K_0402_5%~D
I/O status:
1
+5VAMP +5VAMP a. input/output mount 75 ohm
C
b. input only mount 1K ohm C
4
4
C1929 0.033U_0603_25V7M~D U634A C19310.033U_0603_25V7M~D U634B MIC1_VREFO MIC1_VREFO
AMP_LEFT 1 2 1 2 3 C1932 @ AMP_RIGHT 1 2 1 2 5 C1933 @
P
P
C1928 0.015U_0402_16V7K + AMP_LEFT_C C1930 0.015U_0402_16V7K + AMP_RIGHT_C
1 1 2 7 1 2
+5VAMP OUT +5VAMP OUT
@ 2 @ 6
- -
G
2.2K_0402_5%
@
1U_0603_16V6K~D
TLV2464_TSSOP14 @
1U_0603_16V6K~D
TLV2464_TSSOP14 R34 R35 MIC JACK
11
11
2.2K_0402_5%
1
1
1 R1984 2 1 R1985 2
R1986 R1987
2
4.7K_0603_1% 10K_0402_5%~D 4.7K_0603_1% 10K_0402_5%~D JHP3
1
1
3
R1988 R1989 R36 75_0402_1%
2
2
10K_0402_5%~D 10K_0402_5%~D 1 2 MIC1_L_1 1 2 MIC1_L_R 1
<24> MIC1_L
L10 BLM15AG121SN1D_L0402_2P
1 2 MIC1_R_1 1 2 MIC1_R_R 2
<24> MIC1_R
2
2
R37 75_0402_1% L11 BLM15AG121SN1D_L0402_2P 5
<24> MIC1_PLUG# 6
3
4 SHLD1
PJDLC05C_SOT23-3
1 1
@ @ C40
+3VS 1 2 @ C39 D7 SINGA_2SJ2285-112252
220P_0402_50V8J
C1934 0.012U_0603_50V7K~D
2 2
W=20mil 1
@
2
220P_0402_50V8J CONN@
1
C1935 0.012U_0603_50V7K~D
R1863 @
1
47K_0402_1% +5VAMP
W=40mil
2
<31> SPK_MUTE# 1 1
B
C1886 C1885 B
0.1U_0402_16V7K~D 4.7U_0603_10V6K~D
2 2
either one option.
C1889 Int. Speaker Conn.
6
1 2
0.47U_0603_16V4Z
1 2 AMP_LEFT_R 1 2 AMP_LEFT_RR 3
U633
20mil JSPK
<24> MONO_OUT
VDD
R1990 1K_0603_1% C1888 R1879 3.48K_0603_1% IN+ JWFER2 SPKL+ R19 1 0_0603_5% SPK_L+
2 1
0.47U_0603_16V4Z SUB_L+ SPKL- R21 1 0_0603_5% SPK_L- 1
5 1 2 2
AMP_RIGHT_R 1 AMP_RIGHT_RR VO+ SUB_R- 1 SPKR+ R20 1 0_0603_5% SPK_R+ 2
1 2 1 2 2 4 2 2 3
R1991 1K_0402_1%~D R1861 3.48K_0603_1% IN- 2 SPKR- R1848 1 0_0603_5% SPK_R- 3
2 4
MOLEX_53261-0271~D 4
@ 5
GND
2
220nF_0402_16V7K
1
SHUTDOWN VO-
8 1 C22 6
GND
2
1 R2002 CONN@ 220P_0402_50V8J
GND
GND
1
0_0402_5%~D
C1937
20K_0402_1%~D 2 MOLEX_53780-0470
BYPASS
C1936
PJDLC05C_SOT23-3
D2 D4 1 C23 CONN@
@ 2
1 TPA6211A1DGNRG4_MSOP8 220P_0402_50V8J
2
1
7
9
PJDLC05C_SOT23-3
2 C1887 1 C24
2
2
0.22U_0603_25V7K~D 220P_0402_50V8J
C1945 2
1 C25
1U_0603_16V6K~D
1 For ESD 2
220P_0402_50V8J
1
@
2
MONO_OUT1 2
R1993
@ R1992 0_0603_5% @ C1939
1 2 @ 1 2
100K_0402_1%~D
1U_0603_16V6K~D
+5VAMP
R1994
@
AMP_LEFT 1 2 @
11
<24> AMP_LEFT TLV2464_TSSOP14

100K_0402_1%~D C1940
R1995
4
1 2 9 @ R1996 U634D
R1997 R1998
G
@ - 8 1 2 1 2 12 C1941 @ @
P
AMP_RIGHT 1U_0603_16V6K~D OUT 1K_0402_1%~D 1K_0402_1%~D + AMP_RIGHT_RR

A
<24> AMP_RIGHT 1 2 10 14 1 2 1 2 A
+ OUT
P
100K_0402_1%~D 13 20K_0402_1%~D
-
G
+5VAMP @ U634C 2 1U_0603_16V6K~D

4
@ @ TLV2464_TSSOP14
11
C1942
1
+5VAMP 1U_0603_16V6K~D @
R2000 1
10K_0402_1%~D @
1 2

R2001 Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
10K_0402_1%~D @
Amp TPA6017/subwoofer/ Audio Jack
2
LA-6801P 1.0

5 4 3 2 1
A B C D E
+5VALW
Power share
CB Function
1
2.0A
10K_0402_1%~D
R1941
+5V_CHGUSB
L auto detection charger identification active +5VALW
@ U29
H DP/DM=TDP/TDM 1
GND OC1#
8 USB_OC2# <16>
2 7
IN OUT1
2
1 1
3 6
PWRSHARE_EN# 1 EN1# OUT2
2 4 5
R2007 10K_0402_5%~D EN2# OC2#
1 1
U30 C262 C263 TPS2062ADR_SO8~D
PWRSHARE_EN# 1 8 PWRSHARE_OE#
CEN CB PWRSHARE_OE# <31>
10U_1206_16V4Z
0.1U_0402_16V7K~D
SW_USB20_N9 2 7
DM TDM USB20_N9 <16> 2 2
1
SW_USB20_P9 3 6 2 1
DP TDP USB20_P9 <16> <31> PWRSHARE_EN_EC# 2 1
4 5 +5VALW R203
GND VCC 100K_0402_5%~D D71
9
GND 1SS355TE-17_SOD323-2
2
MAX14566EETA+_TDFN-EP8_2X2~D C261
2
0.1U_0402_16V7K~D PWRSHARE_EN#
1
1
10K_0402_1%~D
R2004
2
@
R262 1 2 0_0402_5%~D
2 2
L40
SW_USB20_P9 1 2 USB20_P9_CONN
1 2
SW_USB20_N9 4 3 USB20_N9_CONN
4 3
WCM2012F2S-900T04_0805 L40 close to JUSB1
R222 1 2 0_0402_5%~D
@
+5VALW close to JUSB1
D26
3 6
V I/O V I/O
1
USB CONN +5V_CHGUSB
3
5
V BUS Ground
2
2.0A
4 3
V I/O V I/O JUSB1
IP4223CZ6_SO6-6
150U_B2_6.3VM_R35M
1 1
USB20_P9_CONN GND
0.1U_0402_16V7K~D
2 1
USB20_N9_CONN USB_P +
3
+5V_CHGUSB USB_N C303 C265
4
VCC
5
GND 2 2
6
GND
7
GND
8
GND
SUYIN_020173MR004S52KZL
CONN@
4 4

USB conn.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6801P 1.0

A B C D E
5 4 3 2 1

+3V +1.05VR
+5VALW +1.5V_3.0 +1.5V_3.0 +3VA +3VA
+5VALW +1.05V
10U_0603_6.3V6M~D
1U_0603_10V6K~D
+1.5V_3.0 UI6 1 2
+1.5V
1A
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
.1U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
.1U_0402_16V7K~D
.1U_0402_16V7K~D
.1U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 1 6 RI21 0_0603_5%~D
VCNTL
CI41
CI42
.1U_0402_16V7K~D
8P_0402_50V8D~D
.1U_0402_16V7K~D
8P_0402_50V8D~D
5 3 +1.5VS 1 2 1 1 1 1 1 1
VIN VOUT
CI43
CI44
@CI45
@
CI46
CI47
@CI48
@
9 4 RI22 @ 0_0603_5%~D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+5VALW VIN VOUT
CI45
CI48
CI49
CI50
CI51
CI52
CI53
CI54
CI55
CI56
CI57
CI58
CI59
CI60
CI61
CI62
CI63
2 2 SYSON 8 +3V_3.0
D EN 2 2 2 2 2 2 D
10U_0603_6.3V6M~D
2 1 7 2 1 RI24 2
GND
RI23 5.1K_0402_1% POK FB 10K_0402_1%~D 1 +3VALW 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CI64
RI25 0_0603_5%~D

APL5930KAI-TRG_SO8 RI26 +3VS 1 2
1

32.4K_0402_1%~D RI27 @ 0_0603_5%~D
2

2

RI28
0_0805_5%
+3V 1 2 +1.05VR +3VA +3V +3VA For EMI request For EMI request
+3V_3.0 +3V +1.05V
UI7 LI1
BLM18AG601SN1D_2P LI2 LI3
U3TXDP2_L 4U3TXDP2 U3TXDN1_L 1U3TXDN1
10U_0603_6.3V6M~D
3 1 1 2 3 2
SYSON 4 VIN VOUT 5
<31,33,53> SYSON VIN/CE VOUT 1
D10
H11
E11
E12
K11
K12
P13
F13
F14
L10
L13
L14
0.2A
CI65
UI5
G3
G4
N4
N5
N6
C4
C5
C6
C7
D5
C8
C9
D8
D9
H3
H4
D7
P3
E3
E4
F3
L9
L5
L8
2 U3TXDN2_L 2 1U3TXDN2 U3TXDP1_L 3 4U3TXDP1
GND
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
U3AVDO33
U2AVDD10
RT9701-PB_SOT23-5 2 DLW21SN670HQ2L_4P DLW21SN670HQ2L_4P
LI4 LI5
CLK_PCIE_USB30 B2 CI66 U3RXDP2_L 3 4U3RXDP2 U3RXDN1_L 2 1U3RXDN1
<14> CLK_PCIE_USB30 PECLKP
<14> CLK_PCIE_USB30#
CLK_PCIE_USB30# B1
PECLKN SPEC Max:+3V---200mA;+1.05V---800mA .1U_0402_16V7K~D
B6 U3TX_C_DP2 1 2 U3TXDP2_L
U3TXDP2
<14> PCIE_PRX_USB3TX_P6
CI67 1 2 .1U_0402_16V7K~D PCIE_PRX_USB3TX_C_P6 D2
PETXP
Idle mode:0.489W: U3RXDN2_L 2 1U3RXDN2 U3RXDP1_L 3 4U3RXDP1
CI68 1 2 .1U_0402_16V7K~D PCIE_PRX_USB3TX_C_N6 D1 A6 U3TX_C_DN2 1 2 U3TXDN2_L
<14> PCIE_PRX_USB3TX_N6 PETXN +3V---43mA;+1.05V---328mA U3TXDN2
N8 U2DN2_L DLW21SN670HQ2L_4P DLW21SN670HQ2L_4P
PCIE_PTX_USB3RX_P6 U2DM2
<14> PCIE_PTX_USB3RX_P6
PCIE_PTX_USB3RX_N6
F2
PERXP D3 mode:0.066W: U2DP2_L
CI69
F1 P8 .1U_0402_16V7K~D LI6 LI7
<14> PCIE_PTX_USB3RX_N6 PERXN +3V---5.4mA;+1.05V---45mA U2DP2
B8 U3RXDP2_L U2DP2_L 3 4 U2DP2 U2DP1_L 3 4 U2DP1
U3RXDP2 3 4 3 4
A8 U3RXDN2_L +3V
U3RXDN2 U2DN2_L U2DN2 U2DN1_L U2DN1
2 1 2 1
RI29 1 2 0_0402_5%~D H2 2 1 2 1
<6,16,22,23,31,32> PLT_RST# PERSTB
C 1 2 PCIE_WAKE#_USB3 K1 G14 OCI2B RI31 1 2 10K_0402_5%~D WCM-2012-670T_4P WCM-2012-670T_4P C
<31> USB_PCIE_WAKE# PEWAKEB OCI2B
RI30 0_0402_5%~D CLKREQ_USB3 K2 Can be attach to EC, either. H13 OCI1B RI32 1 2 10K_0402_5%~D
RI33 PECREQB OCI1B
+3V 1 2 10K_0402_1%~D
@ RI34 1 2100_0402_1%~D J2

RI35 AUXDET +USB3_VCCA +USB3_VCCB
+3V 1 2 10K_0402_1%~DJ1 H14
USB3_SMI#_R @ RI36 PSEL PPON2
1 2 0_0402_5%~D H1 PCI Express/ExpressCard select signal J14
RI37 SMI PPON1
1 2 0_0402_5%~D P4 1:others DI1 DI2
SMIB CI70 U3RXDN2 U3RXDN1
1 8 1 8
RI38 0:Express Card or Mini card R- VCC R- VCC
+3V 1 2 10K_0402_1%~D P5 .1U_0402_16V7K~D U3RXDP2 2 7 U3RXDP1 2 7
PONRSTB U3TX_C_DP1 R+ GND R+ GND
B10 1 2 U3TXDP1_L U3TXDN2 3 6 U2DN2 U3TXDN1 3 6 U2DN1
U3TXDP1 U3TXDP2 T- D- U2DP2 U3TXDP1 T- D- U2DP1
1 2 1 2 4 5 4 5
1 2 SPI_CLK_USB T+ D+ T+ D+
DI3 CI71 1 2 M2 A10 U3TX_C_DN1 1 2 U3TXDN1_L
1SS355TE-17_SOD323-2 1U_0603_10V6K~D SPI_CS_USB# RI39 0_0402_5%~D N2 SPISCK U3TXDN1
N10 U2DN1_L LXES4XBAA6-027_MSOP8 LXES4XBAA6-027_MSOP8
+3V USB_SO_SPI_SI SPISCB U2DM1 CI72
N1
USB_SI_SPI_SO SPISI
M1 P10 U2DP1_L .1U_0402_16V7K~D
SPISO U2DP1
B12 U3RXDP1_L
U3RXDP1
2
+3V RI40 K13 A12 U3RXDN1_L

10K_0402_1%~D GND U3RXDN1 +5VALW +USB3_VCCA
K14
GND
J13
GND 2.0A
2
CI73 UI3 W=60mils

G
1.6K_0402_1%~D .1U_0402_16V7K~D 1 8
CLKREQ_USB3 GND OC1# RI42
<14> USB30_CLKREQ#
1 3 As short as possible RREF
P12 RI41 1 2 1 2 2
IN OUT1
7
N12 3 6 10K_0402_5%~D
D
QI1 +3V C14 U2AVSS USB_PWR_EN# 4 EN1# OUT2 5 1 2 OCI2B

SSM3K7002FU_SC70-3~D GND EN2# OC2#
N11
U2PVSS TPS2062ADR_SO8~D +USB3_VCCB
1
+5VALW
0_0402_5%~D
D6
+3V U3AVSS
2.0A
@
USB3_XT1 N14
XT1
RI43
USB3_XT2 M14
XT2
CI74 UI4 W=60mils
.1U_0402_16V7K~D 1 8
GND OC1#
2
P/N: SA000048H0L (S IC UPD720200AF1-DAP-A FBGA 176P USB3.0) 1 2 2

IN OUT1
7 RI47
2
+3V @ RI57 3 6 10K_0402_5%~D

A version EN1# OUT2 OCI1B
10K_0402_5%~D P6
CSEL 8/11 update <31> USB_PWR_EN# 4
EN2# OC2#
5 1 2
2
TPS2062ADR_SO8~D
G
+USB3_VCCA +USB3_VCCA
0_0402_5%~D
@ P14
USB_PCIE_WAKE# PCIE_WAKE#_USB3 GND
RI48
1 3 A1 P11
B GND GND B
A2 P9
D
GND GND
150U_B2_6.3VM_R35M
QI2 A3 P7 JUSB3 CONN@

GND GND U3TXDP2
10U_0603_6.3V6M~D
SSM3K7002FU_SC70-3 A4 P2 9 1
GND GND SSTX+
1
+3V A5 P1 1
GND GND VBUS 1
CI28
CI29
A7 N13 U3TXDN2 8 RI49 1 2 0_0603_5%~D +
GND GND U2DP2 SSTX-
A9 N9 3
GND GND D+
2
A11 N7 7 RI50 1 2 0_0603_5%~D

+3V RI58 GND GND U2DN2 GND USBGND1 2 2
A13 N3 2 10
@ GND GND U3RXDP2 D- GND CI77
10K_0402_5%~D A14 M13 6 11 1 2 .1U_0402_16V7K~D
GND GND SSRX+ GND
B3 M12 4 12
GND GND GND GND
2
B4 M11 U3RXDN2 5 13
G
GND GND SSRX- GND

1
@ B5 M10
USB3_SMI#_R GND GND SUYIN_020053GR009M2106L
1 3 B7 M9
<16> USB3_SMI# GND GND +USB3_VCCB
B9 M8
D
QI3 GND GND

B11 M7
SSM3K7002FU_SC70-3 B13 GND GND M6 +USB3_VCCB
GND GND
150U_B2_6.3VM_R35M
1 2 B14 M5
GND GND
10U_0603_6.3V6M~D
RI59 0_0402_5%~D C1 M4 JUSB2 CONN@ 1

C2 GND GND M3 U3TXDP1 9
GND GND SSTX+ 1
+
CI30
CI31
C3 L12 1
USB3_XT1 GND GND U3TXDN1 VBUS RI51
C10 L11 8 1 2 0_0603_5%~D
+3V USB3_XT2 GND GND U2DP1 SSTX-
C11 L7 3
+3V GND GND D+ RI52 2 2
L6 7 1 2 0_0603_5%~D
GND U2DN1 GND USBGND2
2 10
D- GND
.1U_0402_16V7K~D
10K_0402_1%~D
U3RXDP1 6 11 CI78 1 2 .1U_0402_16V7K~D

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SSRX+ GND
2
1
47K_0402_5%
4 12
U3RXDN1 GND GND
10K_0402_1%~D
RI44
1 RI20 5 13
SSRX- GND
2
CI75
RI45
100_0402_5%
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4
RI46
SUYIN_020053GR009M2106L
YI1
2
1
1 2 USB3_XT2_R
12P_0402_50V8J~D
12P_0402_50V8J~D
UI8
1
8 1 SPI_CS_USB# 24MHZ_12PF_X5H024000DC1H UPD720200AF1DAPA_FBGA176P-NH~D

7 VCC CS# 2 USB_SI_SPI_SO
NC SO 1 1
Place as close as
CI39
CI40
SPI_CLK_USB 6 3
USB_SO_SPI_SI 5 SCLK WP# 4
SI GND possibile to
2 2 UI5.N14 and UI5.M14
A MX25L5121EMC-20G_SO8 A
Pin compare table for support USB remote wakeup or not
AUXDET(Pin J2) CSEL(Pin P6) CLK
Support USB pull high Tied to GND Must use 24MHz crystal: mount
Security Classification Compal Secret Data Compal
CompalElectronics,
Electronics,Inc.
Inc.
remote wakeup 10k to VDD33 Y1,R19,C40,C41 Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
USB conn.
Not support USB Tied to GND pull high Can use either 48MHz or 24MHz When AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
remote wakeup to VDD33 use 48MHz clock: mount R22,R25 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-6801P 1.0

5 4 3 2 1
A B C D E F G H
<13> SAT A_PT X_DRX_P1_C RS13 2 @ SAT A_PT X_DRX_P1_B

1 0_0402_5%~D RS33 2 @ SAT A_PT X_DRX_P1_RC1
1 0_0402_5%~D +3VS +5VS_HDD2 0.1U_0402_16V7K~D 10U_0805_10V4Z~D
<13> SAT A_PT X_DRX_N1_C RS14 2 @ 1 0_0402_5%~D
SAT A_PT X_DRX_N1_B RS31 2 @ 1 0_0402_5%~D
SAT A_PT X_DRX_N1_RC1
1 1 1 1 1
RS15 2 @ SAT A_PRX_DT X_N1_B
1 0_0402_5%~D RS30 2 @ SAT A_PRX_DT X_N1_RC
1 0_0402_5%~D CS19 CS20 CS21 CS22 CS23
<13> SAT A_PRX_DT X_N1 RS16 @
<13> SAT A_PRX_DT X_P1 2 1 0_0402_5%~D
SAT A_PRX_DT X_P1_B RS32 2 @ 1 0_0402_5%~D
SAT A_PRX_DT X_P1_RC
0.1U_0402_16V7K~D
2 2 2 2 2
1000P_0402_50V7K~D 1U_0402_6.3V6K~D
+3VS
1
@ CS27
0.1U_0402_16V7K~D
2 JHDD
1
1 SAT A_PT X_DRX_P1_RC1
2
2
US2 3 SAT A_PT X_DRX_N1_RC1
3
6 10 4 0.01U_0402_16V7K~D
DNC VDD3P3 4
16 20 5 SAT A_PRX_DT X_N1_RC1 CS26 2 1 SAT A_PRX_DT X_N1_RC
DNC VDD3P3 5 SAT A_PRX_DT X_P1_RC1
6 2 1 SAT A_PRX_DT X_P1_RC
1 6 1
3 13 7 CS28
A_EN# B_EN# 7
RS18 1 2 0_0402_5%~D A2_EQ 17 7 B2_EQ RS19 2 1 0_0402_5%~D 8 0.01U_0402_16V7K~D
A2_EM A_EQ B_EQ B2_EM 8 +3VS_VCC3.3
RS20 1 2 5.1K_0402_1%~D 18 8 RS21 2 1 5.1K_0402_1%~D 9 2 RS17 1 +3VS
RS23 1 A_EM B_EM 9
2 2.7K_0402_5%~D A2_OS 19 9 B2_OS RS24 2 1 2.7K_0402_5%~D 10
A_OS B_OS 10
11 0.022_0805_1%
SAT A_PT X_DRX_P1_C 1 15 SAT A_PT X_DRX_P1_RC CS30 1 2 0.01U_0402_16V7K~DSAT A_PT X_DRX_P1_RC1 11 12 HDD_DET ECT #
AI+ AO+ 12 HDD_DET ECT # <17>
SAT A_PT X_DRX_N1_C 2 14 SAT A_PT X_DRX_N1_RC CS32 1 2 0.01U_0402_16V7K~DSAT A_PT X_DRX_N1_RC1 13
AI- AO- 13 14
14
SAT A_PRX_DT X_N1 CS33 1 2 0.01U_0402_16V7K~D
SAT A_PRX_DT X_N1_C 4 12 SAT A_PRX_DT X_N1_RC 15 +5VS_HDD2 2 RS22 1
BO- BI- 15 +5VS
SAT A_PRX_DT X_P1 CS35 1 SAT A_PRX_DT X_P1_C
2 0.01U_0402_16V7K~D 5 11 SAT A_PRX_DT X_P1_RC 16
BO+ BI+ 16
21 17 0.022_0805_1%
GND1 17
21 22 18 FFS_INT 2_CONN
EP GND2 18
23 19
GND3 19
24 20
GND4 20
PI3EQX6701ZDEX_T QFN20_4X4~D
FOX_GS12201-1011-9F
CONN@
Free Fall Sensor

+3VS
0.1U_0402_16V7K~D
10U_0805_10V4Z~D
1 1
C189
C190
2 2
U19
FFS_INT1 connect to PCH GPIO & EC DE351DLTR
discuss with BIOS to use which pin 1
VDD_IO
6 2
VDD GND
4
FFS_INT 1 8 GND 5
<16> FFS_INT 1 FFS_INT 2 INT 1 GND
<17> FFS_INT 2 9 10
INT 2 GND
12
13 SDO +3VS
2 <6,11,12,14,32> PCH_SM BDAT A SDA / SDI / SDO 2
14
<6,11,12,14,32> PCH_SM BCLK SCL / SPC
3
7 RSVD 11
CS RSVD
DE351DLT R_LGA14_3X5
+3VS +5VS
1
@ R159
100K_0402_5%~D
2
G
FFS_INT 2 3 1 1 2 FFS_INT 2_CONN

S
D24
Q23
SDM 10U45-7_SOD523-2~D
SSM 3K7002FU_SC70-3~D
+3VS
+3VS
3 3
0.01U_0402_16V7K~D
0.1U_0402_16V7K~D
1 1
@ @
CS47
CS48
MAXIM main TI 2nd

1
2 2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
@ @
RS45
RS46
Placea caps. near ODD CONN.

RS43
RS44
@ @
P/N SA00003LH1L SA00003ZX0L +5VS_ODD
US3
2
7 6 HDD_DEW2 +5VS_ODD 0.1U_0402_16V7K~D 10U_0805_10V4Z~D

EN VCC
18
CAD VCC
10
16 HDD_DEW1
RS43 RS44 pop depop 1 1 1 1
SAT A_PT X_DRX_P2_RP VCC CS37 CS38 CS39 CS40
<13> SAT A_PT X_DRX_P2_RP 1 20
SAT A_PT X_DRX_N2_RP 2 AINP VCC
<13> SAT A_PT X_DRX_N2_RP AINM HDD_PE1
CS49 2 @ 0.01U_0402_16V7K~D SAT A_PRX_DT X_N2_RP4
@1 PA
9
8 HDD_PE2 RS47 RS48 depop pop 2 2 2 2
<13> SAT A_PRX_DT X_N2 BOUTM PB
CS50 2 @ 0.01U_0402_16V7K~D SAT A_PRX_DT X_P2_RP5
@1
<13> SAT A_PRX_DT X_P2 BOUTP SAT A_PT X_DRX_P2_P 1000P_0402_50V7K~D 1U_0402_6.3V6K~D
15
AOUTP SAT A_PT X_DRX_N2_P
3
GND AOUTM
14
RS53 RS54 pop depop
10K_0402_5%~D
10K_0402_5%~D
+3VS 13
GND
1
1
0_0402_5%~D
0_0402_5%~D
HDD_EQ1 17 11 SAT A_PRX_DT X_P2_P @ @ @ @

GND BINP SAT A_PRX_DT X_N2_P
RS47
RS48
RS49
RS50
19 12
GND BINM
HDD_EQ2 21
EP
10K_0402_5%~D
10K_0402_5%~D
1
@ @ M AX4951BECT P+T GH7_T QFN20_4X4~D

2
@
RS51
RS52
2
SATA ODD Conn.

1
1
0_0402_5%~D
0_0402_5%~D
SAT A_PT X_DRX_P2_RP RS35 2 1 0_0402_5%~D SAT A_PT X_DRX_P2_BRS36 2 1 0_0402_5%~D SAT A_PT X_DRX_P2_C JODD1
RS53
RS54
@ @ SAT A_PT X_DRX_N2_RP RS37 2 1 0_0402_5%~D SAT A_PT X_DRX_N2_BRS38 2 1 0_0402_5%~D SAT A_PT X_DRX_N2_C
@ 27 28
SAT A_PRX_DT X_N2 RS39 27 28
2 1 0_0402_5%~D SAT A_PRX_DT X_N2_BRS40 2 1 0_0402_5%~D SAT A_PRX_DT X_N2_P SAT A_PT X_DRX_P2_P CS51 2 1 0.01U_0402_16V7K~DSAT A_PT X_DRX_P2_C 25 26
25 26
2
SAT A_PRX_DT X_P2 RS41 2 1 0_0402_5%~D SAT A_PRX_DT X_P2_BRS42 2 1 0_0402_5%~D SAT A_PRX_DT X_P2_P SAT A_PT X_DRX_N2_P CS52 2 @ 1 0.01U_0402_16V7K~DSAT A_PT X_DRX_N2_C 23 24
21 23 24 22
21 22
SAT A_PRX_DT X_N2_P CS44 1 2 0.01U_0402_16V7K~DSAT A_PRX_DT X_N2_C 19 20
SAT A_PRX_DT X_P2_P CS45 1 2 0.01U_0402_16V7K~DSAT A_PRX_DT X_P2_C 17 19 20 18
17 18
15 16
13 15 16 14
ODD_DET ECT #_R 13 14
+5VS RS28
1 2 0_0402_5%~D 11 12
QS1 +5VS_ODD <17> ODD_DET ECT # 11 12
+5VS_ODD 9 10
9 10
RS34 RS25 7 8
7 8
D
6 @ 1 2 0_0402_5%~D ODD_DA#_R 5 6
<16> ODD_DA#
S
1 2 5 4 +5VS_ODD_R 1 2 RS29 3 5 6 4
+5VS +5VS_ODD 1
4 CS41 2 1 3 4 2 4
1 2
0_1206_5%~D 1U_0402_6.3V6K~D 1 0_1206_5%~D
SI3456BDV-T 1-E3 1N T SOP6 E-T _6900-Q14N-00R
G
SW4 2 CONN@
3
SM T 1-05-A_4P B+_BIAS
1 3 ODD_DA#_R
2
2 4
RS26
470K_0402_5%~D
6
5
@
1
ODD_EN
1
D
Reserve for test 1
1.5M_0402_5%~D
0.1U_0402_25V6
2 QS2
Zero Power ODD <17> ODD_EN#
G
S
SSM 3K7002FU_SC70-3 RS27 CS46
Security Clas s ification Compal Secret Data Compal Electronics, Inc.
3
2
1
FFS /HDD/ ODD Connector
Size Docum ent Num ber Rev
LA-6801P 1.0
Date: T uesday, January 25, 2011 Sheet 28 of 61

A B C D E F G H
A B C D E
ON/OFF switch Power Button

+3VALW KSO16 C1918 1 2 100P_0402_50V8J~D KB_DET# C434 1 2 100P_0402_50V8J~D
KSO15 C306 1 2 100P_0402_50V8J~D KSO7 C310 1 2 100P_0402_50V8J~D
2
R263
TOP Side 100K_0402_5%~D
KSO12 C308 1 100P_0402_50V8J~D KSO4 C309 1 100P_0402_50V8J~D
2 2
1
1 SW6 D27 1
SMT1-05-A_4P 2
ON/OFFBTN# ON/OFF <31> KSI0 KSO3
1 3 1 C328 1 2 100P_0402_50V8J~D C311 1 2 100P_0402_50V8J~D
3 51ON# <50>
3
2 4 1 KSO11 C327 1 2 100P_0402_50V8J~D KSI4 C313 1 2 100P_0402_50V8J~D
D28 DAN202UT106_SC70-3
@ C326 KSO10 C314 1 2 100P_0402_50V8J~D KSO2 C315 1 2 100P_0402_50V8J~D
6
5
0.1U_0402_25V6 PESD24VS2UT_SOT23-3~D
2 KSI1 C316 1 2 100P_0402_50V8J~D KSO1 C317 1 2 100P_0402_50V8J~D
1
KSI2 C318 1 2 100P_0402_50V8J~D KSO0 C319 1 2 100P_0402_50V8J~D
KSO9 C320 1 2 100P_0402_50V8J~D KSI5 C321 1 2 100P_0402_50V8J~D

Bottom Side
ON/OFFBTN# <35>
KSI3 C322 1 2 100P_0402_50V8J~D KSI6 C323 1 2 100P_0402_50V8J~D
SW5
SMT1-05-A_4P KSO8 C324 1 2 100P_0402_50V8J~D KSI7 C325 1 2 100P_0402_50V8J~D
1 3
D
1
2 4 EC_ON 2 Q24
<31,52> EC_ON
G
2
S SSM3K7002F_SC59-3
6
5
3
@ R264
10K_0402_5%~D
1
Test Only
INT_KBD Conn.
2 2
KSI[0..7]
KSI[0..7] <31>
KSO[0..16]
KSO[0..16] <31>
CONN@
TYCO_3-2041084-0
FD1 FD2 FD3 FD4
KB_DET# 30 32
<14> KB_DET# 30 GND
KSO10
@ @ @ @
KB detect pin KSO11
29
28
29 GND
31
28
1
KSO9 27
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 KSO14 27
26
KSO13 26
25
KSO15 25
24
H63 H64 KSO16 24
23
H_1P9N H_3P9x1P9N KSO12 23
22
KSO0 22
21
KSO2 21
20
@ @ CLIP1 KSO1 20
19
19
1
EMI_CLIP @ KSO3 18
KSO8 18
17
H39 H40 H58 H59 H60 H61 KSO6 17
1 16
H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 GND KSO7 16
15
KSO4 15
14
KSO5 14
13
3 @ @ @ @ @ @ KSI0 13 3
12
12
1
KSI3 11
CLIP2 KSI1 11
10
EMI_CLIP @ KSI5 10
9
KSI2 9
8
H32 H33 H34 H35 H36 H37 H38 KSI4 8
1 7
H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 GND KSI6 7
6
KSI7 6
5
5
4
@ @ @ @ @ @ @ 4
3
3
1
2
CLIP3 2
1
EMI_CLIP @ 1
JKB
H42 H43 H45 H47 1
H_2P7 H_2P7 H_2P7 H_2P7 GND
@ @ @ @
1
H51
H_2P7
@ ZZZ1 ZZZ
1
4 4
H46 H48 H49 H50 H44 H41

H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 PCB-MB PCBA-DMC/B
45@
Compal Electronics, Inc.
@ @ @ @ @ @
Security Classification Compal Secret Data
1
PWRBTN/SCREWH/KB
LA-6801P
1.0
A B C D E
5 4 3 2 1
System Thermal Sensor 1 +5VS

+3VS
2
D
R2018 D

!"#
0.1U_0402_10V7K~D
0_0805_5%~D
+3VS
1
1
2.2U_0603_6.3V6K~D
SENSOR_DIODE_P1 R1796 1 2 0_0402_5%~D REMOTE_P1 +5VS_FAN 2 1
C1816
U615
1
2
1
2
C C1815 EC_SMB_CK2 C1923
10K_0402_5%~D
10K_0402_5%~D
1 1 8 EC_SMB_CK2 <31,45,58>
VDD SMCLK
2
2 470P_0402_50V7K R1802
@ C1814 B 2 7 EC_SMB_DA2 10K_0402_5%~D
2 DP SMDATA EC_SMB_DA2 <31,45,58>
100P_0402_50V8J~D E Q283
R1800
R1801
2
3
MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N1 R1797 1 2 0_0402_5%~D REMOTE_N1 3 6

DN ALERT
1
JFAN1
1
+3VS 1 2 4 5 1
THERM#/ADDR GND SYSTEM_FAN_PWM 1
<31> SYSTEM_FAN_PWM 2
R1798 4.7K_0402_1%~D SYSTEM_FAN_FB 2
EMC1412-A-ACZL-TR_MSOP8 <31> SYSTEM_FAN_FB 2 1 3 5
D65 3 G5
4 6
CH751H-40PT_SOD323-2~D 4 G6
1 3 MOLEX_53398-0471
S
<52,59> MAINPWON
@ Q303 CONN@
SSM3K7002FU_SC70-3~D
G
2
+3VS
C
System Thermal Sensor 2 C

$%% +3VS
0.1U_0402_10V7K~D
&
!"&'
1
SENSOR_DIODE_P2 R1851 1 2 0_0402_5%~D REMOTE_P2
C1872
U627
1 2
1
1 C C1873 1 8 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <31,45,58>
2 470P_0402_50V7K
@ C1871 B 2 7 EC_SMB_DA2
2 DP SMDATA EC_SMB_DA2 <31,45,58>
100P_0402_50V8J~D E Q279
2
3
MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N2 R1853 1 2 0_0402_5%~D REMOTE_N2 3 6

DN ALERT
+3VS 1 2 4 5
THERM#/ADDR GND
R1856 6.8K_0402_1%~D EMC1412-A-ACZL-TR_MSOP8
1 3
D
S
<52,59> MAINPWON
@ Q304
G
2
+3VS
B B
A A

FAN Controller
LA-6801P
5 4 3 2 1
5 4 3 2 1
+3VALW L43
FBMA-L11-160808-800LMT_0603 KSI[0..7]
KSI[0..7] <29>
R216
1 2
1
0.1U_0402_16V7K~D 0.1U_0402_16V7K~D
1 1 1 2 2
+3VALW_EC 1 2 +EC_VCCA
KSO[0..16]
KSO[0..16] <29>
Board ID
+3VS 0_0805_5%~D C277 C276 C278 C279 C280 C281 1 +3VALW
1 2 BKOFF# 1000P_0402_50V7K~D C282

2 2 2 2 1 1
2
R217 10K_0402_5%~D
1 2 EC_SCI# 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 1000P_0402_50V7K~D 2 0.1U_0402_16V7K~D R219
ECAGND
R218 10K_0402_5%~D Ra 100K_0402_5%~D
D 1 2 M_THERMAL# D
R1943 10K_0402_5%~D
1
AD_BID0
111
125
22
33
96
67
U34
2
1
C283
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
Rb R225
56K_0402_5%
2
1
GATEA20 1 21 0.1U_0402_16V7K~D
<17> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
<17> KB_RST# 2 23 BEEP# <24>
SERIRQ 3 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 26 SYSTEM_FAN_PWM
<13> SERIRQ SERIRQ# FANPWM1/GPIO12 SYSTEM_FAN_PWM <30>
LPC_FRAME# 4 27 ACOFF Analog Board ID definition,
<13> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <50,51>
C284 LPC_AD3 5 2 1 ECAGND
@ 22P_0402_50V8J~D
<13> LPC_AD3
LPC_AD2 7 LAD3
PWM Output C286 100P_0402_50V8J~D Please see page 4.
<13> LPC_AD2 LAD2
2 1 R226 2 1 @ 33_0402_5% <13> LPC_AD1 8 63 BATT_TEMP
LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <59>
LAD0 LPC & MISC
LPC_AD0 10 64 PM_SLP_SUS# +5VS
<13> LPC_AD0 BATT_OVP/AD1/GPIO39 PM_SLP_SUS# <15>
65 ADP_I
ADP_I/AD2/GPIO3A ADP_I <50,51>
CLK_PCI_LPC 12 AD Input 66 AD_BID0
<16> CLK_PCI_LPC PCICLK AD3/GPIO3B
PLT_RST# 13 75 TP_CLK 2 1
<6,16,22,23,27,32> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
R221 2 1 47K_0402_5% EC_RST# 37 76 IMON 4.7K_0402_5%~D R223
+3VALW ECRST# SELIO2#/AD5/GPIO43 IMON <57>
EC_SCI# 20 TP_DATA 2 1
<17> EC_SCI# SCI#/GPIO0E
C285 2 1 0.1U_0402_16V7K~D EN_CAM 38 4.7K_0402_5%~D R224
<21> EN_CAM CLKRUN#/GPIO1D
68
DAC_BRIG/DA0/GPIO3C AC_SEL
70 AC_SEL <50>
EN_DFAN1/DA1/GPIO3D IREF
DA Output IREF/DA2/GPIO3E
71 IREF <51>
KSI0 55 72 CHGVADJ SPK_MUTE# EC_CRY1 EC_CRY2
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <51> SPK_MUTE# <25>
KSI1 56
KSI1/GPIO31
1
KSI2 D @
57 1 1
KSI3 KSI2/GPIO32 EC_MUTE_R R228 2 EC_MUTE SSM3K7002F_SC59-3
58 83 1 0_0402_5%~D 2 C287 C288
KSI3/GPIO33 PSCLK1/GPIO4A
4
KSI4 59 84 PWRSHARE_EN_EC# G Q21
KSI4/GPIO34 PSDAT1/GPIO4B PWRSHARE_EN_EC# <26>
KSI5 60 85 AC_PRESENT S 27P_0402_50V8J~D 27P_0402_50V8J~D
AC_PRESENT <15>
OSC
OSC
KSI5/GPIO35 PSCLK2/GPIO4C 2 2
3
+3VALW KSI6 H_PROCHOT#_EC
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 @
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <35>
1 2 EC_SMB_CK1 KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <35>
R229 2.2K_0402_5%~D KSO1 40
NC
NC
EC_SMB_DA1 KSO2 KSO1/GPIO21
1 2 41
R230 2.2K_0402_5%~D KSO3 42 KSO2/GPIO22 97 VGATE @
KSO3/GPIO23 SDICS#/GPXOA00 VGATE <6,15,57>
3
C KSO4 43 98 EN_WOL# C
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <22>
KSO1 KSO5 HDA_SDO
KSO5/GPIO25 Int. K/B
1 2 44 99 X1
SDIDO/GPXOA02 HDA_SDO <13>
R231 47K_0402_5% KSO6 45 109 LID_SW_IN# 32.768KHZ_12.5PF_Q13MC14610002
KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW_IN# <14,34,35>
1 2 KSO2 KSO7 46 SPI Device Interface
R232 47K_0402_5% KSO8 KSO7/GPIO27
47
KSO9 KSO8/GPIO28 FRD# EC_MUTE
10/1 ENE Recommand 48 119 1 2
KSO10 KSO9/GPIO29 SPIDI/RD# R234 33_0402_5% FWR#
49 120 1 2
KSO11 KSO10/GPIO2A SPIDO/WR# R_SPI_CLK R236
50 SPI Flash ROM 126 1 2 33_0402_5% SPI_CLK R233 10K_0402_5%~D
KSO12 KSO11/GPIO2B SPICLK/GPIO58 R237 33_0402_5% FSEL#
51 128 1 2
EC_MUTE KSO13 KSO12/GPIO2C SPICS#
1 @ 2 52
R238 10K_0402_5%~D KSO14 KSO13/GPIO2D
53
KSO14/GPIO2E
1 @ 2 EC_SMI# KSO15 54 73 PCH_VREG_EN#
KSO15/GPIO2F CIR_RX/GPIO40 PCH_VREG_EN# <19>
R239 1K_0402_1%~D KSO16 81 74 EC_PECI 1 2
KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI <6,17>
1 @ 2 SPK_MUTE# <15> PCH_DPWROK
PCH_DPWROK 82 89 FSTCHG
FSTCHG <51>
R240 43_0402_1%
R241 10K_0402_5%~D KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED#
90
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# <34>
1 2 EC_ESB_CLK 91 CAPS_LED#
CAPS_LED# <35>
Please place R240 close
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED#
R242 4.7K_0402_5%~D
<59> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 BATT_LOW_LED# <34>
to EC with in 750mil CH100
1 2 EC_ESB_DAT <59> EC_SMB_DA1
EC_SMB_DA1 78 93 EN_INVPWR
EN_INVPWR <21>
R_SPI_CLK 2 1
SDA1/GPIO45 SUSP_LED#/GPIO55
R243 4.7K_0402_5%~D EC_SMB_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95 SYSON
SYSON <27,33,53>
@
1 2 LID_SW_IN# <14,51> PCH_SMLCLK 1 R245 2 0_0402_5%~D EC_SMB_DA2 80 121 VR_ON
VR_ON <57>
10P_0402_50V8J~D
R1952 10K_0402_5%~D SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
<14,51> PCH_SMLDATA 1 R246 2 0_0402_5%~D 127 ACIN <34,51>
CH101
AC_IN/GPIO59
1 @ 2 PCIE_WAKE#_R 2 1 EC_ESB_CLK_R 2 1
R2019 10K_0402_5%~D C550 100P_0402_50V8J~D @
<15,34> PM_SLP_S3# 1 R249 2 0_0402_5%~D PM_SLP_S3#_R 6 100 PCH_RSMRST#
PCH_RSMRST# <15>
10P_0402_50V8J~D
1 R250 2 0_0402_5%~D PM_SLP_S5#_R 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 101 EC_LID_OUT#
<15,34> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <14>
EC_SMI# 15 102 EC_ON
<17>EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <29,52>
PS_ID 16 103
<50> PS_ID LID_SW#/GPIO0A EC test PSID EC_SWI#/GPXO06
EC_ESB_CLK R252 1 2 0_0402_5%~D EC_ESB_CLK_R 17 104 PCH_PWROK Reserve for RF please close to U34
SUSP#/GPIO0B ICH_PWROK/GPXO06 PCH_PWROK <6,15>
EC_ESB_DAT 18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF#
BKOFF# <21>
SUSWARN# 19 GPIO 106 CPU1.5V_S3_GATE
<15> SUSWARN# EC_PME#/GPIO0D WL_OFF#/GPXO09 CPU1.5V_S3_GATE <10>
25 107 PCH_APWROK
+3VS <21> EC_INV_PWM EC_THERM#/GPIO11 GPXO10 PCH_APWROK <15>
SYSTEM_FAN_FB 28 108 SA_PGOOD
<30> SYSTEM_FAN_FB FAN_SPEED1/FANFB1/GPIO14 GPXO11 SA_PGOOD <55>
PCH_PWR_EN 29
<33> PCH_PWR_EN FANFB2/GPIO15
EC_TX 30
<32> EC_TX EC_TX/GPIO16
1 2 EC_SMB_CK2 EC_RX 31 110 PM_SLP_S4#
EC_SMB_CK2 <30,45,58> <32> EC_RX EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# <15>
R244 2.2K_0402_5%~D ON/OFF 32 112 ENBKL
<29> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <15>
1 2 EC_SMB_DA2 SUSACK# 34 114 EC_EAPD#
EC_SMB_DA2 <30,45,58> <15> SUSACK# PWR_LED#/GPIO19 GPXID3 EC_EAPD# <24>
R247 2.2K_0402_5%~D USB_PWR_EN# 36 GPI 115 M_THERMAL#
B <27> USB_PWR_EN# NUMLED#/GPIO1A GPXID4 B
116 SUSP#
GPXID5 SUSP# <10,18,33,53,54>
117 PBTN_OUT#
GPXID6 PBTN_OUT# <6,15>
118 PCIE_WAKE#_R 1 2
GPXID7 PCIE_WAKE# <15,22,32>
EC_CRY1 122 R1944 0_0402_5%~D
EC_CRY2 XCLK1 +V18R
<15> SUSCLK_R 1 2 123 124 1 2 USB_PCIE_WAKE# <27>
R253 0_0402_5%~D XCLK0 V18R R2020 0_0402_5%~D
1
AGND
C293
GND
GND
GND
GND
GND
2
1 U620
R1979 4.7U_0805_10V4Z~D EC_ESB_CLK 1 13
+3VS C1947 KB930QF A1 LQFP 128P 2 ESB_CLK TEST_EN#
11
24
35
94
113
69
100K_0402_5%~D 20P_0402_50V8J~D 20mil 2 14

2 <51> CP_SEL GPIO00 GPIO08/CAS_DAT EC_ENVDD <21>
L44
<50,57> VR_HOT#
1
ECAGND 2 1 RST# 3 15
FBMA-L11-160808-800LMT_0603 RST# GPIO09
1
EC_ESB_DAT 4 16
ESB_DAT GPIO0A
2
C1943
R265 0.1U_0402_16V7K~D 5 17 PWRSHARE_OE#
2 <57> CPU_SEL GPIO01 GPIO0B PWRSHARE_OE# <26>
0_0402_5%~D
<51> EMC_ALERT# 6 18
GPIO02 GPIO0C/PWM0 WLES ON/OFF LED# <35>
1
U635 7 19
GPIO03 GPIO0D/PWM1
P
<6> H_PROCHOT# H_PROCHOT# 4 2 H_PROCHOT#_EC Dyn_Turbo_Sel 8 20

Y A <50> Dyn_Turbo_Sel GPIO04 GPIO0E/PWM2
NC
<7> DRAMRST_CNTRL_EC 9 21 EN_TPLED# <35>

GPIO05 GPIO0F/PWM3
2
SN74LVC1G06DCKR_SC70-5
1
1 R1999 10 22
GPIO06 GPIO10/ESB_RUN# LCD_TEST <21>
C1944 100K_0402_5%~D
47P_0402_50V <15,21> VGA_LVDDEN 11 23
+3VALW GPIO07/CAS_CLK GPIO11/BaseAddOpt 3V_F347_ON <34>
2
60 mil
1
12 24 +3VALW
GND
GND VCC
1
SP07000F500 S SOCKET WIESON G6179-100000 8P

SPI ROM 256KB
0.1U_0402_16V7K~D
R248 1
SPIFLASH
47K_0402_5% KC3810_QFN24_4X4 C294
WIESO_G6179-100000_8P
25
+3VALW
2
2
U36 RST#
A 20mils 8 4 2 A
VCC VSS @ @
1
C297 3 R257 C296 C292
0.1U_0402_16V7K~D W SPI_CLK_R 2 1 1 2 0.1U_0402_16V7K~D
7 33_0402_5% 22P_0402_50V8J~D 1
2 HOLD
FSEL# 1 2 SPI_FSEL# 1 Reserve for EMI please close to U36
R258 0_0402_5%~D S
SPI_CLK 1 2 SPI_CLK_R 6
R259 0_0402_5%~D C
FWR#
R260
1 2 SPI_FWR#
0_0402_5%~D
5
D Q
2 SPI_SO
R261
1 2 FRD#
0_0402_5%~D
MX25L1005AMC-12G SOP 8P Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
EC ENE-KB930/ ENE3810
LA-6801P 1.0

5 4 3 2 1
A B C D E
BlueTooth
+3VS +3VS
@ 1
CU1 CU2
0.1U_0402_16V7K~D
1U_0603_10V4Z
2
3
S
G
BT_ON# 1 2 2
1 <17> BT_ON# QU1 1
RU1 10K_0402_5%~D
D AO3419L_SOT23-3
1
CU3 W=40mils
0.1U_0402_16V7K~D +3VS_BT
1
1
CU4 CU5 RU2
300_0603_5%
4.7U_0805_10V4Z~D
2
2
0.1U_0402_16V7K~D
1
D
2 QU2
G SSM3K7002F_SC59-3
S
3
To DMC PCB connector +3VS_BT
C191
1 2
0.1U_0402_16V7K~D
JBT
1
2 2 1 2
<14> BT_DET# 2
COEX1 3
JWDB1 3
4
4
82 81 5
G2 G1 5
6
BT_RADIO_DIS# 6
<17> BT_RADIO_DIS# 7
PCIE_WAKE# PLT_RST# COEX2 7
<15,22,31> PCIE_WAKE# 80 79 PLT_RST# <6,16,22,23,27,31> 8
COEX2 Reserved Reserved 8
78 77 PCH_SMBCLK <6,11,12,14,28> 9
COEX1 Reserved Reserved 9
76 75 PCH_SMBDATA <6,11,12,14,28> <16> USB20_N8 10
WL_OFF# Reserved Reserved 10
<16> WL_OFF# 74 73 <16> USB20_P8 11 13
Reserved Reserved 11 G1
<14> MINI1CLK_REQ# 72 71 USB20_N4 <16> 12 14
VPP_Test SDIO_GPIO2_BLT 12 G2
70 69
SDIO_PWR#_BLT SDIO_GPIO1_BLT USB20_P4 <16>
68 67 LOTES_YBA-WTB-015-K01~D
<14> CLK_PCIE_MINI1# SDIO_RST#_BLT SDIO_D3_BLT
66 65 DMC_RADIO_OFF#
<14> CLK_PCIE_MINI1 SDIO_CMD_BLT SDIO_D2_BLT DMC_RADIO_OFF# <16>
64 63 +UICC_PWR
VSS SDIO_D1_BLT CONN@
<14> PCIE_PRX_WLANTX_N1 62 61
SDIO_CLK_BLT SDIO_D0_BLT UICC_VPP
100P_0402_50V8J~D
<14> PCIE_PRX_WLANTX_P1 60 59
VSS VSS
33P_0402_50V8J~D
10K_0402_5%~D
58 57
Ser_TX BLT_USB3_HOST+
@ C193
56 55 UICC_RESET 1 1
<14> PCIE_PTX_WLANRX_N1 Ser_RX BLT_USB3_HOST-
C192
R167
<14> PCIE_PTX_WLANRX_P1 54 53
VSS VSS UICC_DATA
52 51
BLT_USB2_BioMetric+ BLT_USB1_WWAN_Data+
50 49
BT_RADIO_DIS# BLT_USB2_BioMetric- BLT_USB1_WWAN_Data- UICC_CLK 2 2
48 47
VSS VSS
2
<31> EC_TX 46 45
44 VSS VSS 43
<31> EC_RX VDD 3.3v VDD 3.3v USB20_N5 <16>
<37> DMC_DET# DMC_DET# 42 41
VDD 3.3v VDD 3.3v USB20_P5 <16>
40 39 DP_DMC_HPD
VDD 3.3v VDD 3.3v DP_DMC_HPD <37>
DMC_DAT_AUXN_CONN 38 37
<37> DMC_DAT_AUXN_CONN VDD 3.3v VDD 3.3v
DMC_CLK_AUXP_CONN 36 35 DP_DMC_ML3N_RCC
<37> DMC_CLK_AUXP_CONN VSS VSS DP_DMC_ML3N_RCC <37>
34 33 DP_DMC_ML3P_RCC
VSS VSS DP_DMC_ML3P_RCC <37>
DP_DMC_ML2N_RCC 32 31
<37> DP_DMC_ML2N_RCC M_Clk VSS
DP_DMC_ML2P_RCC 30 29 DP_DMC_ML1N_RCC
<37> DP_DMC_ML2P_RCC VSS BLT_USB_Port1_Dir DP_DMC_ML1N_RCC <37>
DP_DMC_ML0N_RCC
28
26
I2S_BCLK RST_BLT#
27
25
DP_DMC_ML1P_RCC
DP_DMC_ML1P_RCC <37> SIM card board 4.7uF change to 1uF
<37> DP_DMC_ML0N_RCC I2S_DOUT SMBALERT_1
<37> DP_DMC_ML0P_RCC
DP_DMC_ML0P_RCC 24
I2S_DIN SMBDATA_1
23
PCIE_PTX_WANRX_P2 <14>
for Tiger detect issue.
22 21
I2S_LRC SMBCLK_1 PCIE_PTX_WANRX_N2 <14>
<14> MINI2CLK_REQ# 20 19
18 VSS VSS 17
3 NC NC PCIE_PRX_WANTX_P2 <14> +UICC_PWR +UICC_PWR +UICC_PWR 3
16
14
12
BLT_LED_1#
VSS
NC
NC
VSS
eDP_CH1_p
15
13
11
PCIE_PRX_WANTX_N2
CLK_PCIE_MINI2# <14>
<14>
SIM Connector
1
+3VS 10 9
NC eDP_CH1_n CLK_PCIE_MINI2 <14>
8 7 R88 @ R95
VSS VSS 10K_0402_5%~D 10K_0402_5%~D
6 5
LID_Cl# Radio_disable# @ JSIM1 CONN@
4 3
BLT_Sus# PAID_IN
1 2 1 +1.5VS 1 5
VSS VSS VCC GND
2
1 UICC_RESET 2 6 UICC_VPP
C1946 + @ C1924 HRS_DF12(3.0)-80DP-0.5V86 UICC_CLK RST VPP UICC_DATA
1 3 7
47P_0402_50V CONN@ @ C1925 CLK I/O
4 8
330U_D2E_6.3VM_R25~D 47P_0402_50V NC NC
9
2 2 GND
10
2 GND
Reserve for RF please MOLEX_475531001~D
close to JWDB1
Reserve for RF please 1 1 1
close to JWDB1
C428 @ C429 C430
1U_0402_6.3V6K~D 4.7U_0603_6.3V6K~D 0.1U_0402_16V7K~D
2 2 2
U41
Reserve for SIM card does not meet 3 4 UICC_RESET
UICC_VPP V I/O V I/O
rise time and pull-up is needed. 2 5
Ground V BUS +UICC_PWR
1
UICC_CLK 1 6 UICC_DATA C431
V I/O V I/O
IP4223CZ6_SO6~D 0.1U_0402_16V7K~D
2
4
For ESD 4

Mini Card -WLAN / DMC / BT
LA-6801P 1.0

A B C D E
A B C D E
+5VALW to +5VS
+5VALW
+5VALW +5VS
Q26
2
SI4800BDY-T1-E3_SO8
8 1 R1934
7 2 100K_0402_5%~D
2
10U_0805_10V4Z~D
1U_0603_10V4Z
1 1 6 3 1 1
5 C337 C338
1
C335 C336 R267
10U_0805_10V4Z~D 10U_0805_10V4Z~D 470_0603_5%
2 2 2 2
4
DGPU_PWR_EN#
1
1 2
+5VS_D
<10,18,31,53,54> SUSP#
D22
1 1
1
R271 SDMK0340L-7-F_SOD323-2~D D
6
B+_BIAS 1 2 <16,43,55,56> DGPU_PWR_EN
2
0.1U_0603_50V_X7R
R270 G
102K_0402_1% 0_0402_5%~D 1 Q285A Q294 S
3
3
@ 2 SUSP SSM3K7002F_SC59-3
C340
R273 R1938
Q285B 0_0402_5%~D DMN66D0LDW-7_SOT363-6~D 100K_0402_5%~D @
2
1
SUSP 5
2
DMN66D0LDW-7_SOT363-6~D
4
+3VALW to +3V_PCH
+3VALW to +3VS +3VALW
JP3 @
+3VALW +3VS 1 2
Q27 1 2 +5VALW
SI4800BDY-T1-E3_SO8 JUMP_43X79
8 1 +3V_PCH +1.5VSDGPU +1.05VSDGPU
7 2 Q41
1 1 6 3 1 1 SI4800BDY-T1-E3_SO8 40mil
1
5 8 1
C345 C346 C347 C348 7 2 R1939 R1940
10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 1U_0603_10V4Z 1 1 6 3 1 1 R288
2 2 2 2
4
5 470_0402_5% 470_0402_5% 100K_0402_5%~D

C349 C350 C351 C352
2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 1U_0603_10V4Z SUSP
2 2 2 2
1
R276 D
3
B+_BIAS 1 2 2 Q33
<10,18,31,53,54> SUSP#
0.1U_0603_50V_X7R
2 R279 Q296A Q296B G SSM3K7002F_SC59-3 2
0.1U_0603_50V_X7R
102K_0402_1% 0_0402_5%~D 1 R277 S
3
1
1
@ 1 2 DGPU_PWR_EN# 2 DGPU_PWR_EN# 5 1
B+_BIAS
SUSP
C354
0.1U_0603_50V_X7R
2 Q30 R281 R280 R291 @
C360
G SSM3K7002F_SC59-3 0_0402_5%~D 102K_0402_1% 0_0402_5%~D 1 100K_0402_5%~D
2
4
1
D @
S
2
3
PCH_PWR_EN#
C355
2 Q31 R282
2
G SSM3K7002F_SC59-3 0_0402_5%~D
S 2
3
+1.5V To +1.5VS
B+_BIAS U20
+1.5V +1.5VS
SI4634DY-T1-E3_SO8~D
1
8 1
10U_0805_10V4Z~D
0.1U_0402_16V7K~D
R283 7 2
100K_0402_5%~D 6 3 1 1
C356
C357
5
@
2
+1.05V to +1.05VSDGPU Transfer

R284
2 2
4
1 2
10K_0402_5%~D
1
D +3VALW +5VALW
0.1U_0603_50V_X7R
1 @
SUSP 2 R285
+1.05VS
C358
G Q40 0_0402_5%~D U632 +1.05VSDGPU

S SSM3K7002FU_SC70-3 B+_BIAS
2
3
SI4634DY-T1-E3_SO8~D 8A
1
10U_0805_10V4Z~D
8 1
1
C1919
1 7 2 R286
0.1U_0402_16V7K~D
C1920
10U_0805_10V4Z~D
C1921
R1945 6 3 10K_0402_5%~D R287
5 1 1 100K_0402_5%~D
3
330K_0402_5% 3
2
2
PCH_PWR_EN#
<19> PCH_PWR_EN#
2
2 2
1
R1946 D
1 2 2 Q32
<31> PCH_PWR_EN
470_0402_5% 1 G SSM3K7002F_SC59-3
0.1U_0603_50V_X7R
S
1
3
R1947 C1922 @ 1
1
D 0.1U_0402_25V6 R290 @
2
2M_0402_5%~D
DGPU_PWR_EN#
C359
2 100K_0402_5%~D
G Q297
S PMF3800SN_SC70-3 2
3
2
+1.5V_CPU_VDDQ +0.75VS
1
1
R292 R293 +5VALW
220_0402_5%~D 22_0603_5%~D
2
2
+1.5V_CPU_VDDQ_CHG
1
+DDR_CHG
+3V R295
100K_0402_5%~D
2
SYSON#
1
1
D
+1.5VS +VCCP +3V_PCH +3VS R294 2 Q35
<27,31,53> SYSON
1
D
1
D
0.1U_0603_50V_X7R
+1.5V G SSM3K7002F_SC59-3
Q37
Q38
470_0402_5% 2 2 1 S
<6,10> RUN_ON_CPU1.5VS3#
1
3
G G @
2
C361
R296 R297 R298 R299 R300
+3V_USB
S S
3
1
100K_0402_5%~D
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% R289 2
2
2
4 470_0402_5% 4
1
D
2
SYSON# 2
+1.5VS_D
+VCCP_D
+1.5V_D
Q36
+3V_D
+3VS_D
G
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
S SSM3K7002FU_SC70-3
3
6
D
Q4A Q4B Q5A Q5B SYSON# 2
G Q34
SUSP 2 SUSP 5 PCH_PWR_EN# 2 SUSP 5 S SSM3K7002FU_SC70-3 Security Classification Compal Secret Data Compal Electronics, Inc.
3

1
DC/DC Interface
LA-6801P 1.0

A B C D E
5 4 3 2 1
+3.3V_F347 +3.3V_F347
R1569 1 2 0_0603_5%~D +3.3V_F347_VDD
1 1 1 2
C1705 C1706 C1707
1
C1708
1U_0805_10V7 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 22P_0402_50V8J~D R1570 R1571
2 2 2 1 4.7K_0402_1%~D 4.7K_0402_1%~D
2
U602
6 2 SPI_MOCLK
VDD P0.0 SPI_MOSO
1
R1572 USB20_P6 P0.1 SPI_MOSI
4 32
<16> USB20_P6 D+ P0.2
@ 0_0603_5%~D USB20_N6 5 31 SPI_MOCS#
D <16> USB20_N6 D- P0.3 D
1 2 30 I2C_DAT +3.3V_F347
+5VALW P0.4 I2C_DAT <35,36>
W=40mils 7 29 I2C_CLK
+3.3V_F347 REGIN P0.5 I2C_CLK <35,36>
+5VS 1 2 +5VALW_VBUS 8 28 C1710 @ 1 2 0.1U_0402_16V7K~D
VBUS P0.6 R1576 2
27 1
R1575 P0.7
+3.3V_F347 1 2 9
0_0603_5%~D RST#/C2CK SLP_S3 1K_0402_5%~D
10 26
R1577 P3.0/C2D P1.0 25 CHRG_STATE
1 1 P1.1
C1711 C1712 1K_0402_1%~D 18 24 ACIN#
17 P2.0 P1.2 23 LID_SW_IN#
P2.1 P1.3 LID_SW_IN# <14,31,35>
1U_0805_10V7 0.1U_0402_16V7K~D 16 22 BATT_LOW_LED
2 2 15 P2.2 P1.4 21 SLP_S5
P2.3 P1.5 C1713 @ 1 0.1U_0402_16V7K~D
14 20 2
P2.4 P1.6 C1714 @ 1 0.1U_0402_16V7K~D
13 19 2
12 P2.5 P1.7
11 P2.6 3
P2.7 GND
C8051F347-GQ_LQFP32_7X7
0.1U_0402_16V7K~D
C1715
0.1U_0402_16V7K~D
C1716
0.1U_0402_16V7K~D
C1717
0.1U_0402_16V7K~D
C1718
1 1 1 1
+3.3V_F347
@ @ @ @
JP1 2 2 2 2
1
1
2
2
5 3
G1 3
0.1U_0402_16V7K~D
C1719
0.1U_0402_16V7K~D
C1720
0.1U_0402_16V7K~D
C1721
0.1U_0402_16V7K~D
C1722
6 4 1 1 1 1 +3.3V_F347 +3.3V_F347 +3.3V_F347
G2 4
MOLEX_53398-0471~D
1
CONN@ @ @ @ @ 1
2 2 2 2 R1580 C1723
1
10K_0402_5%~D
R1581 R1582 0.1U_0402_16V7K~D
10K_0402_5%~D 10K_0402_5%~D 2
2
U604
SPI_MOCS# 1 8
CE# VDD
2
3 6 R1583 1 2 15_0402_5% SPI_MOCLK
C 7 WP# SCK 5 R1584 1 2 15_0402_5% SPI_MOSI C
4 HOLD# SI 2 R1585 1 2 15_0402_5% SPI_MOSO
VSS SO
1
EN25F80-75HCP_SOP8
C1724
22P_0402_50V8J~D
+3.3V_F347 2
+3.3V_F347
1
1
R1586
100K_0402_1%~D
R1587
100K_0402_1%~D
2
SLP_S3
2
SLP_S5
1
D
+3.3V_F347 behavior
1
Q210 D
<15,31> PM_SLP_S3#
2
G SSM3K7002F_SC59-3 2 Q211
<15,31> PM_SLP_S5#
S G SSM3K7002F_SC59-3 +3VALW +3.3V_F347
STATE
3
S @
3
J11
2
2 1
1 S0 S3 S4 S5 DEVICE SMBUS ADDRESS
+3.3V_F347 JUMP_43X118
MAXIM - LED 0100 000b
+3.3V_F347
AC IN ON ON ON ON
Q212
MAXIM - GPIO 0100 001b
1
SI3456BDV-T1-E3 1N TSOP6
1
BAT only ON ON OFF OFF I2C EEPROM 1010 000b
D
R1588 6
S
100K_0402_1%~D R1664 5 4
100K_0402_1%~D 2 AC mode battery full in S5:turn off ELC controller
2
ACIN# 1 1
2
1
BATT_LOW_LED C1725
G
1
D 4.7U_0603_6.3V6K~D R1589
1
3
1
Q213 D 100K_0402_1%~D
<31,51> ACIN 2
G SSM3K7002F_SC59-3 2 Q249 C1726 2
<31> BATT_LOW_LED#
B S G SSM3K7002F_SC59-3 0.1U_0402_25V6 B
2
3
2
S +3VALW B+_BIAS
3
R1591
100K_0402_1%~D
1
1 2
R1590
1
+3.3V_F347 100K_0402_1%~D D
1M_0402_5%~D
2 Q214 1
2
G SSM3K7002F_SC59-3 C1727
1
S
3
1
D R1951 0.1U_0402_25V6
R1592 2 Q215 2
<31> 3V_F347_ON
2
100K_0402_1%~D G SSM3K7002F_SC59-3
1
S
2
CHRG_STATE R1593
100K_0402_1%~D
1
D
2 Q216
<31> BATT_CHG_LED#
2
G SSM3K7002F_SC59-3
S
3
A A

ELC (1)/STATUS CONN
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
Touchpad LED CONN Indicator CONN

+5VS_TP_LED
<36> 7313_INT#
+3.3V_F347
+3.3V_F347 +5VS
L/R Headlight, Logo C603
+5VS
R1595
1 0.1U_0402_16V7K~D
1 2 C1728 C605
0.1U_0402_16V7K~D JTPMB 1
4.7K_0402_1%~D U605 2
close to JTPMB 7/26 0.1U_0402_16V7K~D 1
1
C1729
1
2 0.1U_0402_16V7K~D
R1594 7313_INT# 2
22 21 3
D
4.7K_0402_1%~D INT#/O16 V+ TP_CLK 3 2 D
+3VALW 4
I2C_CLK LSPK_LED_R_DRV# TP_DATA 4 JCAP
<34,36> I2C_CLK
19 1 +3VS 5
I2C_DAT SCL P0 LSPK_LED_G_DRV# TP_DATA 5
<34,36> I2C_DAT 20 2 <31> TP_DATA 6 1
SDA P1 6 1
2
3 LSPK_LED_B_DRV# TP_CLK 7 LED_R_7313#_1 2

P2 <31> TP_CLK 7 2
2
AD0_0 18 4 RSPK_LED_R_DRV# LID_SW_IN# 8 LED_B_7313#_1 3
AD0_1 AD0 P3 RSPK_LED_G_DRV# TP_LED_R_DRV# 8 LED_G_7313#_1 3
23 5 9 4
AD0_2 24 AD1 P4 6 RSPK_LED_B_DRV# D70 TP_LED_G_DRV# 10 9 CAPS_LED_A# 5 4
AD2 P5 10 5
1
7 TP_LED_B_DRV# 11 WLAN_BT_LED_A# 6
P6 11 6
1
TP_LED_R_DRV# LSPK_LED_R_DRV#
R1596 R1597 TP_LED_G_DRV#
14
15
P12 P7
8
10
5/18 delete PESD5V0U2BT_SOT23-3~D
LSPK_LED_G_DRV#
12
13
12
7
8
GND
4.7K_0402_1%~D 4.7K_0402_1%~D TP_LED_B_DRV# 16 P13 P8 11 LOGO_LED_R_DRV# LSPK_LED_B_DRV# 14 13 GND
P14 P9 LOGO_LED_G_DRV# RSPK_LED_R_DRV# 14 TYCO_2041183-6
17 12 15
P15 P10 15
2
13 LOGO_LED_B_DRV# RSPK_LED_G_DRV# 16 CONN@

P11 16
2
1
9 25 RSPK_LED_B_DRV# 17
GND GND 18 17
MAX7313ATG+T_TQFN24_4X4 18
19
20 19
20
21
<36> 7313_INT# GND1
22
+3.3V_F347 GND2 +5VS
HRS_FH28E-20S-0.5SH(11)
LOGO_LED_R_DRV_1#
1
+3.3V_F347 CONN@ +5VS
CAP, Media, Eyes, Rim 1 R1969
3
C1733 4.7K_0402_1%~D
0.1U_0402_16V7K~D
1
U608 2
1
2
4.7K_0402_1%~D
4.7K_0402_1%~D
4.7K_0402_1%~D
R1970 LOGO_LED_R_DRV 5
1
22 21 4.7K_0402_1%~D Q298B
INT#/O16 V+
6
2N7002DW-7-F_SOT363-6~D
4
R1598 R1599 R1600 I2C_CLK 19 1
SCL P0
2
I2C_DAT 20 2 +5VS
SDA P1
2
3 LOGO_LED_R_DRV# 2 Q298A
P2
2
1
AD2_0 18 4 LED_R_7313#_1 2N7002DW-7-F_SOT363-6~D
AD2_1 AD0 P3 LED_G_7313#_1
23 5
AD1 P4
1
AD2_2 24 6 LED_B_7313#_1 +5VS R1975
C AD2 P5 7 100K_0402_5%~D C
P6
1
HDD_R_7313# 14 8
P12 P7
2
1
R1601 HDD_G_7313# 15 10 WLAN_BT_LED_A#
4.7K_0402_1%~D HDD_B_7313# P13 P8 PWR_R_7313# R1976
16 11
P14 P9
3
17 12 PWR_G_7313# 100K_0402_5%~D
P15 P10 PWR_B_7313# +5VS
13
P11
2
9 25
GND GND
2
WLAN_BT_LED 5 LOGO_LED_G_DRV_1#
1
MAX7313ATG+T_TQFN24_4X4 Q301B +5VS
6
2N7002DW-7-F_SOT363-6~D R1971
3
4.7K_0402_1%~D
HDD_B
1
+5VALW 2 Q301A
<31> WLES ON/OFF LED#
2
2N7002DW-7-F_SOT363-6~D R1972 LOGO_LED_G_DRV 5
check with EC 4.7K_0402_1%~D Q299B
1
1
6
2N7002DW-7-F_SOT363-6~D
4
1
2 Q233
2
G SSM3K7002F_SC59-3 R1603
S 100K_0402_5%~D LOGO_LED_G_DRV# 2 Q299A
3
+5VS
2N7002DW-7-F_SOT363-6~D
HDD_B_7313# +5VS
1
LID_SW
1
1
D
1
HDD_R
R1602 LID_SW_IN# 2 Q232 +5VS R1977
<14,31,34> LID_SW_IN#
100K_0402_5%~D G SSM3K7002F_SC59-3
S 100K_0402_5%~D
1
D
3
2
2
1
SATA_LED_ACT 2 Q234 CAPS_LED_A# +5VS
G SSM3K7002F_SC59-3 R1978
1
3
S LOGO_LED_B_DRV_1#
3
1
PCH_SATALED# 2 Q235 100K_0402_5%~D
<13> PCH_SATALED# +5VS
G SSM3K7002F_SC59-3 HDD_R_7313# SATA_LED_ACT R1973
3
S CAPS_LED 5 4.7K_0402_1%~D
3
Q302B
1
HDD_G 2N7002DW-7-F_SOT363-6~D
2
1
D R1974 LOGO_LED_B_DRV 5
LID_SW 2 Q224 4.7K_0402_1%~D Q300B
B B
6
G SSM3K7002F_SC59-3 CAPS_LED# 2 Q302A 2N7002DW-7-F_SOT363-6~D
<31> CAPS_LED#
4
1
D
S 2N7002DW-7-F_SOT363-6~D
3
2
2 Q225
1
G SSM3K7002F_SC59-3 LOGO_LED_B_DRV# 2 Q300A
S 2N7002DW-7-F_SOT363-6~D
3
1
HDD_G_7313#
Reference AD2 AD1 AD0 MAX7313 +5VS +5VS_TP_LED
PWR BTN Board CONN

D
6
LOGO Board CONN
S
B+_BIAS 5 4
U605 0 1 0 L/R Headlight , Logo, TP 2
1U_0603_10V4Z
1 1 1
2
C1746 Q45
G
+5VS
C184
R173 0.1U_0402_16V7K~D
3
470K_0402_5%~D SI3456BDV-T1-E3 1N TSOP6

2 2
Num, CAP , SCR 1 +5VS
1
EN_TPLED
EJECT, REV, PLAY/PAUSE C1732
0.1U_0402_16V7K~D JBTN
1
D
1
FFWD, Vol_DWN, Vol_UP 2 R1654

1
2
20mil JLOGO ON/OFFBTN#
1
2
1
<31> EN_TPLED# <29> ON/OFFBTN# 2
Wireless ON/OFF G 2M_0402_5%~D C185
0.1U_0402_25V6 LID_SW
1
1
HDD_R
HDD_G
3
3
U608 0 1 1 Q44 S
2
2
2
4
4
3
LOGO_LED_R_DRV_1# HDD_B
AWCC Button SSM3K7002FU_SC70-3 3
3
5
5
2
LOGO_LED_G_DRV_1# 4 +5VALW 6
LOGO_LED_B_DRV_1# 4 LID_SW 6
Alien Adrenaline 5
6
5 PWR_R_7313#
7
8
7
6 PWR_G_7313# 8
Power Button Eyes 7
8
GND PWR_B_7313#
9
10
9
GND 10
Power Button Rim Touchpad LED circuit TYCO_0-1775737-6
11
12 11
CONN@ 12
A 13 A
G1
14
G2
FCI_10089708-012010-LF
CONN@

ELC (2)
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
K/B Backlight CONN

CONN@
TYCO_1-2041070-6~D
18
GND
17
GND
16
16
15
KB_LED_R1_DRV#_A# 15
14
D
KB_LED_G1_DRV#_A# 14 D
13
KB_LED_B1_DRV#_A# 13
12
+3VS KB_LED_R2_DRV#_A# 12
11
11
K/B Backlight
+3.3V_F347 KB_LED_R2_DRV#_A# KB_LED_G2_DRV#_A# 10
KB_LED_B2_DRV#_A# 10
<35> 7313_INT#
9
9
1
+3VS KB_LED_R3_DRV#_A# 8
8
6
R1604 KB_LED_G3_DRV#_A# 7
KB_LED_B3_DRV#_A# 7
AD2 AD1 AD0 4.7K_0402_1%~D 6
6
1
Q262A KB_LED_R4_DRV#_A# 5
5
1
1
+5VS
0 0 1 R1607 KB_LED_R2_DRV 2 DMN66D0LDW-7_SOT363-6~D KB_LED_G4_DRV#_A# 4
4
3 2
R1605 R1606 +3.3V_F347 4.7K_0402_1%~D F3 KB_LED_B4_DRV#_A# 3
4.7K_0402_1%~D 4.7K_0402_1%~D 3
1 2 2
2
1
1
1
2
Q262B 0.5A_13.2V_NANOSMDC050F-13.2-2
2
U609 KB_LED_R2_DRV# 5 DMN66D0LDW-7_SOT363-6~D JKBBL1

22 21
INT#/O16 V+
4
I2C_CLK 19 1 KB_LED_R1_DRV#
<34,35> I2C_CLK SCL P0
I2C_DAT 20 2 KB_LED_G1_DRV#
<34,35> I2C_DAT SDA P1
3 KB_LED_B1_DRV#
AD3_0 18 P2 4 KB_LED_R2_DRV#
AD3_1 AD0 P3 KB_LED_G2_DRV# +3VS
23 5
AD3_2 AD1 P4 KB_LED_B2_DRV#
24 6
AD2 P5 KB_LED_R3_DRV# KB_LED_G2_DRV#_A#
7
P6
1
1
14 8 KB_LED_G3_DRV#
R1608 R1609 P12 P7 KB_LED_B3_DRV# +3VS R1610
15 10
P13 P8
6
4.7K_0402_1%~D 4.7K_0402_1%~D 16 11 KB_LED_R4_DRV# 4.7K_0402_1%~D
P14 P9 KB_LED_G4_DRV#
17 12
P15 P10
1
13 KB_LED_B4_DRV# Q282A
P11
2
2
9 25 R1611 KB_LED_G2_DRV 2 DMN66D0LDW-7_SOT363-6~D
GND GND 4.7K_0402_1%~D
3
MAX7313ATG+T_TQFN24_4X4
1
+3VS
2
Q282B
+3VS KB_LED_G2_DRV# 5 DMN66D0LDW-7_SOT363-6~D KB_LED_R4_DRV#_A#
1
KB_LED_R1_DRV#_A# R1614
1
6
C 4.7K_0402_1%~D C
+3VS R1612 +3VS
4.7K_0402_1%~D 6 Q264A
2
KB_LED_R4_DRV 2 DMN66D0LDW-7_SOT363-6~D
1
1
Q277A +3VS
2
R1613 KB_LED_R1_DRV 2 DMN66D0LDW-7_SOT363-6~D KB_LED_B2_DRV#_A# R1615
1
4.7K_0402_1%~D 4.7K_0402_1%~D
3
3
1
+3VS R1616
2
2
6
Q277B 4.7K_0402_1%~D Q264B
KB_LED_R1_DRV# 5 DMN66D0LDW-7_SOT363-6~D KB_LED_R4_DRV# 5 DMN66D0LDW-7_SOT363-6~D
1
Q267A
2
R1617 KB_LED_B2_DRV 2 DMN66D0LDW-7_SOT363-6~D
4
4
4.7K_0402_1%~D
1
+3VS
2
Q267B
KB_LED_G1_DRV#_A# KB_LED_B2_DRV# 5 DMN66D0LDW-7_SOT363-6~D
1
+3VS
R1618 +3VS
6
4
4.7K_0402_1%~D
KB_LED_G4_DRV#_A#
1
1
Q271A
2
R1619 KB_LED_G1_DRV 2 DMN66D0LDW-7_SOT363-6~D +3VS R1620
6
4.7K_0402_1%~D +3VS 4.7K_0402_1%~D
3
1
KB_LED_R3_DRV#_A# Q265A
2
2
Q271B R1621 KB_LED_G4_DRV 2 DMN66D0LDW-7_SOT363-6~D
KB_LED_G1_DRV# 5 DMN66D0LDW-7_SOT363-6~D +3VS R1622 4.7K_0402_1%~D
3
4.7K_0402_1%~D
1
4
2
Q268A Q265B
2
R1623 KB_LED_R3_DRV 2 DMN66D0LDW-7_SOT363-6~D KB_LED_G4_DRV# 5 DMN66D0LDW-7_SOT363-6~D
+3VS 4.7K_0402_1%~D
4
KB_LED_B1_DRV#_A#
2
1
Q268B
+3VS R1624 KB_LED_R3_DRV# 5 DMN66D0LDW-7_SOT363-6~D
B B
6
4.7K_0402_1%~D
+3VS
1
4
Q273A
2
R1625 KB_LED_B1_DRV 2 DMN66D0LDW-7_SOT363-6~D KB_LED_B4_DRV#_A#
1
4.7K_0402_1%~D
3
+3VS +3VS R1626

1
6
4.7K_0402_1%~D
2
Q273B KB_LED_G3_DRV#_A#
1
1
KB_LED_B1_DRV# 5 DMN66D0LDW-7_SOT363-6~D Q266A
2
+3VS R1628 R1627 KB_LED_B4_DRV 2 DMN66D0LDW-7_SOT363-6~D
6
4.7K_0402_1%~D 4.7K_0402_1%~D
4
3
1
1
Q269A
2
2
+3VS R1629 KB_LED_G3_DRV 2 DMN66D0LDW-7_SOT363-6~D Q266B
4.7K_0402_1%~D KB_LED_B4_DRV# 5 DMN66D0LDW-7_SOT363-6~D
3
KB_LED_B3_DRV#_A#
1
1
2
4
+3VS R1630 Q269B
6
4.7K_0402_1%~D KB_LED_G3_DRV# 5 DMN66D0LDW-7_SOT363-6~D

1
Q278A
2
R1631 KB_LED_B3_DRV 2 DMN66D0LDW-7_SOT363-6~D

4.7K_0402_1%~D
3
1
2
Q278B
KB_LED_B3_DRV# 5 DMN66D0LDW-7_SOT363-6~D
4
A A

ELC (3)
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
PCH/GPU DDC SW for DMC DMC Redriver

+3VS
+3VS +3VS_DELAY
1 2 DP_DMC_AUXN
R1866 1.5K_0402_5%~D +3VS
1 2 DP_DMC_AUXP Close to U158 VCC pins
1 2 PCH_DPD_CLK 1 VGA_DPD_AUXP/DDC
2 R1868 1.5K_0402_5%~D
0.01U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.01U_0402_16V7K~D
R1862 @ 1.5K_0402_5%~D R1867 @ 1.5K_0402_5%~D
1 2 PCH_DPD_DAT 1 2 VGA_DPD_AUXN/DDC 1 2 DMC_SDA_CTL 1 1 1 1
R1864 @ 1.5K_0402_5%~D R1865 @ 1.5K_0402_5%~D @ RV17 4.7K_0402_5%~D
+3VS 1 2 DMC_SCL_CTL
C1879
C1880
C1881
C1882
@ @ @ RV16 4.7K_0402_5%~D
11
15
21
33
40
46
U629 2 2 2 2
D D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1 1
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
C1883
C1884
DP_DMC_ML0P 38
DP_DMC_ML0N IN1p
39
U630 2 2 DP_DMC_ML1P IN1n
41
VGA_DPD_AUXP/DDC DP_DMC_ML1N IN2p
<44> VGA_DPD_AUXP/DDC 2 16 42
VGA_DPD_AUXN/DDC 5 IA0 VCC DP_DMC_ML2P 44 IN2n 23 DP_DMC_ML0P_RCC
<44> VGA_DPD_AUXN/DDC IB0 IN3p OUT1p DP_DMC_ML0P_RCC <32>
R1869 2 @ 1 10K_0402_5%~D 11 DP_DMC_ML2N 45 22 DP_DMC_ML0N_RCC
<44> VGA_DMC_HPD IC0 IN3n OUT1n DP_DMC_ML0N_RCC <32>
14 4 DP_DMC_AUXP DP_DMC_ML3P 47 20 DP_DMC_ML1P_RCC
<14> DMC_PCH_DET# ID0 YA IN4p OUT2p DP_DMC_ML1P_RCC <32>
7 DP_DMC_AUXN DP_DMC_ML3N 48 19 DP_DMC_ML1N_RCC
YB IN4n OUT2n DP_DMC_ML1N_RCC <32>
PCH_DPD_CLK 3 9 DMC_HPD +5VS 17 DP_DMC_ML2P_RCC
<15> PCH_DPD_CLK IA1 YC OUT3p DP_DMC_ML2P_RCC <32>
PCH_DPD_DAT 6 12 DMC_DET# 16 DP_DMC_ML2N_RCC
<15> PCH_DPD_DAT IB1 YD DMC_DET# <32> OUT3n DP_DMC_ML2N_RCC <32>
R1870 2 @ 1 10K_0402_5%~D 10 +3VS 2 14 DP_DMC_ML3P_RCC DP_DMC_ML3P_RCC <32>
<15> PCH_DMC_HPD IC1 POW OUT4p
13 13 DP_DMC_ML3N_RCC
ID1 OUT4n DP_DMC_ML3N_RCC <32>
1.5K_0402_5%~D
1.5K_0402_5%~D
DP_DMC_HPD 30
DGPU_EDIDSEL# HPD_SINK
<17> DGPU_EDIDSEL# 1 8
SEL GND
1
15 +3VS R1871 1 2 4.7K_0402_5%~D 26
EN# I2C_CTL_EN#
R1872
R1873
SEL Y PI5C3257QEX_QSOP16 32
NC/DDCBUF_EN#
@
DMC_OE# 25 7 DMC_HPD
NC/OE# HPD
2
0 A0 B0 C0 D0
<32> DMC_DAT_AUXN_CONN DMC_DAT_AUXN_CONN 8
SDA
1 A1 B1 C1 D1 <32> DMC_CLK_AUXP_CONN
DMC_CLK_AUXP_CONN 9
SCL
29 DP_DMC_AUXN
R2008 0_0402_5%~D DMC_SDA_CTL SDAZ DP_DMC_AUXP
34 28
PCH_DPD_CLK DP_DMC_AUXP +3VS DMC_SCL_CTL SDA_CTL/CFG1 SCLZ
1 2 35
SCL_CTL/CFG0
R2009 0_0402_5%~D R1874 1 2 4.7K_0402_5%~D DMC_PC03
PCH_DPD_DAT DP_DMC_AUXN @ R1875 1 I2C_ADDR0/PC0
1 2 2 4.7K_0402_5%~D DMC_PC14
I2C_ADDR1/PC1
R2010 0_0402_5%~D R1876 1 2 4.7K_0402_5%~D DMC_PC11
PCH_DMC_HPD DMC_HPD GND/PC2
1 2
R2011 0_0402_5%~D 6
DMC_PCH_DET# DMC_DET# REXT
1 2
GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
10
C CEXT C
1
2
R1877 C1893 PS121QFN48G_QFN48_7X7
5
12
18
24
27
31
36
37
43
49
499_0402_1%~D 2.2U_0402_6.3V6M~D
2
1
2
100K_0402_5%~D
@
R1878 PCH_DPD_SW_P0 R1953 1 2 0_0402_5%~D DP_DMC_R_ML0P R1954 1 2 0_0402_5%~D DP_DMC_ML0P
PCH/GPU AUX&LANE SW for DMC

PCH_DPD_SW_N0 R1955 1 2 0_0402_5%~D DP_DMC_R_ML0N R1956 1 2 0_0402_5%~D DP_DMC_ML0N
1
2N7002_SOT23
3
0_0402_5%~D
S
G PCH_DPD_SW_P1 R1957 1 2 0_0402_5%~D DP_DMC_R_ML1P R1958 1 2 0_0402_5%~D DP_DMC_ML1P
+3VS_DELAY 1 2 2 PCH_DPD_SW_N1 R1959 1 2 0_0402_5%~D DP_DMC_R_ML1N R1960 1 2 0_0402_5%~D DP_DMC_ML1N
@ Q291
R1883 D PCH_DPD_SW_P2 R1961 1 2 0_0402_5%~D DP_DMC_R_ML2P R1962 1 2 0_0402_5%~D DP_DMC_ML2P
1
@ PCH_DPD_SW_N2 R1963 1 2 0_0402_5%~D DP_DMC_R_ML2N R1964 1 2 0_0402_5%~D DP_DMC_ML2N
PCH_DPD_SW_P3 R1965 1 2 0_0402_5%~D DP_DMC_R_ML3P R1966 1 2 0_0402_5%~D DP_DMC_ML3P

PCH_DPD_SW_N3 R1967 1 2 0_0402_5%~D DP_DMC_R_ML3N R1968 1 2 0_0402_5%~D DP_DMC_ML3N
Close to U631 Close to U629

499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
499_0402_1%~D
2
6/5 change C188, C1162 0805 to 0603

R1900
R1901
R1902
R1903
R1904
R1905
R1906
R1907
+3VS
1
U631 +3VS
C1894 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_P0 22 42

<44> VGA_DPD_P0 D3-_B VDD
C1895 1 @2 0.1U_0402_10V6K~D @ @ @ @ @ @ @ @ VGA_DPD_SW_N0 23 40 1 2
<44> VGA_DPD_N0 D3+_B VDD
1
VGA_DPD_SW_P1 10U_0603_6.3V6M~D
C1898
C1899
0.1U_0402_16V7K~D
C1896 1 @2 0.1U_0402_10V6K~D 24 30 R931
B <44> VGA_DPD_P1 D2-_B VDD B
C1897 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_N1 25 20
C1900 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_P2 26 18 @ 100K_0402_1%~D
<44> VGA_DPD_P2 D1-_B VDD 2 @ 1
C1901 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_N2 27 16
C1902 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_P3 28 8
<44> VGA_DPD_P3 D0-_B VDD
2
C1903 1 @2 0.1U_0402_10V6K~D VGA_DPD_SW_N3 29 2
<44> VGA_DPD_N3 D0+_B VDD DMC_OE#
C1904 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_P0 31
<15> PCH_DPD_P0 D3-_A
C1905 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_N0 32
<15> PCH_DPD_N0 D3+_A
C1906 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_P1 33
<15> PCH_DPD_P1 D2-_A
C1907 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_N1 34 15 DMC_SW_P0 R1911 1@ 2 0_0402_5%~DDP_DMC_ML0P
<15> PCH_DPD_N1 D2+_A D3-
1
C1908 0.1U_0402_10V7K~D PCH_DPD_SW_P2 DMC_SW_N0 R1912 D
<15> PCH_DPD_P2 1 2 35 14 1@ 2 0_0402_5%~DDP_DMC_ML0N Q292
PCH_DPD_SW_N2 D1-_A D3+ DMC_SW_P1 0_0402_5%~DDP_DMC_ML1P
<15> PCH_DPD_N2
C1909 1 2 0.1U_0402_10V7K~D 36 12 R1913 1@ 2 2 DP_DMC_HPD DP_DMC_HPD <32>
C1910 0.1U_0402_10V7K~D PCH_DPD_SW_P3 D1+_A D2- DMC_SW_N1 R1915 0_0402_5%~DDP_DMC_ML1N
<15> PCH_DPD_P3 1 2 37 11 1@ 2 G
C1911 0.1U_0402_10V7K~D PCH_DPD_SW_N3 D0-_A D2+ DMC_SW_P2 R1916 0_0402_5%~DDP_DMC_ML2P
<15> PCH_DPD_N3
1 2 38 7 1@ 2 S
D0+_A D1-
3
R1920
R1921
R1922
R1923
R1924
R1925
R1926
R1927
6 DMC_SW_N2 R1917 1@ 2 0_0402_5%~DDP_DMC_ML2N 2N7002_SOT23

D1+ 4 DMC_SW_P3 R1918 1@ 2 0_0402_5%~DDP_DMC_ML3P
D0- DMC_SW_N3 R1919 0_0402_5%~DDP_DMC_ML3N
39 3 1@ 2
VSS D0+
1
41
VSS
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
680_0402_1%~D
21
19 VSS
VSS DMC_DGPU_SELECT#
17 9
VSS SEL
13
VSS
2
10
VSS +3VS
5 43 +1.5VS_DMC
VSS GND_PAD
1
VSS
1
+1.5VS_DMC PI3HDMI412FT-BZHE_TQFN42_9X3P5
@ @ R1928
1
0_0402_5%~D D 36K_0402_1%
+3VS 1 2 2 @
R1929 G R1931
2
1
Q293 S 1 1 +1.5VS_DMC +VCCAFDI_VRM DMC_DGPU_SELECT# 1 2 DGPU_SELECT# <16>

3
10U_0603_6.3V6M~D
C1912
0.1U_0402_16V7K~D
C1913
R1930 2N7002_SOT23
1
100K_0402_5%~D 30K_0402_1%
@ R1932 R1933
2 @ 2 @ 2 1 @ 680K_0402_1%
2
A 0_0603_5%~D A
2
AUX_SEL/SEL1&2 Chanel Source Security Classification Compal Secret Data Compal Electronics, Inc.
0 A GPU Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
1 B PCH
DMC MUX/Redriver
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
6/5 change C61 0805 to 0603

DP Redriver +3VS +1.5VS Co-lay
FV1
+3VS_DP
+3VS 1 2
1 1 1
1.5A_6V_1206L150PR~D
0.1U_0402_16V7K~D
CV2
0.1U_0402_16V7K~D
CV3
0.1U_0402_16V7K~D
CV4
10U_0603_6.3V6M~D
CV6
0.1U_0402_16V7K~D
CV11
CV1
0.1U_0402_16V7K~D 1 1 1 RV3 2 @ 1 0_1206_5%~D
2 2 2
2 2 2 JMDP1
D D
36
29
21
17
11
5
UV1
VCC33
VDD15
VDD15
VDD15
VDD15
VDD15
DISP_A0P_VGA CV10 2 1 0.1U_0402_10V6K~D DISP_A0P_VGA_C 1 1
DISP_A0N_VGA CV12 0.1U_0402_10V6K~D DISP_A0N_VGA_C D0+ DISP_HPD_SINK
GND
2 1 2 2
D0- DISP_A0P_C CV5 0.1U_0402_10V6K~D DISP_A0P RV231 DISP_A0P
HPD
28 2 1 3
DISP_A1P_VGA CV7 0.1U_0402_10V6K~D DISP_A1P_VGA_C D0+A DISP_A0N_C CV8 0.1U_0402_10V6K~D DISP_A0N DP_CBL_DET CAB_DET_SINK
LANE0_P
2 1 3 27 2 1 <16> DP_CBL_DET 1 2 4
DISP_A1N_VGA CV9 0.1U_0402_10V6K~D DISP_A1N_VGA_C D1+ D0-A 0_0402_5%~D DISP_A0N
CONFIG1
2 1 4 5
D1- DISP_A1P_C CV13 0.1U_0402_10V6K~D DISP_A1P +3VS DISP_CEC
LANE0_N
26 2 1 6
DISP_A2P_VGA CV14 0.1U_0402_10V6K~D DISP_A2P_VGA_C D1+A DISP_A1N_C CV15 0.1U_0402_10V6K~D DISP_A1N
CONFIG2
2 1 6 25 2 1 7
DISP_A2N_VGA CV16 0.1U_0402_10V6K~D DISP_A2N_VGA_C D2+ D1-A GND
2 1 7 8
D2- GND
1
DISP_A2P_C CV17 0.1U_0402_10V6K~D DISP_A2P DISP_A1P
100K_0402_5%~D
23 2 1 9
DISP_A3P_VGA CV22 0.1U_0402_10V6K~D DISP_A3P_VGA_C D2+A DISP_A2N_C CV23 0.1U_0402_10V6K~D DISP_A2N +3VS DISP_A3P
LANE1_P
RV267
2 1 9 22 2 1 10
DISP_A3N_VGA CV18 2 1 0.1U_0402_10V6K~D DISP_A3N_VGA_C 10 D3+ D2-A DISP_A1N 11
LANE3_P
D3- DISP_A3P_C CV19 0.1U_0402_10V6K~D DISP_A3P DISP_A3N
LANE1_N
20 2 1 12
D3+A LANE3_N
1
DISP_A3N_C CV24 0.1U_0402_10V6K~D DISP_A3N
100K_0402_5%~D
19 2 1 13
D3-A GND
2
RV268
12 14
DP_HPD_C CAD DISP_CLK_AUXP_CONN CAB_DET_SINK# DISP_A2P
GND
13 31 15
HPDSRC AUX_SINK+ 30 DISP_DAT_AUXN_CONN DISP_CLK_AUXP_CONN 16
LANE2_P
CAB_DET_SINK AUX_SINK- DISP_A2N

AUXCH_P
14
CAD_SINK Close connect 17 LANE2_N
2
DISP_HPD_SINK 15 33 DISP_AUXN_C DISP_DAT_AUXN_CONN 18
HPD_SINK AUXSRC+ D AUXCH_N
1
32 DISP_AUXP_C QV14 19
AUXSRC- GND
16 2 20
NC 35 G
DP_PWR
DISP_A0P_VGA DDCSDA
<44> DISP_A0P_VGA 34 S 21
GND
GND
GND
GND
DDCSCL
3
1
DISP_A0N_VGA 2N7002_SOT23
100K_0402_5%~D
<44> DISP_A0N_VGA 22
DISP_A1P_VGA @ DV2
RV270
RV6
CV27
CV28
RV5
<44> DISP_A1P_VGA 23
GROUND
DISP_A1N_VGA PI2EQXDP101ZFEX_TQFN36_6X5 DISP_A0N 1 10 DISP_A0N 24
<44> DISP_A1N_VGA
8
18
24
37
C DISP_A2P_VGA C
<44> DISP_A2P_VGA
1M_0402_5%~D
1
1
DISP_A2N_VGA DISP_A0P 2 9 DISP_A0P 1 1
<44> DISP_A2N_VGA
2
DISP_A3P_VGA RV269 RV4 FOX_3V112M3-RH1HH7-7H
<44> DISP_A3P_VGA
DISP_A3N_VGA DISP_A1P 4 7 DISP_A1P @
<44> DISP_A3N_VGA
1M_0402_5%~D CONN@
DISP_A1N 5 6 DISP_A1N 2 2
2
DISP_AUXP
1M_0402_5%~D
22U_0805_6.3V6M~D
0.1U_0402_10V6K~D
5.1M_0402_5%
<44> DISP_AUXP +3VS_DELAY
DISP_AUXN 3
<44> DISP_AUXN
8
DISP_A0P_VGA_C RV171 1 @ 2 0_0402_5%~D DISP_A0P_R RV172 1 @ 2 0_0402_5%~D DISP_A0P RCLAMP0524P.TCT~D

DISP_A0N_VGA_C RV173 1 @ 2 0_0402_5%~D DISP_A0N_R RV174 1 @ 2 0_0402_5%~D DISP_A0N
1
Place close JDP1
2K_0402_5%~D
2K_0402_5%~D
DISP_A1P_VGA_C RV175 1 @ 2 0_0402_5%~D DISP_A1P_R RV176 1 @ 2 0_0402_5%~D DISP_A1P @ @
RV281
RV282
DISP_A1N_VGA_C RV177 1 @ 2 0_0402_5%~D DISP_A1N_R RV178 1 @ 2 0_0402_5%~D DISP_A1N @ DV1
DISP_A3P 1 10 DISP_A3P
DISP_A2P_VGA_C RV179 1 @ 2 0_0402_5%~D DISP_A2P_R RV180 1 @ 2 0_0402_5%~D DISP_A2P
2
DISP_A2N_VGA_C RV181 1 @ 2 0_0402_5%~D DISP_A2N_R RV182 1 @ 2 0_0402_5%~D DISP_A2N DISP_A3N 2 9 DISP_A3N DISP_AUXN +3VS
DISP_AUXP
DISP_A3P_VGA_C RV183 1 @ 2 0_0402_5%~D DISP_A3P_R RV184 1 @ 2 0_0402_5%~D DISP_A3P DISP_A2N 4 7 DISP_A2N
DISP_A3N_VGA_C RV185 1 @ 2 0_0402_5%~D DISP_A3N_R RV186 1 @ 2 0_0402_5%~D DISP_A3N
1
DISP_A2P DISP_A2P RV233
100K_0402_5%~D
100K_0402_5%~D
5 6
1
DISP_AUXP_C RV187 1 @ 2 0_0402_5%~D DISP_AUXP_R RV188 1 @ 2 0_0402_5%~D DISP_CLK_AUXP_CONN 150K_0402_5%
RV272
RV271
C
DISP_AUXN_C RV189 1 @ 2 0_0402_5%~D DISP_AUXN_R RV190 1 @ 2 0_0402_5%~D DISP_DAT_AUXN_CONN 3 QV9 2 1 2 DISP_HPD_SINK
PMBT3904_SOT23 B
DISP_HPD_SINK RV191 1 @ 2 0_0402_5%~D DISP_HPD_SINK_R RV192 1 @ 2 0_0402_5%~D DP_HPD_C 8 E
3
<13> DP_PCH_HPD 1 RV234 2 0_0402_5%~D
RCLAMP0524P.TCT~D
B B
1
RV235
10K_0402_5%~D
GPU DDC Dongle SW for DP
2
+3VS_DELAY
CV535 2 1 0.1U_0402_10V6K~D 07/29/2010

DP HPD for OPT DGPU output CV506
+3VS
0.1U_0402_16V7K~D
UV19 RV239 1 2
CAB_DET_SINK# 1 14
BE0 VCC
5
DISP_AUXP 2 13 CAB_DET_SINK 0_0402_5%~D UV17
A0 BE3
<16,17,39,55,56> DGPU_PWROK 2 1 1
P
DISP_CLK_AUXP_CONN DISP_AUXP_C CV525 2 0.1U_0402_10V6K~D DISP_AUXP IN1 DP_HPD
3 12 1 4 DP_HPD <44>
B0 A3 DP_HPD_C O
2
IN2
G
CAB_DET_SINK# 4 11
DISP_AUXN BE1 B3 CAB_DET_SINK SN74AHC1G08DCKR_SC70-5
5 10
A1 BE2
3
1
DISP_DAT_AUXN_CONN 6 9 DISP_AUXN_C CV526 2 1 0.1U_0402_10V6K~D DISP_AUXN

B1 A2 RV280
7 8 10K_0402_5%~D 1 2
GND B2
2
0_0402_5%~D
Dongle
PI3C3125LEX_TSSOP14~D
Normal
@ RV240
A A

Mini Display Port
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6801P
5 4 3 2 1
2 1
+3VS_DELAY
1 2 HDMI_DDC_DATA Place close JHDMI1

RV12 4.7K_0402_5%~D
1 2 HDMI_DDC_CLK
RV13 4.7K_0402_5%~D +3VS RV21 1 @ 2 0_0402_5%~D
1 2 HDMI_SDA_CTL Close to U158 VCC pins
@ RV14 4.7K_0402_5%~D LV1
1 2 HDMI_SCL_CTL TMDS_TXCN 1 2 TMDS_L_TXCN
0.01U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.01U_0402_16V7K~D
@ RV15 4.7K_0402_5%~D 1 2
1 1 1 1
TMDS_TXCP 4 3 TMDS_L_TXCP
4 3
CV31
CV32
CV33
CV34
11
15
21
33
40
46
UV2 2 2 2 2 MURATA DLW21SN900HQ2L
@
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
RV27 1 @ 2 0_0402_5%~D W=40mils RV10 0_1206_5%~D
CV516 2 1 0.1U_0402_10V7K~D HDMI_A3P_C_VGA 38 2 1 +VDISPLAY_VCC
<44> HDMI_A3P_VGA IN1p
CV517 2 1 0.1U_0402_10V7K~D HDMI_A3N_C_VGA 39
<44> HDMI_A3N_VGA IN1n
CV518 2 1 0.1U_0402_10V7K~D HDMI_A0P_C_VGA 41 RV30 1 @ 2 0_0402_5%~D DV3 FV2
<44> HDMI_A0P_VGA IN2p
CV519 2 1 0.1U_0402_10V7K~D HDMI_A0N_C_VGA 42 2 1 2 1
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
<44> HDMI_A0N_VGA IN2n +5VS
CV520 2 1 0.1U_0402_10V7K~D HDMI_A1P_C_VGA 44 23 TMDS_TXCP LV2 3 NC 1 1
<44> HDMI_A1P_VGA IN3p OUT1p
CV521 2 0.1U_0402_10V7K~D HDMI_A1N_C_VGA TMDS_TXCN TMDS_TX0N TMDS_L_TX0N 1.5A_6V_1206L150PR~D
CV29
<44> HDMI_A1N_VGA 1 45 22 1 2
CV522 2 0.1U_0402_10V7K~D HDMI_A2P_C_VGA IN3n OUT1n TMDS_TX0P 1 2 BAT1000-7-F_SOT23-3~D CV30
<44> HDMI_A2P_VGA 1 47 20
CV523 2 0.1U_0402_10V7K~D HDMI_A2N_C_VGA IN4p OUT2p TMDS_TX0N
<44> HDMI_A2N_VGA 1 48 19
IN4n OUT2n TMDS_TX1P TMDS_TX0P TMDS_L_TX0P 2 2
17 4 3
OUT3p TMDS_TX1N 4 3
16
OUT3n TMDS_TX2P MURATA DLW21SN900HQ2L
+3VS 2 14
POW OUT4p TMDS_TX2N @
B 13 B
HDMI_R_HPLUG OUT4n RV34 1
30 2 0_0402_5%~D
HPD_SINK
+3VS RV25 1 2 4.7K_0402_5%~D 26

I2C_CTL_EN# RV35 1 @ 2 0_0402_5%~D
32
NC/DDCBUF_EN# LV3
+5VS HDMI_OE# 25 7 HDMI_HPD_C TMDS_TX1N 1 2 TMDS_L_TX1N JHDMI1
NC/OE# HPD 1 2 HDMI_HPLUG 19
1.5K_0402_5%~D HP_DET
2 1 RV28 DDC_DAT_HDMI 8 18
SDA +5V
1.5K_0402_5%~D 2 1 RV29 DDC_CLK_HDMI 9 TMDS_TX1P 4 3 TMDS_L_TX1P 17
SCL HDMI_DDC_DATA 4 3 DDC_DAT_HDMI DDC/CEC_GND
29 HDMI_DDC_DATA <44> 16
HDMI_SDA_CTL SDAZ HDMI_DDC_CLK MURATA DLW21SN900HQ2L DDC_CLK_HDMI SDA
34 28 HDMI_DDC_CLK <44> 15
+3VS HDMI_SCL_CTL SDA_CTL/CFG1 SCLZ SCL
35 14
SCL_CTL/CFG0 RV37 1 @ Reserved
1 2 0_0402_5%~D 13
RV31 1 CEC
2 4.7K_0402_5%~D PC0 3 @ TMDS_L_TXCN 12 20
I2C_ADDR0/PC0 CK- GND
@ RV32 1 2 4.7K_0402_5%~D PC1 4 CV530 11 21
I2C_ADDR1/PC1 10P_0402_50V8J~D TMDS_L_TXCP CK_shield GND
10 22
2 CK+ GND
RV33 1 2 4.7K_0402_5%~D PC2 1 RV38 1 @ 2 0_0402_5%~D TMDS_L_TX2N 9 23
GND/PC2 D0- GND
8
LV4 TMDS_L_TX2P D0_shield
7
TMDS_TX2N TMDS_L_TX2N TMDS_L_TX1N D0+
6 1 2 6
REXT 1 2 D1-
5
D1_shield
GND10
10 TMDS_L_TX1P 4
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
CEXT TMDS_TX2P TMDS_L_TX2P TMDS_L_TX0N D1+
1 4 3 3
4 3 D2-
2
2
RV36 CV47 PS121QFN48G_QFN48_7X7 MURATA DLW21SN900HQ2L TMDS_L_TX0P D2_shield
1
D2+
5
12
18
24
27
31
36
37
43
49
499_0402_1%~D 2.2U_0402_6.3V6M~D
2 RV39 1 @ 2 0_0402_5%~D SUYIN_100042MR019S153ZL
1
CONN@
HDMI_A3P_C_VGA RV193 1 @ 2 0_0402_5%~D TMDS_TXCP_R RV194 1 @ 2 0_0402_5%~D TMDS_TXCP

HDMI_A3N_C_VGA RV195 1 @ 2 0_0402_5%~D TMDS_TXCN_R RV196 1 @ 2 0_0402_5%~D TMDS_TXCN
HDMI_A0P_C_VGA RV197 1 @ 2 0_0402_5%~D TMDS_TX0P_R RV198 1 @ 2 0_0402_5%~D TMDS_TX0P +3VS

HDMI_A0N_C_VGA RV199 1 @ 2 0_0402_5%~D TMDS_TX0N_R RV200 1 @ 2 0_0402_5%~D TMDS_TX0N
1
HDMI_A1P_C_VGA RV201 1 @ 2 0_0402_5%~D TMDS_TX1P_R RV202 1 @ 2 0_0402_5%~D TMDS_TX1P
HDMI_A1N_C_VGA RV203 1 @ 2 0_0402_5%~D TMDS_TX1N_R RV204 1 @ 2 0_0402_5%~D TMDS_TX1N RV273
10K_0402_5%~D@
HDMI_A2P_C_VGA RV205 1 @ 2 0_0402_5%~D TMDS_TX2P_R RV206 1 @ 2 0_0402_5%~D TMDS_TX2P
HDMI_A2N_C_VGA RV207 1 @ 2 0_0402_5%~D TMDS_TX2N_R RV208 1 @ 2 0_0402_5%~D TMDS_TX2N
2
<17> HDMI_PCH_HPD#
HDMI_DDC_DATA RV209 1 @ 2 0_0402_5%~D DDC_DAT_HDMI_R RV210 1 @ 2 0_0402_5%~D DDC_DAT_HDMI
D
1
HDMI_DDC_CLK RV211 1 @ 2 0_0402_5%~D DDC_CLK_HDMI_R RV212 1 @ 2 0_0402_5%~D DDC_CLK_HDMI QV1
2
HDMI_HPLUG RV213 1 @ 2 0_0402_5%~D HDMI_HPLUG_R RV214 1 @ 2 0_0402_5%~D HDMI_HPD_C G
S
3
2N7002_SOT23
LV17
07/29/2010 MBK1608221YZF_2P
1
CV507 HDMI_R_HPLUG HDMI_HPLUG

RV246
499_0402_1%~D
RV247
499_0402_1%~D
RV248
499_0402_1%~D
RV249
499_0402_1%~D
RV250
499_0402_1%~D
RV251
499_0402_1%~D
RV252
499_0402_1%~D
RV253
499_0402_1%~D
2 1 1 2
HDMI HPD for OPT DGPU output +3VS +3VS RV7
A A
0.1U_0402_16V7K~D 1K_0402_5%~D 1
1
RV244 1 2
1
RV9 DV4 CV524
2
0_0402_5%~D UV18 R1950 BAV99-7-F_SOT23-3 220P_0402_50V8J
100K_0402_5%~D
2 1 1 10K_0402_5%~D 2
<16,17,38,55,56> DGPU_PWROK @
P
IN1 HDMI_HPD
@ @ @ @ @ @ @ @ 4 HDMI_HPD <44>
HDMI_HPD_C O
2
IN2
3
G
HDMI_OE#
SN74AHC1G08DCKR_SC70-5
3
D
1
0_0402_5%~D
D
1
+3VS_DELAY 1 2 2 QV13 QV10
G 2 +3VS
1
RV254 S 1 2 G
3
RV255 2N7002_SOT23 S
3
100K_0402_5%~D 0_0402_5%~D 2N7002_SOT23
@
@ RV245 @
2
@
HDMI
Custom
LA-6801P 1.0

2 1
5 4 3 2 1
PLACE NEAR BALLS PLACE NEAR BGA +1.05VSDGPU

UV3A
PEX_IOVDD AR19
4.7U_0603_6.3V6M
10U_0603_6.3V6M~D
22U_0805_6.3V6M~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
<16> PLTRST_VGA# 2 1 AW18 PEX_RST PEX_IOVDD AR26
RV40 0_0402_5%~D PEX_IOVDD AR27 1 1 1 1 1 1 1
VGA_CLKREQ#_R AV18 PEX_CLKREQ PEX_IOVDD AR28
PEX_IOVDD AT18 CV48 CV62 CV63 CV49 CV64 CV50 CV65
<14> CLK_PEG_VGA AT19 PEX_REFCLK
AU19 2 2 2 2 2 2 2
<14> CLK_PEG_VGA# PEX_REFCLK
220nF_0402_16V7K 2 1 CV51 PEG_GTX_HRX_P0 AW19 PEX_TX0

2200mA
<5> PEG_GTX_C_HRX_P0
220nF_0402_16V7K 2 1 CV52 PEG_GTX_HRX_N0 AV19 PEX_TX0
<5> PEG_GTX_C_HRX_N0 +1.05VSDGPU
D <5> PEG_HTX_C_GRX_P0 BB18 PEX_RX0 D
<5> PEG_HTX_C_GRX_N0 BB19 PEX_RX0 PEX_IOVDDQ AR22
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
10U_0603_6.3V6M~D
22U_0805_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
PEX_IOVDDQ AR23
220nF_0402_16V7K 2 1 CV66 PEG_GTX_HRX_P1 AW20 PEX_TX1 PEX_IOVDDQ AR24 1 1 1 1 1 1 1
220nF_0402_16V7K 2 1 CV53 PEG_GTX_HRX_N1 AY20 PEX_TX1 PEX_IOVDDQ AR25
<5> PEG_GTX_C_HRX_N1
PEX_IOVDDQ AT20 CV54 CV55 CV67 CV56 CV57 CV58 CV59
<5> PEG_HTX_C_GRX_P1 BA19 PEX_RX1 PEX_IOVDDQ AT21
AY19 AT25 2 2 2 2 2 2 2
<5> PEG_HTX_C_GRX_N1 PEX_RX1 PEX_IOVDDQ
PEX_IOVDDQ AT27
220nF_0402_16V7K 2 1 CV60 PEG_GTX_HRX_P2 AW21 PEX_TX2 PEX_IOVDDQ AU18
220nF_0402_16V7K 2 1 CV61 PEG_GTX_HRX_N2 AV21 PEX_TX2 PEX_IOVDDQ AU21
PEX_IOVDDQ AU25 PLACE NEAR BALLS PLACE NEAR BGA
BA21 PEX_RX2
<5> PEG_HTX_C_GRX_P2
<5> PEG_HTX_C_GRX_N2 AY21 PEX_RX2
220nF_0402_16V7K 2 1 CV68 PEG_GTX_HRX_P3 AT22 PEX_TX3

220nF_0402_16V7K 2 1 CV69 PEG_GTX_HRX_N3 AU22 PEX_TX3
<5> PEG_HTX_C_GRX_P3 BB21 PEX_RX3

BB22 PEX_RX3
<5> PEG_HTX_C_GRX_N3
<5> PEG_HTX_C_GRX_P4 BA22 PEX_RX4

AY22 PEX_RX4
<5> PEG_HTX_C_GRX_N4 +3VS_DELAY
220nF_0402_16V7K 2 1 CV72 PEG_GTX_HRX_P5 AY23 PEX_TX5
PEG_GTX_HRX_N5
220nF_0402_16V7K 2 1 CV73 AW23 PEX_TX5
PEX_PLL_HVDD AR18 +PEX_VDD_SVDD 2 1
120mA
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
BA24 PEX_RX5 RV41 0_0402_5%~D
AY24 PEX_RX5 PEX_SVDD_3V3 AR17 +PEX_SVDD33 2 1 1 1 1
RV82 0_0402_5%~D
220nF_0402_16V7K 2 1 CV74 PEG_GTX_HRX_P6 AW24 +1.05VSDGPU CV77 CV508 CV75
<5> PEG_GTX_C_HRX_P6 PEX_TX6
220nF_0402_16V7K 2 1 CV76 PEG_GTX_HRX_N6 AV24 PEX_TX6 @
<5> PEG_GTX_C_HRX_N6 2 2 2
2 1
1U_0402_6.3V6K~D
BB24 PEX_RX6 RV276 0_0402_5%~D
<5> PEG_HTX_C_GRX_N6 BB25 PEX_RX6 1
C C
220nF_0402_16V7K 2 1 CV78 PEG_GTX_HRX_P7 AW25 CV527
220nF_0402_16V7K
PEX_TX7 PLACE NEAR BGA
<5> PEG_GTX_C_HRX_N7 2 1 CV79 PEG_GTX_HRX_N7 AV25 PEX_TX7 @
2
BA25 PEX_RX7
Nvidia recommend 08/11
220nF_0402_16V7K 2 1 CV81 PEG_GTX_HRX_N8 AY26 PEX_TX8
VDD_SENSE AN37 RV42 2 1 0_0402_5%~D +NVVDD_SENSE <56>
AY27 PEX_RX8
GND_SENSE AP38 RV43 2 1 0_0402_5%~D GND_SENSE <56>
<5> PEG_HTX_C_GRX_P9 BB27 PEX_RX9

BB28 PEX_RX9
220nF_0402_16V7K 2 1 CV84 PEG_GTX_HRX_P10 AT28 PEX_TX10
220nF_0402_16V7K 2 1 CV85 PEG_GTX_HRX_N10 AU28 PEX_TX10



PEX_TSTCLK_OUT AT24 RV44
220nF_0402_16V7K 2 1 CV88 PEG_GTX_HRX_P12 AY29 PEX_TX12 PEX_TSTCLK_OUT AU24 1 2
220nF_0402_16V7K 2 1 CV89 PEG_GTX_HRX_N12 AW29 PEX_TX12 200_0402_1%
BB30 PEX_RX12
<5> PEG_HTX_C_GRX_P12 +1.05VSDGPU
<5> PEG_HTX_C_GRX_N12 BB31 PEX_RX12 PLACE NEAR BALLS PLACE NEAR BGA
PEG_GTX_HRX_P13
B <5> PEG_GTX_C_HRX_P13
220nF_0402_16V7K
220nF_0402_16V7K
2
2
1 CV90
1 CV91 PEG_GTX_HRX_N13
AW30
AV30
PEX_TX13
PEX_TX13 PEX_PLLVDD AR21 +PEX_PLLDVDD 2
LV5
1
120mA B
4.7U_0603_6.3V6M
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
BLM18PG121SN1D_0603
<5> PEG_HTX_C_GRX_P13 BA31 PEX_RX13 1 1 1 1
AY31 PEX_RX13
CV92 CV93 CV94 CV96
220nF_0402_16V7K 2 1 CV95 PEG_GTX_HRX_P14 AW31 PEX_TX14 RV45
<5> PEG_GTX_C_HRX_P14 2 2 2 2
220nF_0402_16V7K 2 1 CV97 PEG_GTX_HRX_N14 AW32 PEX_TX14 TESTMODE AN3 1 2
10K_0402_5%~D
BB33 PEX_RX14
220nF_0402_16V7K 2 1 CV98 PEG_GTX_HRX_P15 AY32 PEX_TX15
220nF_0402_16V7K 2 1 CV99 PEG_GTX_HRX_N15 AY33 PEX_TX15
RV46
<5> PEG_HTX_C_GRX_P15 BB34 PEX_RX15 PEX_TERMP AU27 1 2
BA34 PEX_RX15 2.49K_0402_1%
N12E-GE_BGA1328~D
+3VS_DELAY
1
+3VS_DELAY
RV47
2.2K_0402_5%~D
2
G
1 3 VGA_CLKREQ#_R
A
<14> PEG_A_CLKRQ# A
D
2N7002_SOT23-3
QV3
2 RV52 1
0_0402_5%~D
@

N12E(1/6)_PCIE
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
MAB2 MAB3
UV3B UV3C
1
MAA2 MAA3 MAA5
<46> MDA[0..63] <47> MDB[0..63]
MDA0 P39 FBA_D0 MDB0 D22 FBB_D0 RV48 RV49
1
MDA1 R37 FBA_D1 MDB1 D24 FBB_D1 10K_0402_5%~D 10K_0402_5%~D
MDA2 R39 FBA_D2 RV50 RV51 RV54 MDB2 E22 FBB_D2
MDA3 R38 FBA_D3 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D MDB3 D23 FBB_D3
2
MDA4 T38 FBA_D4 MDB4 G24 FBB_D4
MDA5 T39 FBA_D5 MDB5 G25 FBB_D5
2
MDA6 U39 FBA_D6 MDB6 E25 FBB_D6
MDA7 V39 FBA_D7 MDB7 F25 FBB_D7
MDA8 M37 FBA_D8 MDB8 D20 FBB_D8 MAB5 MAB18
MDA9 N39 FBA_D9 MDB9 E21 FBB_D9
D D
1
MDA10 M36 FBA_D10 MDB10 D21 FBB_D10
MDA11 M38 FBA_D11 MAA19 MAA18 MDB11 F21 FBB_D11 RV53 RV57
MDA12 K38 FBA_D12 MDB12 G18 FBB_D12 10K_0402_5%~D 10K_0402_5%~D
1
MDA13 K37 FBA_D13 MDB13 F18 FBB_D13
MDA14 L36 FBA_D14 RV55 RV56 MDB14 D18 FBB_D14
2
MDA15 K36 FBA_D15 10K_0402_5%~D 10K_0402_5%~D MDB15 E18 FBB_D15
MDA16 K40 FBA_D16 MDB16 A18 FBB_D16
MDA17 K41 FBA_D17 MDB17 A19 FBB_D17
2
MDA18 J42 FBA_D18 MDB18 B18 FBB_D18
MDA19 K42 FBA_D19 MDB19 C20 FBB_D19
MDA20 M42 FBA_D20 MDB20 B21 FBB_D20 MAB19
MDA21 N40 FBA_D21 MDB21 A21 FBB_D21
1
MDA22 N41 FBA_D22 MDB22 A22 FBB_D22
MDA23 N42 FBA_D23 MDB23 C22 FBB_D23 RV64
MDA24 V41 FBA_D24 MDB24 B27 FBB_D24 10K_0402_5%~D
MDA25 U40 FBA_D25 MDB25 C25 FBB_D25
MDA26 V42 FBA_D26 MDB26 A27 FBB_D26
2
MDA27 V40 FBA_D27 MDB27 C26 FBB_D27
MDA28 R42 FBA_D28 MDB28 B24 FBB_D28
MDA29 R41 FBA_D29 MDB29 C24 FBB_D29
MDA30 P40 FBA_D30 MDB30 B22 FBB_D30
MDA31 R40 FBA_D31 MDB31 C23 FBB_D31
MDA32 AH39 MAA[0..31] <46> MDB32 F35 MAB[0..31] <47>
FBA_D32 FBB_D32
MDA33 AH36 FBA_D33 FBA_CMD0 W36 MAA0 MDB33 E37 FBB_D33 FBB_CMD0 F27 MAB0
MDA34 AH38 FBA_D34 FBA_CMD1 W37 MDB34 C38 FBB_D34 FBB_CMD1 G28
MDA35 AH37 FBA_D35 FBA_CMD2 W38 MAA2 MDB35 D37 FBB_D35 FBB_CMD2 G29 MAB2
MDA36 AG39 FBA_D36 FBA_CMD3 W39 MAA3 MDB36 E34 FBB_D36 FBB_CMD3 E28 MAB3
MDA37 AF39 FBA_D37 FBA_CMD4 W40 MAA4 MDB37 C35 FBB_D37 FBB_CMD4 C27 MAB4
MDA38 AE39 FBA_D38 FBA_CMD5 W42 MAA5 MDB38 C34 FBB_D38 FBB_CMD5 A28 MAB5
MDA39 AE38 FBA_D39 FBA_CMD6 W41 MAA6 MDB39 D34 FBB_D39 FBB_CMD6 B28 MAB6
MDA40 AL39 FBA_D40 FBA_CMD7 Y40 MAA7 MDB40 H37 FBB_D40 FBB_CMD7 C28 MAB7
MDA41 AL37 FBA_D41 FBA_CMD8 Y38 MAA8 MDB41 F38 FBB_D41 FBB_CMD8 D28 MAB8
MDA42 AL36 FBA_D42 FBA_CMD9 AA39 MAA9 MDB42 E40 FBB_D42 FBB_CMD9 F28 MAB9
MDA43 AL38 FBA_D43 FBA_CMD10 AA38 MAA10 MDB43 F39 FBB_D43 FBB_CMD10 D30 MAB10
MDA44 AP39 FBA_D44 FBA_CMD11 AA37 MAA11 MDB44 H40 FBB_D44 FBB_CMD11 E30 MAB11
MDA45 AR40 FBA_D45 FBA_CMD12 AA40 MAA12 MDB45 J39 FBB_D45 FBB_CMD12 C29 MAB12
MDA46 AT41 FBA_D46 FBA_CMD13 AA41 MAA13 MDB46 J38 FBB_D46 FBB_CMD13 B30 MAB13
C MDA47 AT40 FBA_D47 FBA_CMD14 AA42 MAA14 MDB47 J40 FBB_D47 FBB_CMD14 A30 MAB14 C
MDA48 AP40 FBA_D48 FBA_CMD15 AB40 MAA15 MDB48 G41 FBB_D48 FBB_CMD15 C30 MAB15
MDA49 AP42 FBA_D49 FBA_CMD16 AD38 MAA16 MDB49 G42 FBB_D49 FBB_CMD16 D33 MAB16
MDA50 AT42 FBA_D50 FBA_CMD17 AD39 MDB50 J41 FBB_D50 FBB_CMD17 D32
MDA51 AP41 FBA_D51 FBA_CMD18 AC39 MAA18 MDB51 G40 FBB_D51 FBB_CMD18 F31 MAB18
MDA52 AM40 FBA_D52 FBA_CMD19 AB38 MAA19 MDB52 D41 FBB_D52 FBB_CMD19 D31 MAB19
MDA53 AL40 FBA_D53 FBA_CMD20 AE40 MAA20 MDB53 D42 FBB_D53 FBB_CMD20 B34 MAB20
MDA54 AL42 FBA_D54 FBA_CMD21 AE42 MAA21 MDB54 C41 FBB_D54 FBB_CMD21 A34 MAB21
MDA55 AL41 FBA_D55 FBA_CMD22 AE41 MAA22 MDB55 D40 FBB_D55 FBB_CMD22 C33 MAB22
MDA56 AG41 FBA_D56 FBA_CMD23 AD42 MAA23 MDB56 B36 FBB_D56 FBB_CMD23 A33 MAB23
MDA57 AG40 FBA_D57 FBA_CMD24 AB39 MAA24 MDB57 C36 FBB_D57 FBB_CMD24 E31 MAB24
MDA58 AF40 FBA_D58 FBA_CMD25 AB37 MAA25 MDB58 A36 FBB_D58 FBB_CMD25 G32 MAB25
MDA59 AG42 FBA_D59 FBA_CMD26 AC36 MAA26 MDB59 A37 FBB_D59 FBB_CMD26 F30 MAB26
MDA60 AJ40 FBA_D60 FBA_CMD27 AB36 MAA27 MDB60 C39 FBB_D60 FBB_CMD27 E29 MAB27
MDA61 AK41 FBA_D61 FBA_CMD28 AD40 MAA28 MDB61 A39 FBB_D61 FBB_CMD28 B32 MAB28
MDA62 AK40 FBA_D62 FBA_CMD29 AC41 MAA29 MDB62 C40 FBB_D62 FBB_CMD29 C31 MAB29
MDA63 AK42 FBA_D63 FBA_CMD30 AB41 MAA30 MDB63 B40 FBB_D63 FBB_CMD30 B31 MAB30
FBA_CMD31 AB42 FBB_CMD31 A31
<46> DQMA#[7..0] <47> DQMB#[7..0]
DQMA#0 R36 FBA_DQM0 DQMB#0 G23 FBB_DQM0
DQMA#1 K39 FBA_DQM1 DQMB#1 F19 FBB_DQM1
DQMA#2 M41 FBA_DQM2 DQMB#2 C21 FBB_DQM2
DQMA#3 T40 FBA_DQM3 DQMB#3 B25 FBB_DQM3
DQMA#4 AE37 FBA_DQM4 +1.5VSDGPU DQMB#4 E36 FBB_DQM4 +1.5VSDGPU
DQMA#5 AN38 FBA_DQM5 DQMB#5 H39 FBB_DQM5
DQMA#6 AN40 FBA_DQM6 DQMB#6 F42 FBB_DQM6
DQMA#7 AH40 FBA_DQM7 FBA_DEBUG0 Y36 1 2 DQMB#7 B39 FBB_DQM7 FBB_DEBUG0 G27 1 2
FBA_DEBUG1 AE36 RV58 1 2 60.4_0402_1%~D FBB_DEBUG1 E33 RV59 1 2 60.4_0402_1%~D
RV60 60.4_0402_1%~D RV61 60.4_0402_1%~D
<46> QSA[7..0] <47> QSB[7..0]
QSA0 T37 FBA_DQS_WP0 QSB0 F24 FBB_DQS_WP0
QSA1 M39 FBA_DQS_WP1 QSB1 E19 FBB_DQS_WP1
QSA2 M40 FBA_DQS_WP2 FBA_CLK0 V37 CLKA0 QSB2 C19 FBB_DQS_WP2 FBB_CLK0 E27 CLKB0
CLKA0 <46> CLKB0 <47>
QSA3 T42 FBA_DQS_WP3 FBA_CLK0 V36 CLKA0# QSB3 A25 FBB_DQS_WP3 FBB_CLK0 D27 CLKB0#
CLKA0# <46> CLKB0# <47>
QSA4 AG37 FBA_DQS_WP4 FBA_CLK1 AD36 CLKA1 QSB4 D36 FBB_DQS_WP4 FBB_CLK1 G33 CLKB1
CLKA1 <46> CLKB1 <47>
QSA5 AN39 FBA_DQS_WP5 FBA_CLK1 AD37 CLKA1# QSB5 G38 FBB_DQS_WP5 FBB_CLK1 F33 CLKB1#
CLKA1# <46> CLKB1# <47>
QSA6 AN42 FBA_DQS_WP6 QSB6 F41 FBB_DQS_WP6
QSA7 AH41 FBA_DQS_WP7 QSB7 C37 FBB_DQS_WP7
B B
<46> QSA#[7..0] <47> QSB#[7..0]
QSA#0 T36 FBA_DQS_RN0 FBA_WCK01 N38 QSB#0 E24 FBB_DQS_RN0 FBB_WCK01 G22
QSA#1 L39 FBA_DQS_RN1 FBA_WCK01 N37 QSB#1 D19 FBB_DQS_RN1 FBB_WCK01 F22
QSA#2 L40 FBA_DQS_RN2 FBA_WCK23 N36 QSB#2 B19 FBB_DQS_RN2 FBB_WCK23 G20
QSA#3 T41 FBA_DQS_RN3 FBA_WCK23 P36 QSB#3 A24 FBB_DQS_RN3 FBB_WCK23 G21
QSA#4 AG38 FBA_DQS_RN4 FBA_WCK45 AK37 QSB#4 D35 FBB_DQS_RN4 FBB_WCK45 G34
QSA#5 AM39 FBA_DQS_RN5 FBA_WCK45 AK38 QSB#5 G39 FBB_DQS_RN5 FBB_WCK45 G35
QSA#6 AN41 FBA_DQS_RN6 FBA_WCK67 AK36 QSB#6 F40 FBB_DQS_RN6 FBB_WCK67 J36
QSA#7 AH42 FBA_DQS_RN7 FBA_WCK67 AJ36 QSB#7 B37 FBB_DQS_RN7 FBB_WCK67 H36
+FB_PLLAVDD
+FB_PLLAVDD +1.05VSDGPU
300mA LV6 FBB_PLL_AVDD H30
0.1U_0402_16V7K~D
FBA_PLL_AVDD AA35 2 1
0.1U_0402_16V7K~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.5VSDGPU BLM18PG330SN1D_0603 1
1 1 1 1
@ CV104
1
CV100 CV101 CV102 CV105

RV62 2
1.33K_0402_1%~D Rt 2 2 2 2 N12E-GE_BGA1328~D
2
+FB_VREF V5 FB_VREF
1
@ 1
RV63 N12E-GE_BGA1328~D
1.33K_0402_1%~D Rb CV106
0.01U_0402_25V7K~D
2
2
@
@
A A

N12E(2/6)_MemoryA/B
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+1.5VSDGPU +1.5VSDGPU
MAC2 MAC3
UV3E
1
UV3D
RV65 RV68 FBVDDQ H22
<48> MDC[0..63]
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
MDC0 M6 FBC_D0 10K_0402_5%~D 10K_0402_5%~D A2 FBVDDQ FBVDDQ H24
MDC1 N4 FBC_D1 A3 FBVDDQ FBVDDQ H25 1 1 1 1 1 1
MDC2 M7 FBC_D2 AA36 FBVDDQ FBVDDQ H26
2
MDC3 M5 FBC_D3 AB35 FBVDDQ FBVDDQ H27 CV110 CV107 CV108 CV111 CV112 CV109
MDC4 K5 FBC_D4 AC38 FBVDDQ FBVDDQ H28
MDC5 K6 AD35 H29 2 2 2 2 2 2
FBC_D5 FBVDDQ FBVDDQ
MDC6 L7 FBC_D6 GND_REF C3 AD41 FBVDDQ FBVDDQ H31
MDC7 K7 FBC_D7 GND_REF E5 MAC18 MAC19 AE35 FBVDDQ FBVDDQ H32
MDC8 P4 FBC_D8 AF35 FBVDDQ FBVDDQ H33
1
MDC9 R6 FBC_D9 AF36 FBVDDQ FBVDDQ H34
D D
MDC10 R4 FBC_D10 RV66 RV67 AG35 FBVDDQ FBVDDQ H7
MDC11 R5 FBC_D11 10K_0402_5%~D 10K_0402_5%~D AG36 FBVDDQ FBVDDQ H9
MDC12 T5 FBC_D12 AH35 FBVDDQ FBVDDQ J35
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
MDC13 T4 FBC_D13 AK35 FBVDDQ FBVDDQ J4
2
MDC14 U4 FBC_D14 AL35 FBVDDQ FBVDDQ J7 1 1 1 1 1 1
MDC15 T6 FBC_D15 B1 FBVDDQ FBVDDQ J8
MDC16 U3 FBC_D16 B2 FBVDDQ FBVDDQ K35 CV113 CV114 CV115 CV116 CV117 CV118
MDC17 T1 FBC_D17 B29 FBVDDQ FBVDDQ K8
MDC18 V3 MAC5 B33 M35 2 2 2 2 2 2
MDC19 T2 FBC_D19 B6 FBVDDQ FBVDDQ M8
1
MDC20 R3 FBC_D20 C1 FBVDDQ FBVDDQ N35
MDC21 P3 FBC_D21 RV81 C4 FBVDDQ FBVDDQ N8
MDC22 N1 FBC_D22 10K_0402_5%~D D26 FBVDDQ FBVDDQ R35
MDC23 N2 FBC_D23 D3 FBVDDQ FBVDDQ R8
MDC24 J2 FBC_D24 D4 FBVDDQ FBVDDQ T35
2
MDC25 K3 FBC_D25 D5 FBVDDQ FBVDDQ T8
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
MDC26 J3 FBC_D26 D9 FBVDDQ FBVDDQ U35
MDC27 J1 FBC_D27 E32 FBVDDQ FBVDDQ V35 1 1 1 1 1 1
MDC28 M3 FBC_D28 E4 FBVDDQ FBVDDQ V38
MDC29 M2 FBC_D29 E6 FBVDDQ FBVDDQ W35 CV119 CV120 CV121 CV122 CV123 CV124
MDC30 N3 FBC_D30 F2 FBVDDQ FBVDDQ Y35
MDC31 M1 F5 H21 2 2 2 2 2 2
MDC32 F12 MAC[0..31] <48> F6 Y41
MDC33 D13 FBC_D33 FBC_CMD0 H5 MAC0 F7 FBVDDQ
MDC34 G12 FBC_D34 FBC_CMD1 G4 G19 FBVDDQ
MDC35 E12 FBC_D35 FBC_CMD2 G5 MAC2 G30 FBVDDQ
MDC36 E10 FBC_D36 FBC_CMD3 F4 MAC3 G6 FBVDDQ
MDC37 F10 FBC_D37 FBC_CMD4 G2 MAC4 G8 FBVDDQ
MDC38 G11 FBC_D38 FBC_CMD5 G1 MAC5 G9 FBVDDQ
MDC39 G10 FBC_D39 FBC_CMD6 G3 MAC6 H10 FBVDDQ
MDC40 D14 FBC_D40 FBC_CMD7 F1 MAC7 H12 FBVDDQ
MDC41 F15 FBC_D41 FBC_CMD8 J5 MAC8 H13 FBVDDQ
MDC42 D15 FBC_D42 FBC_CMD9 E3 MAC9 H15 FBVDDQ
MDC43 E15 FBC_D43 FBC_CMD10 H6 MAC10 H16 FBVDDQ
MDC44 E16 FBC_D44 FBC_CMD11 C2 MAC11 H18 FBVDDQ
MDC45 D16 FBC_D45 FBC_CMD12 F3 MAC12 H19 FBVDDQ
MDC46 D17 FBC_D46 FBC_CMD13 E2 MAC13
C MDC47 F16 FBC_D47 FBC_CMD14 D1 MAC14 C
MDC48 C17 FBC_D48 FBC_CMD15 D2 MAC15 FBVDDQ_PROBE V8 @ T205 PAD~D
MDC49 A16 FBC_D49 FBC_CMD16 E8 MAC16
MDC50 C18 FBC_D50 FBC_CMD17 D7 +1.5VSDGPU
MDC51 B16 FBC_D51 FBC_CMD18 E7 MAC18
MDC52 C15 FBC_D52 FBC_CMD19 D6 MAC19 FB_CAL_PD_VDDQ V6 1 2
MDC53 C14 FBC_D53 FBC_CMD20 B7 MAC20 RV69 40.2_0402_1%~D
MDC54 A13 FBC_D54 FBC_CMD21 A7 MAC21
MDC55 B13 FBC_D55 FBC_CMD22 C7 MAC22 FB_CAL_PU_GND V7 1 2
MDC56 B9 FBC_D56 FBC_CMD23 A6 MAC23 RV70 40.2_0402_1%~D
MDC57 C10 FBC_D57 FBC_CMD24 E9 MAC24
MDC58 C9 FBC_D58 FBC_CMD25 C5 MAC25 FB_CALTERM_GND V4 1 2
MDC59 A9 FBC_D59 FBC_CMD26 F8 MAC26 RV71 60.4_0402_1%~D
MDC60 C12 FBC_D60 FBC_CMD27 B3 MAC27
MDC61 B12 FBC_D61 FBC_CMD28 C6 MAC28 N12E-GE_BGA1328~D
MDC62 C13 FBC_D62 FBC_CMD29 B5 MAC29
MDC63 A12 FBC_D63 FBC_CMD30 A4 MAC30
FBC_CMD31 B4
<48> DQMC#[7..0]
DQMC#0 K4 FBC_DQM0
DQMC#1 R7 FBC_DQM1
DQMC#2 T3 FBC_DQM2
DQMC#3 L3 FBC_DQM3
DQMC#4 D10 FBC_DQM4 +1.5VSDGPU
DQMC#5 G15 FBC_DQM5
DQMC#6 C16 FBC_DQM6
DQMC#7 C11 FBC_DQM7 FBC_DEBUG0 J6 1 2
FBC_DEBUG1 F9 RV72 1 2 60.4_0402_1%~D +1.5VSDGPU
RV73 60.4_0402_1%~D
<48> QSC[7..0]
QSC0 L4 FBC_DQS_WP0
QSC1 U7 FBC_DQS_WP1
QSC2 R1 FBC_DQS_WP2 FBC_CLK0 H3 CLKB0
CLKC0 <48>
22U_0805_6.3V6M~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
QSC3 K1 FBC_DQS_WP3 FBC_CLK0 H4 CLKB0#
CLKC0# <48>
QSC4 D11 FBC_DQS_WP4 FBC_CLK1 C8 CLKB1 1 1 1 1
CLKC1 <48>
QSC5 G17 FBC_DQS_WP5 FBC_CLK1 D8 CLKB1#
CLKC1# <48>
QSC6 A15 FBC_DQS_WP6 CV125 CV126 CV127 CV128
QSC7 B10 FBC_DQS_WP7
2 2 2 2
B B
<48> QSC#[7..0]
QSC#0 M4 FBC_DQS_RN0 FBC_WCK01 P7
QSC#1 T7 FBC_DQS_RN1 FBC_WCK01 N7
QSC#2 R2 FBC_DQS_RN2 FBC_WCK23 N5
QSC#3 K2 FBC_DQS_RN3 FBC_WCK23 N6
QSC#4 D12 FBC_DQS_RN4 FBC_WCK45 G14
QSC#5 G16 FBC_DQS_RN5 FBC_WCK45 G13
10U_0805_6.3V6M
10U_0805_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
QSC#6 B15 FBC_DQS_RN6 FBC_WCK67 E13
QSC#7 A10 FBC_DQS_RN7 FBC_WCK67 F13 1 1 1 1 1
CV129 CV130 CV131 CV132 CV133
2 2 2 2 2
+FB_PLLAVDD
FBC_PLL_AVDD H8
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
22U_0805_6.3V6M~D
CV142
1 1 1 1
N12E-GE_BGA1328~D 2
CV151 CV152 CV153 CV154
2 2 2 2
A A

N12E(3/6)_MemoryC
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+VGA_CORE +VGA_CORE NVVDD DCPLNG Follows GF106 NVVDD Decap Guidelines DT

UV3F
0.1uF - X5R 0402 x 16 under chip +3VS_DELAY
AA12 VDD VDD AW36 UV3G
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AA14 VDD VDD AW37 0.4mm
AA16 VDD VDD AW38 1 1 1 1 1 1 1 VDD33 AA8 +3VS_DELAY_VDD34 2 1
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AA18 VDD VDD AW39 AJ39 NC VDD33 AB8 RV74 0_0402_5%~D
AA21 VDD VDD AW40 CV190 CV209 CV194 CV185 CV216 CV187 CV179 AK39 NC VDD33 AC8 1 1 1 1 1 1 1 1 1
AA23 VDD VDD AW41 AT9 NC VDD33 AD8
AA25 AW42 2 2 2 2 2 2 2 AU12 AE8 CV170 CV171 CV172 CV173 CV174 CV175 CV176 CV177 CV178
VDD VDD NC VDD33
AA27 VDD VDD AY34 D25 NC VDD33 AF8
AB11 AY35 F34 Y8 2 2 2 2 2 2 2 2 2
VDD VDD NC VDD33
AB13 VDD VDD AY36 J37 NC VDD33 AR16
D AB15 VDD VDD AY37 D
AB17 VDD VDD AY38 PLACE NEAR BALLS PLACE NEAR BGA
AB19 VDD VDD AY39
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AB20 VDD VDD AY40
AB22 VDD VDD AY41 1 1 1 1 1 1 1
AB24 VDD VDD AY42
AB26 VDD VDD BA35 CV181 CV182 CV183 CV186 CV180 CV184 CV213 UV3I UV3J
AB28 VDD VDD BA36
AC12 BA37 2 2 2 2 2 2 2 A40 AG19 BB3 P20
VDD VDD GND GND GND GND
AC14 VDD VDD BA38 N12E-GE_BGA1328~D AA15 GND GND AG20 C32 GND GND P22
AC16 VDD VDD BA39 AA17 GND GND AG22 C42 GND GND P24
AC18 VDD VDD BA40 AA19 GND GND AG24 D29 GND GND P26
AC25 VDD VDD BB36 AA24 GND GND AH12 E11 GND GND P38
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AC27 VDD VDD BB37 AA26 GND GND AH14 E14 GND GND P41
AD11 VDD VDD BB39 1 1 1 1 1 1 1 1 AA28 GND GND AH16 E17 GND GND P5
AD13 VDD VDD BB40 AB12 GND GND AH18 E20 GND GND P8
AD15 VDD VDD BB41 CV188 CV203 CV215 CV189 CV191 CV211 CV192 CV193 AB14 GND GND AH21 E23 GND GND R12
AD17 VDD VDD L11 A41 GND GND AH23 E26 GND GND R14
AD19 L13 2 2 2 2 2 2 2 2 AB16 AH25 E35 R16
AD20 VDD VDD L15 AB18 GND GND AH27 E38 GND GND R18
AD22 VDD VDD L17 AB21 GND GND AJ2 E39 GND GND R21
AD24 VDD VDD L19 AB23 GND GND AJ35 E41 GND GND R23
AD26 VDD VDD L20 AB25 GND GND AJ38 F36 GND GND R25
AD28 VDD VDD L22 AB27 GND GND AJ41 F37 GND GND R27
AE12 VDD VDD L24 SPARE/TEST AC11 GND GND AM2 G26 GND GND T11
AE14 VDD VDD L26 1uF - X5R 0402 x 15 under chip AC13 GND GND AM36 G31 GND GND T13
AE16 VDD VDD L28 AC15 GND GND AM38 G36 GND GND T15
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AE18 VDD VDD M12 AC17 GND GND AM41 G37 GND GND T17
AE21 VDD VDD M14 1 1 1 1 1 1 1 1 AA11 GND GND AR2 G7 GND GND T19
AE23 VDD VDD M16 AC19 GND GND AR20 H11 GND GND T20
AE25 VDD VDD M18 CV212 CV214 CV195 CV196 CV210 CV197 CV198 CV199 AC2 GND GND AR39 H14 GND GND T22
AE27 VDD VDD M21 AC20 GND GND AR41 H17 GND GND T24
AF11 M23 2 2 2 2 2 2 2 2 AC22 AT11 H2 T26
AF13 VDD VDD M25 AC24 GND GND AT14 H20 GND GND T28
AF15 VDD VDD M27 AC26 GND GND AT17 H23 GND GND U12
AF17 VDD VDD N11 AC28 GND GND AT23 H35 GND GND U14
C AF19 VDD VDD N13 AC35 GND GND AT26 H38 GND GND U16 C
AF20 VDD VDD N15 AC40 GND GND AT29 H41 GND GND U18
AF22 VDD VDD N17 AC5 GND GND AT5 L12 GND GND U2
470U_D2E_2.5VM_R9M~D
470U_D2E_2.5VM_R9M~D
AF24 VDD VDD N19 AA13 GND GND AT8 L14 GND GND U21
10U_0805_6.3V6M
10U_0805_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
22U_0805_6.3V6M~D
AF26 VDD VDD N20 1 1 AC7 GND GND AV11 L16 GND GND U23
AF28 VDD VDD N22 1 1 1 1 1 1 AD12 GND GND AV14 L18 GND GND U25
AG12 VDD VDD N24 + + AD14 GND GND AV17 L2 GND GND U27
AG14 VDD VDD N26 CV200 CV201 CV202 CV208 CV204 CV205 CV206 CV207 AD16 GND GND AV2 L21 GND GND U36
AG16 VDD VDD N28 AD18 GND GND AV20 L23 GND GND U38
AG18 P12 2 2 2 2 2 2 2 2 AD21 AV23 L25 U41
AG21 VDD VDD P14 AD23 GND GND AV26 L27 GND GND U5
AG23 VDD VDD P16 AD25 GND GND AV29 L35 GND GND U8
AG25 VDD VDD P18 AD27 GND GND AV31 L38 GND GND V11
AG27 VDD VDD P21 AE11 GND GND AV5 L41 GND GND V13
AH11 VDD VDD P23 AE13 GND GND AV8 L5 GND GND V15
AH13 P25 +VGA_CORE AE15 AY1 L8 V17
AH15 VDD VDD P27 AE17 GND GND B11 M11 GND GND V19
AH17 VDD VDD R11 AE19 GND GND B14 M13 GND GND V20
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AH22 VDD VDD R17 1 1 1 1 1 1 1 1 AE24 GND GND B23 M19 GND GND V26
AH26 VDD VDD R20 CV219 CV222 CV224 CV218 CV221 CV223 CV220 CV217 AE28 GND GND B35 M22 GND GND W12
AH28 VDD VDD R22 AF12 GND GND B38 M24 GND GND W14
AM35 R24 2 2 2 2 2 2 2 2 AF14 B41 M26 W16
AN35 VDD VDD R26 AF16 GND GND B42 M28 GND GND W18
AN36 VDD VDD R28 AF18 GND GND B8 N12 GND GND W21
AP35 VDD VDD T12 AF2 GND GND BA1 N14 GND GND W23
AR29 VDD VDD T18 AF25 GND GND BA17 N21 GND GND Y12
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AR31 VDD VDD T23 1 1 1 1 1 1 1 1 AF38 GND GND BA20 N25 GND GND Y16
AR33 VDD VDD T27 CV236 CV243 CV245 CV235 CV242 CV244 CV241 CV225 AF5 GND GND BA26 P11 GND GND Y2
AR34 VDD VDD U11 AF7 GND GND BA29 P13 GND GND Y21
AR35 U13 2 2 2 2 2 2 2 2 AG11 BA32 P15 Y23
B AR36 VDD VDD U15 AG13 GND GND BA5 P17 GND GND Y25 B
AR37 VDD VDD U17 AG15 GND GND BA8 P19 GND GND Y27
AR38 VDD VDD U19 AG17 GND GND BB2 P2 GND GND Y39
AT30 VDD VDD U20 Y7 GND GND Y5 AT6 GND GND AT7
AT31 VDD VDD U22
AT32 VDD VDD U24
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
AT33 VDD VDD U26 N12E-GE_BGA1328~D N12E-GE_BGA1328~D

AT34 VDD VDD U28 1 1 1 1 1 1 1 1
AT35 VDD VDD V12
AT36 VDD VDD V14 CV226 CV227 CV228 CV229 CV230 CV231 CV232 CV233
AT37 VDD VDD V16
AT38 V18 2 2 2 2 2 2 2 2
VDD VDD
AT39 VDD VDD V21
AU30 VDD VDD V23
AU31 VDD VDD V25
AU33 VDD VDD V27
AU34 VDD VDD W11
AU35 VDD VDD W13
AU36 W15 +3VS +3VS_DELAY +IFPE_IOVDD +IFPC_IOVDD
VDD VDD
AU37 VDD VDD W17 UV3H
AU38 VDD VDD W19 @ AJ4 PD_AJ4 AM4
PD_AM4
AU39 VDD VDD W20 1 2 AJ5 PD_AJ5 PD_AM5 AM5
AU40 W22 RV277 0_0805_5%~D +IFPEF_PLLVDD AJ7 +IFPC_PLLVDD
VDD VDD PD_AJ7 PD_AM7 AM7
AU41 VDD VDD W24
AU42 VDD VDD W26 QV5 AO3419L_SOT23-3 AK4 PD_AN4 AN4
PD_AK4
AV32 VDD VDD W28 3 1 AK5 PD_AK5 PD_AN5 AN5
S
D
10U_0805_6.3V6M
AV33 VDD VDD Y11 +3VALW AK6 AN6

+IFPF_IOVDD PD_AK6 PD_AN6
AV34 VDD VDD Y13 1 AK7 AN7
G
PD_AK7 PD_AN7
AV35 VDD VDD Y15
2
AV36 VDD VDD Y17 CV528 AL4 PD_AL4 PD_AP5 AP5

2
AV37 VDD VDD Y19 AL5 PD_AL5 AP6

2 PD_AP6
AV38 VDD VDD Y20 RV225 AL6 AP7
PD_AL6 PD_AP7
AV39 VDD VDD Y22 100K_0402_5%~D AL7 PD_AL7 AP8
AV40 Y24 PD_AP8
VDD VDD
470_0603_5%
AV41 VDD VDD Y26 PD_AR6 AR6

1
10U_0805_6.3V6M
AW33 VDD VDD Y28 AR7

PD_AR7
2
AW34 VDD 1 2 3VS_Dgate 1 AR8

PD_AR8
AW35 VDD RV278 1K_0402_5%~D RV226
6
A CV529 A
0.1U_0402_16V7K~D
N12E-GE_BGA1328~D 1
QV16A 2 N12E-GE_BGA1328~D
1
DMN66D0LDW-7_SOT363-6~D
1 2 2 DMN66D0LDW-7_SOT363-6~D CV513
<16,33,55,56> DGPU_PWR_EN
RV227 1K_0402_5%~D
2
3
1
0.1U_0402_16V7K~D
1
CV499 QV16B
5 3VS_Dgate
2
4

N12E(4/6)_Power/GND
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UV3K
IFPA_TXC AW13
IFPA_TXC AV13 UV3N
2 @ 1 IFPAB_RSET AR15 IFPAB_RSET

RV75 1K_0402_1%~D DVI-DL DVI-SL/HDMI DP
IFPA_TXD0 AT10
IFPA_TXD0 AU10
I2CY_SDA I2CY_SDA IFPE_AUX AY2
VGA_DPD_AUXN/DDC <37>
I2CY_SCL I2CY_SCL IFPE_AUX BA3 VGA_DPD_AUXP/DDC <37>
2 1 AT12 IFPAB_PLLVDD IFPA_TXD1 AW10
RV221 10K_0402_5%~D IFPA_TXD1 AV10 +3VS_DELAY +IFPEF_PLLVDD
BLM18PG331SN1D_2P~D 440mA TXC TXC IFPE_L3 BA4 VGA_DPD_N3 <37>
4.7U_0603_6.3V6M
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1 2 +IFPEF_PLLVDD AK8 IFPEF_PLLVDD IFPE_L3 BB4
TXC TXC VGA_DPD_P3 <37>
IFPA_TXD2 AW11 1 LV8 1 1 1 1 1
IFPA_TXD2 AY11 IFPE_L2 AY3
VGA_DPD_N2 <37>
D
CV510 CV238 CV239 CV509 CV240 CV234 IFPE TXD0
TXD0
TXD0
TXD0 IFPE_L2 AY4 VGA_DPD_P2 <37> D
@
AW12 2 2 2 2 2 2 2 1 AU5 AW4
IFPA_TXD3 IFPEF_RSET TXD1 TXD1 IFPE_L1 VGA_DPD_N1 <37>
IFPA_TXD3 AV12 1K_0402_1%~D RV76 IFPE_L1 AV4
TXD1 TXD1 VGA_DPD_P1 <37>
IFPE_L0 AY5
TXD2 TXD2 VGA_DPD_N0 <37>
IFPB_TXC AY18 IFPE_L0 AW5 VGA_DPD_P0 <37>
TXD2 TXD2
IFPB_TXC BA18
+1.05VSDGPU +IFPE_IOVDD
2
RV222
1
10K_0402_5%~D
AR11 IFPA_IOVDD IFPB_TXD4 BA13 BLM18PG221SN1D_2P~D 285mA +IFPE_IOVDD
IFPB_TXD4 AY13 1 2
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AR12 IFPB_IOVDD LV12 HPD_E HPD_E GPIO15 AB5
VGA_DMC_HPD <37>
1 1 1 1 1
1
IFPB_TXD5 BA15
IFPB_TXD5 AY15 CV257 CV258 CV259 CV403 CV261 RV127
@
2 2 2 2 2 +IFPE_IOVDD AJ8 100K_0402_5%~D
IFPE_IOVDD
IFPB_TXD6 BB15
2
IFPB_TXD6 BB16
+IFPF_IOVDD AL8 IFPF_IOVDD
I2CZ_SDA IFPF_AUX AW1 DISP_AUXN <38>
IFPB_TXD7 AY16 I2CZ_SCL IFPF_AUX AW2
DISP_AUXP <38>
IFPB_TXD7 BA16
+1.05VSDGPU +IFPF_IOVDD
BLM18PG221SN1D_2P~D 285mA +IFPF_IOVDD
TXC IFPF_L3 AY6
DISP_A3N_VGA <38>
1 2 TXC IFPF_L3 BA6 DISP_A3P_VGA <38>
4.7U_0603_6.3V6M
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
LV13
1 1 1 1 1 TXD3 TXD0 IFPF_L2 BB6 DISP_A2N_VGA <38>
GPIO0 AB4 IFPF_L2 BB7
TXD3 TXD0 DISP_A2P_VGA <38>
CV262 CV263 CV264 CV404 CV266
@ TXD4 TXD1 IFPF_L1 AY7 DISP_A1N_VGA <38>
N12E-GE_BGA1328~D 2 2 2 2 2 IFPF TXD4 TXD1 IFPF_L1 BA7
DISP_A1P_VGA <38>
TXD5 TXD2 IFPF_L0 BA9 DISP_A0N_VGA <38>

TXD5 TXD2 IFPF_L0 AY9
DISP_A0P_VGA <38>
C C
UV3L
HPD_F GPIO21 AE4 DP_HPD
DP_HPD <38>
2 1 IFPC_RSET AU8 IFPC_RSET
1
RV77 1K_0402_1%~D DVI/HDMI DP RV129
100K_0402_5%~D
+IFPC_PLLVDD AN8 IFPC_PLLVDD I2CW_SDA IFPC_AUX AU6 N12E-GE_BGA1328~D
HDMI_DDC_DATA <39>
I2CW_SCL IFPC_AUX AV6 HDMI_DDC_CLK <39>
IFPC
2
TXC IFPC_L3 AU7 HDMI_A3N_VGA <39>
TXC IFPC_L3 AV7 HDMI_A3P_VGA <39>
TXD0 IFPC_L2 AW6 HDMI_A2N_VGA <39>

TXD0 IFPC_L2 AW7 HDMI_A2P_VGA <39> UV3O
TXD1 IFPC_L1 AY8 2 1 AR14 DACA_VDD I2CA_SCL AK2 I2CA_SCL

HDMI_A1N_VGA <39>
TXD1 IFPC_L1 AW8 10K_0402_5%~D RV78 I2CA_SDA AK1 I2CA_SDA
HDMI_A1P_VGA <39>
AT15 DACA_VREF
IFPC_L0 AW9
TXD2 HDMI_A0N_VGA <39>
TXD2 IFPC_L0 AV9 HDMI_A0P_VGA <39> AT16 DACA_RSET DACA_HSYNC AU16
DACA_VSYNC AV16
+IFPC_IOVDD AM8 IFPC_IOVDD GPIO1 AD2 DACA_RED AW17

HDMI_HPD <39>
1
RV130 DACA_GREEN AY17

100K_0402_5%~D
N12E-GE_BGA1328~D
DACA_BLUE AW16
2
UV3M
+3VS_DELAY +IFPC_PLLVDD N12E-GE_BGA1328~D
2 @ 1 IFPD_RSET AU9 IFPD_RSET
B
RV79 1K_0402_1%~D DVI/HDMI DP BLM18PG331SN1D_2P~D 220mA +IFPC_PLLVDD
B
1 2
4.7U_0603_6.3V6M
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
LV14
2 1 AR10 IFPD_PLLVDD I2CW_SDA IFPD_AUX AV3 1 1 1 1 1 1
RV223 10K_0402_5%~D I2CW_SCL IFPD_AUX AW3 UV3P
IFPD CV405 CV406 CV407 CV408 CV409 CV511
@ 2 1 AR13 DACB_VDD I2CB_SCL AH2 I2CB_SCL
2 2 2 2 2 2 I2CB_SCL <58>
IFPD_L3 BB9 RV80 10K_0402_5%~D I2CB_SDA AH3 I2CB_SDA
TXC I2CB_SDA <58>
TXC IFPD_L3 BB10 AU13 DACB_VREF
IFPD_L2 BA10 AT13 DACB_RSET DACB_HSYNC AV15

TXD0
TXD0 IFPD_L2 AY10 DACB_VSYNC AU15
IFPD_L1 BA12 +1.05VSDGPU +IFPC_IOVDD

TXD1
TXD1 IFPD_L1 AY12 DACB_RED AW15
BLM18PG221SN1D_2P~D 285mA +IFPC_IOVDD
IFPD_L0 BB12 1 2 DACB_GREEN AY14
TXD2
4.7U_0603_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
IFPD_L0 BB13 LV15

TXD2
1 1 1 1 1 DACB_BLUE AW14
CV410 CV411 CV412 CV413 CV414

2 1 AR9 IFPD_IOVDD GPIO19 AG5 @
RV224 10K_0402_5%~D 2 2 2 2 2
1
RV274 N12E-GE_BGA1328~D
100K_0402_5%~D
N12E-GE_BGA1328~D
2
+3VS_DELAY
1 2 I2CA_SCL
RV256 2.2K_0402_5%~D
1 2 I2CA_SDA
RV257 2.2K_0402_5%~D
1 2 I2CB_SCL
A RV258 2.2K_0402_5%~D A
1 2 I2CB_SDA
RV259 2.2K_0402_5%~D

N12E(5/6)_DP/HDMI
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
+1.05VSDGPU Spare/Test NOT FOR PRODUCT ION Place close to balls

FOR LAB T EST ONLY
UV3S
LV16 150mA +GPU_PLLVDD
1 2 0.3mm
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_16V7K~D
BLM18PG330SN1D_0603 AH8 PLLVDD
1 1 1 0.3mm AH7 SP_PLLVDD
@
UV3Q CV512 CV267 CV269 0.3mm AG8 VID_PLLVDD
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
V1 2 2 2
MIOAD0 1 1 1
MIOAD1 V2
MIOAD2 W1 CV270 CV271 CV272
MIOAD3 W2
W3 2 2 2 XTAL_SSIN AU4 XTAL_OUTBUFF
MIOAD4 XTALSSIN XTALOUTBUFF AU1
D MIOAD5 Y3 D
1
MIOAD6 AA2
MIOAD7 AA1 AU2 XTALIN XTALOUT AU3 RV89
MIOAD8 AA3 RV88 10K_0402_5%~D
MIOAD9 AB1 10K_0402_5%~D N12E-GE_BGA1328~D
MIOAD10 AB2
2
AA7 MIOACAL_PD_VDDQ MIOAD11 AB3
YV1
AB7 MIOACAL_PU_GND XTALIN 3 4
OUT GND
1
RV279 2 1 XTALOUT
GND IN
0_0402_5%~D 1
W8 MIOA_VREF CV273 1
18P_0402_50V8J~D 27MHZ_16PF_X7T027000BG1H-V
2
CV274
2 18P_0402_50V8J~D
@ 2
MIOA_CTL3 W5
MIOA_HSYNC W7
MIOA_VSYNC W6
MIOA_DE W4
MIOA_CLKOUT Y4 Straps MULTI LEVEL STRAPS

MIOA_CLKOUT AA4 STRAP0
MIOA_CLKIN AA5 STRAP1
STRAP2
ROM_SI
1
N12E-GE_BGA1328~D ROM_SO
ROM_SCLK
RV260 +3VS_DELAY
10K_0402_5%~D
2
1 @ 2 1 2 strap0
RV90 5.1K_0402_5% RV91 45.3K_0402_1%
C 1 2 1 @ 2 strap1 ROM_SI C
RV92 35.7K_0402_1% RV93 10K_0402_1%~D
64MX16 Pull low with
1 @ 2 1 2 strap2 Samsung
RV94 15K_0402_1%~D RV95 30K_0402_1% RV96=20K
UV3R 64MX16 Pull low with
X76@ 1 2 1 @ 2 ROM_SI Hynix
RV96 15K_0402_5%~D RV97 5.1K_0402_1%~D RV96=15K
AH6 BBIASN_NC 128MX16 Pull low with
AH5 BBIASP_NC 1 2 1 @ 2 ROM_SO Samsung
RV100 RV98 10K_0402_1%~D RV99 5.1K_0402_1%~D RV96=45K
ROM_CS AR3 ROM_CS# 10K_0402_5%~D
1 2 @ 128MX16 Pull low with
+3VS_DELAY
1 2 1 @ 2 ROM_SCLK Hynix
ROM_SI AP1 ROM_SI RV101 15K_0402_1%~D RV102 15K_0402_1%~D RV96=35K
ROM_SO AP3 ROM_SO
STRAP0 AT1 STRAP0 ROM_SCLK AP2 ROM_SCLK
STRAP1 AT2 STRAP1
STRAP2 AT3 STRAP2 1
I2CH_SCL AG2 I2CH_SCL
I2CH_SDA AG1 I2CH_SDA CV531
68P_0402_50V8J~D
2
SSI --> Hynix
BUFRST AG7 UV3T
PGOOD_OUT_NC AH4 I2CS_SCL AK3 EC_SMB_CK2_PX

RV261 I2CS_SDA AL1 EC_SMB_DA2_PX +3VS_DELAY
1 2 AP4 MULTISTRAP_REF0_GND CEC AJ3 10K_0402_5%~D
1 2 +3VS_DELAY
RV103 40.2K_0402_1%~D I2CC_SCL AG3 I2CC_SCL
1 2 AR5 MULTISTRAP_REF1_GND I2CC_SDA AH1 I2CC_SDA
RV104 40.2K_0402_1%~D 1
@
GPU_THERMAL_D- AT4 THERMDN CV532
10P_0402_50V8J~D
2
1
GPU_THERMAL_D+ AR4 THERMDP
N12E-GE_BGA1328~D @
B
RV262 RV263 B
AL2 JTAG_TCK
AM3 JTAG_TMS GPIO2 AD3 10K_0402_5%~D 10K_0402_5%~D
2
AN2 JTAG_TDI GPIO3 AD4
AN1 JTAG_TDO GPIO4 AC3
1
AL3 JTAG_TRST GPIO5 AC4 GPU_VID0
+3VS_DELAY GPU_VID0 <56>
@ GPIO6 AD5 GPU_VID1
GPU_VID1 <56>
RV264 GPIO7 AD1
1
10K_0402_5%~D GPIO8 AE1 1 RV228 2 10K_0402_5%~D +3VS_DELAY
1
RV265 GPIO9 AE5 THM_ALERT#
2
+3VS_DELAY GPIO10 AD6 @
VGA Thermal Sensor ADM1032ARMZ 1 RV229 2 10K_0402_5%~D

GPIO11 AA6 RV107 RV108
1
10K_0402_5%~D GPIO12 AE2 AC_BATT
2
Closed to GPU RV105 RV106 GPIO13 AE6 10K_0402_5%~D 10K_0402_5%~D
2
+3VS_DELAY 2.2K_0402_5%~D 2.2K_0402_5%~D AD7 1 2
GPIO14
RV230 10K_0402_5%~D
2
+3VS_DELAY GPIO16 AE7

2
2 RV109 GPIO17 AE3

CV275 4.7K_0402_5%~D GPIO18 AF3
2
0.1U_0402_16V7K~D GPIO20 AF4

1
1
+3VS_DELAY
UV4 EC_SMB_CK2_PX 1 6 GPIO22 AB6
EC_SMB_CK2 <30,31,58>
1 8 EC_SMB_CK2_PX GPIO23 AG4
VDD SCLK
5
1
QV4A GPIO24 AG6
GPU_THERMAL_D+ 2 7 EC_SMB_DA2_PX DMN66D0LDW-7_SOT363-6~D
CV276 D+ SDATA EC_SMB_DA2_PX +3VS_DELAY RV266
4 3 EC_SMB_DA2 <30,31,58>
1 2 3 6 THM_ALERT# 10K_0402_5%~D
D- ALERT# QV4B
2
1
GPU_THERMAL_D- 2200P_0402_50V7K 4 5 1 DMN66D0LDW-7_SOT363-6~D N12E-GE_BGA1328~D AC_BATT
THERM# GND RV275
3
CV533 4.7K_0402_1%~D
ADM1032ARMZ-2REEL_MSOP8 10P_0402_50V8J~D
+3VS_DELAY 2 +3VS_DELAY
2
Address:100_1101 PACIN# 5
1 2 @ QV15B
6
RV110 4.7K_0402_5%~D 2N7002DW-7-F_SOT363-6~D
4
1 2 I2CC_SCL
A RV111 2.2K_0402_5%~D A
1 2 I2CC_SDA 2 QV15A
<51> PACIN
RV112 2.2K_0402_5%~D 2N7002DW-7-F_SOT363-6~D
1
1 2 I2CH_SCL
RV113 2.2K_0402_5%~D
1 2 I2CH_SDA
RV114 2.2K_0402_5%~D

N12E(6/6)_GPIO
C
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UV5 UV6 UV7 UV8
+VREFCA_A1 M8 E3 MDA12 +VREFCA_A1 M8 E3 MDA1 +VREFCA_A2 M8 E3 MDA33 +VREFCA_A2 M8 E3 MDA46

+VREFDA_Q1 VREFCA DQL0 MDA8 +VREFDA_Q1 VREFCA DQL0 MDA4 +VREFDA_Q2 VREFCA DQL0 MDA36 +VREFDA_Q2 VREFCA DQL0 MDA40
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDA15 VREFDQ DQL1 MDA3 VREFDQ DQL1 MDA35 VREFDQ DQL1 MDA47
F2 F2 F2 F2
MAA9 DQL2 MDA11 MAA9 DQL2 MDA5 MAA9 DQL2 MDA37 MAA9 DQL2 MDA43
<41> MDA[0..63] N3 F8 N3 F8 N3 F8 N3 F8
MAA11 A0 DQL3 MDA13 MAA11 A0 DQL3 MDA2 MAA11 A0 DQL3 MDA32 MAA11 A0 DQL3 MDA44
P7 H3 P7 H3 P7 H3 P7 H3
P3 H8 P3 H8 P3 H8 P3 H8
<41> MAA[0..31] N2 G2 N2 G2 N2 G2 N2 G2
P8 H7 P8 H7 P8 H7 P8 H7
MAA24 A4 DQL7 MAA24 A4 DQL7 MAA24 A4 DQL7 MAA24 A4 DQL7
<41> DQMA#[7..0] P2 P2 P2 P2
MAA22 A5 MAA22 A5 MAA22 A5 MAA22 A5
R8 R8 R8 R8
MAA7 A6 MDA18 MAA7 A6 MDA30 MAA7 A6 MDA58 MAA7 A6 MDA53
R2 D7 R2 D7 R2 D7 R2 D7
MAA21 A7 DQU0 MDA20 MAA21 A7 DQU0 MDA27 MAA21 A7 DQU0 MDA60 MAA21 A7 DQU0 MDA51
<41> QSA[7..0] T8 C3 T8 C3 T8 C3 T8 C3
R3 C8 R3 C8 R3 C8 R3 C8
L7 C2 L7 C2 L7 C2 L7 C2
MAA23 A10/AP DQU3 MDA17 MAA23 A10/AP DQU3 MDA28 MAA23 A10/AP DQU3 MDA57 MAA23 A10/AP DQU3 MDA52
D
<41> QSA#[7..0] R7 A7 R7 A7 R7 A7 R7 A7 D
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
T7 A3 T7 A3 T7 A3 T7 A3
MAA14 A14 DQU7 MAA14 A14 DQU7 MAA14 A14 DQU7 MAA14 A14 DQU7
M7 M7 M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU
MAA12 M2 B2 MAA12 M2 B2 MAA12 M2 B2 MAA12 M2 B2

MAA27 BA0 VDD MAA27 BA0 VDD MAA27 BA0 VDD MAA27 BA0 VDD
N8 D9 N8 D9 N8 D9 N8 D9
MAA26 BA1 VDD MAA26 BA1 VDD MAA26 BA1 VDD MAA26 BA1 VDD
M3 G7 M3 G7 M3 G7 M3 G7
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K2 K2 K2 K2
VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD CLKA0 VDD VDD VDD
<41> CLKA0 J7 N9 J7 N9 <41> CLKA1 J7 N9 <41> CLKA1 J7 N9
CK VDD CLKA0# CK VDD CK VDD CK VDD
<41> CLKA0# K7 R1 K7 R1 <41> CLKA1# K7 R1 <41> CLKA1# K7 R1
MAA3 CK VDD MAA3 CK VDD MAA19 CK VDD MAA19 CK VDD
K9 R9 K9 R9 K9 R9 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU
MAA2 K1 A1 MAA2 K1 A1 MAA18 K1 A1 MAA18 K1 A1

MAA0 ODT/ODT0 VDDQ MAA0 ODT/ODT0 VDDQ MAA16 ODT/ODT0 VDDQ MAA16 ODT/ODT0 VDDQ
L2 A8 L2 A8 L2 A8 L2 A8
MAA30 CS/CS0 VDDQ MAA30 CS/CS0 VDDQ MAA30 CS/CS0 VDDQ MAA30 CS/CS0 VDDQ
J3 C1 J3 C1 J3 C1 J3 C1
MAA15 RAS VDDQ MAA15 RAS VDDQ MAA15 RAS VDDQ MAA15 RAS VDDQ
K3 C9 K3 C9 K3 C9 K3 C9
MAA13 CAS VDDQ MAA13 CAS VDDQ MAA13 CAS VDDQ MAA13 CAS VDDQ
L3 D2 L3 D2 L3 D2 L3 D2
WE VDDQ WE VDDQ WE VDDQ WE VDDQ
E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSA1 VDDQ QSA0 VDDQ QSA4 VDDQ QSA5 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSA2 DQSL VDDQ QSA3 DQSL VDDQ QSA7 DQSL VDDQ QSA6 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
DQMA#1 E7 A9 DQMA#0 E7 A9 DQMA#4 E7 A9 DQMA#5 E7 A9

DQMA#2 DML VSS DQMA#3 DML VSS DQMA#7 DML VSS DQMA#6 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSA#1 VSS QSA#0 VSS QSA#4 VSS QSA#5 VSS
G3 J2 G3 J2 G3 J2 G3 J2
QSA#2 DQSL VSS QSA#3 DQSL VSS QSA#7 DQSL VSS QSA#6 DQSL VSS
C B7 J8 B7 J8 B7 J8 B7 J8 C
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
MAA5 VSS MAA5 VSS MAA5 VSS MAA5 VSS
T2 P9 T2 P9 T2 P9 T2 P9
RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV115 NC/ODT1 VSSQ RV116 NC/ODT1 VSSQ RV117 NC/ODT1 VSSQ RV118 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1%~OK J9 D1 243_0402_1%~OK J9 D1 243_0402_1%~OK J9 D1 243_0402_1%~OK J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
VSSQ VSSQ VSSQ VSSQ
2
2
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC11_FBGA96 K4B1G1646E-HC11_FBGA96 K4B1G1646E-HC11_FBGA96 K4B1G1646E-HC11_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B B
CV283 CV284 CV285 CV286 CV298 CV299 CV287 CV288 CV289 CV290 CV282 CV281 CV500 CV294 CV295 CV296 CV293 CV304 CV305 CV300 CV301 CV302 CV303 CV292 CV291 CV501
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU +1.5VSDGPU CLKA1
+1.5VSDGPU +1.5VSDGPU CLKA0
1
RV122 RV121 RV131
1
1.33K_0402_1%~D 1.33K_0402_1%~D 160_0402_1%

RV120 RV119 RV128
1.33K_0402_1%~D 1.33K_0402_1%~D 160_0402_1%
2
2
+VREFDA_Q2 +VREFCA_A2 CLKA1#
2
1
+VREFDA_Q1 +VREFCA_A1 CLKA0#
0.01U_0402_25V7K~D
CV280
0.01U_0402_25V7K~D
CV279
1 1
RV126 RV125
1
1.33K_0402_1%~D 1.33K_0402_1%~D
0.01U_0402_25V7K~D
CV278
0.01U_0402_25V7K~D
CV277
1 1
RV124 RV123
1.33K_0402_1%~D 1.33K_0402_1%~D 2 2
2
2
2 2
A A
2
VRAM P/N :
Samsung : SA000041T00 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA 96P )
Hynix : SA000041S20 (S IC D3 64MX16 H5TQ1G63DFR-11C FBGA 96P ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UV9 UV10 UV11 UV12
+VREFCB_A1 M8 E3 MDB13 +VREFCB_A1 M8 E3 MDB2 +VREFCB_A2 M8 E3 MDB36 +VREFCB_A2 M8 E3 MDB40

+VREFDB_Q1 VREFCA DQL0 MDB8 +VREFDB_Q1 VREFCA DQL0 MDB4 +VREFDB_Q2 VREFCA DQL0 MDB33 +VREFDB_Q2 VREFCA DQL0 MDB46
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDB12 VREFDQ DQL1 MDB3 VREFDQ DQL1 MDB38 VREFDQ DQL1 MDB43
F2 F2 F2 F2
MAB9 DQL2 MDB10 MAB9 DQL2 MDB5 MAB9 DQL2 MDB34 MAB9 DQL2 MDB47
<41> MDB[0..63] N3 F8 N3 F8 N3 F8 N3 F8
MAB11 A0 DQL3 MDB14 MAB11 A0 DQL3 MDB1 MAB11 A0 DQL3 MDB39 MAB11 A0 DQL3 MDB42
P7 H3 P7 H3 P7 H3 P7 H3
P3 H8 P3 H8 P3 H8 P3 H8
<41> MAB[0..31] N2 G2 N2 G2 N2 G2 N2 G2
P8 H7 P8 H7 P8 H7 P8 H7
MAB24 A4 DQL7 MAB24 A4 DQL7 MAB24 A4 DQL7 MAB24 A4 DQL7
<41> DQMB#[7..0] P2 P2 P2 P2
MAB22 A5 MAB22 A5 MAB22 A5 MAB22 A5
R8 R8 R8 R8
MAB7 A6 MDB18 MAB7 A6 MDB30 MAB7 A6 MDB58 MAB7 A6 MDB53
R2 D7 R2 D7 R2 D7 R2 D7
MAB21 A7 DQU0 MDB20 MAB21 A7 DQU0 MDB27 MAB21 A7 DQU0 MDB60 MAB21 A7 DQU0 MDB49
<41> QSB[7..0] T8 C3 T8 C3 T8 C3 T8 C3
R3 C8 R3 C8 R3 C8 R3 C8
L7 C2 L7 C2 L7 C2 L7 C2
MAB23 A10/AP DQU3 MDB17 MAB23 A10/AP DQU3 MDB28 MAB23 A10/AP DQU3 MDB57 MAB23 A10/AP DQU3 MDB52
D
<41> QSB#[7..0] R7 A7 R7 A7 R7 A7 R7 A7 D
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
T7 A3 T7 A3 T7 A3 T7 A3
MAB14 A14 DQU7 MAB14 A14 DQU7 MAB14 A14 DQU7 MAB14 A14 DQU7
M7 M7 M7 M7
MAB12 M2 B2 MAB12 M2 B2 MAB12 M2 B2 MAB12 M2 B2

MAB27 BA0 VDD MAB27 BA0 VDD MAB27 BA0 VDD MAB27 BA0 VDD
N8 D9 N8 D9 N8 D9 N8 D9
MAB26 BA1 VDD MAB26 BA1 VDD MAB26 BA1 VDD MAB26 BA1 VDD
M3 G7 M3 G7 M3 G7 M3 G7
K2 K2 K2 K2
VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD CLKB0 VDD VDD CLKB1 VDD
<41> CLKB0 J7 N9 J7 N9 <41> CLKB1 J7 N9 J7 N9
CK VDD CLKB0# CK VDD CK VDD CLKB1# CK VDD
<41> CLKB0# K7 R1 K7 R1 <41> CLKB1# K7 R1 K7 R1
MAB3 CK VDD MAB3 CK VDD MAB19 CK VDD MAB19 CK VDD
K9 R9 K9 R9 K9 R9 K9 R9
MAB2 K1 A1 MAB2 K1 A1 MAB18 K1 A1 MAB18 K1 A1

MAB0 ODT/ODT0 VDDQ MAB0 ODT/ODT0 VDDQ MAB16 ODT/ODT0 VDDQ MAB16 ODT/ODT0 VDDQ
L2 A8 L2 A8 L2 A8 L2 A8
MAB30 CS/CS0 VDDQ MAB30 CS/CS0 VDDQ MAB30 CS/CS0 VDDQ MAB30 CS/CS0 VDDQ
J3 C1 J3 C1 J3 C1 J3 C1
MAB15 RAS VDDQ MAB15 RAS VDDQ MAB15 RAS VDDQ MAB15 RAS VDDQ
K3 C9 K3 C9 K3 C9 K3 C9
MAB13 CAS VDDQ MAB13 CAS VDDQ MAB13 CAS VDDQ MAB13 CAS VDDQ
L3 D2 L3 D2 L3 D2 L3 D2
E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSB1 VDDQ QSB0 VDDQ QSB4 VDDQ QSB5 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSB2 DQSL VDDQ QSB3 DQSL VDDQ QSB7 DQSL VDDQ QSB6 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQMB#1 E7 A9 DQMB#0 E7 A9 DQMB#4 E7 A9 DQMB#5 E7 A9

DQMB#2 DML VSS DQMB#3 DML VSS DQMB#7 DML VSS DQMB#6 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSB#1 VSS QSB#0 VSS QSB#4 VSS QSB#5 VSS
G3 J2 G3 J2 G3 J2 G3 J2
QSB#2 DQSL VSS QSB#3 DQSL VSS QSB#7 DQSL VSS QSB#6 DQSL VSS
C B7 J8 B7 J8 B7 J8 B7 J8 C
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
MAB5 VSS MAB5 VSS MAB5 VSS MAB5 VSS
T2 P9 T2 P9 T2 P9 T2 P9
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
243_0402_1%~OK
1
1
J1 B1 J1 B1 J1 B1 J1 B1
RV133 NC/ODT1 VSSQ RV134 NC/ODT1 VSSQ NC/ODT1 VSSQ RV136 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ RV135 NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1%~OK J9 D1 243_0402_1%~OK J9 D1 J9 D1 243_0402_1%~OK J9 D1
L9 D8 L9 D8 L9 D8 L9 D8
E2 E2 E2 E2
VSSQ VSSQ VSSQ VSSQ
2
2
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
X76@ X76@ X76@ X76@
B B
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CLKB0
+1.5VSDGPU +1.5VSDGPU CLKB1
1
RV138 RV137
1
1.33K_0402_1%~D 1.33K_0402_1%~D RV146
160_0402_1% RV140 RV139 RV149
1.33K_0402_1%~D 1.33K_0402_1%~D 160_0402_1%
2
+VREFDB_Q1 +VREFCB_A1
2
2
CLKB0#
1
+VREFDB_Q2 +VREFCB_A2 CLKB1#

0.01U_0402_25V7K~D
CV308
0.01U_0402_25V7K~D
CV307
1 1
RV142 RV141
1
1
1.33K_0402_1%~D 1.33K_0402_1%~D
0.01U_0402_25V7K~D
CV310
0.01U_0402_25V7K~D
CV309
1 1
RV144 RV143
2 2 1.33K_0402_1%~D 1.33K_0402_1%~D
2
2 2
A A
2
2
VRAM P/N : Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
VRAM_DDR3 / Channel B
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
UV13 UV14 UV15 UV16
+VREFCC_A1 M8 E3 MDC15 +VREFCC_A1 M8 E3 MDC4 +VREFCC_A2 M8 E3 MDC37 +VREFCC_A2 M8 E3 MDC46

+VREFDC_Q1 VREFCA DQL0 MDC11 +VREFDC_Q1 VREFCA DQL0 MDC6 +VREFDC_Q2 VREFCA DQL0 MDC32 +VREFDC_Q2 VREFCA DQL0 MDC43
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 MDC14 VREFDQ DQL1 MDC0 VREFDQ DQL1 MDC36 VREFDQ DQL1 MDC47
F2 F2 F2 F2
MAC9 DQL2 MDC10 MAC9 DQL2 MDC2 MAC9 DQL2 MDC33 MAC9 DQL2 MDC40
<42> MDC[0..63] N3 F8 N3 F8 N3 F8 N3 F8
MAC11 A0 DQL3 MDC13 MAC11 A0 DQL3 MDC7 MAC11 A0 DQL3 MDC38 MAC11 A0 DQL3 MDC45
P7 H3 P7 H3 P7 H3 P7 H3
P3 H8 P3 H8 P3 H8 P3 H8
<42> MAC[0..31] N2 G2 N2 G2 N2 G2 N2 G2
P8 H7 P8 H7 P8 H7 P8 H7
MAC24 A4 DQL7 MAC24 A4 DQL7 MAC24 A4 DQL7 MAC24 A4 DQL7
<42> DQMC#[7..0] P2 P2 P2 P2
MAC22 A5 MAC22 A5 MAC22 A5 MAC22 A5
R8 R8 R8 R8
MAC7 A6 MDC23 MAC7 A6 MDC29 MAC7 A6 MDC61 MAC7 A6 MDC53
R2 D7 R2 D7 R2 D7 R2 D7
MAC21 A7 DQU0 MDC19 MAC21 A7 DQU0 MDC24 MAC21 A7 DQU0 MDC59 MAC21 A7 DQU0 MDC51
<42> QSC[7..0] T8 C3 T8 C3 T8 C3 T8 C3
R3 C8 R3 C8 R3 C8 R3 C8
L7 C2 L7 C2 L7 C2 L7 C2
MAC23 A10/AP DQU3 MDC20 MAC23 A10/AP DQU3 MDC28 MAC23 A10/AP DQU3 MDC57 MAC23 A10/AP DQU3 MDC52
D
<42> QSC#[7..0] R7 A7 R7 A7 R7 A7 R7 A7 D
N7 A2 N7 A2 N7 A2 N7 A2
T3 B8 T3 B8 T3 B8 T3 B8
T7 A3 T7 A3 T7 A3 T7 A3
MAC14 A14 DQU7 MAC14 A14 DQU7 MAC14 A14 DQU7 MAC14 A14 DQU7
M7 M7 M7 M7
MAC12 M2 B2 MAC12 M2 B2 MAC12 M2 B2 MAC12 M2 B2

MAC27 BA0 VDD MAC27 BA0 VDD MAC27 BA0 VDD MAC27 BA0 VDD
N8 D9 N8 D9 N8 D9 N8 D9
MAC26 BA1 VDD MAC26 BA1 VDD MAC26 BA1 VDD MAC26 BA1 VDD
M3 G7 M3 G7 M3 G7 M3 G7
K2 K2 K2 K2
VDD VDD VDD VDD
K8 K8 K8 K8
VDD VDD VDD VDD
N1 N1 N1 N1
VDD CLKC0 VDD VDD CLKC1 VDD
<42> CLKC0 J7 N9 J7 N9 <42> CLKC1 J7 N9 J7 N9
CK VDD CLKC0# CK VDD CK VDD CLKC1# CK VDD
<42> CLKC0# K7 R1 K7 R1 <42> CLKC1# K7 R1 K7 R1
MAC3 CK VDD MAC3 CK VDD MAC19 CK VDD MAC19 CK VDD
K9 R9 K9 R9 K9 R9 K9 R9
MAC2 K1 A1 MAC2 K1 A1 MAC18 K1 A1 MAC18 K1 A1

MAC0 ODT/ODT0 VDDQ MAC0 ODT/ODT0 VDDQ MAC16 ODT/ODT0 VDDQ MAC16 ODT/ODT0 VDDQ
L2 A8 L2 A8 L2 A8 L2 A8
MAC30 CS/CS0 VDDQ MAC30 CS/CS0 VDDQ MAC30 CS/CS0 VDDQ MAC30 CS/CS0 VDDQ
J3 C1 J3 C1 J3 C1 J3 C1
MAC15 RAS VDDQ MAC15 RAS VDDQ MAC15 RAS VDDQ MAC15 RAS VDDQ
K3 C9 K3 C9 K3 C9 K3 C9
MAC13 CAS VDDQ MAC13 CAS VDDQ MAC13 CAS VDDQ MAC13 CAS VDDQ
L3 D2 L3 D2 L3 D2 L3 D2
E9 E9 E9 E9
VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSC1 VDDQ QSC0 VDDQ QSC4 VDDQ QSC5 VDDQ
F3 H2 F3 H2 F3 H2 F3 H2
QSC2 DQSL VDDQ QSC3 DQSL VDDQ QSC7 DQSL VDDQ QSC6 DQSL VDDQ
C7 H9 C7 H9 C7 H9 C7 H9
DQMC#1 E7 A9 DQMC#0 E7 A9 DQMC#4 E7 A9 DQMC#5 E7 A9

DQMC#2 DML VSS DQMC#3 DML VSS DQMC#7 DML VSS DQMC#6 DML VSS
D3 B3 D3 B3 D3 B3 D3 B3
E1 E1 E1 E1
VSS VSS VSS VSS
G8 G8 G8 G8
QSC#1 VSS QSC#0 VSS QSC#4 VSS QSC#5 VSS
G3 J2 G3 J2 G3 J2 G3 J2
QSC#2 DQSL VSS QSC#3 DQSL VSS QSC#7 DQSL VSS QSC#6 DQSL VSS
C B7 J8 B7 J8 B7 J8 B7 J8 C
M1 M1 M1 M1
VSS VSS VSS VSS
M9 M9 M9 M9
VSS VSS VSS VSS
P1 P1 P1 P1
MAC5 VSS MAC5 VSS MAC5 VSS MAC5 VSS
T2 P9 T2 P9 T2 P9 T2 P9
T1 T1 T1 T1
VSS VSS VSS VSS
L8 T9 L8 T9 L8 T9 L8 T9
1
1
J1 B1 J1 B1 J1 B1 J1 B1
243_0402_1%~OK
RV151 NC/ODT1 VSSQ RV152 NC/ODT1 VSSQ NC/ODT1 VSSQ RV154 NC/ODT1 VSSQ
L1 B9 L1 B9 L1 B9 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ RV153 NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1%~OK J9 D1 243_0402_1%~OK J9 D1 J9 D1 243_0402_1%~OK J9 D1
L9 D8 L9 D8 L9 D8 L9 D8
E2 E2 E2 E2
VSSQ VSSQ VSSQ VSSQ
2
2
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
G1 G1 G1 G1
VSSQ VSSQ VSSQ VSSQ
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
B B
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU +1.5VSDGPU CLKC0 +1.5VSDGPU +1.5VSDGPU CLKC1

1
1
RV156 RV155 RV164 RV158 RV157 RV167
1.33K_0402_1%~D 1.33K_0402_1%~D 160_0402_1% 1.33K_0402_1%~D 1.33K_0402_1%~D 160_0402_1%
2
2
+VREFDC_Q1 +VREFCC_A1 CLKC0# +VREFDC_Q2 +VREFCC_A2 CLKC1#
1
1
0.01U_0402_25V7K~D
CV338
0.01U_0402_25V7K~D
CV337
0.01U_0402_25V7K~D
CV340
0.01U_0402_25V7K~D
CV339
1 1 1 1
RV160 RV159 RV162 RV161
1.33K_0402_1%~D 1.33K_0402_1%~D 1.33K_0402_1%~D 1.33K_0402_1%~D
2 2 2 2
2
2
A A

VRAM P/N : Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
VRAM_DDR3 / Channel C
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V ) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
Power block
CPU OTP
D D
Page 59
Turn Off
Input B+
DC IN Switch Page 51 +3VALWP: TDC:4.8A efficiency: 93%
Always
+5VALWP: TDC:6A efficiency: 90%
RT8205E Page 52
CHARGER
CC:0A~3A +1.8VP: TDC:1.25A SUSP#
C
CV:14.8V(8cell) RT8209B efficiency: 88% C
ISL6251AHAZ-T Page 54
Page 51
+VCCPP: TDC:12.8A SUSP#
Battery RT8209B efficiency: 82% Page 54
+1.5VSDGPUP: TDC:5.6A DGPU_PWR_EN

RT8209B efficiency: 83% Page 55
+GPU CORE efficiency: 88%

DGPU_PWR_EN
TDC:36.8A +1.5VP: TDC:7A SYSON
B ISL6264CRZ-T RT8209B efficiency: 84% B
Page 56
Page 53
+0.75VSP: TDC:1A +3VALW

RT9026
CPU CORE efficiency: 86% Page 53
VR_ON
TDC: 52A
ISL95831CRZ-T +VCCSAP: TDC:4.2A VTTPWRGOOD
Page 57
RT8209B efficiency: 80%
Page 55
GFX CORE efficiency: 85%

A
VR_ON
TDC: 21.5A +1.5VSP: TDC:1.26A SUSP# A
ISL95831CRZ-T RT8209B efficiency: 89%

Page 57 Page 53

POWER BLOCK DIAGRAM
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
PL1
BLM18BD102SN1D_0603~D
PSID 2 1 DETECT_PSID
ADPIN VIN
@ PJDCIN PL2
5 C8B BPH 853025_2P
DETECT
9
GND_4
1 1 2 PreCHG @ PQ1
D DC+_1 D
8
GND_3 VIN @ PR1 TP0610K-T1-E3_SOT23-3
B+
2 1K_1206_5% @ PD1
DC+_2
1 2 2 1 3 1
7 3
GND_2 DC-_1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
@ PR2 RLS4148_LL34-2
100P_0402_50V8J~D
100P_0402_50V8J~D
6 4 1K_1206_5%
GND_1 DC-_2
1
PC2
PC4
1 2
470K_0402_5%
470K_0402_5%
PC1
PC3
1
@ PR3
2
FOX_JPD113D-DB570-7F 1K_1206_5%
PR4
PR5
2
1 2
@ @
@ PR6
2
1K_1206_5%
1 2
1
@PR7
@ PR7
470K_0402_5%
1 2
@ PQ2
+5VALW +3VALW @ PD2 DTC115EUA_SC70-3
<31,51> ACOFF 2 @ PQ3
1 2 DTC115EUA_SC70-3
+5VALW 3
DA204U_SOT323~D
2
RB715F_SOT323-3
PR8
3
2.2K_0402_5%
@ 0_0402_5%
PD3
1 2
3
2
del 12/13
design change
PR9
PR10
1
33_0402_5%
1
DETECT_PSID 1 3 2 1
D
S
PS_ID <31>
PQ4
C FDV301N_NL_SOT23-3~D C
G
2
100K_0402_1%
+5VALW
2
+5VALW
DA204U_SOT323~D
PR11
10K_0402_1%
1
2
PD5
1
2
PR12
C
2 PQ5
15K_0402_1%
B MMST3904-7-F_SOT323~D @
2
E
3
2
PR13
1
@
1
PD4 PR14
SM24_SOT23 1 2 PSID_DISABLE#
1
10K_0402_1% @ PR26
+3VALW 0_0402_5%
2 1
VIN
1000P_0402_50V7K~D
2
1
@ PR17 VL
1000P_0402_50V7K~D
PD6 0_0402_5% PR16
RLS4148_LL34-2 <31> Dyn_Turbo_Sel 2 1 10K_0402_1%
PC23
@ PR24
1
PC8
PD7 0_0402_5%
2
RLS4148_LL34-2 PR19 <51> EMC_THERM# 2 1
2 1 PU1A @ 0_0402_5%
BATT+
1
2
PR18 68_1206_5% PR25 LM393DR_SO8 PR21
1
0_0402_5% D 3 2 1
ADP_I <31,51>
P
+
Pre_V 68_1206_5% VS <31,57> VR_HOT# 2 1 2 1
PQ6 0
G 2 2 1
- AC_SEL <31>
1000P_0402_50V7K~D
G
TP0610K-T1-E3_SOT23-3 S PQ12
2
3
SSM3K7002FU_SC70-3 PR20
1
Pre_V 3 1 add 01/06 0_0402_5%
0.22U_0603_25V7K~D
PC7
B design change B
32.7
2
1
@
1
PR22 PC10
100K_0402_5%
PC9
0.1U_0603_25V7K~D modify 10/07

2
PR23 design change

2
22K_0402_5%
<29> 51ON# 1 2
@ PU2
+CHGRTC MAX1615EUK+_SOT23-5~D PR27
@
1 1 2
IN
1U_0603_25V6-K~D
3
OUT
4.7U_0603_6.3V6K~D
200_0805_5%
1
5
#SHDN
1
PC12
4
GND
5/3+
PC11
2
2
@
2
revise 9/17
A
reduce S5 loss A
PBJ1
1 +RTCBATT +RTCBATT
1
2
2
MOLEX_53261-0271~D
SP020009Z0L
CONN@ modify 10/21
for ME request
PWR-DCIN / Vin Detector
C
LA-6801P 1.0
5 4 3 2 1
A B C D
Iada=0~7.693A(150W/19.5V=7.693A) add 10/19 add 01/20

for EMI request for EMI request
CP = 90%*Iada ; CP = 6.92A
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
ADP_I = 19.9*Iadapter*Rsense
PL102
1
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
PC126
PC128
PC129
PQ101
SI4459ADY-T1-GE3_SO8 P2
PQ102
SI4459ADY-T1-GE3_SO8 P3 PR101
B+ 1 2 CHG_B+ PQ103
SI4459ADY-T1-GE3_SO8
2
0.01_2512_1% @ @ PJP101
VIN 8 1 1 8 1 4 2
2 1
1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5
EMC_SENSE-
2200P_0402_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0603_25V7K~D
CSIP PR103
5600P_0402_25V7K~D
4
4
1
1
47K_0402_1%
PC102
PC103
VIN PreCHG
1 1
VIN
PC104
PC105
1 2
EMC_SENSE+ swap 12/13 PR102 @ PR104
PC101
2
1
3
design change 1 2 1 2
1
1
2
6251VDD
PR105 0_0402_5% 0_0402_5% @ PD101
200K_0402_1% PR108 1 2 ACOFF
0.1U_0603_25V7K~D
1
2
2 PR106 ACSETIN PR107 10K_0402_1%
200K_0402_1% 191K_0402_1% 1SS355_SOD323-2
PC106
2.2U_0603_6.3V6K~D
2
PD102 del 12/21 @ PR109
1 1
BAT_DIS_G
RB751V-40TE17_SOD323-2 ACSETIN 200K_0402_1%
1000P_0402_50V7K~D
PC107
design change
1
1 2 VIN
1 1
15K_0402_1%
1
1
V1 2 PQ104 PD103 1SS355_SOD323-2
10_1206_5%
PC108
2
DTA144EUA_SC70-3 PQ106 @ PD104
PR110
PR111
1 2
DTC115EUA_SC70-3 2 1 2
2
PQ105 PR112
2200P_0402_50V7K~D
2
DTC115EUA_SC70-3 10K_0402_5% 1SS355_SOD323-2
3
1
2 1 PU101 PC111
<31> FSTCHG 0.1U_0603_25V7K~D
PC109
0.1U_0603_25V7K~D
3
D
1
1 2 1 24 DCIN 2 1
SSM3K7002FU_SC70-3
VDD DCIN
2
1
1
PR114 0_0402_5% PC110 2 PACIN
100K_0402_1%
PC112
6251VDD .1U_0402_16V7K~D @
PQ110
1 2 G
PR113 ACPRN @ PQ107
PR115
2 23 ACPRN <52> S
ACSET ACPRN
3
D
1
150K_0402_1% revise 10/25 PR116 PR117 @ SSM3K7002FU_SC70-3
6
D 20_0402_5% 100K_0402_1% 2
2
2
2 6251_EN 3 22 1 2 CSON V1 2 1 G
EN CSON
2
G PQ108A PC113 S
3
5
6
7
8
DMN66D0LDW-7_SOT363-6 0.047U_0603_16V7K~D @
S 4 21 1 2 CSOP del 12/13
CELLS CSOP
1
1
PR118 ACPRN
design change
PC114 6800P_0402_25V7K~D 20_0402_5% PQ111
1 2 5 20 2 1 AO4466L_SO8
ICOMP CSIN
3
2
2 D PR119 4 2
5 PC116 20_0402_5%
G PQ108B 1 2 1 PR120 2 10K_0402_1% 6 19 0.1U_0603_25V7K~D
1 2
VCOMP CSIP
1
PR122 DMN66D0LDW-7_SOT363-6 PR123 PR121 PL101 PR124
47K_0402_1% S PC115 1 2 100_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% 0.02_1206_1% BATT+
4
3
2
1
PACIN 1 2 0.01U_0402_25V7K~D PC117 1 2 7 18 LX_CHG 1 2 CHG 1 4
<45> PACIN ICM PHASE
@ 100P_0402_50V8J~D
4.7_1206_5%
5
6
7
8
1
<31,50> ADP_I 6251VREF 2 3
PC118 6251VREF DH_CHG
PR125
8 17
PR126 VREF UGATE PR127 PC119
1 2
147K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
2 1 .1U_0402_16V7K~D 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ112
<31> IREF CHLIM BOOT
2
1
4 AO4466L_SO8
0.01U_0402_25V7K~D
1
1
PQ113
PC124
PC121
PC125
PC122
1
DTC115EUA_SC70-3 PR128 6251aclim 6251VDDP PD105
680P_0402_50V7K~D
PC120
10 15
100K_0402_1% PR129 ACLIM VDDP RB751V-40TE17_SOD323-2
PC123
2
2
6251VREF
1 2 1 26251VDD
3
2
1
2
ACOFF 2 +3VALW 11 14 DL_CHG
<31,50> ACOFF VADJ LGATE
2
6251VREF
2
11.5K_0402_1% PR130
1
4.7_0603_5%
10K_0402_1%
2
PR131 12 13 PC127
GND PGND
1
6.98K_0402_1% 4.7U_0603_6.3V6K~D
PR143
1 2
3
@ PR142
4.53K_0402_1% ISL6251AHAZ-T_QSOP24
2
D
1
<31> CP_SEL @
1
2 PQ115
G SSM3K7002FU_SC70-3
@ PR132
.1U_0402_16V7K~D
S
3
2
25.5K_0402_1%
PC133
<31> CHGVADJ 1 2
1
@
2
3 modify 10/06 3
PR133 customer request

43.2K_0402_1%
1
reserve 12/07
6251VDD
CP point select
PR136 PU102
EMC1701-2-AIZL-TR_MSOP10
2
10K_0402_1%
1
1 2 ACIN <31,34>
N/C
EMC_SENSE-
CP mode PR134
47K_0402_1% PR135
3
SENSE- SMCLK
1 PCH_SMLCLK <14,31>
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) 10K_0402_1%
PACIN
EMC_SENSE+ 4
SENSE+ SMDATA
10
PCH_SMLDATA <14,31>
Vaclim=2.39*((6.98K//152K)/((11.5K//152K)+(6.98K//152K)))
2
1 2
+5VS 5 9 1 2 EMC_ALERT# <31>

VDD ALERT#
ADDR_SEL
@ PR141
PQ114 8 0_0402_5%
1U_0402_6.3V6K~D
.1U_0402_16V7K~D
THERM# EMC_THERM# <50>
2
DTC115EUA_SC70-3
PC131
PC132
GND
1
ACPRN
CC=3.3A
10K_0402_1%
10K_0402_1%
2
1
1
PR139
PR140
6
7
PR137
14.3K_0402_1%
IREF=1*Icharge @ @
3
2
1
20K_0402_1%
2
IREF=0.25V~3.3V
PR138
CHGVADJ CV mode
2
+3VS
4
0V 3.99V per cell 4
slave address : 0101101

BATT Type Charging Voltage CV mode please placemnet near R-sense
1.93V 4.2V per cell
(0x15)
Normal 4S LI-ON Cells

3.3V 4.35V per cell
14800mV 14.80V Security Classification Compal Secret Data Compal Electronics, Inc.
PWR-CHARGER
Custom
LA-6801P 1.0

A B C D
5 4 3 2 1
2VREF_RT8205E
Note:
1U_0603_10V6K~D
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
1
D D
PC201
2
PR201 PR202
13K_0402_1% 30K_0402_1%
add 01/20 1 2 1 2
for EMI request
PR203 PR204
RT8205E_B+ 20K_0402_1% 20K_0402_1%
1.2UH_1231AS-H-1R2N=P3_2.9A_30% 1 2 1 2 RT8205E_B+
PL201 Typ: 175mA
HCB2012KF-121T50_0805 PL204
B+ 1 2 1 2 +3VLP
ENTRIP2
ENTRIP1
PR205 PR206
2200P_0402_50V7K~D
2200P_0402_50V7K~D
10U_0805_25V6K~D
0.1U_0603_25V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0603_25V7K~D
1
PJP205 71.5K_0402_1% 88.7K_0402_1%

680P_0402_50V7K~D
PC202
PC203
PC210
2 1 1 2 1 2
4.7U_0805_10V6K
2 1
1
1
PC222
PC204
PC205
PC206
PC207
PC208
PC209
2
@ JUMP_43X118
8
7
6
5
5
6
7
8
@
2
2
@ PQ201
PC211
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
AO4466L_SO8
25
P PAD
2
4 4
reserve 01/21 7 24
C VO2 VO1 SPOK <59> C
8 23 PR208 PC213 PQ202
PR207 VREG3 PGOOD 2.2_0603_5% .1U_0402_16V7K~D AO4466L_SO8
1
2
3
3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL202 PC212 UG_3V 10
VFB=2.0V 21 UG_5V PL203
4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D .1U_0402_16V7K~D UGATE2 UGATE1 4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
3.3VALWP LG_3V 12 19 LG_5V
4.7_1206_5%
4.7_1206_5%
LGATE2 LGATE1
5
6
7
8
PR209
PR210
TDC 4.8 A
SKIPSEL
VREG5
1 2 PU201
330U_D_6.3VM_R18M~D
330U_D_6.3VM_R18M~D
Peak Current 8.93 A <30,59> MAINPWON
GND
RT8205EGQW_WQFN24_4X4
VIN
EN
NC
1 1
2
2
PR211 @ PR221
OCP current 10.67 A +
4
@ 499K_0402_1% 0_0402_5% +
PC214
PC217
4
13
14
15
16
17
18
1
1
reserve 10/06
680P_0402_50V7K~D
680P_0402_50V7K~D
B+ 1 2
PQ203
PC215
PC216
2 SI4634DY-T1-E3_SO8 PR212 PQ204 2
2
1
2
3
2
PJP201 499K_0402_1% SI4634DY-T1-E3_SO8
3
2
1
2 1 VS 1 2
2 1
1
100K_0402_1%
1 2
1U_0603_10V6K~D
VL
1
@ JUMP_43X118 PR215
PC218
1
@ 499K_0402_1% PR213 PR214 Typ: 175mA
PC219
4.7U_0805_10V6K
2
PJP202 @ 0_0402_5%
0_0402_5%
Pre_V 1 2
PR222
+3VALWP 2 1 +3VALW
2 1
2
2
@ JUMP_43X118 ENTRIP1 ENTRIP2
PJP203
1
2 1
RT8205E_B+ 2 1
0.1U_0603_25V7K~D
6
D D reserve 10/27 @ JUMP_43X118
2
B PJP204 B
PC220
2 5
PQ205A G G 2VREF_RT8205E +5VALWP 2
2 1
1 +5VALW
DMN66D0LDW-7_SOT363-6
S S PQ205B @ JUMP_43X118
1
DMN66D0LDW-7_SOT363-6
2 1
5VALWP
VL PR216 TDC 6A
100K_0402_1%
Peak Current 11.24 A
1
PR217
<30,59> MAINPWON
1 2
OCP current 13.24 A
0_0402_5%
2
1 2
VS PR218
100K_0402_1% PQ206
40.2K_0402_1%
2.2U_0603_10V6K~D
D
1
DTC115EUA_SC70-3
3
1
PR220
PC221
<51> ACPRN 1 2 2
G
1
PR219 S
3
200K_0402_1%
2
<29,31> EC_ON 2
PQ207
SSM3K7002FU_SC70-3
PQ208
3
DTC115EUA_SC70-3
A A

3VALWP/5VALWP
Custom
LA-6801P 1.0

5 4 3 2 1
A B C D
modify 10/20
for EMI request
PL301
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
1.5V_B+ 1 2
PJP301
B+
2200P_0402_50V7K~D
1
0.1U_0603_25V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1 2 @ PC302
1 2 680P_0402_50V7K~D
@
JUMP_43X79
2
1
1
5
6
7
8
PC301
PC303
PC304
PC305
PC306
2
2
@
PR301
1
267K_0402_1% 4 1
PR302 1 2
0_0402_5%
1 2 PQ301
<27,31,33> SYSON SI4172DY-T1-GE3_SO8
3
2
1
PR303 PC307 PL302
2.2_0603_5% 0.1U_0603_25V7K~D 1UH_PCMB062D-1R0MS_9A_20%
15
14
+1.5VP
1
PU301 BST_1.5V 1 2 BST_1.5V-1 1 2 1 2
PC308
EN/DEM
BOOT
NC
.1U_0402_16V7K~D
2
2 13 DH_1.5V
TON UGATE
10U_0805_6.3V6M~D
.1U_0402_16V7K~D
220U_D2_2VY_R15M
220U_D2_2VY_R15M
1 1 PJP302
1
3 12 LX_1.5V 2 1
VOUT PHASE 2 1
5
6
7
8
1
PC310
PC311
+
PC312
PR304 +
VFB=0.75V +5VALW
PC309
4 11 1 2 4.7_1206_5% @ JUMP_43X118
VDD CS PR305
2 2
2
5 10 6.49K_0402_1% +1.5VP PJP303 +1.5V
FB VDDP
2
2 1
2 1
1
6 9 4
PGOOD LGATE
PGND
PR306 PC313 @ JUMP_43X118
GND
1
10_0603_5% 4.7U_0805_10V6K PC314 @
2
1 2 PQ302 680P_0402_50V7K~D
+5VALW RT8209MGQW_WQFN14_3P5X3P5 DL_1.5V SI4634DY-T1-E3_SO8
3
2
1
2
1
PC316
1.5VP
1U_0603_10V6K~D TDC 7 A
2
PR307
Peak Current 10 A
1 2 OCP current 12 A
10K_0402_1%
1
Low Side MOS RDS(on)=5.5m ohm(Typ),6.7m ohm(Max)
PR308 DDR GPIO Output Voltage Selection
1
10K_0402_1%
2 add 12/20 PR312 2
2
+3VALW 75K_0402_1% bit2 = 1.5DDR_VID0 bit1 = 1.5DDR_VID1 DDR Vout
design change
1
0 0 1.65V
PR313
DMN66D0LDW-7 2N SOT363-6
10K_0402_5%
6
+3VALW
0 1 1.6V
PQ303A
2
PR314 2 add 12/13 1 0 1.55V

1
10K_0402_5%
for EE request
10K_0402_5%
0.01U_0402_25V7K~D
+3VALW
1 1 1.5V (Default)
3
PC325
PR316 PQ303B
<16> 1.5VDDR_VID0
2
1
PR315
10K_0402_5%
1 2 5 PR309
2
1.2K_0402_1%
2
1
1
0.01U_0402_25V7K~D
1
4
10K_0402_5%
PR317
PC326
PR318
2
150K_0402_1%
2
1
@
2
PR310
1K_0402_1% PU302
RT9026_MSOP10
2
+3VALW
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
1U_0603_10V6K~D
1 10 +3VALW
VDDQSNS VIN
PJP304
1
1
PC319
2
PR319 VLDOIN
+1.5VP 1 2
1 2
1
10K_0402_5%
6
2
+3VALW
PC317
PC318
@ 8
PQ304A JUMP_43X79 GND
6
VTTREF
2
2
3
VTT
1
PR320 2 +0.75VSP @
1
10K_0402_5%
3
5 9 3
VTTSNS S5
4.7U_0805_6.3V6K~D
4.7U_0805_6.3V6K~D
PC320
3
PGND
7 .1U_0402_16V7K~D
GND
S3
2
10K_0402_5%
0.01U_0402_25V7K~D
PR321 PQ304B PR311

<16> 1.5VDDR_VID1
2
10K_0402_5% 10K_0402_5%
1
PC321
PC322
1 2 5 2 1
1
11
PR322
PC327
1
0.01U_0402_25V7K~D
4
1
@ PC323 SUSP# <10,18,31,33,54>

1
2
PC328
@ PR323 .1U_0402_16V7K~D
2
2
10K_0402_5%
2
2
PJP305
add 12/20
+0.75VSP 1 2 +0.75VS
design change 1 2
@
JUMP_43X79
PL303
4
@ PJP306 1UH_PCMC063T-1R0MN_11A_20%
2 1 1.5VS_PIN 10 2 LX_1.5VS 1 2
+5VALW +1.5VSP
PG
2 1 PVIN LX
2
JUMP_43X79 9 3
PVIN LX PR324
1
PC329
10U_0805_10V6K~D
PC330
10U_0805_10V6K~D
8
SVIN
4.7_1206_5%
+1.5VSP
Imax=1.26A
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
6
FB
2
2 1
5 1.5VS_SNB
EN Ipeak=1.8A
1
1
NC
NC
TP
PC332
PC333
PC331
680P_0603_50V7K~D Iocp(minimum)=4A
11
EN_1.5VS
4 4
1 2
<10,18,31,33,54> SUSP# PJP307
1U_0402_6.3V6K~D
PR325 1.5VS_FB 1 2 +1.5VSP 1 2 +1.5VS

1 2
2
PC334
0_0402_5%
1
PR326 PR327 @
JUMP_43X79
1
1M_0402_1% PU303 15.8K_0402_1%

@ RT8061AZQW_WDFN10_3X3 2 1
2
PR328
1
10.5K_0402_1% PC335
68P_0402_50V8J~D
2

PWR-+1.5VP/+0.75VSP/+1.5VSP
C
LA-6801P 1.0
A B C D
5 4 3 2 1
revise 10/25
design change
VCCPP @ PL401
HCB2012KF-121T50_0805
PR401
0.01_1206_1%
TDC 12.8 A VCCP_B+ 1 2 1 4
B+
Peak Current 18.3 A
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
PJP401 2 3
1
2 1 @ PC401
OCP current 22.4 A 2 1 680P_0402_50V7K~D
1
PC404
PC405
PC406
@ JUMP_43X118
2
PC402
PC403
CPU_IN_B+
2
Low Side MOS RDS(on)=2.6m ohm(Typ),3.2m ohm(Max) @
D D
<58> CPU_VIN-
<58> CPU_VIN+
5
PR402
267K_0402_1%
1 2
PR403
0_0402_5% 4
1 2 PQ401
<10,18,31,33,53> SUSP# AON6414AL-1N_DFN
1
PR404 PC408
15
14
1
@ PC407
@PC407 PU401 2.2_0603_5% 0.1U_0603_25V7K~D PL402
3
2
1
.1U_0402_16V7K~D BST_VCCP 1 2BST_VCCP-1 1 2 0.42UH_FDUE0640-R42M_20.2A_20%~D
+VCCPP
EN/DEM
BOOT
NC
2
2 1
2 13 DH_VCCP
TON UGATE
1
3 12 LX_VCCP
VOUT PHASE PR406
10U_0805_6.3V6M~D
.1U_0402_16V7K~D
330U_D2_2.5VY_R9M
4 11 1 2 1
VDD CS
+5VALW
AON6702L-1N_DFN8
5.9K_0402_1% PR405
1
5 VFB=0.75V 10 4.7_1206_5% +
FB VDDP
1 2
2
4
PC409
PC410
PC413
PR408 6 9
PGOOD LGATE 2
2
PGND
PQ402
10_0603_5% PC414 PR407
GND
+5VS 1 2 4.7U_0805_10V6K 10_0402_5%
+5VALW
2
PC411
3
2
1
1
RT8209MGQW_WQFN14_3P5X3P5 DL_VCCP 680P_0402_50V7K~D
2
8
PR409 PC415
@ 10K_0402_5% 1U_0603_10V6K~D
2
revise 01/11 Output voltage is adjusted to 1.06V
VCCP_AGND
@ PR410 PR411 PR412
EE request from EE requirement at 2011/01/11
1
1 2 2 1 0_0402_5%
10K_0402_5%
100K_0402_5%
2
0.01U_0402_16V7K~D
0_0402_5% @ PR414 PR415
1
PR413
35.7K_0402_1% 4.12K_0402_1%
1
1
PC417
C 3 1 1 2 1 2 PJP402 C
2 1
S
2 1
<8> VCCP_PWRCTRL @ PR418 PR419
2
1
@ @ @ PQ403 0_0402_5% 0_0402_5% @ JUMP_43X118
PR417 <9> VSSIO_SENSE 1 2 VCCP_AGND 2 1 VCCIO_SENSE <9>
2
SSM3K7002FU_SC70-3 PR416 1 2 +3VS +VCCPP PJP403 +VCCP

10K_0402_1% 2 1
10K_0402_1% 2 1
2
<55> VTTPWRGOOD @ JUMP_43X118
2
@ PR426 PJP406 +1.05VS
PR420 1 2 +3VALW 2 1
2 1
10K_0402_1%
@ 10K_0402_1% @ JUMP_43X118
1
reserve 01/11
PU402
RT8061AZQW_WDFN10_3X3
PL403
4
@ PJP404 1UH_PCMC063T-1R0MN_11A_20%
2 1 1.8VS_PIN 10 2 LX_1.8VS 1 2
+5VALW +1.8VSP
PG
2 1 PVIN LX
2
JUMP_43X79 9 3
PVIN LX PR421
1
PC419 1 PC420 8 4.7_1206_5%

10U_0805_10V6K~D 10U_0805_10V6K~D SVIN
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
6
FB
2
2 1
5 1.8VS_SNB
EN
1
NC
NC
TP
B B
PC422
PC423
PC421
680P_0603_50V7K~D
11
2
1 2 EN_1.8VS
<10,18,31,33,53> SUSP#
1U_0402_6.3V6K~D
PR422 1.8VS_FB 1 2
2
PC424
0_0402_5% 1
PR424 PR423
1
1M_0402_1% 28.7K_0402_1%
@ 2 1
2
PR425
1
14.3K_0402_1% PC425
68P_0402_50V8J~D
2
PJP405
+1.8VSP 2 1 +1.8VS
2 1
@ JUMP_43X118
1.8VSP
TDC 1.25 A
Peak Current 1.75 A
OCP current 4 A
A A

PWR+VCCPP/+1.8VSP
C
LA-6801P 1.0
5 4 3 2 1
5 4 3 2 1
PJP501
VCCSAP_B+ 2 1
D 2 1 CPU_IN_B+ D
@ JUMP_43X79
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1
1
+VCCSAP
PC501
PC502
PC503
PC504
TDC 4.2A
2
Peak Current 6 A
PR501
267K_0402_1% 4 PQ501 OCP current 7.2 A
PR502 1 2 AON7408L_DFN8-5
0_0402_5%
<54> VTTPWRGOOD 1 2
3
2
1
PR503 PC507 PL502
2.2_0603_5% 0.1U_0603_25V7K~D 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
15
14
1
1
PU501 BST_SAP 1 2BST_SAP-1 1 2 2 1 +VCCSAP
@ PC506
@PC506
330U_D2_2.5VY_R9M
EN/DEM
BOOT
NC
.1U_0402_16V7K~D
2
2 13 DH_SAP
TON UGATE
10U_0805_6.3V6M~D
.1U_0402_16V7K~D
1
1
PR504 3 12 LX_SAP
VOUT PHASE
1
PC510
+
PC508
10_0603_5% PR506
PC509
+5VALW
1 2 4
VDD VFB=0.75V CS
11 1 2 +5VALW 4.7_1206_5%
PR505 PR508
2
1
2
10_0402_5%
5 10 10.7K_0402_1% PQ502 0_0402_5%
FB VDDP
PR507
PC511 4 SI7716ADN-T1-GE3_POWERPAK8-5 1 2
1
1U_0603_10V6K~D 6 9
PGOOD LGATE
2
VSSSA_SENSE <10>
PGND
PC512
GND
1
4.7U_0805_10V6K PC513
1
680P_0402_50V7K~D
3
2
1
RT8209MGQW_WQFN14_3P5X3P5 DL_SAP
2
+VCCSAP PJP502 +VCCSA
C 2 1 C
PR510 2 1
PR509
+3VS 0_0402_5% @ JUMP_43X118
1 2 1 2
1
PR526 VCCSA_SENSE <10>

2K_0402_1%
2
10K_0402_5%
1
PR511 PR512 1 2
<10> VCCSA_SEL 10K_0402_5% 15K_0402_1%
+3VS
PR513
2
30K_0402_1%
VID[0] VID[1] VCCSA Vout Required on 2011 / 2012 Required
1
PR514 PR527
2
1
10K_0402_5% D
0_0402_5%
1 2 2 0 0 0.9V Yes / Yes
G
0 1 0.8V Yes / Yes
1
1
PMBT2222A_SOT23-3
PR515 S PQ503
3
1
1
100K_0402_5%
1 2 2 SSM3K7002FU_SC70-3
.1U_0402_16V7K~D
PQ504
PR516
PC515
2
0_0402_5%
3
@ PR517
@ @ <31> SA_PGOOD
2
10K_0402_5%
1
@ PL503
HCB2012KF-121T50_0805
1.35V_B+ 1 2
GPU_IN_B+
PJP503
2200P_0402_50V7K~D
1
0.1U_0603_25V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2 1 @ PC516
2 1 680P_0402_50V7K~D
@ JUMP_43X79
2
B B
5
6
7
8
PC517
PC518
PC519
PC520
PC521
2
2
@
PR518
267K_0402_1% 4
@ PR519 1 2
100K_0402_1% revise 9/21
1 2 RF request PQ505
<16,33,43,56> DGPU_PWR_EN AO4466L_SO8 Output voltage is adjusted to 1.54V
3
2
1
PR528 PR520 PC522 PL504 from EE requirement at 2011/01/11
0_0402_5% 2.2_0603_5% 0.1U_0603_25V7K~D 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
15
14
+1.5VSDGPUP
1
1 2 PU502 BST_1.35V 1 2BST_1.35V-1 1 2 1 2

<56> VGA_PWROK PC523
EN/DEM
BOOT
NC
.1U_0402_16V7K~D
2
2 13 DH_1.35V
TON UGATE
10U_0805_6.3V6M~D
.1U_0402_16V7K~D
add 10/19 PJP504
220U_D2_2VY_R15M
220U_D2_2VY_R15M
1 1
1
3 12 LX_1.35V 2 1
for EE request VOUT PHASE 2 1
5
6
7
8
1
+ +
PC527
PC525
PC526
PR521
VFB=0.75V +5VALW
PC524
4 11 1 2 4.7_1206_5% @ JUMP_43X118
VDD CS PR522
2 2
2
5 10 5.76K_0402_1% PJP505
FB VDDP
2
+1.5VSDGPUP 2 1 +1.5VSDGPU
2 1
1
6 9 4
PGOOD LGATE
PGND
PR523 PC528 @ JUMP_43X118

GND
1
10_0603_5% 4.7U_0805_10V6K PC529 @
2
1 2 PQ506 680P_0402_50V7K~D
+5VALW RT8209MGQW_WQFN14_3P5X3P5 DL_1.35V SI4634DY-T1-E3_SO8
7
3
2
1
2
1
PC531 revise 01/11

1.5VSDGPUP (for VRAM)
1U_0603_10V6K~D
for EE request TDC 5.6 A
2
revise 9/21
PR524 RF request Peak Current 8 A
1 2 OCP current 9.6 A
A A
10.5K_0402_1%
PR529
1
10K_0402_5%
1 2 +3VS
PR525
10K_0402_1%
2
2
PR530
0_0402_5%

1
add 10/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+VCCSAP/+1.5VSDGPUP
<16,17,38,39,56> DGPU_PWROK Size Document Number Rev
for EE request AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
LA-6801P 1.0
5 4 3 2 1
5 4 3 2 1
+3VS_DELAY
modify 8/11
2
+3VS_DELAY
<16,33,43,55> DGPU_PWR_EN
N12E-GE-B PR647 PR604
PR609
10K_0402_5%
2 1 2 1 PR644
(N11E-GE for SSI) 0_0402_5%
1
0_0402_5% @ 10K_0402_1% 1 2 GPU_VID1 <45>
GPU_VID1 GPU_VID0 VGA_CORE
add 10/19 +3VS_DELAY
1 1 0.825V for EE request +3VS_DELAY revise 10/25
0 0 0.875V design change
2
GPU_VID0 <45>
.1U_0402_16V7K~D
2
PR610
0 1 0.925V
2
PC634
10K_0402_5% PR645 PL601 PR601
+3VS 10K_0402_5% HCB2012KF-121T50_0805 0.01_1206_1%
VGA_B+ 1 2 1 4
D
B+ D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2200P_0402_50V7K~D
1
PR648 +3VS_DELAY PQ610 PR646 2 3
1
0_0402_5% D SSM3K7002FU_SC70-3 0_0402_5%
1
PC602
PC603
PC604
add 10/19 2 1 +3VS +3VS_DELAY 2 1 2
<55> VGA_PWROK
PC601
PR602 G
for EE request 10K_0402_5% S
2
5
@ PR603 GPU_IN_B+
1
0_0402_5%
0_0402_5%
AON6414AL_DFN8-5
2 1
<16,17,38,39,55> DGPU_PWROK
10K_0402_5%
10K_0402_5%
10K_0402_5%
<58> GPU_VIN-
<58> GPU_VIN+
0_0402_5%
2
+3VS UG_VGA1 4
2
2.2_0603_5%
VCC_PRM
2
PR611
2
PQ601
PR605
PC605
0.22U_0603_25V7K~D PL602
3
2
1
2
2
10K_0402_5%
10K_0402_5%
PR607
PR608
PR613
PR614
0.42UH_FDUE0640-R42M_20.2A_20%~D
+VGA_CORE
1
PHASE_VGA1 2 1
10K_0402_1%
PR606
PR612
1_0402_5%
5
5
1000P_0402_50V7K~D
2
150K_0402_1%
AON6702L_DFN8-5
AON6702L_DFN8-5
PR620
PR621
@
1000P_0402_50V7K~D
2
36.5K_0402_1%
4.7_1206_5%
.047U_0402_16V7K~D
PR622
2
2
6.81K_0402_1%
5.49K_0402_1%
3.65K_0805_1%
10K_0402_1%
40
39
38
37
36
35
34
33
32
31
2
PC607
PR615
PR617
PR618
2
PR623
PC608
PR616
PR619
LG_VGA1 4 4 PC609
PGOOD
VR_ON
PSI_L
VID5
VID4
VID3
VID2
VID1
VID0
BOOT1
1
1
PC606
0.22U_0603_16V7K~D
1
PQ603
PQ604
@ 1 2
1
1
680P_0603_50V7K~D
1 30
SET UGATE1
1
@ VGA_ISEN2
3
2
1
3
2
1
2 29
RBIAS PHASE1
1
VGA_ISEN1 VCC_PRM
PC610
3 28
OFS PGND1
2
4 27 PR624 0_0402_5%
SOFT LGATE1 VSUM
2 1 +5VS
PR625 PC611 5 26
C 97.6K_0402_1% 470P_0402_50V7K~D OCSET PVCC VGA_B+ C
2 1
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
1 2 1 2 6 25 PC612
VW LGATE2
2200P_0402_50V7K~D
PC613 PU601 4.7U_0603_6.3V6K~D
220P_0402_50V8J~D 7 ISL6264CRZ-T_QFN40_6X6 24
COMP PGND2
1
PC615
PC616
PC617
1 2
PC614
8 23
FB PHASE2
2
9 22 UG_VGA2
VDIFF UGATE2
5
PR626
1K_0402_1% 10 21 2 1
VSEN BOOT2
AON6414AL_DFN8-5
2 1
DROOP
330P_0402_50V7K~D
ISEN2
ISEN1
VSUM
PR628 PC621 41 PR627
GND
GND PAD
VDD
RTN
DFB
2
2
VIN
255_0402_1% 1000P_0402_50V7K~D 2.2_0603_5%
VO
2
1 2 1 2 PC623 4
PC622
330P_0402_50V7K~D
1
11
12
13
14
15
16
17
18
19
20
1
1
PQ605
PC624
<40> +NVVDD_SENSE 2 1 @ 0.22U_0603_25V7K~D PL603
3
2
1
VGA_ISEN1 0.42UH_FDUE0640-R42M_20.2A_20%~D
PR629 PC626 PHASE_VGA2 2 1 +VGA_CORE
1000P_0402_50V7K~D
10K_0402_1%
PR630 0_0402_5% 180P_0402_50V8J~D
2
1_0402_5%
10_0402_5% 1 2 VGA_ISEN2
+VGA_CORE
PC625
AON6702L_DFN8-5
AON6702L_DFN8-5
2 1 PR631 PR632
2
PR633
PR634
1K_0402_1% 787_0402_1%
1
from output Bulk Cap 2 1 1 2 PR635
2
4.7_1206_5%
3.65K_0805_1%
10K_0402_1%
PR638 B+ +5VS LG_VGA2 4 4
PR636
PR637
10_0402_5% PC627
1
PQ607
PQ608
1 2 0.22U_0603_16V7K~D
Close to Phase1 Choke PL18 1 2
1
10_0402_5%
10_0402_5%
VCC_PRM VGA_ISEN1
2
3
2
1
3
2
1
10K_0603_5%_TSM1A103J4302RE
680P_0603_50V7K~D
PR640
PR641
2 1
<40> GND_SENSE
2
1
11K_0402_1%
VGA_ISEN2 VCC_PRM
PC628
PH601
PR639
PR642
0_0402_5%
1
2
0.22U_0402_6.3V6K~D
.1U_0402_16V7K~D
.1U_0402_16V7K~D
2
VSUM
PC629
B B
1
1
PC630
PC631
0.01U_0402_50V7K~D
1U_0402_6.3V6K~D
1
2
2.61K_0402_1%
1
PC632
PC633
PR643
2
1
VSUM
VGA_CORE
TDC 36.8 A +VGA_CORE
Peak Current 46 A
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
OCP current 55 A 1 1 1
Cesr=9 mOHM + + +
DCR=1.48 mOHM+-7%
PC618
PC619
PC620
2 2 2
A A

VGA_CORE
C
LA-6801P 1.0
5 4 3 2 1
5 4 3 2 1
HCB4532KF-800T90_1812 CPU_IN_B+
@ PC701 CPU_B+ 1 2
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
2 1 NTCG
680P_0402_50V7K~D
680P_0402_50V7K~D
1
1
PL701
PC703
PC702
5
5
470P_0402_50V7K~D
1
PR701
PQ701
PQ702
PC704
PC705
PC706
PC707
2
AON6414AL-1N_DFN
AON6414AL-1N_DFN
2 1 2 1 PH701
3.83K_0402_1% UGATEG @ @
1000P_0402_50V7K~D
2
470KB_0402_5%_ERTJ0EV474J
4 4
8.06K_0402_1%
1
2 1 1 2 revise 9/21 PL702
1
PR703 0.36UH_ETQP4LR36AFC_28A_20%~D
PR702
1
PC767 27.4K_0603_1%~D 4 1
PC708
470P_0402_50V7K~D +VCC_GFXCORE_AXG
3
2
1
3
2
1
PR767 +VCC_GFXCORE_AXG 3 2
2
4.99K_0402_1% PR704 PHASEG PC709
1
PC710 2 1 PR705 0.1U_0603_25V7K~D PR708
5
D 330P_0402_50V7K~D 10_0402_1% BOOTG 2 1 2 1 PQ704 PR707 1_0402_5% D
PR709
4.7_1206_5%
VCC_AXG_SENSE <10>
330P_0402_50V7K~D
1
AON6702L-1N_DFN8
AON6702L-1N_DFN8
1 2 2.2_0603_5% PQ703 10K_0603_1%
1
499K_0402_1%
1
PC711 PR710 PC712 PH702
PR706
VSS_AXG_SENSE <10>
680P_0402_50V7K~D
2
2 1 2 1 2 1 PC714 10K_0402_5%_ERTJ0ER103J
PC713
422_0402_1% 2 1 LGATEG 4 4 PR711 1 2 1 2 1 2
1 2
@ 39P_0402_50V8J~D 330P_0402_50V7K~D +5VS 7.5K_0402_1%
2
PC716 PR712 PR713 0.01U_0402_16V7K~D PR714 PC715
PC717
2 1 2 1 2 1 2 1 1 2 .1U_0402_16V7K~D
1U_0603_10V6K~D
1
475K_0402_1%~D 2.43K_0402_1% 10_0402_1% PR715 11K_0402_1%
0_0603_5%
1
3
2
1
3
2
1
2
150P_0402_50V8J~D revise 10/25 @ PR717
PC718
IMONG PR716 PC719 1 2 1 2
2
1
PR719
18.2K_0402_1%
16.5K_0402_1%
+VCCP 2 1 .1U_0402_16V7K~D 100_0402_1%
0.047U_0603_25V7M~D
1
2.2_0603_5%
PR718
ISPG
ISNG
NTCG
1
CPU_B+ 1 2
PC720
PC723
UGATEG
PHASEG
LGATEG
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
470P_0402_50V7K~D
1
1
BOOTG
PC721
PR721
2
5
PU702 PC722 0.022U_0402_16V7K~D
130_0402_1%
54.9_0402_1%
.1U_0402_16V7K~D
2
5 1 0.1U_0603_25V7K~D @
PQ705
PQ706
PR722
PR720
<10> VSS_AXG_SENSE VCC BOOT
1
AON6414AL-1N_DFN
AON6414AL-1N_DFN
@ PR723
PC724
PC725
PC726
PC727
PC728
1
1
6 8 487_0402_1%
FCCM UGATE
2
revise 8/23 +3VS
2
ISPG
@ 2 7 4 4 @ revise 10/25
49
48
47
46
45
44
43
42
41
40
39
38
37
PWM PHASE
ISNG
3 4
1.91K_0402_1%
GND
COMPG
FBG
VSENG
RTNG
ISPG
ISNG
NTCG
BOOTG
UGG
PHG
LGG
PROG2
<9> VR_SVID_DAT GND LGATE
1
1 36 BOOT2 9 PL703
<9> VR_SVID_ALRT# PR724 VWG BOOT2 PGND
3
2
1
3
2
1
1
0.36UH_ETQP4LR36AFC_28A_20%~D
2 35 UGATE2 PR725 ISL6208ACRZ-T_QFN8_3X3 4 1
0_0603_5%
<9> VR_SVID_CLK
2
IMONG UG2 +VCC_CORE
5
Alert# PU resister need close CPU, VGATEG 3 34 PHASE2 PQ707 PQ708 3 2 PR726
4.7_1206_5%
PGOODG PH2
1
PR728 2 1ISEN1
so the PU resister in HW schematic.
AON6702L-1N_DFN8
AON6702L-1N_DFN8
SVID_SDA 4 33 @ PR729 ISEN3 1 2 10K_0402_1%
PR727
but DAT and CLK need close PWM-IC, SDA VSSP2 0_0603_5% 10K_0603_1%
680P_0402_50V7K~D
C so the PU resister in POWER schematic. SVID_ALERT# 5 32 LGATE2 1 2 +5VS C
ALERT# LG2 PR731
4 4
1 2
SVID_SCLK 6 31 1 PR730 2 PR732 2 1ISEN2
SCLK VDDP VSUM+ 10K_0402_1%
1 2
PC729
<31> VR_ON
1 PR733 2 7 30 0_0603_5% 3.65K_0603_1%
<9> VSSSENSE VR_ON PWM3
1U_0603_10V6K~D
1U_0603_10V6K~D
0.047U_0603_25V7M~D
3
2
1
3
2
1
2
1 2 0_0402_5% 8 29 LGATE1 PR735
PC731
PC732
+3VS
18.7K_0402_1%
PGOOD LG1
1
PR734 ISL95831CRZ-T_TQFN48_6X6 VSUM-

2 1
1
1
1.91K_0402_1% 9 28 1_0402_5%
PC730
IMON VSSP1
10 27 PHASE1
PR736
VR_HOT# PH1
2
2
2
<6,15,31> VGATE 11 26 UGATE1 CPU_B+

ISEN3/ FB2
NTC UG1
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
IMON
5
12 25 BOOT1 add 10/26
PROG1
1 1 1
ISUMN
ISUMP
VW BOOT1
COMP
ISEN2
ISEN1
VSEN
PQ709
PQ710
100U_25V_M
100U_25V_M
100U_25V_M
design change
VDD
RTN
1
AON6414AL-1N_DFN
AON6414AL-1N_DFN
VIN
@ PC736 + + +
FB
PC737
PC738
PC739
PC740
PC733
PC734
PC766
1
<31,50> VR_HOT# 2 1
PC735 PU701
2 2 2
13
14
15
16
17
18
19
20
21
22
23
24
2
PR738 470P_0402_50V7K~D UGATE2 4 4 @
2
@ PR737 43P_0603_50V8
1 2 1 2
+VCCP 1 2 PH703
499_0402_1% 3.83K_0402_1%
470KB_0402_5%_ERTJ0EV474J PL704
3
2
1
3
2
1
2 1 0.36UH_ETQP4LR36AFC_28A_20%~D
PR739 PR742 PHASE2 4 1 +VCC_CORE
1
27.4K_0402_1% 0_0603_5%
D
1
1 2 PC742 3 2
0_0402_5%
4.7_1206_5%
8.06K_0402_1%
1000P_0402_50V7K~D
1
1
2Quad_SEL PR743 0.1U_0603_25V7K~D
G BOOT2 2 1 2 1
PQ711
PQ712
PR741
PC741
PR740
PR744
CPU_B+
AON6702L-1N_DFN8
AON6702L-1N_DFN8
@ PC743 S @ PQ719 2.2_0603_5%
680P_0402_50V7K~D
2
3
PR745 SSM3K7002FU_SC70-3
10P_0402_25V8J 2 1 +5VS PR746 PR747
2
1 2
1 2 2 1 LGATE2 4 4 ISEN2 1 2 2 1ISEN1
PC746
1U_0603_10V6K~D
1_0603_5% 10K_0603_1% 10K_0402_1%
PC744
ISEN2
ISEN1
ISEN3
B @ PR750 PC748
39P_0402_50V8J~D PC745
Vboot=0 B
PC747
2
499K_0402_1% 2 1 2 1 2 1 2 1 0.22U_0603_25V7K~D PR748 PR749
2
3
2
1
3
2
1
PR768 PC768 0.22U_0402_6.3V6K~D VSUM+
1 2 2 1 ISEN3
2K_0402_1% 680P_0402_50V7K~D PC750 3.65K_0603_1% 10K_0402_1%
VSUM- 2 1 VSUM+ PR752
2 1 2 1 2 1 2 1PC749 0.22U_0402_6.3V6K~D VSUM- 2 1
PC752 PR754 PR751 470P_0402_50V7K~D PC751 1 1_0402_5%
150P_0402_50V8J~D 316K_0402_1% 499_0402_1% 2 1
0.068U_0402_16V7K~D
0.068U_0402_16V7K~D
0.22U_0402_6.3V6K~D PR753 CPU_B+

0.47U_0603_16V7K~D
2 1 2.61K_0402_1%
11K_0402_1%
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
1
5
+5VS +5VS PR755
1
1 2
3.74K_0603_1%~D
PQ713
PQ714
PR756
1
AON6414AL-1N_DFN
AON6414AL-1N_DFN
PC753
PC754
PC755
PC756
PC757
PC758
@ PC759
1
1 3 2 1 PH704
D
@ PR770 10K_0402_5%_ERTJ0ER103J
2
2
5.11K_0402_1% @ @ UGATE1 4 4
PR771 PR772 Quad_SEL# PQ718 revise 10/25
G
2
+3VALW 10K_0402_5% 10K_0402_5% SSM3K7002FU_SC70-3 VSUM-

2 1 DCR:0.82mOHM
2
+VCC_CORE 2 1 PR758
1
Quad_SEL# Quad_SEL PR757 953_0402_1% PL705

.1U_0402_16V7K~D
1
3
2
1
3
2
1
@ 10_0402_1% PC760 0.36UH_ETQP4LR36AFC_28A_20%~D
PC763
330P_0402_50V7K~D
6
2 1 2 1 1 3 PHASE1 4 1
D
+VCC_CORE
2
3
PR773 330P_0402_50V7K~D @ PR769

PC761
10K_0402_5% <9> VCCSENSE 1.27K_0402_1% PC764 3 2
4.7_1206_5%
2
1
2 2 1 PQ717 0.1U_0603_25V7K~D PR760
G
<9> VSSSENSE
2
5 PC762 SSM3K7002FU_SC70-3 BOOT1 2 1 2 1
PQ715
PQ716
PR761
<31> CPU_SEL
AON6702L-1N_DFN8
AON6702L-1N_DFN8
PR774 0.01U_0402_16V7K~D Quad_SEL# 2.2_0603_5%
680P_0402_50V7K~D
2
PQ720B @ 100K_0402_5% 2 1
4
DMN66D0LDW-7 2N SOT363-6 PR759 PR762 PR763
1 2
PR775 PQ720A @ 10_0402_1% LGATE1 4 4 ISEN1 1 2 2 1 ISEN2
@ 100K_0402_5% DMN66D0LDW-7 2N SOT363-6 10K_0603_1% 10K_0402_1%
PC765
1 2
2
A +VCC_CORE 3 PR764 PR765 A
2
1
3
2
1
VSUM+1 2 2 1 ISEN3
3.65K_0603_1% 10K_0402_1%
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1 1 1 PR766
VSUM- 2 1
Quad & Dual CORE selection + + + 1_0402_5%
PC780
PC781
PC782
CORE CPU_SEL Quad_SEL Quad_SEL# PR758//PR769 PR755//PR770 PROG1 2 @ 2 @ 2 @

Dual L L H TBD TBD 4.32k Issued Date 2011/01/25 Deciphered Date 2012/01/25 Title
Quad THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
(Default) H H L 953 3.74k 0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
LA-6801P 1.0
5 4 3 2 1
5 4 3 2 1
VENTURA +3VS
+3VS_DELAY
D D
2
@ PR801 @ PR802
2.2K_0402_5% 2.2K_0402_5%
1
2
<44> I2CB_SDA I2CB_SDA 1 6 I2CB_DATA2 1 EC_SMB_DA2 <30,31,45>
PR823
5
@ PQ801A 0_0402_5%
2N7002DW-T/R7_SOT363-6
I2CB_SCL 4 3 I2CB_CLK 2 1
<44> I2CB_SCL EC_SMB_CK2 <30,31,45>
PR824
@ PQ801B 0_0402_5%
2N7002DW-T/R7_SOT363-6
connect to EC 10/05
2 1 PR804 1 2 0_0402_5%
<54> CPU_VIN+
PR803 0_0402_5%
1
1
@PC801
@PC801 @PC802
@PC802
.1U_0402_16V7K~D .1U_0402_16V7K~D PU801
2
2
C 1 8 CPU_A1 C
PR805 1 VIN+ A1 CPU_A0
<54> CPU_VIN- 2 0_0402_5% 2 7
VIN- A0 I2CB_DATA
3 6
GND SDA I2CB_CLK
+3VS 4 5
VS SCL
INA219AIDCNRG4_SOT23-8
2 1 PR807 1 2 0_0402_5%
<56> GPU_VIN+
PR806 0_0402_5%
1
@PC803
@PC803 @PC804
@PC804
.1U_0402_16V7K~D .1U_0402_16V7K~D PU802
2
1 8 GPU_A1
PR808 1 VIN+ A1 GPU_A0
<56> GPU_VIN- 2 0_0402_5% 2 7
VIN- A0 I2CB_DATA
3 6
GND SDA I2CB_CLK
+3VS 4 5
VS SCL
INA219AIDCNRG4_SOT23-8
+3VS +3VS
B B
2
@ PR809 @ PR810
0_0402_5% 0_0402_5% PR811 @ PR812
0_0402_5% 0_0402_5%
1
CPU_A0 2 1 I2CB_DATA
1
PR813 0_0402_5% GPU_A0 2 1 I2CB_DATA

1
PR814 0_0402_5%
1
PR815
@ 0_0402_5% PR816
@ 0_0402_5%
2
CPU_A1 2 1 I2CB_CLK
@ PR817 0_0402_5% GPU_A1 2 1 I2CB_CLK
2
@ PR818 0_0402_5%
2
PR819 @ PR820
0_0402_5% 0_0402_5% @ PR821 @ PR822
0_0402_5% 0_0402_5%
1
Ventura for CPU side

slave address : 1000010 Ventura for GPU side
A
please placemnet near R-sense slave Address 1000110 A
please placement near R-sense

VENTURA
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
revise 8/09
ESD request
1
PD9 PD10
PESD24VS2UT_SOT23-3 PESD24VS2UT_SOT23-3
BATT+ BATT++
D D
3
PL3
BATT+
SMB3025500YA_2P
1 2 BATT++
+3VALWP
100P_0402_50V8J~D
1
1
100P_0402_50V8J~D
1
Battery Connect/OTP
PC14
PC16
PC15 1000P_0402_50V7K~D
PC13
2
0.01U_0402_25V7K~D
2
PR30 Place clsoe to EC pin

47K_0402_5%
1 2 BATT_TEMP BATT_TEMP <31>
PH1 under CPU botten side :
1
PR31
2
1K_0402_5%
MOLEX_87437-1173_11P-T PC17
CPU thermal protection at 90 degree C
SP020907230
PJP30 battery connector 0.1U_0402_16V7K~D Recovery at 50 degree C
1
11 @
11 PR32
10
SMART
10
9
9
Battery:
8 3S/4S# 1K_0402_5%
8 VL VL
7 2 1
7
6 1 2 +3VALWP
6
11.BAT+
5
5 PR33
4
10.BAT+
4 6.49K_0402_1%
3
3
2
2
9.BAT+ 2
1
1 PH1 PR35
8.ID
1 2 47K_0402_1%
EC_SMB_DA1 <31>
100K_0402_1%_TSM0B104F4251RZ
C
7.B/I @ PJP30 PR34 C
1
6.TS
100_0402_5% PR36
MAINPWON <30,52>
47K_0402_1%
5.SMD 1 2
4.SMC
modify 9/27
1 2 PR38 VL
reduce S5 loss
3.GND
EC_SMB_CK1 <31>
8
13.7K_0402_1%
D
1
PR37 OTP-1 OTP-25
2.GND
1 2
P
100_0402_5% + OTP-3 PQ9
7 2
1.GND
OTP-4 0 SSM3K7002FU_SC70-3
6 G
-
G
PU1B S
3
LM393DR_SO8
4
1000P_0402_50V7K~D
17.8K_0402_1%
0.22U_0603_25V7K~D
1
1
1
PR39
2 1 VL
PC18
PC19
PR40
1
100K_0402_1%
2
PQ10 PR41
TP0610K-T1-E3_SOT23-3 100K_0402_1%
2
B+ 3 1 B+_BIAS
revise 12/06
0.22U_1206_25V7K~D
100K_0402_1%
adjust OTP setting point

1
1
PR42
PC20
@ PC21
0.1U_0603_25V7K~D
2
B @ B
2
PR43
+5VALW 22K_0402_1%
1 2
2
PR44
100K_0402_1%
PR45
1
D
1
0_0402_5%
1 2 2 PQ11
<52> SPOK
G SSM3K7002FU_SC70-3
0.1U_0402_16V7K~D
S
3
1
PC22
2
A A

PWR-BATTERY CONN
Custom
LA-6801P 1.0

5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 50 PWR-DCIN / Vin Detector 10/09/17 COMPAL reduce S5 loss add PU2;PR27;PC11;PC12 0.2
D 2 55 +VCCSAP/+1.5VSDGPUP 10/09/21 COMPAL RF request add PR521;PC529 change PR520 from 0 to 2.2 0.2 D
3 57 +CPU_CORE 10/09/21 COMPAL design change change PR703 from 0 to 27.4K 0.2
4 51 CHARGER 10/10/06 COMPAL design change change PC131 from 0.1u to 1u 0.2
5 50 PWR-DCIN / Vin Detector 10/10/07 COMPAL design change add PQ12;PC23 0.2
6 54 +VCCPP/+1.8VSP 10/10/07 COMPAL design change modify 1.8VSP solution 0.2
7 51 CHARGER 10/10/19 COMPAL EMI request add PC126;PC128 0.2
8 55 +VCCSAP/+1.5VSDGPUP 10/10/19 COMPAL EE request add PR528;PR529;PR530 del PR519 0.2
9 56 +VGA_CORE 10/10/19 COMPAL EE request add PR647;PR648 del PR603;PR604 0.2
10 51 CHARGER 10/10/25 COMPAL design change change PR114 from 47K to 0 0.2
11 54 +VCCPP/+1.8VSP 10/10/25 COMPAL design change for use ventura curcuit change PR401 from 0 to 0.01 0.2
12 56 +VGA_CORE 10/10/25 COMPAL design change for use ventura curcuit change PR601 from 0 to 0.01 0.2
C C
13 57 +CPU_CORE 10/10/25 COMPAL change CPU OCP setting change PR758 from 887 to 953 0.2
14 57 +CPU_CORE 10/10/25 COMPAL change GFX OCP & LL setting change PR723 from 442 to 487 change PR713 from 2.61K to 2.43K 0.2
15 57 +CPU_CORE 10/10/25 COMPAL quad & dual core CPU switch setting design add PQ717;PQ718;PQ720;PR771;PR772;PR773;PR767;PR768;PC767;PC768 0.2
16 58 VENTURA 10/10/25 COMPAL add ventura connect to EC add PU801;PU802;PR803;PR804;PR805;PR806;PR807;PR808 0.2
;PR811;PR813;PR814;PR819;PR823;PR824 0.2
17 57 +CPU_CORE 10/10/26 COMPAL design change for solve acoustic issue add PC766 0.3
18 52 3VALWP/5VALWP 10/10/27 COMPAL design change for reserve adjust working frequency add PR222 0.3
19 59 BATTERY CONN 10/12/06 COMPAL adjust OTP setting point change PR39 from 16.9K to 17.8K 0.3
20 50 PWR-DCIN / Vin Detector 10/12/13 COMPAL design change for delete prechange circuit del PR1;PR2;PR3;PR4;PR5;PR6;PR7;PD1;PD2;PQ1;PQ2;PQ3 0.3
21 51 CHARGER 10/12/13 COMPAL design change for delete prechange circuit del PR104;PQ110 add PR102 0.3
22 53 +1.5VP/+0.75VSP/+1.5VSP 10/12/13 COMPAL EE request for use memory over clocking circuit add PR312;PR318 0.3
B B
23 53 +1.5VP/+0.75VSP/+1.5VSP 10/12/20 COMPAL design change for adjust original output voltage swap PR314;PR317 and PR320;PR323 0.4
24 51 CHARGER 10/12/21 COMPAL design change for delete prechange circuit del PC109 0.4
25 50 PWR-DCIN / Vin Detector 11/01/06 COMPAL design change for add AC peak power function add PR25 0.4
26 54 +VCCPP/+1.8VSP 11/01/11 COMPAL EE request for adjust output voltage change PR415 from 4.02K to 4.12K 0.4
27 55 +VCCSAP/+1.5VSDGPUP 11/01/11 COMPAL EE request for adjust output voltage change PR524 from 10K to 10.5K 0.4
28 51 CHARGER 11/01/20 COMPAL EMI request add PL102 0.4
29 52 3VALWP/5VALWP 11/01/20 COMPAL EMI request add PL204 0.4
A A

PWR-PIR
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
1 23 Card Reader RTS5209 10/11/26 COMPAL Add a cardreader conn JERAD1 to co-lay for 2nd source ALPS. The requirement from ME 0.3
D D
2 33 DC/DC Interface 10/11/29 COMPAL Net name changed from +1.5V_D to +3V_USB The discharge circuit for power rail +3V of USB3.0 0.3
3 29 PWRBTN/SCREWH/KB 10/12/01 COMPAL footprints changed from H_2P7 to H_3P0 The requirement from ME 0.3
4 31 EC ENE-KB930/ ENE3810 10/12/06 COMPAL Add a net CP_SEL link U620.2 to PQ115.2 The requirement from PWR 0.3
to avoid EC damaged by ESD. Fix issue DF434042 (2) [S_PT] Memory Matrix
5 31 EC ENE-KB930/ ENE3810 10/12/07 COMPAL Remove the net 3S/4S# from U34.103 to PJP30 test, system 7 beeps error 0.3
6 31 EC ENE-KB930/ ENE3810 10/12/07 COMPAL Add a cap. 20p_0402 on XCLK0 of KB930 to follow the suggestion from ENE 0.3
7 16 PCH (4/8) PCI, USB, NVRAM 10/12/07 COMPAL GPIO10 changed to GPIO14 for USB3_SMI# for common design with Voyager 0.3
8 10 PROCESSOR(6/6) PWR,VSS 10/10/19 COMPAL BOM changed for QC4, Maximum derateing changed from 12V to 20V safe to pass derateing 0.3
power rail changed from +vs to +valw to fix issue can't wake from S3 by
9 27 +VGA_CORE 10/10/19 COMPAL Del RI22,RI27, Add RI21,RI25 port of USB3.0 0.3
10 13 CHARGER 10/10/25 COMPAL Del RH260,RH261 The requirement from PWR 0.3
11 10 PROCESSOR(6/6) PWR,VSS 10/10/25 COMPAL BOM changed for CC176, Maximum derateing changed from 2V to 2.5V safe to pass derateing 0.3
12 21 VGA / LVDS /camera conn. 10/10/25 COMPAL Add FV3, Del R2012 The requirement from Safty 0.3
13 39 HDMI 10/10/25 COMPAL Add FV2, Del RV10 The requirement from Safty 0.3
C 14 38 Mini Display Port 10/10/25 COMPAL BOM changed for QV9 The requirement from Sourcer.(Fairchild support no good) 0.3 C
15 31 EC ENE-KB930/ ENE3810 10/10/25 COMPAL BOM changed for R225 for Board ID changed 0.3
16 22 GLAN AR8151 AL1A/ RJ45 10/10/25 COMPAL BOM changed for CL39 for shortage 0.3
17 21 VGA / LVDS /camera conn. 10/10/26 COMPAL BOM changed for L31,L32,L103,C540,C541,C542,C537,C538,C539 The requirement from EMC for CRT 0.3
18 18 PCH (6/8) PWR 10/10/27 COMPAL Del RH211, Add RH212 +VCCAFDI_VRM come from +1.5VS changed to U47 LDO_VOUT 0.3
B B
A A

HW-PIR
1.0
5 4 3 2 1
www.s-manuals.com

Compal La-6801p r1.0 Schematics

Uploaded by

Copyright:

Available Formats

Compal La-6801p r1.0 Schematics

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Compal La-6801p r1.0 Schematics

Uploaded by

Copyright:

Available Formats

A B C D E

MODEL NAME : PALB0

Specter (Huron River) 2

Sandy Bridge(PGA) + Cougar Point(standard)

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal Confidential CPU XDP

LVDS LVDS Port 2

CRT Port 0 USB 2.0

DisplayPort Intel Port 2

P.49~59 P.35 P.29 P.31

Security Classification Compal Secret Data Compal Electronics, Inc.

40 pin LCD Panel

FRONT LIGHT L/B FRONT LIGHT R/B

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel

CLKOUT DESTINATION 13 None

SATA2 ODD Lane 3 MINI CARD-1 WLAN

PEG_ICOMPI and RCOMPO signals should be shorted and routed

PCI EXPRESS* - GRAPHICS

K27 PEG_HTX_GRX_P9 CC210 1 2 220nF_0402_16V7K PEG_HTX_C_GRX_P9 <40> G29

Security Classification Compal Secret Data Compal Electronics, Inc.

<15,31> PCH_PWROK +3VALW

RC41 XDP_PREQ# 51_0402_5% 1 @ 2 RC47

for EMC request, close to CPU 7/26 XDP_TRST#_R 51_0402_5% 1 2 RC54

AP29 XDP_PRDY# RC1211 2 0_0402_5%~D XDP_PRDY#_R

RC49 AR27 XDP_TMS RC1241 2 0_0402_5%~D XDP_TMS_R

H_PM_SYNC_R TMS XDP_TRST# RC1251 XDP_TRST#_R

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_A_D31 M7 AG2 DDR_B_D29 N5 AE4 M_ODT2

DDR SYSTEM MEMORY B

<6> H_DRAMRST# DDR3_DRAMRST# <11,12>

RC77 1 2 DRAMRST_CNTRL_PCH <14>

Date: Tuesday, January 25, 2011 Sheet 7 of 61

CFG Straps for Processor

@ <6> CFG15 CFG15 AM27 H16 @ T12 PAD~D CFG4

VSS_AXG_VAL_SENSE AH31 AT33 @ T16 PAD~D

PAD~D T19 @ AJ26

PAD~D T25 @ F25

PAD~D T30 @ G25 AK32 @ T31 PAD~D CFG6

PAD~D T44 @ J20

VSS_VAL_SENSE PEG DEFER TRAINING

A 0: PEG Wait for BIOS for training A

INTEL 12/28 recommand

Date: Tuesday, January 25, 2011 Sheet 8 of 61

PEG AND DDR

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Tuesday, January 25, 2011 Sheet 9 of 61

1 1 1 1 1 1 1 1 AT21 AP10 AE35

AT20 AP7 AE34

1 1 1 1 1 1 1 1 AP20 AN4 AC8

AP18 RC126 QC4 AM29 AC6

AN17 VAXG23 J8 AM7 VSS51 VSS131 AB32

VAXG25 VDDQ1 +1.5V VSS53 VSS133

VAXG29 VDDQ5 VSS57 VSS137

VAXG49 VSS77 VSS157

add CC181 , CC182, 4 caps are all pop.

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Tues day, January 25, 2011 Sheet 10 of 61

+1.5V RD2 0_0402_5%~D +1.5V +1.5V

DDR_A_D49 165 166 DDR_A_D53