01 (Handout)
01 (Handout)
CHAPTER 11
kowtow work
IWSI :
aur D bit
Assoc.Prof. Dr.Yuttapong Rangsanseri
Ubm's
I/O
Dts
cnonivoowriv
{ ter
Cpu
ex '
cow
inv prog IDATA
.
"' VII )
port Timer
-71
trini:c:[
'
:c:c::
t DIA
Snow WIE ovolo
Parallel vs. Serial Communication
Group o's roup
tr d
Rx Tx
logo
'
shoutout win 9mm's ions-
riiidwsyncw moonyBoynton
Faster transfer and less overhead.
,
V
10
AVR chip has a built-in USART I
lardon
5
① y Microprocessor Theory and Applications
Asynchronous Serial Communication
♦ With asynchronous communication, the transmitter and
receiver do not share a common clock
Add: Start, Stop, Parity Bits Remove: Start, Stop, Parity Bits
Transmitter + – Receiver
Data
O D0 D1 D2 D3 D4 D5 D6 D7
n ablution
GB w MSB
↳ 7ms
1 Asynchronous Byte
.
.
coil ow vosiov 1
:
•
even parity .
a. of slums duo's Nonpolar serial
l baud : i bit
or
't
wool
it ÷÷÷::.÷:
'
do
.
:*
#¥1111
ro
Ht T
y baud : 2 bit r
bitrate
1000×6
:
bitrate : Ishii bit
data
ex
.
unman
bitrate
①
115200 * 8 / 10 = ↳
92160 bits/sec
Tx 9 Rx
?
Mosfet Otsu ,
( Data
1 Data format framing l Protocol
:{
.
ow data bit = ?
6,718,9
}gn÷I
.
" 'v ?
'
'"
OY
"
%
"
aging
'
. .
2 .
Munn baud rate
ex . 4800 bps
9600
:
775.200
Tx NLM ex .
baud rate
-
-
1kHz
T =
1ms
Rx TT TT TT TT
Mifune sampling
safmpling
w i.
1ms
uhsriwims
mwbavdratennhewnlwa.fm/umintso:W error
i. ring's error Ivo :p n' lihhifvinlstop bit
( Wh
:
Olooiisgiin error Toi
-
50%
t.in:im:*
Assignment tab not .
""
[ Attendance
.
Chiodos )
serial communication riwnnTNw Hardware module ringworm's
UART -
↳ N' w Hardware nd support Nos serial port to ,
I ruin serial
Parallel-to-Serial and Serial-to-Parallel conversion
Start and Stop Bit framing
Parity Generation Cpu speed a. IS baud
µ 1- serial
232
urn
oioiwriiv serial VARI 2
"
6,7,8,9 data bits
Eto
,
'
-
It
Parity bit optional rioiwniwsn level rundownis
Stop bit
Nfu wit wins Nunn w
♦ Voltage levels
:
minion
n' ovine in {
-
3h33
I
Tindouf
Hornik noise
?
I
÷
" '
?
♦ 2 types of connectors: DB-25 andO
.
DB-9 9 Tv 9 -
timer
♦ Since it is asynchronous, no external clock is .
mssriw
Nain modem
if ur Null modem
rioslvihiv
(
from a single 5V supply. This IC also includes two receivers and two
transmitters in the same package
suywo su-
YWIOV - - -
Dumb
D
converse
"
ii:
0108MW Mcintyre
sin controller
' ,
T
④
WMU "
system
www.onsdo
(
embedded
9
font ,
pconnnuoilrq.IM?MffYwinxmet
(
goes
Kyung roup
FEI
→
④
→
ENE Uonlhirvsriu
I 0
quickie:& ,
-
Protocol :
8E2 219600 d8E49b00
"
ow .
stop bit →
④
Baud rate : 9600 bps ( noiuwniminushloi )
Df Df ,
-
. . .
Do
Data : O O 7 O O 7 O 2
Even
Bitstream :
-w
Do Dt
③ I 0100 100 ①④
%×8bit=€ (9600×82)
85-2/9600
f ( www.umoiw )
bit
start
stop bit
-9
UART '
-
USA RT
AVR Serial Port Programming / Cortinarius
AVR I built in UART Tsd support mode sync Won VSART
y
. .
.
ruwnasync
(USART Data Register)
.
A
=
③
②♦ UCSRA,
O UCSRB, UCSRC
(USART Control Status Register)
Z z
( register
Luo
⑤
Mw :
ninth
♦ UBRR 4jm%J7
D prog .
①
UBBRH I It
UBRRH
UBRRL 8 bit
fat
CPU 8 bit ( Register mm;D 8 bits 9MW 72bithoimosdzm.mn otw '
(byte
)
①I
'
viuoinloimhsrwdgunuu iiwrttsvono
♦ Assuming that Fosc = 8 MHz
-
b9Vdr⇒
With XTAL
=
:
11.0592 MHZ lbcxtl )
11059200
=
153600kt 153600
VBRR= ? to have a 9600
X I
77
0
2 I
UCSRA RXC TXC €0543
UDRE FE DOR PE U2X MPCM
"
6%0009
✓
WT U 3MW .
2 0
3 I
UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8
Bavdrale character
(
sent
Img, ,vr
new