BENCHMARQ

1990/91
Data Book

2611 Westgrove Drive, Suite 101

Carrollton, Texas 75006
Fax: (214) 407-9845
Tel: (214) 407-0011
Benchmarq 1990/91 Data Book

Copyright © 1990, Benchmarq Microelectronics, Inc.

All rights reserved.
No part of this book may be reproduced in any form or means, without express permission from Benchmarq.

This data book contains new product information. Benchmarq reserves the right to make changes in its products
without notice.
Benchmarq assumes no responsibility for use of any products or circuitry described within. No license for use of
intellectual property (patents, copyrights, or other rights) owned by Benchmarq or other parties is granted or implied.
Benchmarq does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Benchmarq components are used in life-support systems, the user assumes all
responsibilities and indemnifies Benchmarq from all liability or damages.

Benchmarq, Energy Management Unit, EMU, Processor Management Unit, PMU, Cloaked Memory, and
Soft Landing are trademarks ofBenchmarq Microelectronics, Inc.
IBM is a registered trademark of International Business Machine Corporation.
ZBO is a registered trademark of Zilog.
MCS and Intel are registered trademarks of Intel Corporation.

Printed in U.S.A.

ii
~ BENOIMARQ _ _ _ _A_b_o_u_t_B_e_"_c_h_m_8_r......;;.q

Our Products
At Benchmarq, we provide integrated ciruit and module solutions for power-
sensitive and portable electronic systems.
Power-sensitive AC-powered systems in the office and industry must grace-
fully deal with the loss of power, maintaining the integrity of important data
and selfsufficiently continuing critical operation. Portable systems share the
design requirements of their powercord-bound counterparts, but add entirely
new challenges-including power supervision, energy management, data
security, and size minimization.
The product families described in this data book directly address these require-
ments, taking full advantage of advanced analog and digital VLSI technologies
and state-of-the-art battery and packaging expertise. Power supervision,
energy management, size reduction, nonvolatility, data security, and retrofit
capability are integral to Benchmarq's product line.

Our Commitment
When you choose to integrate Benchmarq products within your own, be
assured that Benchmarq is committed to providing the specific solutions you
need today and to developing creative solutions to the growing challenges of
tomorrow-supported by the best customer service and the highest overall
quality.
The drive for excellence in all dimensions of quality is a cornerstone of our
company.

iii
How To Use This Book

Data Book Organization

This data book is organized into general information sections and product family sections.
You can locate information in this book in several ways.

To locate information by: See pages:

Table of Contents V

Alphanumeric Product Index VI

Family Summary and Selection Guides 1-2 through 1-6

Product Cross-Reference Tables 1-7

Detailed product information is included in Chapters 2 through 6. Each product family

section includes product data sheets and applicable design notes:
>- Each data sheet provides the device specifications for one family member.
>- Design notes at the end of applicable family sections provide important hardware and
software information to aid in the application of family members.
Packaging information is included in Chapter 7, and sales offices and distributors are listed
in Chapter 8.

For More Information ...

If you haven't found it here ... Ask!
Contact your local sales office, listed in the back of this data book, for help or more informa-
tion.
Additional Benchmarq information is available from your Benchmarq distributor or sales
office, or by contacting Benchmarq Customer Service at (214) 407-0011.
Factory technical assistance is available by phone or fax.
Benchmarq Microelectronics, Inc.
2611 Westgrove, Suite 101
Carrollton, Texas 75006
Phone: (214) 407-0011
Fax: (214) 407-9845

iv
 Table of Contents

Introduction .................................................................................................................. 1
The Benchmarq Quality Policy ................................................................. 1-1
Family Summary and Selection Guides ................................................... 1-2
Processor Management Unit ............................................................... 1-2
Energy Management Unit ................................................................... 1-3
Nonvolatile Static RAM ....................................................................... 1-4
Nonvolatile Controller ......................................................................... 1-5
Real-Time Clock ................................................................................... 1-6
Product Cross-Reference Tables for NVSRAM and RTC ........................ 1-7
Ordering Information ............... .... ......... ......... .... .......... ... ...... ...... .............. 1-8

Processor Management .................................................................................... 2

bql00l Processor Management Unit ........................................................ 2-1
bql002 Processor Management Unit (address latch) .............................. 2-23
Designing With the PMU .......................................................................... 2-45

Energy Management .......................................................................................... 3

bq2001 Energy Management Unit ............................................................ 3-1
bq2002 Energy Management Unit ............................................................ 3-27
Designing With the EMU ......................................................................... 3-29

Static RAM Nonvolatile Controller ..................................................... 4

bq2201 Nonvolatile Controller (by one) .................................................... 4-1
bq2204 Nonvolatile Controller (by four) ................................................... 4-9

Real-Time Clock ........................................................................................................ 5

bq3285 Real-Time Clock IC ....................................................................... 5-1
bq3287lbq3287AReal-Time Clock Module ............................................... 5-19
bq3385 Real-Time Clock + 4K x 8 SRAM IC ............................................ 5-37
bq3387 Real-Time Clock + 4K x 8 SRAM Module .................................... 5-39
bq3485 Real-Time Clock + 8K x 8 SRAM IC ............................................ 5-41
bq3487 Real-Time Clock + 8Kx 8 SRAM Module .................................... 5-43

Nonvolatile Static RAM .................................................................................... 6

bq4010 -8K x 8 NVSRAM ..................................................................... 6-1
bq4011 -32K x 8 NVSRAM ................................................................... 6-11
bq4011H -32K x 8 High-Speed NVSRAM ............................................... 6-21
bq4013 -128K x 8 NVSRAM ................................................................. 6-33
bq4014 -256K x 8 NVSRAM ................................................................. 6-43
bq4015 -512K x 8 NVSRAM ................................................................. 6-53
bq4024 -128Kx 16 NVSRAM ............................................................... 6-63
bq4025 -256K x 16 NVSRAM ............................................................... 6-73

Package Drawings ................................................................................................. 7

Sales Offices and Distributors .................................................................. 8

v
Alphanumeric Product Index

Part No. Description Page

bql00l Processor Management Unit (PMU) + 2KNVSRAM 2-1

bql002 PMU + 2K NVSRAM, Address Latch 2-23
bql00llbq1002 PMU Design Note 2-45

bq2001 Energy Management Unit 3-1

bq2001 EMU Design Note 3-29
bq2002 Energy Management Unit 3-27

bq2201 Nonvolatile SRAM Controller, by one 4-1

bq2204 Nonvolatile SRAM Controller, by four 4-9

bq3285 Real-Time Clock IC 5-1

bq3287lbq3287A Real-Time Clock Module 5-19
bq3385 Real-Time Clock + 4KB SRAM IC 5-37
bq3387 Real-Time Clock + 4KB SRAM Module 5-39
bq3485 Real-Time Clock + 8KB SRAM IC 5-41
bq3487 Real-Time Clock + 8KB SRAM Module 5-43

bq4010 8Kx8 Nonvolatile SRAM 6-1

bq4011 32Kx8 Nonvolatile SRAM 6-11
bq4011H 32Kx8 High-Speed Nonvolatile SRAM 6-21
bq4013 128Kx8 Nonvolatile SRAM 6-33
bq4014 256Kx8 Nonvolatile SRAM 6-43
bq4015 512Kx8 Nonvolatile SRAM 6-53
bq4024 256Kx 16 Nonvolatile SRAM 6-63
bq4025 512Kx 16 Nonvolatile SRAM 6-73

vi
vii
Important Information

Data Sheet Types

Product infonnation data sheets progress in detail as the product goes from design to full
production.
The three types of data sheets are defined below.
~ Advance Information: Benchmarq Advance Information data sheets provide
infonnation for early product planning. These data sheets describe a product in the
design or development stage. Specifications may change in any manner.
~ Preliminary: Benchmarq Preliminary data sheets provide preliminary specifications
for product design. They describe a product through its early production stage.
Supplementary data may be published at a later date.
~ Final: Benchmarq data sheets not labeled Advance Infonnation or Preliminary are
considered Final. They describe a product in full production and provide specifications
for product design.

Engineering Prototype
Prior to full production, Benchmarq may provide limited quantities of Engineering
Prototypes. Engineering Prototypes are suitably tested for evaluation and restricted use. Any
necessary errata data accompanies engineering prototype parts. They are marked with the
part number and an EP or Engineering Prototype identification.

Electrostatic Discharge (ESD) and Integrated Circuit (IC) Handling

Benchmarq ICs, as all ICs, are sensitive to electrostatic discharge (ESD). Although
Benchmarq ICs are designed to withstand high ESD voltages, improper handling may cause
damage. Standard ESD-prevention handling procedures should be followed. ESD-prevention
considerations include proper grounding of operators, work surfaces and chip-handling equip-
ment; appropriately high relative humidity levels; and use of antistatic handling and packag-
ing materials. The ICs should be stored and shipped in antistatic tubes. The antistatic tubes
containing the ICs must be brought to the same potential as the work area/operator before
the individual ICs are handled.

viii
Introduction '. . , 1
~ BENCHMARQ _ _ _ _ _ _ln_t_ro_d_u_c_t_io_n

The Benchmarq Quality Policy

It is the policy of Benchmarq to provide the highest quality products in support
-
of our customers' needs. We recognize that we are in the business of providing
not only the physical product, but also documentation, technical support, sales
and marketing support, and timely product delivery. Our commitment to our
customers begins with product concept and must extend long after actual
product purchase and receipt.
We are dedicated to establishing partnerships with our customers and know
that to succeed we must help our customers succeed. We will do this by:
~ Holding ourselves and our vendors accountable for establishing carefully
considered methods and procedures for design, test and production with
clear and concise documentation,
~ Responding professionally and expeditiously to customer or vendor
problems that arise, bringing to bear the company's strongest resources,
~ Developing an industry-leading "Quality Technology" to drive incremental
improvements in all the products we provide, and to contribute to a
continuous reduction in new product time to market, and
~ Continuously providing products and services to meet or exceed the best
expectations of our customers.

8/16/90
DCN# 60-000001-102
Rev. 1.02
From Page 1 of Benchmarq Quality Manual

1-1
Processor Management Unit (PMU) Summary and Selection Guide

Single-chip "soft landing" solutions for power-sensitive microprocessor and microcontroller

systems.

Dual threshold voltage microprocessor and Battery-backup nonvolatile fast SRAM

supervisor
> 2K bytes for storage of critical data
> Programmable NMI voltage during power-downlpower-up cycles
threshold for power-fail early
warning and power-recovery > Complete nonvolatile control:
notification automatic write-protection and
switching to battery backup on
> Programmable Reset voltage power loss
threshold for power-downlpower-up
microprocessor control Simultaneous nonvolatile control for
optional external CMOS SRAM
-5% or -10% voltage trigger point
> Memory speeds of 45 or 70 ns;
> Programmable microprocessor data-retention current under 1 ~
watchdog monitor
> "Cloaked" mode allows overlapped
memory address map.

PMU Selection Guide

Read/Write NMIVoltage
Bus Cycle Threshold Part Page
Interface Times Input Pins / Package Number Number

Non-muxed 45,70 ns Vee orVTH 40 I DIP bq1001 2-1

44 I PLCC
Muxed (address latch) 45,70 ns Vee 28 I DIP bq1002 2-23
28/PLCC

1-2
 Energy Management Unit (EMU) Summary and Selection Guide

Compact single-chip energy monitoring, recharge control, and energy management solutions l1li
for battery-powered systems.
~ "Gas Gauge" for direct measurement of
battery consumption and capacity ~ Backup voltage supply output regulated
from the main battery
~ Programmable fast charge and
conditioning control for nominal ~ Programmable open-drain outputs for
3.6V-12V NiCd, lead acid and NilMH power management or status indication
batteries
~ Operates from 4.5V-18Vbattery
Programmed constant charge, pulsed charger supply or 4.5V-5.5V system Vee
charge, or "burp" charge
~ Direct microprocessor bus interface,
Full charge determined by -tN, operation to 12 MHz
programmed maximum voltage, and
programmed maximum charge time

EMU Selection Guide

Backup Supply Part Page

Configuration Output Voltage Pins I Package Number Number

Microprocessor 3.3V 24 / .300" SDIP, SOIC hq2001 3-1

peripheral
5.3V 24 / .300" SDIP, SOIC hq2002 3-27

1-3
Nonvolatile SRAM Summary and Selection Guide

Fast access time, unlimited read/write cycles, and internal lithium backup battery provide
simple CMOS SRAM operation and reliable automatic nonvolatility. Eliminates the slow
write time and limited write cycles of EEPROM.

~ Data retention in the absence of power ~ Conventional SRAM operation;

unlimited write cycles
~ Automatic write-protection during
power-up/power-down cycles ~ 10 or 5 years minimum data retention
in the absence of power
~ Industry-standard pinout
~ Battery internally isolated until power
is first supplied

Nonvolatile SRAM Selection Guide

Config- Access Minimum Data- Part Page .

Density uration Time (ns) Retention Time Pins I Package Number Number

64Kb 8Kbx8 85,150,200 10 years 28 I DIP bq4010 6-1

256Kb 32 Kbx 8 100,150,200 10 years 28 I DIP bq4011 6-11
35,45 10 years 28 I DIP bq4011H 6-21

20,25 10 years 28 I DIP bq4011H 6-31

1Mb 128 Kbx8 85,120 10 years 32 I DIP bq4013 6-33
2Mb 256 Kbx8 85,120 10 years 32 I DIP bq4014 6-43
128 Kbx 16 85,120 10 years 40 I DIP bq4024 6-63
4Mb 512 Kbx8 85,120 5 years 32 I DIP bq4015 6-53

256 Kb x 16 85,120 5 years 40 I DIP bq4025 6-73

1-4
 Nonvolatile Controller Summary and Selection Guide

Protects standard CMOS SRAMs against unexpected power loss by write-protecting the
memory and automatically switching to a 3V backup battery.

~ Power monitoring and switching for 3

volt battery-backup applications
~ Less than 10 ns chip enable propagation
delay
-
~ Automatic write-protection during ~ 5% or 10% supply operation
power-up/power-down cycles
~ Control up to 4 banks of SRAM
~ Automatic switching from Vee to first
backup battery and from first backup ~ DIP or SOIC packages
battery to second backup battery

Nonvolatile Controller Selection Guide

- Standby
Banks CE Delay Current lOUT Part Page
Controlled (Max.) (Max.) (Typ.) Pins I Package Number Number

1 10 ns 100nA 150mA 81 DIP, sOle bq2201 4-1

4 10 ns 100nA 150mA 161 DIP, sOle bq2204 4-9

1-5
Real-Time Clock Summary and Selection Guide

Space-saving nonvolatile PC-compatible real-time clock family eliminates unpredictable user

lifetimes and the need for external circuitry.

~ Direct clock/calendar replacement for ~ BCD or binary format representation of

IB~ AT-compatible computers and clock and calendar
other applications
~ Calendar in days, day of the week,
~ Functionally compatible with the months, and years, with automatic
MC146818A leap-year adjustment
~ Completely self-contained modules ~ Time of day in seconds, minutes, and
operate for more than 10 years in the hours
absence of power
12- or 24-hour format
~ IC versions only require a crystal and
battery Optional daylight-saving adjustment

~ 160 ns cycle time allows fast bus ~ Three individually maskable interrupt
operation event flags.

~ Selectable Intel or Motorola bus timing ~ Better than one minute per month clock
accuracy

Real-Time Clock Module Selection Guide

User RAM Bus Part Page
(bytes) Interface Pins I Package Number Number

50 IntellMotorola 241 DIP bq3287 5-19

50 IntellMotorola 241 DIP bq3287A 5-19
50+4K Intel 24 1 DIP bq3387 5-39
50+8K Intel 241 DIP bq3487 5-43

Real-Time Clock IC Selection Guide

User RAM Bus Clock Standby Part Page
(bytes) Interface Current Pins I Package Number Number

50 IntellMotorola 0.51J.A 24 I DIP, sorc bq3285 5-1

28 1 PLCC
50+4K Intel 1.0 IJ.A 24 I DIP, sorc bq3385 5-37
28/PLCC
50+8K Intel 1.0 IJ.A 24 I DIP, sorc bq3485 5-41
28 1 PLCC

1-6
 Product Cross-Reference Tables

NVSRAM Cross-Reference

Density
Dallas
Semiconductor
I SGS-
Thomson Benchmarq
-
64Kb - MK48Z08-10 bq4010-85
- - I----~------ ---- ---- -- -- ._---"--- -
----~j
- MK48Z18-10 bq4010Y-85
,--
DS1225AB-150 MK48Z08-15 bq4010-150
-- -----

DS1225AD-150
MK48Z18-15 bq4010Y-150
DS1225Y-150
DS1225AB-200 MK48Z08-20 bq4010-200
- - - ---"-

DS1225AD-200
MK48Z18-20 bq4010Y-200
------ "
DS1225Y-200
256Kb DS1230AB-1OO - bq4011-100
DS1230Y-1OO - bq4011Y-1OO
,--------

DS 1235AB-150 - bq4011-150
DS1235Y-150 - bq4011Y-150
- ------ - --
DS1235AB-200 - bq4011-200
-- -~--

DS1235Y-200 - bq4011Y-200
f---~--~- --
1Mb DS1245AB-1OO - bq4013-85
r------
DS1245Y-1OO - bq4013Y-85
-- ---
DS 1245AB-120 - bq4013-120
-- ------
DS1245Y-120 - bq4013Y-120
---

Real-Time Clock Cross-Reference

Dallas SGS-
Sem iconductor Thomson Benchmarq

DS1285 MK48T85 bq3285

DS1287 MK48T87 bq3287
DS1287A MK48T87A bq3287A
DS1385 - bq3385
DS1387 - bq3387

1-7
Ordering Information

Benchmarq's standard products are available in several packages and operating ranges. A
valid order number is a sequence of:
~ Device
~ Package Options
~ Speed Options
~ Temperature Range
Valid options for a specific device are defined in the ordering information section at the end of
its data sheet. Contact your Benchmarq sales office about non-standard requirements or to
place an order. Sales offices are listed at the end of this data book.

bq40xx MA-

lI L Temperature Range:
blank= co=•.-cial

Speed Options:
35, 45, 85, ... , 200, or blank

Package Options:
P = Plastic DIP
PN =Narrow Plastic DIP
S =SOIC
SN = Narrow SOIC
Q = QuadPLCC
Mx = x-type module

Device:
bqlOOl
bq2201
bq4011HY
etc. Examples:
bql001Q-70
bq2201SN
bq4011HYMA-45

1-8
Introduction ~

Processor Management 2

Energy Management ,I

Static R~M NOllvolatile Controllers ['I

Real·time Clocks I

NOllvolatile Static R~Ms ,"

Package Drawings 'I

Sales Offices and Distributors ' B

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~ BENCHMARQ _ _ _ _ _ _A_re~_imin_ary_b_q_1_0_0_1
"11 Processor Management Unit (PMU)
Features General Description With its "cloaked" mode of access,

-=-
the 2K byte PMU memory can be
The CMOS bqlOOl Processor transparent to the system memory
>- 2K bytes of SRAM Management Unit (PMU) is a spe- map, or it can occupy a nonover-
- Power-down write protection cialized battery-backup static RAM lapped address block. ~
that provides all functions required
- "Cloaked" SRAM may share On power-up, the reset is held active
for graceful power-downlpower-up
address space with system for processor initialization. Critical
sequencing in applications where
memory information from the nonvolatile
uninterrupted processing is essen-
>- Two supply thresholds for power tial. memory may be retrieved, and
failure "soft landing" processing may resume at the point
Early power-fail detection is of the previous power-fail detection
- Impending power-faillpower- provided via a user-definable and/or in a manner incorporating
restored notification threshold input that gates a non- specific information stored at power
- Power-downlpower-up maskable interrupt output. A reset fail.
microprocessor reset is produced as the power supply
decays to an out-of-tolerance condi- A watchdog function is also provided
>- Automatic switching to backup tion. to verify valid execution during nor-
power mal operation. The bqlOOl is
During a power failure, the time managed through eight con-
>- Microprocessor watchdog monitor period between the non-maskable trol/status registers, which occupy
interrupt and the reset allows for a the upper eight bytes of its internal
>- Access times of 45 and 70 ns "soft landing." Critical information 2Kmemory.
>- 40-pin plastic DIP; 44-pin PLCC held in registers, counters, pointers,
etc. may be stored into the special
SRAM, which operates as a true
nonvolatile memory when connected
to a 3V backup supply.

Pin Connections Pin Names

40-Pin PDIP 44-Pin PLCC Ao-Al5 Address inputs
DQo-DQ7 Data input/output
VTH Threshold voltage input
VOUT 1 Vee
VTH BC ACS Address compare strobe input
NMI RST WD Watchdog strobe input
0--:1:501-11-
ACS
RST °1:0:00. . 00°"''''°
<zz»z>ma:a:z DEF Default setting override input
nnnnnnnnnnn
DEI' A'5 u)lO~(f)C\I""~~~;!;
OE Output enable input
A,• CEeoN DEF 7 o 39 PWD
A'2 WE Al' 8 38 PA15 WE Write enable input
A7 A'3 A12 9 37 PCECON
A7 l~ 10 38 PWE CE Chip enable input
A8 A8 Ae 11 35 PA13
A5 A9 As 12 3' PAs CEcON Conditioned chip enable
A, 13 33 ~ As output
A.
A3
An
bE A3 ,. 32 All
NMI,NMI Non-maskable interrupt
A2 15 31 POE
A2
A,
A10
CE
Al 18
Ao 17 91 ~ ~ ~ ~ ~ ~ ~ ~ ~
r
30 A10 outputs
:::s29 P CE RST,RST Reset outputs
Ao D0 7
DO o D0 8 OO ..... C\I(I)OC"l"'ltlC')(Dt-.
BC 3 volt backup cell input
DO, D0 5 zggg~zggggg
PL-l NC No connect
D0 2 DO,
Vss D03 VOUT Supply output
PN-l
Vee +5 volt supply input
Vss Ground
Sept. 1990 1/22

2-1
bq1001 Preliminary

Pin Descriptions OE Output enable input, active low

Ao-Alfi Address inputs WE Write enable input, active low

DQo-DQ7 Data input/output CE Chip enable input, active low

Threshold voltage input CEeON Conditioned chip enable output

When the VTH input voltage goes below the NMI Non-maskable interru.pt output, active high
internal 2.50V reference voltage, and this is
the selected VNMI input, the NMI and NMI NMI Non-maskable interrupt output, active low
signals are asserted. RST Reset output, active low
ACS Address compare strobe input, active low RST Reset output, active high
ACS latches addresses on a high-to-Iow tran- BC 3 volt backup cell input
sition. The latched address is used for PMU
memory "open" and "close" address com- VOUT Supply output
parison.
VOUT provides the higher of Vee or Be,
Watchdog strobe input, active low switched internally, to supply external RAM.
Default setting override input, active low Vee +5V supply input
DEF is intended to be used as a user-inter- Vee provides the operating supply and is also
face input (pushbutton to ground). DEF the voltage comparison input for the VRST
pulled low forces the RST and RST outputs and (if selected) the VNMI thresholds.
active for time tRSW and returns all control
and status registers to the default setting. Vss Ground

Truth Table
Memory Memory Memory 1/0
Mode State Address CE WE OE Operation CECON Power
Read Open PMU L H L DOUT H Active
Write Open PMU L L X DIN H Active
Output disabled Open PMU L H H HighZ H Active
Not selected Open PMU H X X HighZ H Standby
Not selected Open External L X X HighZ L Standby
Not selected Open External H X X HighZ H Standby
Not selected Closed X L X X HighZ L Standby
Not selected Closed X H X X HighZ H Standby

2122 Sept. 1990

2-2
 Preliminary bq1001

address location in the system 1/0 map or memory map,

Functional Description followed by CE high. Note that if a write cycle is used to
open PMU memory, data integrity at the accessed loca-
Special Internal Memory tions is not guaranteed.

The PMU contains 2K bytes of special static RAM that As address inputs Ao to A15 are held valid, a high-to-Iow
can be operated as nonvolatile memory and as "cloaked" transition on the address compare strobe input, ACS,
memory. The upper 8 bytes of this memory are used for
control and status monitoring. The remaining 2040
latches the I6-bit address location into a compare
register, independent of chip enable. The 2K byte PMU
memory is accessible after three consecutive address
III
bytes of memory can be used to store critical data or
program information during a power-down cycle. matches are made, followed by CE high. The PMU
Cloaked memory, which is transparent from the main memory occupies 2K of the 64K segment controlled by
system memory map, can be used for general memory the PMU CE input.
map expansion or for secure data fields. Once opened, the PMU disables access to any external
memory occupying the same 2K bytes address space as
Mapping PMU Memory its internal mem~ This is achieved by unconditionally
The 2K byte PMU memory can be mapped in several deactivating the CECON output. Access to memory loca-
ways, depending on the system's physical address range. tions outside the PMU memory space is available as
When used by a system that addresses a maximum of usual.
64K bytes, the PMU is mapped as shown in Figure l.
Closing PMU Memory
When used by a system that addresses greater than 64K
bytes, the PMU memory may reside in any 64K byte PMU memory must be closed for either of the following
segment starting on a 2K byte boundary. In either case, purposes:
the PMU memory can occupy the upper (default) 2K or • To access external memory locations within PMU
the lower 2K bytes of the 64K segment. address space when:
Accessing PMU Memory - PMU memory is open.
The PMU memory may be accessed any time after it is
opened. Opening the PMU memory involves performing - PMU memory address space overlaps that
three consecutive read or write cycles to a user-definable particular location of the external memory.
• To update contents of registers when:

FFFF - PMU memory is open.

U
Default Location
F800 FFF8

~
FFFF
- Registers are written.
Closing the PMU memory involves issuing a set of three
F800 consecutive read or write cycles to the same address
used during the PMU open process, followed by CE high.
The open and close address location is user-definable as
described in the PMU Registers section. The default
open and close address location is 07FF.
Any updates to PMU memory, including the PMU

/ U
07F8
registers, are retained when PMU memory is closed. The
07FF
PMU is reconfigured based on register updates only
when the PMU memory is closed with a valid update
07FF pattern in the access control registers.
Optional Location
0000 0000
When the PMU is configured based on control register
~ PMU Registers MM-l
bit 3 = 1 (non-automatic open, default), and power-down
occurs with the PMU memory open, the PMU memory is
not accessible on power-up. To access the PMU memory
from this state, a c0!!!E.lete close cycle (three address
Figure 1. Memory Map matches followed by CE high) must precede the open
cycle.
Sept. 1990 3/22

2-3
bq1001 Preliminary

PMU Memory Nonvolatility

Detect
Nonvolatility is achieved by connecting a 3V backup Point
supply to the PMU BC input pin. When Vee falls to an
out-of-tolerance condition, the PMU unconditionally
write-protects its internal SRAM, independent of the R1
state of the chip enable input, CEo If a valid access is in bq1001
NMII----
process during power-fail detection, that memory cycle
may continue to completion before the memory is write-
protected. If the memory cycle is not terminated, the NMII---_
PMU unconditionally write-protects its memory within R2
time twPr.
The out-of-tolerance voltage level is VRST, which is the FG-1
same level as set for the reset output. As the supply
continues to fall below VRST, the PMU memory is sus-
tained by the external 3V source (lithium cell). On Figure 2. Threshold Voltage Monitor
power-up, the PMU memory is held inactive for time
teER (120 ms maximum) after the supply has reached
VRST to allow f~rocessor initialization, independent of Power-Down/Power-Up Reset Threshold
the state of the CE input. The bq1001 also provides reset outputs when the supply
Note that if no battery is provided, the BC pin must be voltage (Vee) passes an out-of-tolerance threshold below
grounded. which the system performance is questionable. A
precision comparator monitors the supply at the Vee pin
relative to an internal reset voltage level (VRST). The
Power Failure Detection level of VRST is user-selectable at nominal thresholds of
4.50V and 4.30V. Vee must be beyond VRST for three
Non-Maskable Interrupt Threshold consecutive 251lsec samples. During power-down, the
reset outputs are forced active as the supply falls below
The PMU warns the host processor of an impending VRST, and are held active as the supply continues to fall.
power failure and a return to full power via an output Both an active-high RST and an active-low RST are
that can be used as a non-maskable interrupt. An inter- made available to the user. The active-high output slews
nal precision comparator monitors the threshold voltage down with the supply. During power-up, the reset out-
input (VTH) or supply input (Vee) relative to an accurate puts are held active for time tRsw after Vee = VRST.
internal voltage reference. Once the VTH or Vee pin
passes this reference voltage, the non-maskable inter- The reset outputs can be inhibited for nonvolatile proces-
rupt is forced active for the time period tNMW. The VTH sor operation as described in the PMU Registers section.
or Vee input must be beyond the reference voltage for
three consecutive 251lSec samples. The threshold voltage Watchdog
input can be derived from the 5V supply, or from a
higher DC voltage upstream of the supply. Both an The bq1001 provides a watchdog function to monitor
active high NMI and an active low NMI output are made processor execution during power-valid operation. If the
available to the user. watchdog timer is enabled, then~igh-to-Iow transition
at the watchdog strobe input WD must occur during
Because the comparator threshold voltage is user-selec-
tWTO, or the watchdog timeout will take place.
table (as described in the PMU Registers section), the
PMU can directly monitor Vee if a higher voltage supply The watchdog timer can also be reset under software
is not available or is not needed. If a higher-voltage DC control by opening or closing PMU memory (see the
level is chosen for early power-fail detection, a simple PMU Registers section). If this open or close is com-
resistor divider network can be used to set the VTH volt- pleted before time tWTo, the timer is reset, and the out-
age input to the desired threshold (see Figure 2). The puts are not forced active.
internal reference voltage is set to 2.50V.
The timeout period tWTO is user-selectable as 125 ms,
Note: The active low NMI normally slews down with 500 ms, 2 sec, or infinity (i.e., disabled). The default
Vee, but can be programmed to be held high as described setting configures "a disabled watchdog monitor.
in the PMU Registers section.
The watchdog timer can be programmed to output a
NMIINMI instead of the default RSTIRST (as dermed in
the PMU Registers section).

4/22 Sept. 1990

2-4
 Preliminary bq1001

External Nonvolatile SRAM Control The DEF input can be used during valid 5V operation, or
can be used in the data-retention mode (Vcc < VBC). If
An external CMOS static RAM can be battery-backed the DEF pin is forced to ground while in data-retention
using the control output pins from the bq1001. As with mode, however, the external energy source at BC is loaded
the reset control feature, the bq1001 monitors the volt- (approximately 10K ohms) while this pin is forced low.
age level at the 5V Vcc input. As this voltage input
decays to below VRST, the conditioned chip enable pin PMU Registers
CECON is forced inactive independent of the chip enable
input CE. This activity unconditionally write-protects The PMU registers occupy the top eight bytes of the 2K
Ell
external SRAM as Vcc falls below VRST. If a valid access bq1001 memory as shown in Figure 4. Once configured,
is in progress during power-fail detection, that memory these registers maintain valid settings in the event of
cycle continues to completion before the memory is write- power loss-provided the BC pin has a valid input. Table
~tected. If the memory cycle is not terminated, the 1 shows the PMU registers and their default settings.
CECON output unconditionally write-protects the The PMU configures itself per the contents of these
memory within time twPr. registers when closed with the valid update pattern in
the access control registers.
The voltage level defined as out-of-tolerance is the same
level as set for the reset output VRST. As the supply falls
below VBC during an out-of-tolerance condition, an inter-
nal switching device forces VOUT and CECON to the exter-
nal 3V source. During power-up, VOUT and CECON are
FFFF -----~~- .-------~--

switched back to the +5V supply as Vcc rises above VBC. Default Location SCR FFFF
The CECON output is held inactive for time tCER (120 ms F800
CR
max) after the supply has reached VRST, independent of
OPENH
the CE input, to allow for processor initialization.
During normal 5V operation, the CE input is passed OPENL
----
through to CECON with a typical propagation delay of 7 AC4
ns. Nonvolatility is achieved by hardware hookup as AC3
shown in Figure 3. If external SRAM nonvolatility is not AC2
required, the VOUT and CECON outputs can be disabled AC1 FFF8
as described in the PMU Registers section.

Default Setting Override

The DEF input provides a manual override that changes 07FF
all settings in control registers back to default. It is in- Optional Location
0000
tended to be used as a user-interface input (pushbutton MM-2
to ground) and should not be driven by or connected to
any active component. See the PMU Registers section.
When the DEF pin is forced active, the RST and RST
outputs are forced active. The RST and RST outputs Figure 4. Default PMU Registers Location
remain active for time tRSW after DEF returns inactive.

+5V

L vcc Your vcc

PMU CMOS
- - SRAM
CE CON CE

-
- CE BC~3V
BACKUP
--.I.... CELL BD-3

Figure 3. Hardware Hookup

Sept. 1990 5/22

2-5
bq1001 Preliminary

Table 1. PMU Registers

Default Default Bit Settings

Symbol Name Address
7 (MSB) 6 5 4 3 2 1 o (lSB)
ACl Access control byte 1 FFF8 1 1 0 0 0 1 0 1
AC2 Access control byte 2 FFF9 1 0 1 0 0 1 1 0
AC3 Access control byte 3 FFFA 0 0 1 1 1 0 0 1
AC4 Access control byte 4 FFFB 0 0 1 0 1 0 1 1
OPENL Open and close low byte FFFC 1 1 1 1 1 1 1 1
OPENH Open and close high byte FFFD 0 0 0 0 0 1 1 1
CR Control register FFFE 0 0 1 1 1 0 1 -
SCR Status/control register FFFF - - - 1 1 1 1 1

Access Control Registers (AC1-AC4) the remaining access control bytes should be written
after the control registers are modified. This ensures
Access control bytes 1 through 4 (ACl-AC4) contain ac- that only a completed register update is recognized on
cess control information. All settings of other PMU closing.
registers are held to existing definitions until the PMU
memory is closed with the access control registers Open and Close Location Registers
written with the update pattern shown in Table 2. (OPENH and OPENL)
The upper four PMU registers (SCR, CR, OPENH, and Registers OPENH and OPENL contain the address loca-
OPENL) can be read or written at any time, but the tion for opening and closing the PMU memory. Register
PMU does not recognize register updates until the PMU OPENH contains the high address byte; that is, address
memory is closed with a valid update pattern in the bits A15-As. Register OPENL contains the low address
access control registers. When the PMU is closed with a byte, address bits A7-An. Although these two bytes can
valid update pattern, ACl-AC4 are reset to the default be read or written at any time while the PMU memory is
settings. open, they do not become active unless a valid update
During a control register update, at least one access con- pattern is present as PMU memory is closed. Any new
trol byte should be written prior to any changes to the programmed address location becomes valid only after
upper four control bytes. If the update is disrupted the PMU memory has been closed. The address location
before completion, the non-default access control pattern used to open the PMU memory must also be used to close it.
subsequently indicates that the control register data
may not be the active setting. The update pattern for

Table 2. Access Control Registers Update Pattern

Default Valid Update Bit Settings

Symbol Name Address
7 (MSB) 6 5 4 3 2 1 o (lSB)
ACl Access control byte 1 FFF8 0 0 1 1 1 0 1 0
AC2 Access control byte 2 FFF9 0 1 0 1 1 0 0 1
AC3 Access control byte 3 FFFA 1 1 0 0 0 1 1 0
AC4 Access control byte 4 FFFB 1 1 0 1 0 1 0 0

6122 Sept. 1990

2-6
 Preliminary bq1001

Control Register (CR) CR Bit 3

The control register CR is used to program: 7 6 5 4 3 2 1 0
- - - - 1 - - - Normal
• NMI threshold voltage VNMI operation
• Out-of-tolerance voltage VRST - - - - 0 - - - Automatic
open
• Assertions ofNMI and Reset
Bit 3 enables the automatic opening of PMU memory. If
• PMU memory location this bit is set to 0, PMU memory is automatically opened
on power-down when the monitored supply falls below
VNMI. If this method of operation is chosen, and a valid
CR Bit 1 access to memory is in progress when power failure
7 6 5 4 3 2 1 0 occurs, PMU memory is not opened until the user ter-
- - - - - - 1 - Normal RST/- minates the access to memory. PMU memory is also
RST assertions opened on subs~quent power-up and must be closed for
normal memory map allocation. The default setting of 1
- - - - - - 0 - RSTIRST
at hit 3 presents normal operation during power-
outputs disabled
down/power-up, which necessitates the use of the PMU
The least-significant bit, bit 0, is not used. opening procedure if user access to PMU memory is
required.
Bit 1 is used to inhibit the RST and RST outputs from
being active. The default setting of 1 in this bit provides CR Bit4
normal operation for the reset outputs. If nonvolatility 7 6 5 4 3 2 1 0
of the host processor is required, this bit can be cleared. - - - 1 - - - - Normal
This prevents the RST and RST outputs from being operation
active - - - 0 - - - - Output
CR Bit2 control
7 6 5 4 3 2 1 0
- - - - - 0 - - PMU memory at Bit 4 is used to control the RST and NMI outputs during
upper block power-down. When bit 4 is set to the default setting of 1,
these outputs behave as described previously, and any
- - - - - 1 - - PMU memory at output with a high level slews down with Vee.
lower block
If bit 4 is written to 0:
Bit 2 determines the location of the PMU memory within
the 64K byte segment. If this bit is set to 0, the default • When Vee is below VBe, the battery holds the
setting, the PMU memory resides at the upper block. If active-low outputs high, and the active-high outputs
set to 1, the PMU memory resides at the lower block. slew down with Vee.
• NMIINMI is asserted on power-down and power-up
as described previously.
• RSTIRST is not asserted on power-down, but is
asserted on power-up.
For nonvolatile microprocessor operation, writing both
bit 1 and bit 4 to 0 may be necessary.

Sept. 1990 7/22

2-7
bq1001 Preliminary

CR Bit5 SCR Bit 1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
- - 1 - - - - - VRST = 4.30 V - - - - - - 1 - CEeONnot
- - 0 - - - - - VRST = 4.50 V forced high
- - - - - - 0 - CEeoN forced
Bit 5 is used to define the out-of-tolerance voltage, VRST. high
The default setting of 1 in bit 5 dermes VRST as 4.30
volts. If a 0 is written into this bit, VRST is 4.50 volts. Bit 1 is used to set the level of the conditioned chip
enable signal CEeoN during power failure. If this bit is
CR Bits 6 and 7 set to 1 (default), the CEeoN output is not held high by
the battery during power failure. If CEeoN is to be held
7 6 5 4 3 2 1 0
high (for write-protection of an SRAM designed for non-
0 0 - - - - - - VNMI=4.60V volatility) during and throughout an out-of-tolerance
0 1 - - - - - - VNMI= 4.75 V condition, this bit must be set to O.
1 0 - - - - - - VNMI= 2.50V
SCR Bit2
1 1 - - - - - - VNMI=2.50V
7 6 5 4 3 2 1 0
Bits 6 and 7 are used to define the voltage VNMI. As - - - - - 1 - - RSTIRST output
determined by these bits, when the VTH or Vee input pin - - - - - 0 - - NMIINMI output
falls below VNMI, the NMI and NMI outputs are forced
active. A value of 1 in these bits selects the VTH pin Bit 2 of this control byte is used for defining which out-
threshold. This value for VNMI allows the use of an puts are forced active when the watchdog timer is vio-
external voltage divider network to sense power-fail con- lated. If this bit is set to 1, the RST and RST outputs are
ditions on the VTH pin. Bits 6 and 7 may alternatively forced active at watchdog violation. If this bit is set to 0,
be programmed to detect early power-fail using either of the NMI and NMI outputs are forced active. The default
two VNMI thresholds directly at Vee. The default value of setting is 1.
o in both bits selects a VNMI threshold on Vee of 4.60V.
The three combinations are user-selectable as shown. SCR Bits 3 and 4
7 6 5 4 3 2 1 0
Status/Control Register (SCR)
- - - 1 1 - - - Disabled
The status/control register SCR contains NMI status
bits, controls watc~ timeout and outputs, and sets
- - - 1 0 - - - 2 sec
the condition of the CEeoN and VOUT outputs. - - - 0 1 - - - 500 msec
- - - 0 0 - - - 125 msec
SCR BitO
Bits 3 and 4 of the control byte are used for setting the
7 6 5 4 3 2 1 0
timeout period tWTO for the watchdog monitor. The
- - - - - - - 1 VOUT not forced
high
default setting of 11 disables the watchdog monitor so
that no input at WD is required for valid operation.
- - - - - - - 0 External non- Other timeout periods are defined above.
volatile device

The least-significant bit, bit 0, determines the condition

of the VOUT output. The default setting of 1 dermes VOUT
as not being used for an external nonvolatile device.
That is, the VOUT pin is not forced high by the battery
after a power failure. If an external device (processor,
SRAM, etc.) is to be made nonvolatile, this bit should be
set to O. If this setting is chosen, the VOUT pin is held
high by the battery as Vee slews below the BC input.

8/22 Sept. 1990

2-8
 Preliminary bq1001

SCR Bits 5, 6, and 7 Bit 6 is a read/write bit that indicates whether or not a
watchdog failure has occurred.
7 6 5 4 3 2 1 0
1 - - - - - - - Power If the NMI outputs are forced active from a watchdog
fail violation, and power failure is detected during the active
- - - NMI output pulse, the NMI outputs return to the inac-
- 1 - - - Watchdog
tive state following the NMI pulse width tNMW, and are
violation
automatically forced active again within tNMW/2. This ~
- - 1 - - - - - Power automatic additional active pulse interrupts the proces- ...
valid sor due to a loss of power when this loss of power
The three most-significant bits, bits 5, 6, and 7, are real- occurred during an active NMI condition as a result of
time status bits that indicate the current power condi- the watchdog violation. If bit 6 is automatically written
tion and software-execution condition of a given system. to a 1 due to a watchdog failure, it can subsequently be
cleared only by the user writing a 0 to this location. The
Bits 5 and 7 are read-only bits that indicate the current user cannot write a 1.
power condition. If the VTH or Vee input pin (as
selected) is above VNMI, bit 5 is 1 and bit 7 is O. If the
input pin voltage falls below VNMI, bit 5 is 0 and bit 7 is
1. That is, bits 5 and 7 are always complementary.

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT ~ Vee + 0.3
relative to Vss _.._--

louT VOUT current 150 rnA

TOPR Operating temperature o to +70 "C

- _..

TSTG Storage temperature -55 to +125 "C

- - ---
TBIAS Temperature under bias -10 to +85 "C

TSOLDER Soldering temperature 260 "C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes

Vee Supply voltage VRST 5.0 5.5 V VRST is user-selectable per

PMU Registers section

Vss Supply voltage 0 0 0 V

--
VIL Input low voltage -0.3 - 0.8 V
VlH Input high voltage 2.2 - Vee + 0.3 V

VBe Backup cell voltage 2.0 - 4.0 V

VTH Threshold voltage input -0.3 - Vee + 0.3 V
Sept. 1990 9/22

2-9
bq1001 Preliminary

DC Electrical Characteristics (TA = 0 to 70"C, VCC = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±2 J-lA VIN = Vss to Vee

lLO Output leakage current - - ±2 J-lA CE = VIR or OE = VIR or
WE=VIL
VOH Output high voltage 2.4 - - V IOH = -2.0 rnA
VOHB VOH, BC supply VBe - 0.3 - - V VBe > Vee, IOH = -10J-lA
VOL Output low voltage - - 0.4 V IOL = 4.0 rnA
ISBl Standby supply current (TTL) - 7 15 . rnA CE = VIR
Standby supply current CE 2 Vee - 0.2V,
ISB2 (CMOS) - 1 3 rnA OV S VIN S 0.2V,
or VIN 2 Vee - 0.2V
Min. cycle, duty = 100%,
Icc Operating supply current - 45 70 rnA CE = VIL, IOH = OmA,
IOL = OrnA
VRST Reset trip point VRST - VRST VRST+ V VRST is user-selectable per
0.06 0.06 PMU Registers section
-
VNMI is user-selectable per
VNMI NMI trip point VNMI- VNMI VNMI+ V PMU Registers section and
0.06 0.06 is monitored at Vee or VTH.
Vso Supply switch-over voltage - VBe - V
Does not include data-
retention current provided
leeDR Data-retention current - 0.1 1.0 J-lA through VOUT to additional-
memory. TA = 25"C,
VBe = 3V
VOUTl VOUT voltage Vee - 0.3 - - V lOUT = 100rnA
Vee < VBe, VOUT enabled
VOUT2 VOUT voltage VBe - 0.3 - - V per PMU Registers section,
lOUT = 100J-lA
louTl V OUT current - 100 - rnA VOUT > Vee -0.3V
VOUT > VBe -0.3V, VOUT
IOUT2 VOUT current - 100 - J-lA enabled per PMU Registers
section

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3V.

10/22 Sept. 1990

2-10
 Preliminary bq1001

Capacitance (TA = 2S'C, F = 1MHz, VCC = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CliO Input/output capacitance - - 10 pF VIla = OV
CIN Input capacitance - - 8 pF VIN = OV

Note: This parameter is sampled and not 100% tested.

AC Test Conditions

Parameter Test Conditions

Input pulse levels o to 3.0 V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 5 and 6

960n 960n

Output 0--~-----4 Output 0 - - - 1 " - - - - - +

510 n 1- 100pF 510n 5pF

rL----=:l. . OL-16 OL-3

Figure 5. Output Load A Figure 6. Output Load B

Sept. 1990 11/22

2-11
bq1001 Preliminary

Read Cycle (TA =0 to 70·C, VCC =5V ± 10%)

-45 -70
Symbol Parameter Unit Notes
Min. Max. Min. Max.
tRC Read cycle time 45 - 70 - ns
tAA Address access time - 45 - 70 ns Output load A
tACE Chip enable access time - 45 - 70 ns Output load A
tOE Output enable access time - 20 - 35 ns Output load A
tCLz Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 5 - 5 - ns Output load B
tcHZ Chip disable to output in high Z 0 15 0 25 ns Output load B
tOHZ Output disable to output in high Z 0 15 0 25 ns Output load B
tOH Output hold from address change 5 - 5 - ns Output load A

Read Cycle No.1 (Address Access) 1,2

~----------------------tRC----------------------~

Address

=--=--tOH-=-_tAA=--=:--~~
:==1:

------p-re-v-io-u-s-o-a-t-a-V-a-li-d-----kZZz*:--o-a-t-a-V-a-li-d---
°our

RC-1

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = VIL.

12122 Sept. 1990

2-12
 Preliminary bq1001

Read Cycle No.2 (CE Access) 1,2,3

CE
III
DOUT

RC-2

Read Cycle No.3 (OE Access) 1,4

Address _tl+----_-_tRC-==~_
t -------+l~1 t AA

OE

14---- t OE - - - - . t

tOLZ

Dmrr --------~~~~------__< Data Valid

High-Z High-Z

RC-3
Notes: 1. WE is held high for a read cycle.
2. Address is valid prior to or coincident with CE transition low.
3. OE =VIL.
4. Device is continuously selected: CE =VIL.

Sept. 1990 13/22

2-13
bq1001 Preliminary

Write Cycle (TA =0 to 70·C, VCC =5V ± 10%)

-45 -70 Conditions!
Symbol Parameter Units Notes
Min. Max. Min. Max.
twc Write cycle time 45 - 70 - ns
tcw Chip enable to end 40 - 60 - ns (1)
of write
tAW Address valid to 40 - 60 - ns (1)
end of write
tAS Address setup time 0 - 0 - ns Measured from address valid to
beginning of write. (2)
twp Write pulse width 35 - 55 - ns Measured from beginning of write
to end of write. (1)
tWR Write recovery
time
3 - 5 - ns Measured from earlier of CE or
WE going high to end of write cycle.
tDW Data valid to end 20 - 30 - ns Measured from first low-to-high
of write transition of either CE or WE.
tDH Data hold time 0 - 0 - ns Measured from first low-to-high
transition of either CE or WE.
twz Write enable to 0 15 0 25 ns I/O pins are in output state. (3)
output in high Z
tow Output active 5 - 5 - ns I/O pins are in output state. (3)
from end of write

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-
impedance state.

14122 Sept. 1990

2-14
 Preliminary bq1001

Write Cycle No. 1 (WE-Controlled) 1,2,3

~---------------twe----------------~

Address

14-------------- tAw --------------<oI4-tWR

-..--....--.......----..-~ ~----------- tew -------------+/ /"~-r_.,__r~-r_-r
CE

~-----twp-------+/

WE
~--tDW ----~>--

DIN

tow ----j .
oOUT High-Z ----K"""X~X~X""7'
WC-1

Write Cycle No.2 (CE-Controlled) 1,2,3

Address

CE

~-----twp--------+I

WE
~---- tDW ----~f--

----------------------~~ Data-in Valid

DOUT

WC-2

Notes: 1. Because 110 may be active COE low) during this period, data input signals of opposite polarity
to the outputs must not be applied.
2. CE or WE must be high during address transition.
3. IfOE is high, the 110 pins remain in a state of high impedance.

Sept 1990 15/22

2·15
bq1001 Preliminary

Open and Close Cycle Timing

·45 ·70
Symbol Parameter Unit
Min. Max. Min. Max.

tACS Address valid to ACS fall 10 - 10 - ns

tACW Address compare strobe width 25 - 25 - ns
tACH Address hold from ACS fall 0 - 0 - ns
tcEH Chip enable high following 5 - 5 - ns
third strobe
tCES Chip enable setup time 0 - 0 - ns

Open and Close Cycle Timing

ACS
------------------->t::t ... ~.~I~-------tAcH f--
CE
1+-----tAcw ---------+I

t~ t
OC-1

Note: 1. CE high following the third compare strobe completes the PMU open or close operation.

16/22 Sept. 1990

2-16
 Preliminary bq1001

Power-Down/Power-Up Timing (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes

tPFD
tNMW
VNMI detect to NMI, NMI
NMI, NMI pulse width
---------- _... ---
25
12
-~---
75
25
150
40
liS
lis
Ell
tNMR NMI, NMI asserted after 50 150 200 lis Vcc > VNMI or VTH > VNMI
RST, RST inactive
tRST VRST detect to RST, RST 25 75 150 lis Power-down/up sequencing
per PMU Registers section.
tRSW RST, RST pulse width 40 80 120 ms
tPF Vcc slew, VNMI to VRST 40 - 400,000 lis
tFS Vcc slew, 4.25V to Vso 10 - - lis
tVRS Vcc valid to RST, RST 25 75 150 liS Power-down/up sequencing
per PMU Registers section.
tpu Vcc slew, VRST to VNMI 0 - - liS
tCED Chip enable propagation - 7 10 ns
delay
tCER is time required after
tCER Chip enable recovery - tRSW - ms power-valid to allow for
processor stabilization.
tWPT Write-protect time 40 100 150 liS Write-protect occurs inter-
nally and by bringing
CEcoNhigh.
tVTHF VTH slew, 3.0V to 2.0V 40 - 400,000 liS
tVTHR VTH slew, 2.0V to 3.0V 0 - - liS
Note: Typical values indicate operation at TA = 25·C.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Sept. 1990 17/22

2-17
bq1001 Preliminary

Power-Up Case 1: NMI/NMI Delayed by RST/RST Active

RST

RST

NMI
NMI

CE

tceD
CE CON VOHB

PU-2
Note: 1. SCR bit 1 = O.

Power-Up Case 2: NMI/NMI Not Delayed

NMI

NMI

PU-3

Note: 1. RST and RST are inactive before VNMI is reached.

18/22 Sept. 1990

2-18
 Preliminary bq1001

Power-Up Case 3: Under VTH Sensing

tVTHR

2.0

NMI
_ _ ------.I*_
---tlt4---I......---t
NMW
_
NMI

PU-5

Power-Up Case 4: Power-Up With CR Bit 4 = 0

VNMI
vee
Vso

t RSW
(1)

RST
VOHB
RST

VOHB
NMI /
NMI

PU-4

Note: 1. CR bit 1 = 1; RSTIRST goes active on power-up.

If CR bit 1 = 0, RST/RST is disabled.

Sept. 1990 19122

2-19
bq 1001 Preliminary

Power-Down Case 1: Under Vee Sensing

Vee

NMI +-- slew with Vee ct)

NMI

RST +-- slew with Vee Cll,C2)

RST

CE

CEeON
_________________ t_w_p_'~---------------V-~--B----------------­
PD-2
Note: 1. CR bit 4 = 1.
2. CR bit 1 = l.
3. SCR bit 1 = O.

Power-Down Case 2: Under VTH Sensing

1 + - - - tYTHF------*i

3.0

t~Lt"":1 ~
~_+--
NMI
NMI ====================>k= ___s_le_w__
w_it_h_V_C_c_C1)_______________
PD-3

Note: 1. CR bit 4 = 1.
20122 Sept. 1990

2-20
 Preliminary bq1001

Watchdog/Default Timing (TA =0 to 70°C)

Symbol Parameter Minimum Typical Maximum Unit Notes

tRsw
tWD
RST, RST pulse width
WD pulse width
40
25
"-""--""--- 1-------"-1--
80
-
120
-
ms
ns
-

--
III
tWH WD high time 50 - - ns
tWTO Watchdog timeout period 0.5 tWTO tWTO 1.5 tWTO - tWTO is user-selectable per
PMU Registers section.

Note: Typical values indicate operation at TA = 25°C.

Watchdog Timing

t WH ------J~
WD
t WTO
J'"-----------"~
WD-1

DEFTiming

DEF

RST
~~-~----------~-1L-L------tR-~----------~~l.----------
RST --------~)(~--------------------~>K
DEF-1

Sept. 1990 21/22

2-21
bq1001 Preliminary

Ordering Information

bq1001

11 Speed Option:
45=45ns
70 = 70 ns
-Package Option:
P = 40-pin plastic DIP
Q = 44-pin PLCC

-Device:
bqlOOl Processor Management Unit

22122 Sept. 1990

2·22
 ~ 8ENOIMARQ _ _ _ _ _ _ _
pre_fim_ina_ry_b_q=-1_0_0_2
Processor Management Unit (PMU)
General Description nonvolatile memory when connected
Features to a 3V backup supply.
~ 2K bytes of SRAM with latched The CMOS bql002 Processor
address Management Unit (PMU) is a spe- With its "cloaked" mode of access,
cialized battery-backup static RAM the 2K byte PMU memory can be
- Power-down write protection transparent to the system memory
that provides all functions required
- "Cloaked" SRAM may share for graceful power-down/power-up map, or it can occupy a nonover-
address space with system sequencing in applications where lapped address block.
memory uninterrupted processing is essen-
On power-up, the reset is held active
tial. Internally latched address for processor initialization. Critical
~ Two supply thresholds for power provides a low-pin-count interface to
failure "soft landing" information from the nonvolatile
multiplexed microprocessor address! memory may be retrieved, and
- Impending power-fail/power- data buses. processing may resume at the point
restored notification
Early power-fail detection is of the previous power-fail detection
- Power-downlpower-up provided via a user-definable and/or in a manner incorporating
microprocessor reset threshold input that gates a non- specific information stored at power
maskable interrupt output. A reset fail.
~ Automatic switching to backup
power is produced as the power supply A watchdog function is also provided
decays to an out-of-tolerance condi- to verify valid execution during nor-
~ Microprocessor watchdog monitor tion. mal operation. The PMU is
~ Access times of 45 and 70 ns During a power failure, the time managed through eight con-
period between the non-maskable trol/status registers, which occupy
~ Multiplexed address/data bus interrupt and the reset allows for a the upper eight bytes of its internal
"soft landing." Critical information 2Kmemory.
~ 28-pin plastic DIP; 28-pin PLCC
held in registers, counters, pointers,
etc. may be stored into the special
SRAM, which operates as a true

Pin Connections Pin Names

ADo-AD7 ~ult%lexed address/data
28-Pin PDIP 28-Pin PLCC mput output
As-A\s Address inputs
BC .... AS Address strobe input
0
::l I-
en:::;;-

0 0 0 en :t
<z»ma:<
1

DEF Default setting override input

A14 OE Output enable input
CECON
VolE WE Write enable input
CECON
A 1S WE CE Chip enable input
A12 CE AIS CECON Conditioned chip enable
All OE CE output
AIO AD7 OE
NMI Non-maskable interrupt
Ag ADs AD7 output
As 11 ADs ADs
~ ~ ~ ~ se ~ ~ RST Reset output
ADo [ 12 AD4 LlDDOOO-
0-N0(1)"'1O BC 3 volt backup cell input
ADI 13 ADa c c c "'ccc
AD2 Vss « <>«< VOUT Supply output
PL-2
Vee +5 volt supply input
PN-2 Vss Ground

Sept. 1990 1/22

2-23
bq1002 Preliminary

Pin Descriptions returns all control and status registers to the

default setting. The RST output remains ac-
ADo-AD7 Multiplexed address/data input/output tive for time tRSW after DEF returns inactive.
The bql002 bus cycle consists of two phases: Output enable input, active low
the address phase and the data-transfer
phase. The address phase precedes the data Write enable input, active low
transfer phase. During the address phase,
low-byte address placed on ADo-AD7 is Chip enable input, active low
latched into the bql002 on the falling edge of CEeON Conditioned chip enable output
the AS signal. During the data-transfer
phase, the ADo-AD7 pins serve as a bidirec- NMI Non-maskable intelTUpt output, active low
tional data bus.
RST Reset output, active high
As-A15 Address inputs
BC 3 volt backup cell input
AS Address strobe input
VOUT Supply output
For memory access operations, a falling edge
on AS latches the address on ADo-AD7, VOUT provides the higher of Vee or BC,
demultiplexing the address data bus. For switched internally, to supply external RAM.
PMU memory "open" and "close" operations,
a falling edge on AS is used to latch address Vee +5V supply input
data on ADo-AD7 and As-A15 into the
address compare register (see Accessing Vee provides the operating supply and is also
PMU Memory). the voltage comparison input for the VRST
and the VNMI thresholds.
Default setting override input, active low
Vss Ground.
DEF is intended to be used as a user-inter-
face input (pushbutton to ground). DEF
pulled low forces the RST output active and

Truth Table
Memory Memory Memory I/O
Mode State Address CE WE OE Operation CECON Power
Read Open PMU L H L DOUT H Active
Write Open PMU L L X DIN H Active
Output disabled Open PMU L H H HighZ H Active
Not selected Open PMU H X X HighZ H Standby
Not selected Open External L X X HighZ L Standby
Not selected Open External H X X HighZ H Standby
Not selected Closed X L X X HighZ L Standby
Not selected Closed X H X X HighZ H Standby

2122 Sept. 1990

2-24
 Preliminary bq1002

write cycle is used to open PMU memory, data integrity

Functional Description at the accessed locations is not guaranteed.
As address inputs ADo to AD7 and As to A15 are held
Special Internal Memory valid, a high-to-low transition on the address strobe
The PMU contains 2K bytes of special static RAM that
can be operated as nonvolatile memory and as "cloaked"
memory. The upper 8 bytes of this memory are used for
input, AS, latches the 16-bit address location into a com-
pare register, independent of chip enable. The 2K byte
PMU memory is accessible after three consecutive
Ell
control and status monitoring. The remaining 2040 address matches are made, followed by CE high. The
bytes of memory can be used to store critical data or PMU memorY.Qccupies 2K of the 64K segment controlled
program information during a power-down cycle. by the PMU CE input.
Cloaked memory, which is transparent from the main Once opened, the PMU disables access to any external
system memory map, can be used for general memory memory occupying the same 2K byte address space as its
map expansion or for secure data fields. internal memorY,---This is achieved by unconditionally
deactivating the CECON output. Access to memory loca-
Mapping PMU Memory tions outside the PMU memory space is available as
The 2K byte PMU memory can be mapped in several usual.
ways, depending on the system's physical address range.
When used by a system that addresses a maximum of Closing PMU Memory
64K bytes, the PMU is mapped as shown in Figure l. PMU memory must be closed for either of the following
When used by a system that addresses greater than 64K purposes:
bytes, the PMU memory may reside in any 64K byte • To access external memory locations within PMU
segment starting on a 2K byte boundary. In either case, address space when:
the PMU memory can occupy the upper (default) 2K or
the lower 2K bytes of the 64K segment.
- PMU memory is open.
Accessing PMU Memory
- PMU memory address space overlaps that
The PMU memory may be accessed any time after it is particular location of the external memory.
opened. Opening the PMU memory involves performing
• To update contents of registers when:
three consecutive read or write ..9:'2les to a user-definable
address location, followed by CE high. Note that if a
- PMU memory is open.
FFFF ~-----

I~u~~~
Default Location - Registers are written.
F800
Closing the PMU memory involves issuing a set of three
consecutive read or write cycles to the same address
~ used during the PMU open process, followed by CE high.
The open and close address location is user-definable as
described in the PMU Registers section. The default
open and close address location is 07FF.
Any updates to PMU memory, including the PMU
registers, are retained when PMU memory is closed. The
PMU is reconfigured based on register updates only

07FF
0000
I-----~--

Optional Location
IU"" 07F8

0000
when the PMU memory is closed with a valid update
pattern in the access control registers.
When the PMU is configured based on control register
bit 3 = 1 (non-automatic open, default), and power-down
occurs with the PMU memory open, the PMU memory is
not accessible on power-up. To access the PMU memory
~ PMU Registers MM-l
from this state, a co~lete close cycle (three address
matches followed by CE high) must precede the open
cycle.
Figure 1. Memory Map

Sept 1990 3/22

2-25
bq1002 Preliminary

PMU Memory Nonvolatility RST can be inhibited for nonvolatile processor operation
as described in the PMU Registers section.
Nonvolatility is achieved by connecting a 3V backup
supply to the PMU BC input pin. When Vee falls to an
out-of-tolerance condition, the PMU unconditionally Watchdog
write-protects its internal SRAM, independent of the The PMU provides a watchdog function to monitor
state of the chip enable input, CEo If a valid access is in processor execution during power-valid operation. If the
process during power-fail detection, that memory cycle watchdog timer is enabled, then the PMU memory must
may continue to completion before the memory is write- be opened or closed during time tWTO, or the watchdog
protected. If the memory cycle is not terminated, the timeout will take place.
PMU unconditionally write-protects its memory within
time twPT. The timeout period tWTO is user-selectable as 125 ms,
500 ms, 2 sec, or infInity (Le., disabled). The default
The out-of-tolerance voltage level is VRST, which is the setting confIgures a disabled watchdog monitor.
same level as set for RST. As the supply continues to fall
below VRST, the PMU memory is sustained by the exter- The watchdog timer can be programmed to output NMI
nal 3V source (lithium cell). On power-up, the PMU instead of the default RST (as defIned in the PMU
memory is held inactive for time teER (120 ms maxi- Registers section).
mum) after the supply has reached VRST to allow for
,E!2cessor initialization, independent of the state of the External Nonvolatile SRAM Control
CE input.
An external CMOS static RAM can be battery-backed
Note that if no battery is provided, the BC pin must be using the control output pins from the PMU. As with the
grounded. reset control feature, the PMU monitors the voltage level
at the 5V Vee input. As this voltage inE!1 decays below
Power Failure Detection VRST, the conditioned chip enable pin CEeoN is forced
inactive independent of the chip enable input CEo This
Non-Maskable Interrupt Threshold activity unconditionally write-protects external SRAM as
Vee falls below VRST. If a valid access is in progress
The PMU warns the host processor of an impending during power-fail detection, that memory cycle continues
power failure and a return to full power via an output to completion before the memory is write.:E!:otected. If
that can be used as a non-maskable interrupt. An inter- the memory cycle is not terminated, the CEeoN output
nal precision comparator monitors supply input Vee unconditionally write-protects the memory within time
relative to an accurate internal voltage reference. Once tWPT.
the Vee pin passes this reference voltage, NMI is forced
active for the time period tNMW. The Vee input must be The voltage level defIned as out-of-tolerance is the same
beyond the reference voltage for three consecutive 25~sec level as set for the reset output VRST. As the supply falls
samples. The reference voltage is user-selectable as below VBe during an out-of-tolerance condition, an inter-
described in the PMU Registers section. nal switching device forces VOUT and CEeoNto the exter-
nal 3V source. During power-up, VOUT and CEeoN are
Note: NMI normally slews down with Vee, but can be switched back to the +5V supply as Vee rises above VBe.
programmed to be held high as described in the PMU The CEeoN output is held inactive for time teER (120 ms
Registers section. max) after the supply has reached VRST, independent of
the CE input, to allow for processor initialization.
Power-Down/Power-Up Reset Threshold During normal 5V operation, the CE input is passed
through to CEeoN with a·typical propagation delay of 7 ns.
The PMU also provides reset outputs when the supply
voltage (Vee) passes an out-of-tolerance threshold below Nonvolatility is achieved by hardware hookup as shown
which the system performance is questionable. A in Figure 2. If external SRAM nonvolatility is not re-
precision comparator monitors the supply at the Vee pin quired, the VOUT and CEeoN outputs can be disabled as
relative to an internal reset voltage level (VRST). The described in the PMU Registers section.
level of VRST is user-selectable at nominal thresholds of
4.50V and 4.30V. Vee must be beyond VRST for three
consecutive 25~sec samples. During power-down, RST is
forced active as the supply falls below VRST, and is held
active as the supply continues to fall. RST slews down
with the supply. During power-up, RST is held active for
time tRSW after Vee = VRST.

4122 Sept. 1990

2-26
 Preliminary bq1002

+5V
f vee VOUT vee

PMU
- -
CMOS
SRAM III
CE eoN CE

-
- CE BC ~3V
-, BACKUP
----L- CELL BO-3

Figure 2. Hardware Hookup

Default Setting Override

FFFF
The DEF input provides a manual override that changes Default Location SCR FFFF
all settings in control registers back to their defaults. It F800
CR
is intended to be used as a user-interface input (pushbut-
ton to ground) and should not be driven by or connected OPENH
to any active component. See the PMU Registers sec- OPENL
tion. AC4
When the DEF pin is forced active, the RST output is AC3
forced active. The RST output remains active for time AC2
tRsw after DEF returns inactive. The DEF input can be
AC1 FFF8
used during valid 5V operation, or can be used in the
data-retention mode (Vee < VBe). If the DEF pin is
forced to ground while in data-retention mode, however,
the external energy source at BC is loaded
(approximately 10K ohms) while this pin is forced low.
07FF
Optional Location
PMU Registers 0000
MM-2
The PMU registers occupy the top eight bytes of the 2K
PMU memory as shown in Figure 3. Once configured,
these registers maintain valid settings in the event of
power loss-provided the BC pin has a valid input. Figure 3. Default PMU Registers Location
Table 1 shows the PMU registers and their default set-
tings. The PMU configures itself per the contents of
these registers when closed with the valid update pat-
tern in the access control registers.

Sept. 1990 5/22

2-27
bq1002 Preliminary

Table 1. PMU Registers

Default Default Bit Settings

Symbol Name Address
7 (MSB) 6 5 4 3 2 1 o (LSB)
AC1 Access control byte 1 FFF8 1 1 0 0 0 1 0 1
AC2 Access control byte 2 FFF9 1 0 1 0 0 1 1 0
AC3 Access control byte 3 FFFA 0 0 1 1 1 0 0 1
AC4 Access control byte 4 FFFB 0 0 1 0 1 0 1 1
OPENL Open and close low byte FFFC 1 1 1 1 1 1 1 1
OPENH Open and close high byte FFFD 0 0 0 0 0 1 1 1
CR Control register FFFE 0 0 1 1 1 0 1 -
SCR Status/control register FFFF - - - 1 1 1 1 1

Access Control Registers (AC1-AC4) may not be the active setting. The update pattern for
the remaining access control bytes should be written
Access control bytes 1-4 (AC1-AC4) contain access con- after the control registers are modified. This ensures
trol information. All settings of other PMU registers are that only a completed register update is recognized on
held to existing definitions until the PMU memory is closing.
closed with the access control registers written with the
update pattern shown in Table 2. Open and Close Location Registers
The upper four PMU registers (SCR, CR, OPENH, and (OPENH and OPENL)
OPENL) can be read or written at any time, but the Registers OPENH and OPENL contain the address loca-
PMU does not recognize register updates until the PMU tion for opening and closing PMU memory. Register
memory is closed with a valid update pattern in the OPENH contains the high address byte; that is, address
access control registers. When the PMU is closed with a bits A15-As. Register OPENL contains the low address
valid update pattern, ACI-AC4 are reset to the default byte, address bits A7-Ao. Although these two bytes can
settings. be read or written at any time while PMU memory is
During a control register update, at least one access con- open, they do not become active unless a valid update
trol byte should be written prior to any changes to the pattern is present as PMU memory is closed. Any new
upper four control bytes. If the update is disrupted programmed address location becomes valid only after
before completion, the non-default access control pattern the PMU memory has been closed. The address location
subsequently indicates that the control register data used to open the PMU memory must also be used to close it.

Table 2. Access Control Registers Update Pattern

Default Valid Update Bit Settings

Symbol Name Address
7 (MSB) 6 5 4 3 2 1 o(LSB)
AC1 Access control byte 1 FFF8 0 0 1 1 1 0 1 0
AC2 Access control byte 2 FFF9 0 1 0 1 1 0 0 1
AC3 Access control byte 3 FFFA 1 1 0 0 0 1 1 0
AC4 Access control byte 4 FFFB 1 1 0 1 0 1 0 0

6122 Sept. 1990

2-28
 Preliminary bq1002

Control Register (CR) CR Bit 3

The control register CR is used to program: 7 6 5 4 3 2 1 0
- - - - 1 - - - Normal
• NMI threshold voltage VNMI operation
• Out-of-tolerance voltage VRST - - - - 0 - - - Automatic
open
• Assertions ofNMI and RST
Bit 3 enables the automatic opening of PMU memory. If
• PMU memory location this bit is set to 0, PMU memory is automatically opened
The least-significant bit, bit 0, is not used. on power-down when the monitored supply falls below
VNMI. If this method of operation is chosen, and a valid
access to memory is in progress when power failure
CR Bit 1
occurs, PMU memory is not opened until CE is high.
7 6 5 4 3 2 1 0 PMU memory is also opened on subsequent power-up
- - - - - - 1 - NormalRST and must be closed for normal memory map allocation.
assertions The default setting of 1 at bit 3 presents normal opera-
r--- tion during power-down/power-up, which necessitates
- - - - - - 0 - RST disabled
the use of the PMU opening procedure if user access to
PMU memory is required.
Bit 1 is used to inhibit the RST output from being active.
The default setting of 1 in this bit provides normal CR Bit4
operation for the reset output. If nonvolatility of the 7 6 5 4 3 2 1 0
host processor is required, this bit can be cleared. This
prevents the RST output from being active.
- - - 1 - - - - Normal
operation
CR Bit 2 - - - 0 - - - - Output
control
7 6 5 4 3 2 1 0
- - - - - 0 - - PMU memory at Bit 4 is used to control the RST and NMI outputs during
upper block power-down. When bit 4 is set to the default setting of 1,
- - - - - 1 - - PMU memory at these outputs behave as described previously, and RST
lower block slews down with Vee.

Bit 2 determines the location of the PMU memory within Ifbit 4 is written to 0:
the 64K byte segment. If this bit is set to 0, the default • When Vee is below VBe, the battery holds NMI high.
setting, the PMU memory resides at the upper block. If
set to 1, the PMU memory resides at the lower block. • NMI is asserted on power-down and power-up as
described previously.
• RST is not asserted on power-down, but is asserted
on power-up.
For nonvolatile microprocessor operation, writing both
bit 1 and bit 4 to 0 may be necessary.

Sept. 1990 7122

2-29
bq 1002 Preliminary

CR Bit 5 SCR Bit 1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
- - 1 - - - - - VRST = 4.30 V - - - - - - 1 - CEeONnot
- - 0 - - - - - VRST= 4.50 V forced high

Bit 5 is used to define the out-of-tolerance voltage, VRST.

- - - - - - 0 - CEeoN forced
high
The default setting of 1 in bit 5 defines VRST as 4.30
volts. If this bit is set to 0, VRST is 4.50 volts. Bit 1 is used to set the level of the conditioned chip
enable signal CEeoN during power failure. If this bit is
CR Bits 6 and 7 set to 1 (default), the CECON output is not held high by
the battery during power failure. If CEeoN is to be held
7 6 5 4 3 2 1 0
high (for write-protection of an SRAM designed for non-
0 0 - - - - - - VNMI= 4.60V volatility) during and throughout an out-of-tolerance
0 1 - - - - - - VNMI = 4.75V condition, this bit must be set to O.
1 0 - - - - - - NMI disabled
SCR Bit 2
1 1 - - - - - - NMI disabled
7 6 5 4 3 2 1 0
Bits 6 and 7 are used to define the voltage VNMI. As - - - - - 1 - - RSToutput
determined by these bits, when the Vee input pin falls - - - - - 0 - - NMIoutput
below VNMI, the NMI output is forced active. The default
value of 0 in both bits selects VNMI = 4.60V. The com- Bit 2 of this control byte is used for defining which out-
binations are user-selectable as shown. puts are forced active when the watchdog timer is vio-
lated. If this bit is set to 1, the RST output is forced
Status/Control Register (SCR) active at watchdog violation. If this bit is set to 0, the
NMI output is forced active. The default setting is 1.
The status/control register SCR contains NMI status
bits, controls watc~ timeout and outputs, and sets
SCR Bits 3 and 4
the condition of the CEeoN and VOUT outputs.
7 6 5 4 3 2 1 0
SCR BitO
- - - 1 1 - - - Disabled
7 6 5 4 3 2 1 0 - - - 1 0 - - - 2 sec
- - - - -
- - 1 VOUT not forced - - - 0 1 - - - 500 msec
high - - - 0 0 - - - 125 msec
- - - - - - - 0 External non-
volatile device Bits 3 and 4 of the control byte are used for setting the
timeout period tWTO for the watchdog monitor. The
The least-significant bit, bit 0, determines the condition default setting of 11 disables the watchdog monitor.
of the VOUT output. The default setting of 1 defines VOUT Other timeout periods are defmed above.
as not being used for an external nonvolatile device.
That is, the VOUT pin is not forced high by the battery
after a power failure. If an external device (processor,
SRAM, etc.) is to be made nonvolatile, this bit should be
set to O. If this setting is chosen, the VOUT pin is held
high by the battery as Vee slews below the BC input.

8122 Sept. 1990

2-30
 Preliminary bq1002

SCR Bits 5, 6, and 7 Bit 6 is a read/write bit that indicates whether or not a
watchdog failure has occurred.
7 6 5 4 3 2 1 0
1 - - - - - - - Power If the NMI output is forced active from a watchdog viola-
fail tion, and power failure is detected during the active NMI
output pulse, the NMI output returns high following the
- 1 - - - - - - Watchdog

- - 1 - - - - -
violation
Power
NMI pulse width tNMW, and is automatically forced low
again within tNMw/2. This automatic additional active
pulse interrupts the processor due to a loss of power
III
valid when this loss of power occurred during an active NMI
condition as a result of the watchdog violation. If bit 6 is
The three most-significant bits, hits 5, 6, and 7, are real- automatically written to 1 due to a watchdog failure, it
time status hits that indicate the current power condi- can subsequently be cleared only by the user writing 0 to
tion and software-execution condition of a given system. this location. The user cannot write a 1.

Bits 5 and 7 are read-only bits that indicate the current

power condition. If the VTH or Vee input pin (as
selected) is above VNMI, bit 5 is 1 and bit 7 is O. If the
input pin voltage falls below VNMI, bit 5 is 0 and bit 7 is
1. That is, bits 5 and 7 are always complementary.

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT~Vee+0.3
relative to Vss
lOUT VOUT current 150 rnA
TOPR Operating temperature o to +70 °C

TSTG Storage temperature -55 to +125 °C

TBIAS Thmperature under bias -10 to +85 °C
TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods oftime may affect device reliability.

Recommended DC Operating Conditions (T A = 0 to 70°C)

Symbol Parameter Minimum Typical Maximum Unit Notes

Vee Supply voltage VRST 5.0 5.5 V VRST is user-selectable per

PMU Registers section
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V
VBe Backup cell voltage 2.0 - 4.0 V

Sept.1990 9/22

2-31
bq1002 Preliminary

DC Electrical Characteristics (TA = 0 to 70·C, VCC = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±2 ~ VIN = Vss to Vcc

lLO Output leakage current - - ±2 ~ CE = VIH or OE = VIH or
WE=VIL
VOH Output high voltage 2.4 - - V IOH= -2.0 rnA
VOHB VOH, BC supply VBC - 0.3 - - V VBC > Vcc, IOH = -1O~
VOL Output low voltage - - 0.4 V IOL = 4.0 rnA
ISB! Standby supply current (TTL) - 7 15 rnA CE =VIH
Standby supply current CE ;?: Vcc - 0.2V,
ISB2 (CMOS) - 1 3 rnA OV ~ VIN ~ 0.2V,
or VIN;?: Vcc - 0.2V
Min. cycle, duty = 100%,
Icc Operating supply current - 45 70 mA CE = VIL, IOH = OrnA,
IOL = OmA
VRST Reset trip point VRST - VRST VRST+ V VRST is user-selectable per
0.06 0.06 PMU Registers section
VNMI is user-selectable per
VNMI NMI trip point VNMI- VNMI VNMI+ V PMU Registers section
0.06 0.06 and is monitored at Vcc.
Vso Supply switch-over voltage - VBC - V
Does not include data-
retention current provided
ICCDR Data-retention current - 0.1 1.0 ~ through VOUTto addition-
al memory. TA = 25·C,
VBC =3V
VOUTl VOUT voltage Vcc - 0.3 - - V lOUT = 100rnA
VCC < VBC, VOUT enabled
VOUT2 VOUT voltage VBC - 0.3 - - V per PMU Registers section,
lOUT = 100~
lOUT! VOUT current - 100 - rnA VOUT > Vcc -0.3V
VOUT > VBC -0.3V, VOUT
IOUT2 VOUT current - 100 - ~ enabled per PMU
Registers section

Note: Typical values indicate operation at TA = 25·C, Vcc = 5V or VBC = 3V.

10/22 Sept. 1990

2-32
 Preliminary bq1002

Capacitance (TA = 25'C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIIO Input/output capacitance - - 10 pF VIla= OV
CIN Input capacitance
.-.---~"--
- - 8 pF VIN = OV

Note: This parameter is sampled and not 100% tested.

AC Test Conditions

Parameter Test Conditions

Input pulse levels o to 3.0 V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 4 and 5

960n 960n

Output o--~---,~~~~~ Output o-~---,~~~~--+

510n
-----I 100pF
510n

OL-16 OL-3

Figure 4. Output Load A Figure 5. Output Load B

Sept. 1990 11/22

2-33
bq1002 Preliminary

Read Cycle (TA = 0 to 70'C, Vcc = 5V ± 10%)

-45 -70
Symbol Parameter Unit Notes
Min. Max. Min. Max.

tRC Read cycle time 45 - 70 - ns

tACE Chip enable access time - 45 - 70 ns Output load A
tOE Output enable access time - 20 - 35 ns Output load A
tCLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 5 - 5 - ns Output load B
teHZ Chip disable to output in high Z 0 15 0 25 ns Output load B
tOHZ Output disable to output in high Z 0 15 0 25 ns Output load B
tASW Address strobe width 20 - 20 - ns
tAS Address setup time 10 - 10 - ns
tAR Address hold time 0 - 0 - ns
tASF Delay, AS fall to CE, OE 0 - 0 - ns
tASR Delay, CE, OE to AS rise 0 - 0 - ns
tOA Delay, OE to address change 0 - 0 - ns
teA Delay, CE to address change 0 - 0 - ns

12122 Sept. 1990

2-34
 Preliminary bq 1002

Read Cycle No.1 (CE Access)1,2

AS

High Z

- - t
AC
-~dc
RC-6

Read Cycle No.2 (OE Access)1,3

AS

High Z

--~?-
=1-
1 4 - - - - - - - - - - - t RC

RC-7

Notes: 1. WE is held high for a read cycle.

2. DE = VIL.
3. Device is continuously selected: CE = VIL.

Sept. 1990 13/22

2-35
bq1002 Preliminary

Write Cycle (TA = 0 to 70'C, vcc = 5V ± 10%)

-45 -70 Conditions!

Symbol Parameter Units Notes
Min. Max. Min. Max.
twc Write cycle time 45 - 70 - ns

tcw Chip enable to end of 40 - 60 - ns (1)

write
twp Write pulse width 35 - 55 - ns Measured from beginning of write
to end of write. (1)
tWR Write recovery time 3 - 5 - ns Measured from earlier of CE or WE
going high to end of write cycle.
tDW Data valid to end of write 20 - 30 - ns Measured from first low-to-high
transition of either CE or WE.
tDH Data hold time 0 - 0 - ns Measured from first low-to-high
transition of either CE or WE.
twz Write enable to output in 0 15 0 25 ns I/O pins are in output state. (3)
highZ
tow Output active from end 5 - 5 - ns 110 pins are in output state. (3)
of write
tABW Address strobe width 20 - 20 - ns
tAB Address setup 10 - 10 - ns
tAH Address hold time 0 - 0 - ns
tASF Delay, AS fall to CE, WE 0 - 0 - ns
tASR Delay, CE, WE to AS rise 0 - 0 - ns

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-
impedance state.

14122 Sept. 1990

2-36
 Preliminary bq1002

Write Cycle No. 1 (WE-Controlled)

AS
-
1+---- tew - - - - - . I
~----------~~~~ ,-~~----------
CE

~---- twp - - - - - t - - - + i

WE

tow

AD OUT

WC-10

Notes: 1. Because I/O may be active COE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
2. CE or WE must be high during address transition.
3. IfOE is high, the I/O pins remain in a state of high impedance.

Sept. 1990 15/22

2-37
bq1002 Preliminary

Write Cycle No.2 (CE-Controlled)

AS

twp

WE

tcw

CE

tDW

AD IN

_ _tnt-
AD OUT

~----------------------twc ~
WC-11

Notes: 1. Because 1/0 may be active (OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
2. CE or WE must be high during address transition.
3. IfOE is high, the 110 pins remain in a state of high impedance.

16122 Sept. 1990

2-38
 Preliminary bq 1002

Open and Close Cycle Timing

-45 -70
Symbol Parameter Unit
Min. Max. Min. Max.

tAS Address setup time 10 - 10 - ns

tASL Address strobe low time 25
-
- 25 - ns
tAB Address hold time 0 - 0 - ns
tCEH Chip enable high following 5 - 5 - ns
third strobe
tCES Chip enable setup time 0 - 0 - ns

Open and Close Cycle Timing

AD o-AD7.
A8-A~ -------->t ________________________.

t AS _~+I!.---- t
f
AH - - - - . I
____________________

AS

CE
1 4 - - - - - - t ASL - - - - - + I

'= t
OC-2

Note: 1. CE high following the third strobe completes the PMU open or close operation.

Sept 1990 17/22

2-39
bq1002 Preliminary

Power-Down/Power-Up and Watchdog Timing (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes

tPFD VNMI detect to NMI 25 75 150 fls

tNMW NMI pulse width 12 25 40 fls
tNMR NMI asserted after RST 50 150 200 flS Vcc> VNMI
inactive
tRST VRST detect to RST 25 75 150 flS Power-down/up sequencing
per PMU Registers section.
tRsw RST pulse width 40 80 120 ms
tPF Vee slew, VNMI to VRST 40 - 400,000 fls
tFS Vcc slew, 4.25V to Vso 10 - - flS
tVRS Vcc valid to RST 25 75 150 flS Power-down/up sequencing
per PMU Registers section.
tpu Vcc slew, VRST to VNMI 0 - - flS
tCED Chip enable propagation - 7 10 ns
delay
tcER is time required after
tCER Chip enable recovery - tRsw - ms power-valid to a.How for
processor stabilization.
Write-protect occurs
tWPT Write-protect time 40 100 150 fls internally and by bringing
CECONhigh.
tWTO Watchdog timeout period 0.5tWTO tWTO 1.5 tWTo - tWTO is user-selectable per
PMU Registers section.

Note: Typical values indicate operation at TA = 25'C.

DEFTiming

DEF

"'-----~-t _ t R S W_ ,

RST
----------~~ ~~------
DEF-2

18122 Sept. 1990

2-40
 Preliminary bq1002

Power-Up Case 1 : NMI Delayed by RST Active

RST

tNMR
tNMW

NMI

CE

PU-6

Note: 1. SCR bit 1 = o.

Power-Up Case 2: NMI Not Delayed

NUl
tpFD ~t~_t_NMW~~----~ _____
PU-7
Note: 1. RST is inactive before VNMI is reached.

Sept. 1990 19/22

2-41
bq 1002 Preliminary

Power-Up Case 3: Power-Up With CR Bit 4 = 0

V NM1

Vso

-....f--- t RSW
(1)

RST

__V._OH_B__________ ~/~---------------------t-N-M~R~tMM~
NMI

PU-8

Note: 1. CR bit 1 = 1; RST goes active on power-up.

rfCR bit 1 = 0, RST is disabled.

20/22 Sept. 1990

2-42
 Preliminary bq1002

Power-Down Case: Under Vee Sensing

Vee
VNM1 -
tPFD

NMI - slew with Vee /11

_- slew with Vee /11,/21

RST

CE

tWPT~________________V_OH__B__________________
CEeON
------------------- PD-7

Note: 1. CR bit 4 = 1.
2. CR bit 1 = 1.
3. SCR bit 1 = O.

Sept. 1990 21/22

2-43
bq1002 Preliminary

Ordering Information

bq1002 -

11 Speed Option:
45=45ns
70 = 70 ns
- Package Option:
P =28-pin plastic DIP
Q = 28-pin PLCC

Device:
hql002 Processor Management Unit

22122 Sept. 1990

2-44
 ~ BENOIMARQ _ _D_e_si~g_n_in......;;;;g_W_ith_th_e_P_M_U
Using the bq10011bq1002
Nonvolatility of PMU memory is essential for proper
Introduction device operation through power-down/power-up cycles.
Integral control circuitry makes PMU memory non-
This design note is provided to simplify the design of
systems using the bql00l or bql002 Processor Manage-
ment Unit (PMU). Use this note with the bql00l or
volatile when the BC pin is connected to a 3V backup
source.
fill
bql002 data sheet. PMU memory can be located at the top or bottom 2K
block of the 64K segment as shown in Figure 1. The 64K
The PMU provides the functionality of a microprocessor segment is any segment within the system address space
supervisory circuit and 2K bytes of nonvolatile SRAM. that starts on a 2K boundary. The default PMU memory
Unlike other supervisory circuits, the PMU operation is location is at the top of the 64K segment.
configured and controlled through a set of eight con-
trol/status registers. These registers occupy the top eight PMU memory can exist in either "open" or "closed" state.
bytes of the 2K byte PMU memory. This makes accessing PMU memory is accessible only in the open state. PMU
PMU memory a significant aspect of the design. memory is not accessible in the closed state.
The design issues discussed here are grouped under the PMU memory is opened or closed by perform~ three
following topics: consecutive address match cycles followed by CE high.
During an address match, address data on the 16
• Memory interface address lines is latched into a 16-bit compare register on
Hardware the falling edge of ACS (AS for bql002). The 16 address
lines of the bql00l are Ao-A15; the bql002 address lines
Software are ADo-AD7 and As-A15. The latched address is com-
pared with the configured open/close address in registers
• Microprocessor supervisor interface OPENH and OPENL. When three consecutive matches
Power-faillpower-recovery detection are made, the PMU memory switches states following
CE high.
Reset generation
Nonvolatile memory control
Watchdog monitor
Wherever necessary, design concepts are supported by
logical diagrams and assembly-code listings for repre-
sentative microprocessors and microcontrollers. Num-
bers related to address space are expressed in
hexadecimal.
FFFF
FBOO
Oefault Location

\ r1 FFFF
FFFB

FBOO

Memory Interface
The 2K byte PMU memory has the following charac-

/ lj
teristics:
07FF
• 2040 bytes for general storage and 8 bytes for 07FB
control registers
• Nonvolatile when operated with a 3V backup source 07FF
Optional Location
0000 0000
• Relocatable within a 64K address space
• Controlled access ~ PMU Registers MM-l

Figure 1. Memory Map

2-45
Designing With the PMU

Memory Interface Hardware Regardless of the address space, if the PMU and exter-
nal SRAM are the onJL devices that share the PMU 64K
The bq1001 memory interface is typical of that for an address space, then CECON can directly drive the CE of
SRAM. The interface for the bq1002 is similar to that of the external memory device.
an SRAM with an integral address latch. In either case,
the logic for generating CE and ACS (AS for bq1002) ACS/AS Logic
requires some special consideration. The ACS pin on the bq1001 is responsible only for the
PMU memory open/close operation. On the bq1002, AS
CE Logic
serves two purposes: latching the open/close address and
The logic circuit for generating CE is dictated by two demultiplexing the address/data bus, ADo-AD7. To keep
PMU memory attributes. hardware/software overhead to the minimum, it is sug-
gested that a write data strobe signal (WR for the Intel
• Ability to exist in either open or close state. bus) be used to drive the logic for ACS/AS during an
open/close operation.
• Ability to decode its own address space within the
64K segment. "Cloaking" PMU Memory
These attributes suggest two distinct logic circuits for The ability to open/close allows PMU memory to reside
CE depending on system address space. within the same address space as external memory.
• For systems that address a maximum of 64K bytes, This is accom~hed by using the condition~ chip-
drive CE of PMU with either a data strobe or an enable output (CECON) of the PMU to drive the CE logic
address strobe, whichever is easily available. This of external memory (see Figures 2 and 3). PMU memory
follows from the open/close requirement that CE is cloaked (or transparent) when used in this way.
must be high at the end of an open/close cycle. Table 1 summarizes PMU memory cloaked operation for
When used this way, any address decode logic the circuit shown in Figure 2. As shown in the last row of
required for other devices in the system should Table 1, PMU memory shadows the top 2K bytes of the
gate the CECON output of the PMU to avoid bus SKxSSRAM.
contention.
Cloaked mode of operation requires that:
• For systems that address beyond 64K, the address
decode logic for the PMU should ensure that CE is • CE of the PMU is active for both the PMU and
low for the PMU 64K segment. Any address decode external SRAM address space
logic required for devices that are mapped within
the 64K segment should gate the CECON output of • CE logic of external SRAM is driven by the CECON
the PMU to avoid bus contention. output of the PMU.

Table 1. PMU Memory Cloaked Operation

PMU Memory Address Space PMU Memory External Memory

Closed xxxx-xxxx Not accessible Accessible if addressed
Open EOOO-F7FF Not accessible Accessible
Open FSOO-FFFF Accessible Not accessible

x= Any hexadecimal digit.

2-46
 Designing With the PMU

DATA

ADDRESS
l
RD r-- r-- Ell
WR I-- I--

AS
(Addre88 Strobel

-
1
CE
" 7
Ao-A,. 0 0 -0 , WE
-
DE CECON CE
7 "
AO-A,. 0 0 -0 ,
-
WE
-
DE

bq1001 VDUT -----. Vee CMOS SRAM

C1I 8K x 8

(11 For Nonvolatile Operation

BD-19

Figure 2. Example of PMU Setup in Cloaked Mode

SYSTEM PMU SRAM

FFFF , . - - - - - - - - , FFFF I Selected FFFF~

F800 L ._ _ _ _- '

EOOO~

07FF I Optional
0000 ' - - - - - - - - - ' 0000 L .- - - - - '

F//7/:l SRAM
Address Space 8tladowed
~ By Selected PMU Memory Block BO-20

Figure 3. Address Map of Circuit Shown in Figure 2

2-47
Designing With the PMU

Microprocessor Interfaces
The following figures illustrate typical PMU interfaces to
common microprocessors.

bq1001 to 8-Bit Microprocessors: Zilog Z80®

bq1001
°0-07 V' " °0-07
~ v
(1)
ACS VOUT ---- -. VCC

- -
RO OE

-
WR WE
CMOS
SRAM
(3,4)

zeo bq1001

A, (1),(2)
Ao-A 15 Ao-A 15 CE CON ----
-V
- -
UREQ
-CE BC

G
l
80-21

Notes: 1. For nonvolatile control of external SRAM.

2. For cloaked mode of operation.
3. If this is not the only device, an address decoder gated with CECON should be used.
4. Address and data bus per standard connection to CMOS SRAM.

2-48
 Designing With the PMU

bq1001 to 16-Bit Microprocessors: Intel® 80x86

M/iO
-
RO /

-
WR

"16-"19 Address ~
V Decoder
STB
8086
"LE

'~ Latch
j ADDRESS /
"00-"0 15

'" rV i-- I

O"TA /

MN/M"X - - V e e
LH
"0"15 0 0-0 7 eE -WE -OE AeS
,H
"ci"n 00 .0 7 WE
-OE

CMOS
bq1001
VOUT ~. Vee SRAM
-
.r- Be CE eON
eE
- (3)

(11,(21
IL __________
•
JI
BD-30

Notes: 1. For nonvolatile control of external SRAM.

2. For cloaked mode of operation.
3. If this is not the only device, an address decoder gated with CECON should be used.

2-49
Designing With the PMU

bq1001 to 16-Bit Microprocessors: Motorola 680xO

«t
Your -----t Yee

CMOS
AS Address ........----t-~CE 8RAM
Decoder C8.41
6aoxO bq1001

UD8 1 - - - - - . - - - - - /
CE CON
DTACK 14----+----------1

RM 1---..--+--/ >--------.! WE Be

) - - - - - - - . t OE l
BD-22

Notes: 1. For nonvolatile control of external SRAM.

2. For cloaked mode of operation.
3. If this is not the only device, an address decoder gated with CECON should be used.
4. Address and data bus per standard connection to CMOS SRAM.

2-50
 Designing With the PMU

bq1002 to a-Bit Microcontrollers: Intel® MCS®-51

•
ADO-AD 7 v~ ~
,/
ADO-AD7

Ali A 16 -;
v
A8-~5 V OUT
(1)
- - - - - . , . VCC

ALE
pte .J
AS
CMOS
MCS-51 bq1002 SRAM
- 13,4)
CE

-
RD
-
OE

WR
-WE
(1),12) _
CECON - - - - - . , . CE
BC
~

80-23

Notes: 1. For nonvolatile control of external SRAM.

2. For cloaked mode of operation.
3. If this is not the only device, an address decoder gated with CECON should be used.
4. Address and data bus per standard connection to CMOS SRAM.

2-51
Designing With the PMU

bq1002 to 8-Bit Microcontrollers: Motorola 68HC11

111
A8~5~ ______________________- , / VOUT - - - - - .. VCC

AS 1--.__--1

PA3 f--f---+ )--------tlAS

68HCII bq1002 CMOS

SRAM
'---+--------------------~ CE 13,41

R/W I--~--Q
)O--*"-----------.!WE

E I----+--+

0 - - - - - - - - - 1 OE
111,121 _
- - - - - .. CE
, - - - - 1 BC

80-31

Notes: 1. For nonvolatile control of external SRAM.

2. For cloaked mode of operation.
3. If this is not the only device, an address decoder gated with CECON should be used.
4. Address and data bus per standard connection to CMOS SRAM.

2-52
 Designing With the PMU

Memory Interface Software The following steps are recommended to accomplish

PMU initialization/configuration:
The software design for the PMU memory interface is
1. Open PMU memory.
concerned with:
2. Write the valid update pattern (see the data
• PMU initialization sheet) in register AC1.
•
•
Power-fail operation
Opening and closing PMU memory
3. Write new values to SCR, CR, OPENH, and
OPENL as required.
Ell
The control/status registers occupy the top eight bytes of 4. Write the valid update patterns to the remaining
the 2K PMU memory, as shown in the memory map of registers AC2-AC4.
Figure 4. These registers control the following: 5. Close PMU memory.
• Location of the 2K PMU memory block After the last step, registers ACI-AC4 are returned to
their default pattern. This default pattern in the ACl-
• Open/close address and auto-open mode ofPMU
memory AC4 registers indicates that PMU operation conforms to
existing settings in the top four control registers. If the
• Nonvolatile control of external SRAM above steps are followed, any other pattern in ACI-AC4
indicates that values in the control registers may not be
• Microprocessor supervisory functions as intended.
When power is first applied, these registers are set to Power-Fail Operation
their default values, and PMU memory comes up in a
closed state. The default open/close address is set at The power-fail notification signal (NMl) generated by
07FF. The default PMU memory location is the top 2K the PMU may initiate the following:
block of the 64K segment.
1. Open PMU memory.
PMU Initialization
2. Save the contents of registers, counters, and
On first power-up, the PMU may be initialized to meet other critical data in the 2040 bytes of PMU
application and system requirements. This may also be memory or external nonvolatile memory.
necessary when the DEF pin has been activated or when 3. Close PMU memory.
the PMU needs to be reconfigured at any time after
power-up. If the PMU is configured for auto-open (bit 3 of CR = 0),
step 1 is not necessary; PMU memory is automatically
opened after the NMI threshold is detected on power-
down and after Vcc reaches VRST on power-up (see sec-
FFFF ----- tions on microprocessor supervisor interface).
SCR FFFF
FFF8
CR If PMU memory is not configured for auto-open and
F800
OPENH PMU memory is open when Vee becomes invalid, then
PMU memory enters a semi-closed state.
OPENL
----
AC4 To access PMU memory not configured for auto-open
AC3 after the PMU has cycled through power-fail and
recovery, follow this procedure.
AC2
ACl FFF8 1. Call the open/close routine described in the fol-
lowing section.
2. Read the PMU OPENH, OPENL registers.
07FF If the contents match the configured
-~ open/close address, then PMU memory is
07F8
~Registers open.
0000
MM-7 If the contents don't match, then PMU
memory is closed. Repeat step 1 to open PMU
Figure 4. Memory Map of PMU Registers memory.
3. Set a flag, say open_close_flag, to indicate status
of PMU memory: 1 = open 0 = closed.

2-53
Designing With the PMU

Once the PMU memory state is established on power-up, the corresponding hardware interface illustrated in the
successive calls to the open/close routine should toggle . logic diagrams.
the flag bit, to avoid inadvertent problems related to
PMU memory access. For the memory interface between the bq 1002 to 8-bit
microcontrollers, ensure that the open/close address is
Opening and Closing PMU Memory outside the PMU memory address space. If this is not
observed, data at the open/close address may be cor-
One subroutine is called to perform both the open and rupted.
close operations.
The assembly-language code in each of the five following
listings opens or closes PMU memory when used with

bq1001 to 8-Bit Microprocessors: Zilog Z80®

1
2 PUBLIC OPENCLOSE
3
4 OPNCLSADR EQU 07FFH ;default open/close address
5
6 OPENCLOSE: ;open/close routine begins here
7 DI ;disable interrupts
8 LD HL,OPNCLSADR ;load HL with open/close address
9 LD A, (HL) ;save contents at open/close address
10 LD (HL) ,A ;write contents of reg. A
11 LD (HL) ,A ;to the open/close address three
12 LD (HL) ,A ;consecutive times, restoring data
13 EI ;enable interrupts
14 RET ; return
15

bq1001 to 16-Bit Microprocessors: Intel®80x86

1 TEXT SEGMENT
2
3 OPENCLOSE PROC ;open/close routine begins here
4 CLI ;inhibit interrupts
5 PUSH DS ;save contents of DS
6 LDS BX,DWORD PTR CS:OPNCLSADR ;load DS:BX with open/close address
7 MOV AL, [BX] ;save the contents at OPNCLSADR
8 MOV [BX] ,AL ;write the saved contents
9 MOV [BX] ,AL ;to open/close address
10 MOV [BX] ,AL ;three consecutive times
11 POP DS ;restore DS
12 STI ;enable interrupts
13 RET ; return
14 OPENCLOSE ENDP
15
16 OPNCLSADR: DW 07FFH * 2 ;allign open/close address
17 DW OOOOH ;to fallon even boundary
18
19 TEXT ENDS

2-54
 Designing With the PMU

bq1001 to 16-Bit Microprocessors: Motorola 680xO

1
2 OPNCLSADR EQU $07FF * 2 ;a1ign open/close address
3 ito fall on even boundary
4
5
Ell
6 OPENCLOSE LINK A6, #0 ;open/close routine begins here
7 ORI #$0700,SR ;disable interrupts
8 MOVE A #OPNCLSADR,AO
9 MOVE.B (AO) ,DO ; save contents at OPNCLSADR
10 MOVE.B DO, (AO) iwrite saved contents back
11 MOVE.B ])0, (AO) ito open/close address
12 MOVE.B DO, (AO) ;three consecutive times
13 ANDI #$F8FF,SR ; enable interrupts
14 UNLK A6 ;delete stack frame
15 RTS ;return

bq1002 to 8-Bit Microcontrollers: Intel®MCS®-51

1 OPENCLOSE: ;open/close routine begins here

2 ORL PSW,#18H ;switch to alternate register set
3
4 MOV DPTR,#07FFH ;open/close address
5
6 MOV R1,IE ;clear interrupt
7 MOV IE,#O ; enables
8 SETB PL6 ;select WR
9 MOVX A,@DPTR ;save contents at
10 MOV RO,A ;open/close address
11 MOV A,#OFFH ;low byte of open/close address
12
13 MOVX @DPTR,A ;write to open/close
14 MOVX @DPTR,A ;address three
15 MOVX @DPTR,A itimes
16
17 MOV A,RO ;restore contents at
18 MOVX @DPTR,A ;open/close address
19
20 CLR PI. 6 ;select ALE
21 MOV IE,R1 ;enable interrupts
22
23 ANL PSW,#OE7H ;restore register set
24 RET ; return

2-55
Designing With the PMU

bq1002 to 8-Bit Microcontrollers: Motorola 68HC11

1
2 OPNCLSADR EQU $07FF ;default open/close address
3 REGBASE EQU $1000 ;SFR base address
4
5 OPCLINIT EQU * ;set up port A bit 3 for open/close
6 LDX #REGBASE ;load reg X with SFR base address
7 BCLR $20,X $03 ;disconnect timer from PA3
8 RTS ;return
9
10 OPEN CLOSE EQU * ;open/close routine begins here
11 SEI ;inhibit interrupts
12 LDAB OPNCLSADR ;save the contents at OPNCLSADR
13 LDAA #$FF ;load acc. A with the l.s.byte of $07FF
14 BSET O,X $08 ;set port A bit 3, PA3-select write strobe
15 STAA OPNCLSADR ;write contents of acc. A to
16 STAA OPNCLSADR ;location OPNCLSADR, three
17 STAA OPNCLSADR ;consecutive times
18 BCLR O,X $08 ;clear port A bit 3, PA3-select address strobe
19 STAB OPNCLSADR ;restore contents at OPNCLSADR
20 CLI ;enable interrupts
21 RTS ;return
22

Summary • Need to prevent watchdog time-out (using software

signal):
The following is a list of situations where closing PMU
PMU memory is open.
memory is necessary for proper operation:
The following is a list of situations where opening PMU
• Need to access external memory location within
PMU address space:
memory is necessary for proper operation:

PMU memory is already open. • Need to access PMU memory:

PMU memory is closed.
PMU memory address space overlaps that
particular location of external memory.
• Need to configure PMU:

• Need to update contents ofPMU registers: PMU memory is closed.

PMU memory is already open.
• Need to prevent watchdog time-out (using software
signal):
PMU registers have been modified.
PMU memory is closed.
• Need to recover PMU memory from a semi-closed
state: There are two situations where CECON should be used to
drive the CE logic of external memory:
PMU memory was open.
PMU memory is not configured for auto-open • For nonvolatile control of external SRAM.
(bit 3 of CR = 1).
• When address space of external memory overlaps
that ofPMU memory.
Power failed and recovered.

2-56
 Designing With the PMU

Power-Fail Sensing Hardware

Microprocessor Supervisor
Interface Follow these guidelines when using the PMU for power-
fail sensing.
The PMU offers the following supervisory functions: Proximity ofPMU
• Power-fail warning and power-recovery notification

• Reset generation
The PMU should be physically located as near to the
processor as possible. This is necessary to detect true
Vee conditions that directly affect processor operation.
Ell
• Nonvolatile memory control
Slew rate of Vee
• Watchdog monitor
The PMU generates early power-fail warning by sam-
pling the Vee or VTH input every 25 J..ls (typical) and
Power-Fail/Power-Recovery Detection comparing the result with the programmed VNMI
threshold. If the sampled value is below VNMI for each of
The PMU notifies the host processor of an impending the three consecutive sampling periods, NMI is
power-failure or power-recovery by asserting a non- generated. The same technique is followed for NMI
maskable interrupt, NMI. The PMU may be configured generation during power-up, except that sampled values
to generate this signal under Vee (default) or VTH should be greater than VNMI for each of the three con-
sensing. secutive sample periods.
Vee Sensing To avoid multiple NMI generation, the Vee fall time tPF
Clearing bit 7 of register CR selects Vee sensing for NMI (slew time between VNMI and VRST) must not exceed the
generation. maximum value specified in the data sheet. This maxi-
mum value was determined for a 200mV peak-peak ran-
Two programmable thresholds are available to accom- dom noise on Vee. The Vee fall time is dictated by the
modate power supply tolerances. The selected threshold power supply hold time and the bypass capacitor on the
is detected during power-down and power-up as shown PMU. The dominant factor is the power-supply hold time
in the power-up/power-down timing diagrams in the data parameter. A bypass capacitor in the range of 0.01 to 0.1
sheet. J..lF is recommended.
During a power failure, the user has the time between If Vee slews down at the tPF (minimum) rate, then the
VNMI and VRST to save critical data in nonvolatile time between VNMI and VRST is one sample period (40 J..ls
memory (for example, PMU memory). During power-up, maximum).
NMI is generated to allow the processor to recover data
saved earlier. Slew rate OfVTH
The above restrictions on Vee slew time apply to the VTH
VTH Sensing slew time, tVTHF.
This mode of sensing is available on the bq1001 only. The lower limit on tVTHF requires special consideration.
A 1 in bit 7 of register CR selects this mode of power- If Vee is independent of the supply monitored at VTH,
fail/power-recovery sensing. A voltage-divider network, NMI is generated even if VTH slews down in less than
illustrated in the following section, should be used to tVTHF time. If Vee and VTH are derived from the same
generate a threshold voltage of2.5Vat VTH. supply source, then the minimum slew time on VTH
should be such that VTH slews down to the internal VTH
This mode is used for early power-fail detection reference of2.5V at least one sample period (40 J..ls maxi-
upstream of the power supply or for monitoring a supply mum) before Vee slews past VRST.
independent of Vee.

2-57
Designing With the PMU

Hardware Setup Figures Example: VTP = 7.0 V; Vn = 0.7 V

Figure 5 illustrates the hardware setup for Vee sensing. Inserting values into the above equation gives:
Figure 6 illustrates the hardware setup for VTH sensing. R11R2 = 4.1
Diodes D1 and D2 are used to prevent the VTH voltage
from falling below 1.0y. This prevents spurious NMI Selecting a value of lOOK for R2 gives R1 as 410K.
generation when VTH has slewed down past 1.0V and The values for R1 and R2 can be large enough to reduce
Vee is still valid. power dissipation and at the same time should maintain
The ratio, R11R2 is related to the trip point voltage, VTP the forward bias current for diodes D1 and D2.
and diode drop, Vn:
VTP = R1IR2 (2.5 - 2Vn) + 2.5

+5V
+5V
.--------,
0.1 I' F
I Vee NMI ,-----4------1 Vee NMI
0.11' F
bq1001 bq1002

vTH
NMI GND

GND

80-28

Figure 5. Hardware Setup for Vee Sensing

7V-16V +6V
7806 Vee NMI

O.I 11 F
T
Rl bq1001

V TH NMI
QND

R2

Dl
D2

80-29

Figure 6. Hardware Setup for VTH Sensing

2-58
 Designing With the PMU

Power-Fail Sensing Software Reset Generation

The following steps may be added to the PMU initializa- The PMU generates a reset when Vee falls below or rises
tion procedure described previously. above the configured out-of-tolerance threshold, VRST.
1. If Vee sensing is required, set bit 7 to 0 and bit 6
per system requirements.
Bits 7,6: 00 - VNMI =4.60V (default)
On power-up, when Vee slews up past VRST, a reset
pulse (lOOms typical) is generated. This puts the proces-
sor in an initialized state while Vee stabilizes. During
-=-
...
power-down, a reset is generated after Vee slews past
Bits 7,6: 01- VNMI = 4.75V VRST, inhibiting any processor activity.
2. If VTH sensing is required, set bit 7 to 1 (for For nonvolatile processor operation, reset generation
bql00lonly). during power-downlpower-up may be disabled, and NMI
may be configured to be pulled high to the battery volt-
The interrupt-handler routine for NMI is invoked under
age during periods of invalid Vee. .
the following conditions:
• On power-down, when Vee or VTH (bq1001 only) Reset Generation Hardware
falls below the VNMI threshold The bql001 provides an active-low and an active-high
• On power-up, when Vee or VTH (bqlOOI only) rises reset, while the bql002 only provides an active-high
above the VNMI threshold reset. Using a pushbutton to strobe the DEF pin
provides manual reset generation.
• On watchdog time-out, if programmed to generate
NMI Reset Generation Software
The NMI interrupt-handler routine may do the following: The following steps may be added to the PMU initializa-
tion procedure:
1. Open PMU memory (if not already open).
1. Enable reset by writing a 1 in bit 1 of register
2. Read register SCR to determine what caused CR.
NMI:
2. Set bit 5 of CR according to the out-of-tolerance
Ifbit 7 = 1 (NMI on power-down), then store threshold required:
critical data into PMU memory. Skip to step 3.
Bit 5 : 1 ; VRST = 4.30V (default)
Ifbit 6 = 1 (NMI due to watchdog time-out),
clear bit 6 and perform the watchdog recovery Bit 5 : 0 ; VRST = 4.50V
procedure (described below). Skip to step 3.
3. For nonvolatile processor operation, clear bits 1
If bit 7 = 0 (NMI on power-up), then retrieve and 4 of register CR.
data saved earlier. Skip to step 3. The system initialization routine invoked after reset
3. Close PMU memory. should do the following:
4. Perform other NMI handler tasks. 1. Open PMU memory (if not already open).
For the bql00l, NMI due to power-fail/recovery can be 2. Read register SCR:
disabled by tying VTH to Vee and writing a 1 in bit 7 of
Ifbit 6 = 1, then a watchdog time-out caused
register CR. For the bql002, VNMI detection is disabled
the reset. Clear bit 6 and perform the
by writing a 1 in bit 7 of register CR. watchdog recovery procedure (described
below). Skip to step 4.
3. Perform system initialization tasks.
4. Close PMU memory (if not already closed).

2-59
Designing With the PMU

Nonvolatile Memory Control Two ways to prevent a time-out are available:

• Strobing the WD input
The PMU integral control circuitry write-protects its
internal memory and switches it to the backup energy • Opening/closing PMU memory under software
source at BC during power-down. If enabled, VOUT and control
CECON outputs provide this functionality for external
SRAM. The bq1001 has a WD input that, when toggled low once
every tWTO time, prevents the watchdog timer from
Nonvolatile Memory Control Hardware timing out.
The hardware hookup is shown in Figure 7. The software approach is recommended when hardware
is not available to toggle the WD input. The software
Nonvolatile Memory Control Software approach prevents a watchdog time-out by opening or
closing PMU memory within the configured time-out
For nonvolatile control of external memory, clear bits 0 period (tWTO). This is the only way to reset the watchdog
and 1 of register SCR as part of the PMU initialization timer on the bql002.
procedure described previously.
Watchdog Monitor Hardware
Watchdog Monitor The strobing of the WD input can be performed using a
The PMU watchdog monitor is used to supervise proces- port pin from a microcontroller. To reduce hardware
sor operation. The watchdog monitor incorporates a overhead, where a port pin is not available, the software
timer, which generates a reset (default) or NMI at the approach is recommended.
programmed time-out period.
This time-out period is user-selectable. The default set-
ting is watchdog disabled. NMI may be substituted for
reset as the watchdog time-out output.

+5V

L_ vcc V our vcc

bq1001 CMOS
- bq1002 SRAM
- - - CE

VCC
- -

3V
BACKUP
rl BC
CE CON
I
I
I
I
ADDRESS
DECODER
(2)

L _______________ J
I
I
CE

CELL

80-51
Notes: 1. Address, data, and control pins are per standard hookup.
2. The address decoder logic must be of the 74HC type. If PMU and external SRAM are the
only devices sharing the PMU 64K address space, the decoder is not required.
3. If SRAM has an active-high chip enable pin, this pin must be tied to VOUT.

Figure 7. Nonvolatile Memory Hookup

2-60
 Designing With the PMU

Watchdog Monitor Software • Generate a reset when Vee cycles through

out-of-tolerance conditions:
The following steps may be added to the PMU initializa-
tion procedure: Valid Vee operating range is 5V +/- 10%.
1. Set bits 4,3 of register SCR according to the • Provide for nonvolatile control of external SRAM
time-out period required:
• Detect and recover from abnormal system
Bits 4,3
Bits 4,3
00 ; tWTO = 125 ms
01 ; tWTO = 500 ms
operation:
Longest loop execution time or inactive time is
Ell
less than 125 milliseconds.
Bits 4,3 10 ; tWTO = 2 seconds
Bits 4,3 11 ; twTO = infmity (timer disabled)
PMU Initialization Procedure
1. Open PMU memory (if not already open).
2. If NMI is required on watchdog time-out, then
clear bit 2 of register SCR. 2. Write the valid update pattern in register AC1.
Watchdog Recovery Procedure 3. Set register CR as follows:
The watchdog timer generates either a reset or an NMI
if not reset within the programmed time-out period, Re~ ister CR Bits
tWTO. A system initialization routine or an NMI inter- 7 6 5 4 3 2 1 0 Meaning
rupt handler is invoked depending on which output was
selected for the watchdog time-out. If the run time of 1 0 VNMI= 2.5V
either routine is greater than the configured tWTO time, (VTH sensing)
the system may never recover from the watchdog time- 1 VRST = 4.3V
out condition.
The following procedure may be added to the system 1 NormalNMII
initialization routine and the NMI interrupt handler to reset operation
avoid such a situation: 1 NormalPMU
memory opera-
1. Configure the PMU to disable the watchdog tion
timer by setting bits 4 and 3 of register SCR.
0 PMU memory at
2. Perform the remaining tasks in the system top block
initialization routine or NMI interrupt handler. 1 - Reset enabled
3. Configure the PMU according to system require-
ments. This may involve enabling the watchdog
timer by setting bits 4 and 3 of register SCR to 4. Set register SCR as follows:
the desired time-out period.
Register SCR Bits
Summary 7 6 5 4 3 2 1 0 Meaning
X X X Status bits
The following paragraphs present example procedures
for PMU initialization, system initialization, and NMI
handling. The procedures reflect only the steps required 0 0 Watchdog time-
to perform supervisory functions for a target system out: 125 ms
using a bq 1001. 1 Reset signals
watchdoe: time-ou
The system specifications for supervisory functions are:
0 0 External non-
• Detect and generate power-fail warning and volatile control
power-recovery notification:
The detect point is the unregulated DC supply. 5. Write the update patterns to the remaining
registers, AC2-AC4.
The trip point is 7V (2.5V at VTH).
6. Close PMU memory

2-61
Designing With the PMU

System Initialization Procedure NMI Handler Procedure

This procedure describes PMU management within the 1. Open PMU memory (if not already open).
system initialization routine.
2. Read register SCR:
1. Open PMU memory as explained in the power-
fail operation section. If bit 7 = I, then store critical data to PMU memory.
Available locations are FSOO-FFF7.
2. Read register SCR; if bit 6 = 1, then clear bit 6
and disable watchdog timer:
If bit 7 = 0, then retrieve data stored at PMU memory
a. Write update pattern to AC 1. locations FSOO-FFF7.

b. Set bits 4 and 3 of register SCR. 3. Close PMU memory.

c. Write remaining update patterns to AC2-AC4. 4. Perform other NMI handler tasks.
d. Close PMU memory.
3. Perform system initialization tasks.
4. Enter PMU initialization procedure (described
above).

2-62
Energy Management 3
~ BENOIMARQ _ _ _ _ _A_clv._'8I7_ce_'nfQ_fTn_cm_on_b_q..;:.,2_0_0_1
Energy Management Unit (EMU)
delta voltage (-LlV) method, a
Features General Description maximum voltage threshold, and a
~ Microprocessor peripheral for the The CMOS bq2001 Energy Manage- maximum time limit. Trickle charge
total energy management of ment Unit (EMU) is a low-power control begins after full charge is deter-
battery-operated systems microprocessor peripheral providing mined. Non-operational discharge
battery and energy management before charge may be selected for oell
~ Direct measurement of battery services for systems using recharge- conditioning or capacity measurement.
consumption and capacity able (secondary) batteries. The Charge patterns may be programmed
~ Fast charging and conditioning bq2001 works directly from the DC to be constant, pulsed, or "burp"
control for nominal 3.6V to 12V
nickel cadmium, lead acid, or
nickel hydride batteries
charging supply, operating as
programmed, or from 5V Vee,
operating as a microprocessor
(alternating charge/discharge).
For the power-off condition, the
III
peripheral. bq2001-based systems bq2001 regulates the secondary bat-
~ Full-charge detection by negative can easily incorporate sophisticated tery input to maintain its own
delta voltage method, maximum capacity monitoring, battery programmed state while it simul-
voltage, and maximum time management, backup supply ser- taneously sources a backup cell out-
vices, and power-conservation put to maintain a real-time clock or
~ Register-controlled outputs for capabilities. other 3V battery-backed ICs. A 3V
energy management backup cell provides system data-
The "gas gauge" register provides retention current when the secon-
~ Provides and controls 3V the actual charge consumption from dary battery is depleted or removed.
battery-backup supply the secondary battery and allows
measurement of the battery Power management is supported by
~ Operates from 4.5-18V DC or
capacity. The programmed end-of- seven open-drain outputs controlled
4.5-5.5V Vee supplies by the EMU or the host processor.
discharge voltage (EDV) threshold
~ 24-pin SDIP or SOlC determines full discharge. These may be allocated for subsys-
tem control, LED activation, EMU
Battery management includes status indication, and system power
charge control at standard to fast switch control.
charge rates, with full charge deter-
mined using the preferred negative

Pin Connections Pin Names PS Power switch input

PSC Power switch control output
DS Data strobe input
POI Charging indicator or
RS Register select input programmable output I
DQ Data input/output POz End-of-discharge voltage indica-
INT Interrupt request output tor or programmable output 2
DC Charging supply input P03 Backup cell low indicator or
programmable output 3
SB Secondary battery input
P04 DC valid indicator or program-
BC Backup cell output mabie output 4
BCl Backup cell input P05 Gas gauge threshold indicator
CC Charge control output or programmable output 5

CPC Charge pump capacitor P06 Secondary battery fault or

output programmable output 6

CPD Charge pump diode output PO? Programmable output 7

CD Discharge control output Vee +5V system supply input

PN-3 SR Sense resistor input Vss System ground

Sept. 1990 1/26

3-1
bq2001 Advance Information

Block Diagram

iii
ii8
lIS
DO --
Buo

Pin Descriptions preceding CMR read or write command. An

incomplete data byte being transferred to or
DS Data strobe TTL input from the bq2001 is terminated if a low is
present on RS when DS becomes active,
DS is used to identify the time when read allowing synchronization of a data-byte
data is used to drive DQ or for latching write transfer (return to CMR to restart the
data present on DQ. During read cycles, sequence).
valid data is output on DQ after time tAcS
following DS asserted low._During write DQ Data bit bidirectional TTL inputJoutput
cycles, the rising edge on DS latches the
input data on DQ into the bq2001. DQ is used to transfer one bit of data from or
to the bq2001. During a read cycle, the
RS Register select TTL input bq2001 outputs one bit of data on the DQ pin
at time tACS after the falling edge of DS and
RS is used during an access cycle to identifY returns the output driver to the high-im-
the data byte type. RS low identifies the pedance state tnHR time after DS rises.
data bit as part of a command byte to be Valid write data must be presented for time
written to the command register, CMR. RS tnw before the rising edge ofthe DS pulse.
high identifies the data bit as part of a read
or write data byte for th.e control and status
register or storage RAM as addressed in the
2126 Sept. 1990

3-2
 Advance Information bq2001

Interrupt request output and secondary battery replaced. SB also

powers the BC output and bq2001 data
INT, an open-drain output, goes low for time retention.
tINT to indicate an interrupt request. The
interrupt request is activated by secondary BC Backup cell output
battery low, the gas gauge threshold, or a
low transition on the PS pin. INT may be BC is the backup cell supply output pin. A
tied to the NMI of the host processor so that the voltage regulated from SB is output on BC as
system can not overlook this request. INT goes a backup source for a real-time clock, data
to high impedance in the absence ofVcc. retention, and other battery-backed require-
ments (see Figure 1).
DC DC supply input
Backup cell input
DC is the secondary battery charging supply
input. DC must be provided a valid voltage
during charge actions. The DC input powers
BCI is the supply input for a 3V backup cell.
No protective circuits are required between
III
the bq2001 during charge actions in the the backup cell and BCI (see Figure 1).
absence of Vcc.
When the BC output voltage regulated from
SB Secondary battery supply input SB falls below the backup cell voltage, the
backup cell is switched directly through the
SB is the secondary battery input pin. SB is bq2001 to the BC output.
monitored for negative delta voltage (-/1V),
maximum battery voltage, end-of-discharge BCI is monitored for the backup cell low-voltage
voltage (EDV), secondary battery inoperable, threshold.

Backup Supply
to System
BC 1 - - - - - _

bq2001
EMU
3V
Backup
Cell
~---I SB BCI
Secondary I
Battery ~

Backup Cell

BD-12A

Figure 1. Backup Supply and Sources

Sept. 1990 3/26

3-3
bq2001 Advance Information

CC Chargecontrolou~ut during the discharge period of a charge

action interval. (See Charge Action.)
CC is an open drain output that is high
impedance during the charging period of a SR Sense resistor input
charge action interval. CC provides charge
control if used to switch an external n-chan- SR, part of the gas gauge subsystem, is used
nel power FET. For full n-FET turn-on, the along with SB to measure the voltage across
voltage at CC may be two times the voltage the sense resistor. The sense resistor should
at DC. be chosen by fitting it to the profile of the
secondary battery discharge rate, allowing
CPC Charge pump capacitor ou~ut the highest gas gauge accuracy. Typical ap-
plications achieve the highest accuracy when
CPC is part of the voltage-doubler circuit. the voltage drop across the sense resistor is
The voltage-doubler output is only available in the range of 50 to 125 m V during the dis-
to pin CC. This pin should be connected to charge periods that dominate battery drain.
one end of a capacitor. The capacitor value (See Capacity Monitoring for details.)
must be as large as the input capacitance of
the n-FET being controlled and may be a Caution: To avoid damaging the device,
maximum of 1J.IF. (See Figure 2.) the sense resistor must be in the
discharge path and must not be in the
If the voltage doubler is not used, CPC must charge path. See Figure 3.
be left open.
Power switch input
CPD Charge pump diode output
PS indicates system on/off status to the
CPD is part of the voltage-doubler circuitry. bq2001. PS is pulled to VBC by a lOOK ohm
The CPD pin supplies the charge pump for resistor. In conjunction with PSC output, PS
the voltage doubler. This output is inactive may be used as the control input of a FET
when CC is low. switch.
CD Discharge control output PS low causes the following actions:
CD is an open drain output used to control an 1. Activates PSC ifPSC is inactive.
n-channel power FET during a bq2001-control-
led discharge. CD is high impedance during 2. Discontinues any existing charging action
the discharge phase of a charge action or prior to PSC being activated.
DC

CPC CC 1 - - - - - - - '
Charge

bq2001
=h Path

CPO II.
EMU n bq2001 S8 I------<r------+
EMU
"'~
CC

Discharge
80-10 Path

80-11

Figure 2. Voltage Doubler and Charge Figure 3. Sense Resistor in Discharge Path
Control
4126 Sept. 1990

3-4
 Advance Information bq2001

3. Sets the power switch state bit, status register bit 2 = 0, P03 is controlled by output
register bit 7, to 1. control register (OCR) bit 2.
4. Generates an INT low output for time tINT. P04 DC valid indicator or programmable out-
put 4
Power switch control output
P04 is an open-drain output that may be
PSC is an open-drain output that may be programmed to indicate the condition of
used for turning system power on or off. PSC status register (SR) bit 4, DC valid (mask
is activated (low impedance to Vss) following register bit 3 = 1). When mask register bit 3
PS low and deactivated by writing the = 0, P04 is controlled by output control
power-off command to the command register register (OCR) bit 3.
(CMR). The polarity is meant to drive a p-
channel FET. P05 Gas gauge threshold or programmable _
output 5
When PSC is active, a charge action may
only be initiated through the command P05 is an open-drain output that may be
register, CMR. programmed to indicate the condition of
status register (SR) bit 5, gas gauge notifica-
When PSC is inactive, a charge action may tion (mask register bit 4 = 1). When mask
be initiated by the appearance of DC. register bit 4 = 0, P05 is controlled by output
control register (OCR) bit 4.
The status of PSC is reflected in the status
register (SR) power switch state bit. P06 Secondary battery fault indicator or
programmable output 6
Charging indicator or programmable out-
put! P06 is an open-drain output that may be
programmed to indicate the condition of
POI is an open-drain output that may be status register (SR) bit 6, secondary battery
programmed to indicate the condition of fault (mask register bit 5 = 1). When mask
status register (SR) bit 1, charging (mask
°
register bit = 1). When mask register bit
= 0, POI is controlled by output control
° register bit 5 = 0, P06 is controlled by output
control register (OCR) bit 5.
register (OCR) bit 0. P07 Programmable output 7
End-of-discharge voltage indicator or P07 is an open-drain output. When mask
programmable output 2 register bit 6 = 0, P07 is controlled by output
control register (OCR) bit 6.
P02 is an open-drain output that may be
programmed to indicate the condition of Vee Vee supply input
status register (SR) bit 2, end-of-discharge
voltage (mask register bit 1 = 1). When mask Vee, 5V system supply, must be valid during
register bit 1 = 0, P02 is controlled by output system operation to operate the microproces-
control register (OCR) bit 1. sor interface and-in the absence of DC-the
gas gauge.
Backup cell low indicator or program-
mable output 3 Vss Ground
P03 is an open-drain output that may be Vss is the system ground pin. All bq2001
programmed to indicate the condition of supplies are defined relative to this pin.
status register (SR) bit 3, backup cell low
(mask register bit 2 = 1). When mask

Sept. 1990 5/26

3-5
bq2001 Advance Information

Functional Description DS (data strobe input pin) is used during write cycles to
latch the data at DQ into memory, and during read
Microprocessor Interface cycles to clock the EMU data out on DQ. DS should be
gated with the chip select generated for the bq2001.
The bq2001 provides a simple and space-efficient three- Input data is accepted as valid only after the last bit of a
pin serial data interface to Intel, Motorola, and other bus complete byte is written.
architectures. This interface is active only when Vee is
valid. Table 1 shows the microprocessor interface truth A fourth microprocessor interface pin, INT (interrupt
table. request output), allows the EMU to generate interrupt
requests to the host processor. The interrupt flag bit
The interface uses command bytes (written to command (INTF) in the status register (SR) is set to 1 when INT
register, CMR) that direct access to 17 data bytes used goes active. Powered by Vee, INT becomes active for any
for control and status, and to 32 data bytes provided for of three reasons:
nonvolatile storage of programmer-defined information.
CMR is used to directly write any of three direct control • PS (power switch input) is pulled low, indicating a
commands or to manage subsequent data-byte access. power-on or power-off request.
Data-byte access through CMR involves writing one of • Gas gauge notification COON) status is set, indicating
the four access commands. Two of the commands direct the secondary battery has discharged to the
access to the control and status registers, and two direct programmed gas gauge threshold.
access to the storage RAM. Each of the four data-byte • End-of-discharge voltage (EDV) status is set,
access commands includes the internal data-byte indicating the secondary battery has discharged to
address. the programmed voltage threshold. Specific actions
The physical interface uses bidirectional DQ (data 110 may be called for to avoid disruption of work in
pin) to read or write data one bit at a time. The logic progress.
level on RS (register select input pin) identifies the byte
currently being accessed as CMR (command register) or
a data byte.

Table 1. Microprocessor Interface Truth Table

Immediately Prior
Command Byte
Mode RS OS I/O Operation
Command Field Address Field
Output disable X H XXX XXXXX HighZ
Command L L XXX XXXXX DIN
Control and Status Register:
Read H L 011 XXXXX DOUT
Write H L 101 XXXXX DIN
Storage RAM:
Read H L 010 XXXXX DOUT
Write H L 100 XXXXX DIN

6126 Sept. 1990

3-6
 Advance Information bq2001

Capacity Monitoring secondary battery capacity. When the battery discharges

to EDV, the last gas gauge value is automatically loaded
The bq2001 incorporates a "gas gauge" that provides a into the last capacity register pair.
real measurement of the charge drawn from the secon-
dary battery. When DC or Vee is valid, the gas gauge The system may poll the gas gauge to read actual con-
monitors current from the secondary battery, increment- sumption. The system compares the reading to the pre-
ing the value in the gas gauge register pair, GG. The gas vious actual or the nominal capacity for that battery.
gauge is reset by a full recharge, by the host processor, or Additionally, when the gas gauge has passed the gas
by battery replacement. gauge threshold (programmed in the gas gauge
threshold r~ter pair), an interrupt request is
The secondary battery discharge rate is monitored by generated on INT, and the status register (SR) interrupt
measuring the voltage across a sense resistor using SR, flag and gas gauge notification bits are set to 1. Mask
sense resistor input, and SB, secondary battery input. register bit 5 may be programmed so that passing the _
The sense resistor should be chosen by fitting it to the gas gauge threshold also activates P05.
system battery discharge rate profile to achieve the
highest gas gauge accuracy. Figure 4 indicates the gas The gas gauge register is reset to 0 by:
gauge error with respect to a range of voltage drops
• Charge action termination due to -!'J.V, maximum
across the sense resistor. charge time, or maximum voltage determination, any
The sense resistor should be carefully selected to mini- of which indicates full charge.
mize total error, especially for systems that include sig- • An abort charge actions command written to CMR
nificant battery discharge across a wide range of cur- (command register).
rents. Typical applications achieve the highest accuracy
when the voltage drop across the sense resistor is in the • The reappearance of a valid voltage at SB, which
range of 50mV to 125mV around the dominant battery indicates the battery was removed and replaced.
discharge rates.
The gas gauge register may be interpreted in conjunction
The gas gauge count rate is proportional to the voltage with charge setup register 2 (CSR2) bit 6, gas gauge not
drop, except for the error shown in Figure 4. A time- valid (GGNV), and CSR2 bit 7, battery replaced (BR).
averaged 100mV signal causes the gas gauge counter to
wrap around after 14 hours. A time-averaged 200mV GGNV = 1 indicates to the host that the gas gauge
signal wraps around after 7 hours. register value does not reflect discharge from bq2001-
determined full charge, and may not be valid.
Removed capacity is determined as follows:
GGNV is set to 1 by:
. gas gauge value
Removed capaCIty (mAh) = 46 x SR Q • The start of a charge phase.

A gas gauge measurement to full battery discharge (end- • The reappearance of a valid voltage at SB, which
of-discharge voltage, EDV) is a measure of the actual indicates the battery was removed and replaced.

11
! I
10 ! .
i L.
• I
f--l
Relative
Measurement Error
(%) II
I
If -----,-tuI
I I

l
1-1---- I -

I -
I ._1
40 80 120 160 200 240 280 320
Voltage Across Sense Resistor (mV)
G-'

Figure 4. Gas Gauge Measurement Error

Sept 1990 7/26

3-7
bq2001 Advance Information

GGNV is only reset to 0 by: purposes. The second phase is the charge phase. The
status register (SR) charging bit is 1 through both
• Charge action termination due to -1')V, maximum phases.
charge time, or maximum voltage determination, any
of which indicates full charge. If PSC is active (power switch state bit = 1), a pro-
grammed charge action will only initiate following a
BR = 1 indicates to the host that the battery has been start charge action command written to the command
removed and replaced; it is used to validate a new last register, CMR.
capacity register value following DC-initiated charge.
The battery replaced bit is set to 1 with the reap- If PSC is inactive (power switch state bit = 0), a pro-
pearance of a valid voltage at SB and is reset by an abort grammed charge action is initiated by the presence of
charge action command. valid DC. DC-initiated charge action may be qualified to
occur only if the CSR2 GGNV status bit is 1 by setting
GGNV and BR values are interpreted as follows: CSR1 bit 7 (GGNV qualified charge) to 1. This qualifica-
tion allows the system to prevent DC-initiated charge
Values actions with a battery of known charge (GGNV = 0).
Interpretation Replacing the battery sets GGNV, allowing DC-initiated
GGNV BR
charge.
0 0 Full charge completed; new last
capacity is valid. When PS is toggled low to activate PSC, any charge
action is discontinued before PSC goes active. Charge
0 1 Battery replaced; full charge com- action may be reinitiated after PSC is active, through
pleted; new last capacity is not valid. CMR.
1 0 Charge action terminated before full Charge action is prevented from starting when any of
charge; unknown charge state. the following conditions occurs (see Table 2, Charge Ac-
1 1 Battery replaced; unknown charge tion Initiation Truth Table):
state.
• CSR1 bit 6 (charge action enable) is O.
• SR bit 7 (power switch state) is 0, CSR1 bit 7 (GGNV
Charge Action qualified charge) is 1, and the CSR2 GGNV status bit
The bq2001 initiates a charge action as programmed. A is O. This only prevents DC-initiated charge action.
charge action may consist of two phases. The first phase • Status register (SR) bit 4 (DC valid) is o.
may be a non-operational discharge, draining the secon-
dary battery for conditioning or capacity determination • Status register (SR) bit 6 (secondary battery fault) is 1.

Table 2. Charge Action Initiation Truth Table

Charge Action, SR Bit 4 SR Bit 6 CSR1 Bit6 CSR1 Bit7 CSR2 Bit6 SR Bit 7
as Programmed Secondary Charge GGNV Gas Power
DC Battery Action Qualified Gauge Switch
Discharge I Charge Valid Fault Enable Charge Not Valid State
Phase Phase
,
Disabled 0 X X X X X
Disabled X 1 X X X X
Disabled X X 0 X X X
Ignored I DC Initiated 1 0 1 X 1 0
Disabled 1 0 1 1 0 0
DC Initiated 1 0 1 0 0 0
Command Initiated 1 0 1 X X 1

8126 Sept. 1990

3-8
 Advance Information bq2001

Any charge action is stopped when any of the following The full discharge threshold is the end-of-discharge volt-
occurs (see Table 3, Charge Action Termination Truth age (EDV) determined from the number of cells
Table): programmed in charge setup register 1 and the end-of-
discharge cell voltage register value. At EDV, the gas
• PS is toggled low to activate PSC. gauge value is written to the last capacity register.
• Abort charge actions command is written to CMR. At completion of the programmed discharge phase, the
• Status register (SR) bit 4 (DC valid) is o. charge action enters the charge phase.

• Status register (SR) bit 6 (secondary battery fault) is l. In a DC-initiated charge action (power switch state bit =
0), when the gas gauge not valid (GGNV) bit = 1, any

-
• Full charge is determined. programmed discharge phase is ignored, and the charge
action commences with the charge phase.
Discharge Phase
Charge Phase
The discharge phase of a charge action consists of the
bq2001 activating the CD output, turning on a discharge The charge phase of a charge action consists of the
path for the secondary battery. The gas gauge is opera- bq2001 modulating the CC output and optionally the CD
tional during the discharge phase. The discharge phase output. The charge phase may be continuous, pulsed, or
continues until a programmed threshold is reached or "burp" (alternating charge/discharge pulses).
charge action is terminated.
The charge phase consists of eight-second charge inter-
The bq2001 is programmed for discharge in CSR1 to: vals, which repeat until charge termination. The bq2001
is programmed for periods of charge, no action, and dis-
• Not discharge prior to charge, charge, which occur during each eight-second interval.
• Discharge to the value in the gas gauge threshold The CC output controls charging by switching an
register (to full discharge if it occurs first), or n-channel power FET. This pulses the DC supply at a
• Discharge fully if the gas gauge is already beyond the duty cycle that results in the desired average charging
gas gauge threshold register value. current. 'lb minimize heat generation in high charging
current applications, two pins are available to build a
The second option may be used for periodic cell con- charge pump that doubles the DC voltage, allowing full
ditioning to avoid any voltage-depression effect or for a turn-on of an n-channel FET.
forced full discharge to measure battery capacity. The
last option may be used to force full discharge for The period for the full charging rate is programmed into
conditioning or to measure capacity. It may also be used the charging period register, with time specified in units
to allow full discharge only when the battery is near of 1/32 seconds. The charging period register can be
empty. programmed for continuous charging (charging period =
256 units) or for pulsed charging (charging period < 256
units). See Figure 5.

Table 3. Charge Action Termination Truth Table

Gas Gauge CSR2 Bit6 Trickle Charge

Cause of Termination Reset (GGNV) (if enabled)
PS low to activate PSC (SR bit 7 from 0 to 1) No 1 No
DC not valid (SR bit 4 = 0) No 1 No
Secondary battery fault (SR bit 6 = 1) No 1 No
Abort charge action command Yes 1 No
-IN detected Yes 0 Yes
Maximum charge time Yes 0 Yes
Maximum charge voltage Yes 0 Yes

Sept. 1990 9/26

3-9
bq2001 Advance Information

For burp charging, the discharge period register can be Note: For -~V determination, the charging voltage per
programmed with a discharge-after-charge period, which cell (with the number of cells as programmed in the
is programmed as in the charging period register. See CSR1 register) must be above the end-of-discharge cell
Figure 5. In operation, the charging period takes voltage (EDCV) and less than EDCV plus l.0Y. For
precedence over the discharge period. The discharge example, if a five-cell battery has an end-of-discharge
period may be no longer than the remainder of the eight- voltage of l.OV per cell, -~V detection requires a charg-
second interval following completion of the charge ing voltage between 5V and lOV.
period.
Trickle Charge
Full charge is normally determined by negative delta
voltage (-~V) sensing, with a voltage sensitivity of less When the trickle enable bit in charge setup register 2 is
than 10mV per cell. The sampling period for the -~V set, on full charge the EMU initiates the charge-sustain-
determination is defined in charge setup register 2. ing trickle charge defmed by the period in the trickle
Longer sampling periods may be necessary for slower period register. See Figure 5. Full charge is indicated by
charge rates. charge action termination due to -~V determination,
maximum charge time, or maximum voltage determina-
The host processor can use the -~Venable control field in tion. When DC-initiated charge action is blocked by
charge setup register 2 to disable -~V full charge deter- GGNV qualified charge bit = 1 and GGNV = 0, and
mination. In applications where the host processor uses trickle is enabled, DC-initiated trickle charge will occur.
subsystem power switching for power management, the
charging current provided to the battery may vary with Trickle charge is terminated if:
subsystem activity. Briefly disabling -~V response coinci-
dent with each charging current decrement prevents • Status register (SR) bit 4 (DC valid) is 0 or
false full charge determination. • PS is pulsed low to activate PSC (status register
Full charge is also determined if the charge phase exceeds power switch state bit switches from 0 to 1).
the maximum charge time register value or the cell volt-
age exceeds the maximum charge voltage per cell.

Constant Charge 7~~

,

CC Active ~I
Pulse Charge
....;;....-----1
Lrr--!
I-- CC Active

Burp Charge
--_......
Lr Lr
7 /V U
I-- CC Active --I
--1
I
r- CD Active

Trickle Charge nL.-_ _ _ _-InL.-_ _ _ _-InL--_77'/ r---f1'-------t-----

--II-- CC Active

~------------;--------------+------7~//~/~--~------------~
Interval 1 Interval 2 Interval N

Initiation Termination

CC-4

Figure 5. Charge Phase and Trickle Charge Modulation

10126 Sept. 1990

3-10
 Advance Information bq2001

Backup Power Management supply to various subsystems (such as the display, back-
light, hard disk, serial port, and coprocessor). Each
The bq2001 sources the external 3V battery-backed output supports a maximum voltage of 18V. Subsystem
integrated circuits through BC, backup cell output. The on/off switching to conserve power may be part of a
bq2001 regulates power from the secondary battery for configuration routine or may be dynamic. Dynamic
internal data retention and for output at BC. The BC power conservation based on software activity monitor-
output can be used in the absence of system power as a ing and timeout periods may be part of a power-manage-
battery-backup source for static CMOS devices such as a mentBIOS.
real-time clock or static RAM.
These outputs are not restricted in use. For example,
When the secondary battery is removed or becomes one of these outputs may also be used to switch to a
depleted, an external power source must support the second (lower) charging current for charging actions
bq2001 and external data retention. This source may be when the system is on.
a lithium cell directly connected to BCI. This backup
automatically switches in as the data-retention power
source for the bq2001 and the circuits sustained by BC
Writing any of mask register bits 0 to 6 to a value of 0
sets the associated output pin POI to P07 to become
III
as an output. (See Figure 1.) active whenever its corresponding control bit in the out-
put control register is written to 1.
Power Management Annunciation
OnlOff Control
Programmable open-drain outputs POI through P07
may be used to activate annunciators such as The bq2001 may be used for ~tem on/off control by
LEDs. These seven outputs are programmable to become hardware and software inputs. PS and PSC may be used
active (low impedance to Vss) based on internal EMU to control an external pFET.
status or as written by the host processor. PS is the power switch input, pulled high internally. PS
• Writing any of mask register bits 0 to 5 to a value of may be toggled to turn the system on, and may be
1 causes the associated output pin POI to P06 to toggled to initiate a request to turn off.
become active whenever the EMU sets the PSC, power switch control output, is an open-drain out-
corresponding status register bit to a value of 1. put intended to drive a p-channel FET, which may con-
• Writing any of mask register bits 0 to 6 to a value of trol the system supply. PSC is activated by PS toggled
o sets the associated output pin POI to P07 to low and deactivated by a system off command written to
become active whenever the corresponding control bit CMR.
in the output control register is written to 1. When PS is pulled low and PSC is inactive, the bq2001
Thus POI to P06 can be selected to be activated by the sets the status register power switch state bit to 1, turns
host processor (with system power on) or by internal off any charge action or trickle charge, and activates
EMU status. P07 is activated only by the host processor. PSC. The power switch state bit is reset to 0 when the
system off command is written to CMR.
Rewriting a mask register bit between power-on and
power-off may allow the corresponding output pin to be When PS is pulled low, the bq2001 generates an eight-
active as written by the processor when power is on and microsecond pulse on INT, and the status register (SR)
active reflecting EMU status when power is off (and DC interrupt flag bit is set.
is valid). Note: Because the state of PSC determines the means
of charge action initiation (see Charge Action), PSC may
Power Conservation need to reflect system power status even if PSC is left
Microprocessor control of open-drain output pins POI to open.
P07 allows anyone of them to be used to switch a p-
channel FET or PNP transistor controlling the power

Sept. 1990 11/26

3-11
bq2001 Advance Information

Register Description The start charge action command starts a charge ac-
tion if all other conditions are met (see Charge Action).
The bq2001 has two data groups independently addres- This command begins a charge action when DC is valid or
sable through the write-only command and address later becomes valid. This command is the only way to start
register, CMR: (1) storage RAM and (2) control and a charge action ifPSC is on (power switch state bit = 1).
status registers.
The abort charge action command causes any charge
CMR is accessed with RS low. CMR may be written with action to be discontinued. The bq2001 resets the gas
command bytes that serve as direct commands or that gauge and goes into a current-monitoring (gas gauging)
control the access of a subsequent data byte. state. This command may be used to reset the gas gauge
to 0 or to stop a charge cycle.
The storage RAM provides 32 data bytes of general-
purpose nonvolatile RAM storage capability, accessed Storage RAM
with RS high.
One of the 32 bytes of storage RAM is written following a
The control and status registers consist of 17 bytes, also CMR command of 100AAAAA and read following a CMR
accessed with RS high. command of 010AAAAA. AAAAA is the byte address,
from 00000 to 11111. This RAM is intended for storing
Command Register (CMR) cycle history and charge capacity for one or more bat-
The write-only CMR register is accessed when register teries, and for recording power-management configura-
select, RS, is zero during a write access. CMR is used to tion settings and other data for a power-management
start an action such as charge a battery or abort BIOS. Data in the storage RAM is nonvolatile in the
charging. The CMR register is also used to select the presence of a valid secondary battery or backup cell.
address and action to be performed on any data byte.
Control and Status Registers
The address field (bits 0-4) contains the address of the
data byte to be accessed. The values for this field may One of the 17 bytes of control and status registers is
range from 00000 to 11111 for the storage RAM and from written following a CMR command of 10lAAAAA and
00000 to 10000 for the control and status registers, with read following a CMR command of 011AAAAA. AAAAA
all other values not allowed. is the byte address, with only 00000 to 10000 allowed.
Data in the control and status registers is nonvolatile in
The command field (bits 5-7) of this register indicates the the presence of a valid secondary battery or backup cell.
action to be taken. Acceptable command field values are: Table 4 summarizes the control and status registers.

Charge Period Register (CPR)

Bits
--
Command Field Values The charge period register (CPR) is programmed to
7 6 5 define the charge period of a charge phase interval. The
0 0 0 No operation eight-second charge phase interval consists of a charge
period and optional off and discharge periods. Each
0 0 1 System off command period may be programmed to be 1 to 256 of the 256 time
0 1 0 Read from address AAAAA of the segments per interval. The charge period is one plus the
bq2001 storage RAM programmed value. The programmed value may be 0 to
255.
0 1 1 Read from address AAAAA of the
bq2001 control and status registers The following are examples of charge period duty cycle
values:
1 0 0 Write to address AAAAA of the
bq2001 storage RAM CPR Result
1 0 1 Write to address AAAAA of the OFFH Provides continuous current during
bq2001 control and status registers .' charging.
1 1 0 Start charge action command 63H Provides for 3.13 seconds offull charge
1 1 1 Abort charge action command current out of every 8 seconds.

The system off command may be used to shut the system Values less than OFFH are used to reduce the effective
down. When the system issues this command, the power current during a charge and/or to provide time for a
switch control output, PSC, becomes high impedance, and depolarization action by allowing time for a period of
the status register power switch state bit is cleared to O. discharge (see Discharge Period Register).
12126 Sept. 1990

3-12
 Advance Information bq2001

Table 4. Control
.. __._-
and Status Registers (X=Don't Care)
.. _. ----~- --_.- - .------~---"

Sym- Register Address Read/ Control Field or Status Bit

bol Name (TBD) Write - - Units
I 7(MSB) 6 5 4 3 2 1 0
CPR Charge period RIW - - - - - - - - 1132
register sec
- - ..

CSR1 Charge setup RIW GGNV CA discharge number of

register 1 .. _.. _-- ---.<ltll.l2d +e~able method
- - ---,
cells
..-

CSR2 Charge setup RIW BR ,GGNV. X X -tN -I"V trickle

DPR
register 2
Discharge
-_. . _ - ---
RIW -
I
I

- -
-
-
sample time
- -
enable enable
- - 1/32
III
period register sec
End-of-
EDCV discharge cell RIW - - - - - - - - 10mV
voltage register
._ ..- - - - ----- I .-

GGH Gas gauge, Read - - - - - - - - 1

high byte 46 mVh

Pc Gas gauge
r---
Gas gauge,
low byte
. ._-

Read - - -
--r---
- - - - - 1
46 mVh

1
GGTH threshold, RIW - - - - - - - - 46 mVh
high byte
-- --.-~

Gas gauge 1
GGTL threshold, RIW - - - - - - - - 46 mVh
low byte

Last capacity
..lmVh
LCRH register, high Read - - - - - - - - 46
byte
- -_. - - - - - " ...- -- --
Last capacity
J'-mVh
LCRL register, low Read - - - - - - - - 46
byte if------
--- -. .- - - ..-- - -_ ... _" . --
! ..

i Maximum
MCT charge time RIW - - - - - - - - 8 min
register I
----- - --
MCV Maximum cell RIW - - - - - - - - lOmV
voltage register
c------ - -----'--
MR Mask register
--
RIW - - - - - - - X
..-
_._------ - -- ~-----.- -.--~

OCR Output control RIW - - - - - - - X

register
----- f------- -- - - .. -
SR Sta tus register Read PS SBF GGN DCV BCL EDV CHG INTF
.-

TPR Trickle period RIW - - - - - - - - 1132

register sec
--.--

Sept 1990 13/26

3-13
bq2001 Advance Information

Charge Setup Register 1 (CSR1)

10 Discharge fully if the gas gauge value is
Charge setup register 1 (CSR1) contains four configura- greater than the gas gauge threshold. The
tion fields. discharge is terminated by the EDV limit.
This method may be used to determine the
The number of cells field (bits 0-3) contains the num- battery capacity. At the end of this cycle,
ber of cells used to make up the battery. This register is the final gas gauge value is stored in the
programmed with a scale factor, typically the number of last capacity register.
cells, to relate the measured battery voltage back to the
single-cell voltage. 11 Never discharge.

CSR1 Bits The charge action enable field (bit 6) is programmed

to 0 when charging and discharging are not to be per-
7 6 5 4 2 1 o formed. This bit may be set to 0 for the use of non-
N N N rechargeable batteries.
The E field values are:
The maximum cell number is 10 (the initial default), and
the minimum is 1. The value need not be the real num- CSR1 Bits
ber of cells, but must be scaled such that this value times
the values in registers EDCV and MCV, respectively, are 7 6 5 4 3 2 1 o
the EDV and maximum charge voltage limits. E

Caution: Where E is:

Using the EMU with improperly programmed
voltage thresholds may damage the device. o Inhibits charge action initiation (the initial
default value).
The discharge method field (bits 4-5) is the nonopera- 1 Allows charge action.
tional discharge method selector. Discharge-before-
charge may be initiated on application of a valid DC The GGNV qualified charge field (bit 7) is pro-
level or when a charge action command is issued in the grammed to 1 to force GGNV to qualify DC initiation of
CMR. charge action (power switch status bit =0). When this bit
is one and the power switch status bit is 0, charge action
The discharge method field is programmed to defme the is initiated only if the CSR2 GGNV status bit = 1. This
discharge method as follows: allows the host processor to block DC-initiated charge ac-
tions on a known fully charged battery. If enabled in
CSR1 Bits I CSR2, trickle charge occurs.

f-_7_+-_6_+-_~_+-_~_-I1~_3_+-_2_+-_1_+-_0----j The Q field values are:

'-------'-------'--------'----'-----'------'----'---------' I ~ CSR1 Bits

Where DD is: . 6 5 4 I 3 2 1 o
00 Never discharge (the initial default value).
01 Discharge until the gas gauge register value
is greater than or equal to the gas gauge WhereQis:
threshold register value or EDV is reached. o No GGNV qualification of charge action.
This method may be used to provide bat-
tery conditioning cycles by deliberately con- 1 DC-initiated charge action only ifGGNV = 1.
trolling discharge depth. If full discharge
(EDV) occurs, the final gas gauge value is
stored in the last capacity register.

14126 Sept 1990

3-14
 Advance Information bq2001

Charge Setup Register 2 (CSR2) Where SS is:

Charge setup register 2 (CSR2) contains three configura- 00 8 seconds between samples
tion fields and two read-only status bits. Bits 4 and 5 are
not used. 01 32 seconds between samples

The trickle enable field (bit 0) is programmed to 1 to 10 128 seconds between samples
enable trickle charge. When this bit is 1, trickle charge 11 512 seconds between samples
follows charge action termination due to full charge
(indicated by -t;.V, maximum time, or maximum voltage). The gas gauge not valid read-only status bit (GGNV)
is set to indicate to the host processor that the gas gauge

-
The trickle enable field values are: value does not reflect discharge from bq2001-determined
full charge and is potentially invalid.
CSR2 Bits
7

2 o
I I
o Trickle charge disabled
1 Trickle charge enabled Where GGNV is:

The -t;.V enable field (bit 1) is programmed to 1 to o Gas gauge value reflects discharge from
enable -t;.V sensing for full charge determination. When bq2001-determined full charge
this bit is 1, a -t;.V observation is interpreted as full 1 Charge state not known; battery replaced or
charge. When this bit is 0, a -t;.V observation is ignored. charge action not completed.
The -t;.Venable fields are: GGNV is set to 1 by either the start of a charge action or
by SB going valid. GGNV is reset to 0 on charge action
CSR2 Bits termination due to -t;.V, maximum voltage, or maximum
time determination.

~
7 2 o
If GGNV is 1 and the power switch state bit equals 0,
I I any discharge phase of a charge action is skipped.
The battery replaced read-only status bit (BR) indi-
Where Vis: cates to the host that the battery has been removed and
o Ignore -t;.V. replaced; it is used to validate a new last capacity
register value following DC-initiated charge. The bat-
1 Interpret -t;.V as full charge. tery replaced bit is set to 1 with the reappearance of a
valid voltage at SB and is reset by an abort charge action
The sample time field (bits 2-3) is programmed to command.
select the time between voltage samples used to deter-
mine -t;.v. Shorter times may be chosen when a rapid BR values are:
charge is required and the end of charge must be
detected as soon as possible. Longer times may be CSR2 Bits
chosen when slow charge rates are required.
2 o
The sample time field values are :

CSR2 Bits
Where BRis:
7 2 o
o Battery has not been replaced since last reset.
S
1 Battery has been replaced.

Sept. 1990 15/26

3-15
bq2001 Advance Information

Discharge Period Register (DPR) field). During operational discharge, reaching this limit
generates an interrupt request on INT, sets the status
The discharge period register (DPR) is programmed to register interrupt flag and gas gauge notification bits
define the optional discharge period-used for and, if selected, activates P05.
depolarization-of each charge phase interval. DPR is
non-zero for burp charging. Each period may be Last Capacity Registers (LCR)
programmed to be 0 to 254 of the 256 time segments per
interval. The number of segments in the period is the The read-only last capacity register pair (LCR) is used
same as the programmed value. The value in CPR has to keep a copy of the most recently measured battery
precedence over DPR. This means that within any eight- capacity. LCR is automatically loaded with the gas
second interval, the charge period is completed before gauge value when the EDV limit is reached.
the discharge period is started, such that the maximum
period allowed for discharge is 255 minus the CPR value. Maximum Cell Voltage Register (MCV)
The gas gauge is not valid during discharge periods The maximum cell voltage register (MCV) is
within charge phase intervals. programmed to define the maximum voltage per cell
limit. This is one of three determinants of full charge. If
End-of-Discharge Cell Voltage Register (EDCV) the maximum voltage is reached before the -tN deter-
mination or maximum charge time is obtained, then the
The end-of-discharge cell voltage register (EDCV) is charge action is terminated, and the gas gauge and
programmed with the value used to determine the secon- GGNV are reset. The MCV value need not be the real
dary battery end-of-discharge voltage (EDV) threshold single-cell voltage, but-with the number of cells value
during operational or non-operational discharge. This in CSRl--defines the maximum battery voltage.
value need not be the real single-cell voltage, but must
multiply by the number of cells value in CSRI to equal Maximum Charge Time Register (MCT)
the EDV. Discharging to the EDV threshold generates
an interrupt request on INT, sets the status register in- The maximum charge time register (MCT) is
terrupt flag and EDV bits, loads the value from GG into programmed to define the maximum time for the charge
LCR, and-if selected-activates P02. phase of a charge action. This is one of three deter-
minants of full charge. If this time value is reached
Example: before the -t!.V determination or maximum battery volt-
For a termination voltage of l.OV per cell, the value age is obtained, then the charge action is terminated and
placed in EDCV should be 64H. the gas gauge and GGNV are reset. The units for this
register are eight minutes, for a maximum time of 34
Gas Gauge Registers (GG) hours.

The read-only gas gauge register pair (GG) indicates the Mask Register (MR)
capacity that has been removed from the battery. The
GG value is interpreted by: The mask register (MR) is programmed to define which
output pins-POI to P07-are controlled by specific bits
GG = SR(ohms) x Removed Capacity(mAh) x 46 ofthe status register (SR) or by specific bits of the output
control register (OCR). Each of these open drain output
The gas gauge register pair is reset to 0 by: pins can be set up to follow internally generated status
• Charge action termination due to negative delta bits or to reflect bits set by the host processor. See Table 5.
voltage, maximum charge time, or maximum voltage
determination, any of which indicates full charge. Output Control Register (OCR)

• An abort charge actions command written to CMR The output control register (OCR) is the control register
(command register). ~which the host processor can activate any of outputs
POI to P07. POI to P07 reflect the status of OCR bits 0
• The reappearance of a valid voltage at SB, which to 6, respectively (l=output active), provided that host
indicates the battery was removed and replaced. control is enabled (the appropriate masking bit in the
mask register, MR, is set to 0). See Table 5.
Gas Gauge Threshold Registers (GGT)
The gas gauge threshold register pair (GGT) is
programmed to set the gas gauge threshold. At initia-
tion of a charge action, this limit may determine the
discharge phase activity (see CSRl, discharge method

16/26 Sep1.1990

3-16
 Advance Information bq2001

output from the buffer with the subsequent bit access.

Table 5. Mask Register INTF is only set when PS = l.
Charging (CHG) is set whenever a charge action is in
Bit Value Result progress. CRG equals 0 during no action or during
0 0 Not valid. trickle charge.
1 Not valid. End-of-discharge voltage (EDV) is set when the
secondary battery voltage is at or below the threshold
1 0 POI follows OCR bit l.
defined by the CSRI number of cells field value and the
1 PO~f()}lows SR charging bit. --
EDCV register value. Otherwise, this bit is O.

2
0
1
P02 follows OCR bit 2.
P02 follows SR end-of-discharge
voltage bit.
Backup cell low (BCL) is set to indicate low backup
cell voltage. Ifthe voltage at BC, is less than or equal to
2.1 (± O.IlY, then BCL is set to l. Otherwise this bit is O.
Ell
0 P03 follows OCR bit 3. DC valid (DCV) is set to indicate valid DC. The bit is
3 set to 1, allowing charge action to occur, if DC is greater
1 P03 follows SR backup cell low bit. than 4.5Y. The bit is set to 0 whenever DC is less than
0 P04 follows OCR bit 4. 4.4V (IOOmV hysteresis). If this bit is 0, no charge ac-
4 tion may occur.
1 P04 follows SR DC valid bit.
P05 follows OCR bit 5. Gas gauge notification (GGN) is set when the gas
0
gauge reaches or exceeds the programmed gas gauge
5 1 P05 follows SR gas gauge notifica- threshold.
tion bit.
Secondary battery fault (SBF) is set to indicate a pos-
0 P06 follows OCR bit 6. sible open or short cell. This bit is set to 1 if the voltage
6 monitored at SB is less than 0.5V times the number of
1 P06 follows SR secondary battery
fault bit. cells defined in CSRl. If this bit is set, no charge action
may occur.
0 P07 follows OCR bit 7.
7 Power switch state (PS) indicates PSC status. This bit
1 Not valid. is set to one by a PS input that activates PSC and set to
o by execution of the CMR power-off command to deac-
tivate PSC. The application may need to ensure that the
Status Register (SR)
power switch state bit reflects the system power status.
The read-only status register (SR) indicates the status of
various battery operations and conditions. The bits are Trickle Period Register (TPR)
defined as:
The trickle period register (TPR) is programmed to
define the charge period during trickle charge. This
SR Bit Bit Name If Set to 1 register is used following full charge determination to
provide a lower effective current for charge maintenance.
0 INTF Interrupt flag
Each period may be programmed to be 1 to 256 of the
1 CRG Charging 256 time segments per interval. The charge period is
one plus the programmed value. The programmed value
2 EDV End-of-discharge voltage
may be 0 to 255.
3 BCL Backup cell low
TPR examples include:
4 DCV DC valid
5 GGN Gas gauge notification TPR Result
6 SBF Secondary battery fault 7 Provides for an average current of about
7 PS Power switch state equals ON 1/32 of the maximum charge current.
--
0 Provides for an average current of 11256
Interrupt flag (lNTF) is set when INT becomes active. of the maximum charge current.
INTF is reset to 0 when a CMR read command causes
the SR byte to be loaded into the read buffer. INTF is

Sept. 1990 17/26

3-17
bq2001 Advance Information

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

VDC DC voltage applied on DC relative to Vss -0.3 to 18 V

VSB DC voltage applied on SB relative to Vss -0.3 to 18 V
Vcc DC voltage applied on Vcc relative to Vss -0.3 to 7.0 V
VBCI DC voltage applied on BCI relative to Vss -0.3 to 7.0 V
VOP DC voltage applied on all open drain -0.3 to 36 V
outputs relative to Vss
VSR DC voltage applied on SR relative to Vss -0.3 to 18 V VSR ~ VSB + 0.3
VIF DC voltage applied on DS, RS, DQ, and INT -0.3 to 7.0 V
relative to Vss
IBc Output current on BC 20 rnA
ToPR Operating temperature o to +70 °C
TSTG Storage temperature -55 to +125 °C
TBIAS Temperature under bias -10 to +85 °C
TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

18126 Sept. 1990

3-18
 Advance Information bq2001

Recommended DC Operating Conditions (TA = 0 to 70·C)

Symbol Parameters Minimum Typical Maximum Unit Notes

VDC DC supply voltage 4.5 - 18 V

VSB SB supply voltage 3.0 - 18 V
Vcc supply voltage 4.5

-
Vcc 5.0 5.5 V
VBCl BCl supply voltage 2.0 - 6.0 V
VBcl-O.Ol VBCl VBCl+O .01 V Regulated VSB > VBCl
VBC BC output supply voltage
VBCl - 0.3 - VBCl V Regulated VSB < VBCl
Vss Supply voltage 0 0 0 V
VSR Sense resistor input voltage Vss - VSB + 0.3 V
VlL Logic low-level input voltage -0.3 - 0.8 V
for DS, RS, DQ
VIR Logic high-level input voltage 2.2 - VCC + 0.3 V
for DS, RS, DQ
VOL Logic low-level output voltage - - 0.4 V IOL= 4.0mA
forDQ
VOH Logic high-level output 2.4 - - V IOH= -2.0rnA
voltage for DQ
Vocc Charge control output voltage - - 36 V IOD = 0
VOD Open-drain output voltage - - 18 V All open-drain outputs other
than charge control, IOD = 0
IOD QE.en-drain sink current for - - 20 rnA VOD=2V
P01-P07, CC, CD, PSC, INT
ILl Input leakage current for DS, - - ±1 ~
RS,DQ
lLO Output leakage current for DQ - - ±1 ~ Outputs in high impedance
Icc Operating current, DC or VCC - 3 5 rnA
supply
ICCDR Data-retention current from - 0.1 1 ~ IBC = 0, Ips = 0
BCl input
IcCSB Data-retention current from - 1 10 ~ IBC = 0, Ips = 0
SB input
IBC Output current on BC - - 1 mA SB or BCl supplied; VBC =
3.0V, TA = 25°C
Ips PS active input current 20 30 45 ~ Internal 100K ohm pullup to
VBCl

Sept. 1990 19/26

3-19
bq2001 Advance Information

DC Thresholds

Symbol Parameter Minimum Typical Maximum Unit Notes

VSBF Secondary battery fault 0.45 xN 0.5N 0.55N V N = number of cells

perCSR1
VMAXC Maximum charge voltage MCVx MCVxN MCVx V N = number of cells
(0.99 x N) (1.01 xN) perCSR1
VEncv End-of-discharge voltage EDCVx EDCVxN EDCVx V N = number of cells
(0.99 x N) (1.01 x N) perCSR1
VBCL Backup cell low voltage 2.0 2.1 2.2 V
--
DC valid voltage (on) 4.4 4.5 4.6 V
Vncv 100mV hysteresis
DC valid voltage (om 4.3 4.4 4.5 V

Note: Typical values indicate operation at TA = 25°C.

Impedance

Symbol Parameter Minimum Typical Maximum Unit

RsB SB input resistance 400 500 600 1m

Notes: Typical values indicate operation at TA = 25°C.

This parameter is sampled and not 100% tested.

Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CliO Logic input/output capacitance (DQ) - - 10 pF VIIO = OV

--
CIN Logic input capacitance (DS, RS) - - 8 pF VIN= OV
Note: This parameter is sampled and not 100% tested.

20126 Sept. 1990

3-20
 Advance Information bq2001

AC Test Conditions

Parameter Test Conditions

Input pulse levels OVto3.0V
Input rise and fall times 5 ns

-
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load for DQ (including scope and jig) See Figures 6 and 7
Output load for all open-drain outputs See Figure 8

+5V +5V

9600 9600

Output Output
o---r
O~::L_I5p' 510 n ~ l~ lOOp'

OL-3 OL-16

Figure 6. Output Load A Figure 7. Output Load B

+5V

1.15K 0

Open-Drain
0--- -~-----
Outputs

OL-4

Figure 8. Output Load C

Sept. 1990 21/26

3-21
bq2001 Advance Information

Charge Action Timing (TA = 0 to 70'C, DC = 4.SV to 18V)

Signal Characteristic Minimum Typical Maximum Units

tncs DC slew rate - - 18 mV/lls

tcpc Charge pump time 6 8 10 Il s
tncp Diode out after CC high 4 - - Il s
tDTC Discharge phase to charge phase 6 8 10 Il s
transition time
tCA Charge action interval 6 8 10 s
tc Charge period tCA - teA s
256
tI Charge period to discharge period - teA - s
transition time 128
tn Discharge period 0 - 254 S
(teA x 256)-
te
tT Trickle charge period tCA - teA s
256
tCT Charge time 0 - 255(60 x s
tCA)

Note: Typical values indicate operation at TA = 25·C.

22126 Sept. 1990

3-22
 Advance Information bq2001

Charge Pump Timing

CPC

teA
tc

CC ~ \ j III
[ tocp
----J ----J

CPO I
CC-1

Charge Action Timing

1 4 - - - - - - t CA -------.j

14--- t c ----+I

CC
-----.t1
CO
\'-----__', ~14------ t CA

n~M,---
~

CC-2

Trickle Charge Timing

t=~-------- t CA ----------.!1
CC
---<F 'T 1'------~/,------,~'_______
CC-3

Sept. 1990 23/26

3-23
bq2001 Advance Information

Bus Timing (TA = 0 to 70'C, VCC = 5V± 10%)

,--
Signal Characteristic Minimum Typical Maximum Unit Conditions

tcYC Cycle time 250 - - ns

---------~ j------ ------- -- ---
tDR DS recovery time 155 - - ns
j------

tDSL
--------
Data strobe low time
-- - -
80 - - ns

tAcs Read data access time - - 30 ns Output load A

1---- - - t------
tDHZ Read data to high Z 0 - 30 ns Output load B
f----
tDW Write data setup time 40 - - ns
tDHW Write data hold time 0 - - ns
t--------- "._---- --
tAS RS setup time 0 - - ns
f-----~--

tAR RS hold time 0 - - ns

c--------- - --
tINT Interrupt pulse width 6 8 10 ~s Output load C
tlRT Interrupt recovery time 6 8 10 ~s Output load C
~---- --
Note: Typical values indicate operation at TA = 25'C, Vcc = 5.0V.

Read/Write Timing

~tAs1 r-- t AH -----

RS )K ')K
tCYC

/'
OS
'" ~

tOSl
7
tOR
" r-...

DO 1/ "-
(READ)
"- /
~ t ACS -----+ J.- tOHR --

V
DO
(WRITE)
'" '"
/

tow tOHW -I

RC-8

24/26 Sept. 1990

3-24
 Advance Information bq2001

Interrupt Timing

INT
III
INT-2A

Sept. 1990 25/26

3-25
bq2001 Advance Information

Ordering Information
bq2001

- LpaCkage Option:
PN = 24-pin narrow plastic DIP
S = 24-pin SOle

-Device:
bq2001 Energy Management Unit

26126 Sept. 1990

3-26
 ~ BENCHMARQ _ _ _ _ _A_dv._'8I7_ce_l_'nfQ_rm_afi,_on_b_q....;...2_0_0_2_
Energy Management Unit (EMU)
Features General Description voltage threshold, and a maximum
time limit. Trickle charge control
~ Microprocessor peripheral for the The CMOS bq2002 Energy Manage- begins after full charge is determined.
total energy management of ment Unit (EMU) is a low-power N on-operational discharge before
battery-operated systems microprocessor peripheral providing charge may be selected for cell con-
battery and energy management ditioning or capacity measurement.
~ Direct measurement of battery services for systems using recharge- Charge patterns may be programmed
consumption and capacity able (secondary) batteries. The to be constant, pulsed, or "burp"
~ Fast charging and conditioning bq2002 works directly from the DC (alternating charge/discharge).
control for nominal 3.6V to 12V
nickel cadmium, lead acid, or
nickel hydride batteries
charging supply, operating as
programmed, or from 5V Vee,
operating as a microprocessor
When system power is off, the
bq2002 may power DRAM sleep
DI
peripheral. bq2002-based systems mode operation through the battery
~ Full-charge detection by negative can easily incorporate sophisticated backup output (BB). The bq2002
delta voltage method, maximum capacity monitoring, battery regulates 6.5V to 18V from the
voltage, and maximum time management, DRAM sleep mode secondary battery to a 5.3V output
supply services, and power-conserva- on BB. When system power is on,
~ Register-controlled outputs for tion capabilities. the 5.3V supply may be used to
energy management charge a backup battery that sus-
The "gas gauge" register provides tains the DRAM when the secondary
~ Regulated 5V output to sustain the actual charge consumption from battery is absent or depleted. To
DRAM sleep mode the secondary battery and allows prevent overdepletion, the battery
~ Operates from 4.5-18V DC or measurement of the battery backup output is shut off when the
4.5-5.5VVee supplies capacity. The programmed end-of- secondary battery voltage falls
discharge voltage (EDV) threshold below O.9V per cell.
~ 24-pin SDIP or SOIC determines full discharge.
Power management is supported by
Battery management includes charge eight open-drain outputs controlled
control at standard to fast charge by the EMU or the host processor.
rates, with full charge determined These may be allocated for subsys-
using the preferred negative delta tem control, LED activation, EMU
voltage (-~V) method, a maximum status indication, and system power
switch control.

Pin Connections Pin Names PS Power switch input

PSC Power switch control output
DS Data strobe input
24 l PO, Charging indicator or
RS Register select input
programmable output I
23 DQ Data input/output
P02 End-of-discharge voltage indica-
22
INT Interrupt request output tor or programmable output 2
21
DC Charging supply input P03 Backup cell low indicator or
20 programmable output 3
SB Secondary battery input
P04 DC valid indicator or program-
18 BB Battery-backup output
mable output 4
17 BCI Backup cell input
P05 Gas gauge threshold indicator
16 CC Charge control output or programmable output 5
15 P06 Secondary battery fault or
CPC Charge pump capacitor
14 output programmable output 6
13 PO? Programmable output 7
CPD Charge pump diode output
CD Discharge control output Vee +5V system supply input
PN-3
SR Sense resistor input Vss System ground
Sept. 1990 1/2

3-27
bq2002 Advance Information

Block Diagram

BB
Bystem
Backup
BC I

Backup
Cal
l

tIT
OS Bu.
R8 Interface
DO

8y,''''
8upply
Control

80-4

5V Backup Management

8B DRAM and
Refresh Control
Secondary
Battery

bq2002
EMU

4.8V NICd
Backup
Battery

80-13
2/2 Sept. 1990

3-28
~ BENCHMARQ _ _D_e_s--:iQ=-n_i_nQ.=......-W_i_th_th_e_E_M_U
"11 Using the bq2001
Introduction
Table 1. Energy Sources
This design note provides information to simplify the
integration of the bq2001 EMU within microprocessor
and microcomputer systems. It is to be used with the Source Functions Powered
bq2001 data sheet. Battery monitoring and charging are
DC input All except micro interface and backup
discussed to provide a framework for understanding
cell output
EMU functionality. EMU application strategies and
hardware and software interfaces are outlined.
Battery application manuals, engineering handbooks,
Vee input All except voltage doubler and backup
cell output
III
and specifications should be obtained from the battery SB input Only backup cell output and nonvolatile
supplier. memory
The EMU functional blocks are shown in Figure 1. The BCr input Only backup cell output and nonvolatile
EMU application normally involves four energy sources, memory
as described in Table 1 and discussed below.

Backup
Cell

NT
iii au.
lIS 1nIetf_
DO

Figure 1. EMU Block Diagram

3-29
Designing With the EMU

Energy Sources Microprocessor Interface

The DC charging supply input must be from 4.5V to lSV. The EMU is a microprocessor peripheral with control
Voltages below 4.5V are not considered valid. The DC and storage registers that are programmed to perform
input powers all the EMU's operations except for the various energy management functions. The state and
microprocessor interface and the backup cell output, BC. condition of the secondary battery may be determined by
When the EMU is powered from DC, capacity monitoring reading the EMU registers.
and programmed charge actions may occur.
The Vcc input powers all blocks of the EMU except the Microprocessor Hardware DeSign
voltage doubler outputs, CPC and CPD, and the backup
Figure 2 shows a typical interface between a
cell output, BC. When the EMU is powered from Vcc,
microprocessor and the EMU. The microprocessor com-
any charge actions require a valid DC input. munication with the EMU is performed using a three-
The secondary battery input, SB, must be greater than line serial interface to a standard microprocessor bus.
0.5 V per cell to be valid. The secondary battery input is The EMU interface is powered by V cc.
the primary input for EMU nonvolatility and for power-
ing the backup cell output, BC. Microprocessor Software DeSign
The backup cell input, BCl, must be at least 2V to be The serial software interface to the EMU is best
valid. When the voltage at SB can no longer provide a described by example. The code in Listing 1 is an
BC output greater than the BCl input, the backup cell example of EMU interface software for a PC environ-
input becomes the input for EMU nonvolatility and for ment. Other systems have similar requirements.
powering the backup cell output, BC.
When a command, read, or write operation is per-
formed, the system must inhibit interrupts from
the EMU during the complete transfer time.

~~--~~=-------------------------------------~~,
Data Bus
~~--~====----------------------------------~-'V/

110 Requeat (lOR)

Read CAD)

Micro- Write (WR)

Processor Interrupt IINTI

Addreaa Bus
v

" 7

I os RS
Addreaa I ~ bq2001 OATAO
Decode '---L../>-------I OS EMU OQ
BO-8

Figure 2. Microprocessor Interface

3-30
 Designing With the EMU

Listing 1. EMU Communication Functions (1 of 3)

1 .LIST
2 PAGE 50,130
3 TITLE EMU Utilities
4 NAME EMU Util
5 .MODEL COMPACT
6
7 ;***************************************************************
8
9
10
11
DESCRIPTION: Provides READ, WRITE, and COMMAND access to EMU

PROTOTYPE: unsigned char emu read(unsigned char command)

III
12 void emu_cmd(unsigned char command)
13 void emu_wrt(unsigned char command, unsigned char emu data)
14
15 FUNCTION: emu read returns the requested data from the EMU.
16 emu cmd writes the requested command to the EMU.
17 emu wrt writes the requested data to the EMU.
18
19 ENTRY: command is an unsigned char containing the command
20 or command plus address to be sent to the EMU.
21 ;For emu read, command should contain either:
22 1. 011AAAAA for read a control or
23 status register at location AAAAA.
24 2. 010AAAAA for read a storage register
25 at location AAAAA.
26 ;For emu cmd, command should contain anyone of
27 ;the following commands where XXXXX is don't
28 ;care:
29 ;1. OOOXXXXX for a no operation.
30 ;2. 001XXXXX for system-off command.
31 ;3. 110XXXXX for start a charge action.
32 ;4. 111XXXXX for abort a charge action.
33 ;For emu_wrt, command should contain either:
34 1. 011AAAAA for write a control or
35 status register at location AAAAA.
36 2. 010AAAAA for write a storage register
37 at location AAAAA.
38 ;emu data is an unsigned character containing the data
39 ;to be written to a control/status or storage
40 ; register.
41
42 RETURN: emu read returns an unsigned character that contains
43 ;the data from-a control/status or storage
44 ;register.
45 emu cmd returns a void.
46 emu wrt returns a void.
47
48 ;****************************************************************
49
50 TEXT SEGMENT WORD PUBLIC 'CODE'
51 TEXT ENDS

3-31
Designing With the EMU

Listing 1. EMU Communication Functions (2 of 3)

52
53 ;********************************
54
55 ;EMU I/O port address
56
57 EMU CMD REG EQU 710H
58 EMU DAT REG EQU 711H
59
60 ;********************************
61
62 TEXT SEGMENT
63
64 emu read PROC
65
66 Public emu read
67
68 Push BP
69 Mov BP,SP
70
71 Send command to EMU
72
73 Mov CX,8 ;eight bits
74 Mov AL, [BP+6] ;of command
75 Mov DX,EMU_CMD REG ;at this port
76 Cli ;disable interupts
77 send rc:
78 Out DX,AL ;one bit at a
79 Shr AL,l ;time through
80 Loop send rc ;data bit 0
81
82 Get EMU data
83
84 Mov CX,8 ;eight bits
85 Inc DX ;of data from EMU
86 get rd:
87 In AL,DX ;get a bit
88 ROR AX,l isave it
89 Loop get rd ;get the next
90
91 Sti ;enable interrupts
92 Mov AL,AH ;return byte
93 Xor AH,AH
94 Pop BP
95 Ret
96 emu read ENDP
97
98 emu cmd PROC
99
100 Public emu cmd
101
102 Push BP

3-32
 Designing With the EMU

Listing 1. EMU Communication Functions (3 of 3)

103 Mov BP,SP

104
105 Send command to EMU
106
107 Mov CX,8 ;eight bits
108 Mov AL, [BP+6] ;of command
109 Mov DX,EMU- CMD REG iat this port
110 Cli ; disable interupts
111
112
113
send cmd:
Out
Shr
DX,AL
AL,l
jone bit at a
itime through
III
114 Loop send cmd ;data bit 0
115
116 Sti ; enable interrupts
117 Pop BP
118 Ret
119 emu cmd ENDP
120
121 - emu wrt PROC
122
123 Public emu wrt
124
125 Push BP
126 Mov BP,SP
127
128 Send command to EMU
129
130 Mov CX,8 ; eight bits
131 Mov AL, [BP+6] ;of command
132 Mov DX,EMU- CMD- REG ;at this port
133 Cli ;disable interupts
134 send wrt:
135 Out DX,AL jone bit at a
136 Shr AL,l itirne through
137 Loop send wrt ;data bit 0
138
139 Get EMU data
140
141 Mov CX,8 ; eight bits
142 Inc DX ;of data
143 Mov AL, [BP+8] ito EMU
144 send wr:
145 In AL,DX ;get a bit
146 Shr AL,l isave it
147 Loop send wr ;get the next
148
149 Sti ;enable interrupts
150 Pop BP
151 Ret
152 emu wrt ENDP
153 TEXT ENDS
154 END

3-33
Designing With the EMU

Command Request Write Data Operation

As shown, all communications with the EMU must start The write data command is sent first during a write
with a command written to the command register, CMR. operation, identifying the register set and containing the
There are two groups of commands, the action com- address of the register to be written. The write operation
mands and the data commands. is similar to the read operation and is shown in Listing
1, lines 141 through 147. After the write command, data
The transmission of a command is shown in Listing 1, is sent bit by bit using data bit 0 and an OUT instruction
lines 73 through 80, lines 107 through 114, and lines 130 to an odd EMU address. The odd address makes the RS
through 137. A command is sent one bit at a time input high during each bit transfer. The data transfer
through data bit 0 using an OUT instruction. The RS takes eight OUT instructions. The least-significant bit is
input is made low by connecting it to address line AO and sent first. An arithmetic shift right is used to place the
using an OUT instruction to an even EMU address. The next data bit into bit 0 after each OUT instruction.
complete command transmission requires eight out
instructions. The least-significant bit is sent first. Seven Interrupt Request Service
arithmetic shifts are used to position the next data bit in
bit o. Within the transmission loop, software delay time The INT pin, if used, requires software service. Three
may be required depending on execution speed. events can cause an interrupt request:

Action Command • Power switch request

Each action command instructs the EMU to perform one • End-of-discharge voltage reached
of the following actions:
• Gas gauge threshold reached
• Start a charge action Each event requires its own particular service.
interrupt event sets the interrupt flag, INTF, to 1.
Each
• Stop a charge action
The INTF is a read-once flag and is automatically
• Turn the system off
cleared after each read. The EMU interrupt service
• No operation routine should check the state of INTF in the EMU
status register SR. INTF is read by first issuing a control
The actual command codes required to initiate these ac- and status register read command with the SR address
tions are listed in Listing 1, lines 29 through 32. and then reading the SR data (described above in Read
Data Commands Data Operation).
INTF should be checked as part of the system initializa-
The four data commands instruct the EMU to prepare to
receive or send data from a particular EMU register. tion routine. INTF is set if the PS input is toggled during
system startup. INTF is cleared after it is read, freeing it
The EMU has two register sets. One set contains 17
bytes dedicated to the control and status of the EMU. for future interrupt request indications. The system
should also retain the status of the gas gauge notifica-
The other register set contains 32 bytes for general non-
volatile storage. Each register set has its own pair of tion bit, GGN, and the end-of-discharge voltage bit, EDV.
Determination of a gas-gauge-threshold-reached or end-
commands for read and write. The four data command
codes are listed in Listing 1, lines 22 through 25 and of-discharge-voltage-reached event is accomplished by
lines 34 through 37. reading the GGN and EDV bits at the same time as the
INTF bit, and comparing their values to their previous
Read Data Operation states. Appropriate actions in response to these events
are discussed later.
The read data command is sent first during a read
operation, identifying the register set and containing the Determination of a power switch event is also done by
address of the data to be retrieved. The read operation examining the GGN and EDV bits. If neither GGN nor
code is shown in Listing 1, lines 84 through 89. The data EDV has become active, then the system should assume
is read using an IN instruction to an odd EMU address, that a power switch service request has been issued.
causing RS to be high during each access. The least- The system must then take the appropriate action for
significant bit is read first. Each data bit is rotated to the power switch service. This action may be either
the high byte of AX. At the end of eight INs and RORs, accept that the system has been powered up (that is,
the EMU data is in the AlI register. This data is then take no action) or issue a command to the EMU to turn
returned back to the calling routine. off the PSC (power switch control) output.

3-34
 Designing With the EMU

replacement bit, BR, and gas gauge not valid bit, GGNV,
Secondary Battery Monitoring are set to 1, and the gas gauge register pair is reset.
The EMU provides real-time monitoring of the secondary The charge control aspect ofthe SB input is discussed in
battery when powered by the DC input or the Vee input. greater detail in the Battery Charging and Condition
The secondary battery capacity consumption and the section.
voltage per cell are determined so that the system may
take appropriate action. Sense Resistor Input
SR, the sense resistor input pin, is the other voltage
Battery-Monitoring Hardware Design input for secondary battery monitoring. The voltage
across the sense resistor is determined between the SB
SB and SR are the two inputs to the secondary battery
monitor.
and SR inputs. This voltage drop is used to determine the
rate of discharge from the secondary battery. This timed
rate of discharge is summed by the EMU and is avail-
III
Secondary Battery Input
able in the gas gauge register pair.
SB, the secondary battery input pin, is used to monitor
the secondary battery voltage. The secondary battery Sense Resistor Selection
voltage is internally divided by the number of cells as The voltage across the sense resistor is determined by
programmed in charge setup register 1 (CSRl) to deter- the resistance of the sense resistor and the current
mine the voltage per cell. The voltage per cell is used to through the resistor. The sense resistor should be chosen
determine: such that the capacity measurement error is minimized
• Secondary battery fault (less than 0.5V per cell) over the range of system operating currents.

• End-of-discharge cell voltage threshold (as Figure 3 shows the relative error in the determination of
programmed in the EDCV register) the voltage across the sense resistor versus the voltage
being measured. This should be considered when choos-
• Maximum voltage per cell (as programmed in the ing the proper resistor for capacity determination. The
MCV register) least relative error occurs around 70 mv' The EMU
provides less than 2 percent relative measurement error
• Delta voltage over the range from 30 to 170 mV, nearly a 6-to-l supply
The SB input also monitors the secondary battery volt- current ratio.
age to determine that the secondary battery has been
replaced. As the SB input rises through IV, the battery

11
I
10 ,
9
8
I
I
I
I
i

I I
I
I
I !
7 I \ I I
I
Relative 6
Measurement Error
(%) 5
4

3
\ -
2
I'" f--
I - I-- I--
i
o
o 40 80 120 160 200 240 280 320
Voltage Across Sense Resistor (mV)
G-6

Figure 3. Gas Gauge Measurement Error

3-35
Designing With the EMU

The resistor value may be selected following determina- where:

tion of typical system operating current profIles and
applying one ofthe two following equations. R Sense resistance (ohms)

For many applications, particularly if the system has a ti Relative operating time when
narrow range of operating current, the resistor choice the current is Ii
can be made using the average current method of Equa- Ii A particular operating current associated
tion 1. with time ti (amperes)
Equation 1. Simple Method for Sense Resistor Choice
Equation 2 can be used to account for a wide range of
operating currents associated with the various system
R = 0.0707 operations. The designer may partition the current
usage and estimate the active time for that usage. This
lavg data is then used in Equation 2 to determine the sense
resistor value for minimum capacity error.
where: The following example demonstrates Equations 1 and 2
methods, as applied to two different use conditions:
R Sense resistance (ohms)
Iavg Time-average system operating current
(amperes)
System Capacity =1.0 Ah
For those systems where the minimum absolute capacity Use Current
error is desired, Equation 2 can be used. Condition Level Time(%) Capacity (%)
Equation 2. Optimum Sense Resistor Determination 0.5A 30 15
Use A
(3:1) LOA 40 40
1.5 A 30 45

R = 0.0707 (i Ii
i==O
ti
i==O
ti Ii 2)~ UseB
(6:1)
0.5A
1.5A
30
40
9
36
3.0A 30 55
--
Results are shown in the tables below.

Equation 1 Results

Use TimeAvg Resistance Vmin Vmax Vavg Relative

Condition Current (A) (mQ) (mV) (mV) (mV) Error (%)

Use A 1.0 70.7 35.4 106 81.3 1.520

UseB 1.65 42.9 21.4 129 95.6 1.662

Equation 2 Results

Use RMS Resistance Vmin Vmax Vrms Relative

Condition Current (A) (mQ) (mV) (mV) (mV) Error (%)

Use A 1.07 65.9 33.0 98.9 70.7 1.516

UseB 1.92 36.9 18.5 112 70.7 1.642

3-36
 Designing With the EMU

Observations • Battery replaced

• Wide operating supply ranges can be supported at

low average error.
• Gas gauge not valid
In general, battery capacity monitoring should be con-
• Current levels contributing smll-II portions of
capacity drain may operate at relatively high error
sidered as relative and approximate, despite the
accuracy discussed above. A reasonable parallel might be
to achieve lowest average error. the gas gauge of a car.
Either analysis might similarly be performed on The key difference is that for cars, the auto gas gauge is
"nominal," "low drain," and "high drain" capacity usage the source of inaccuracy while the gas tank capacity is
profiles to select a compromise sense resistor well-suited constant; for battery applications, the EMU gas gauge is
to a range of system applications having different supply accurate but the battery capacity fluctuates. The
current profiles. capacity of a single battery varies significantly with the
rate of discharge (see Figure 4) and the temperature at
Other Selection Factors charge and discharge (see manufacturers' battery
specifications). For specific conditions, the minimum
The maximum voltage drop across the sense resistor capacity for a new battery is per the data sheet, but
must also be considered when choosing the resistor capacity variations across a battery population can be
value. The sense resistor voltage drop reduces the effec- large.
tive battery voltage to the system. The maximum voltage
drop occurs at maximum system supply current, plus Gas Gauge Registers
any simultaneous EMU-controlled discharge current.
Voltage drop may be minimized by designing to monitor The gas gauge, gas gauge threshold, and the last
only current consumption across a reasonable range of capacity register pairs record capacity removed. They
currents. Extremely low currents typically do not con- are used to monitor the remaining capacity of the secon-
tribute significantly to system discharge and may be dary battery, as determined from discharge current.
reasonably estimated based on duration.
The gas gauge is a 16-bit totalizer that maintains the
Average voltage drop may also be considered when total discharge from the battery through the sense resis-
choosing the resistor value for applications where the tor. The gas gauge rolls over and continues counting if
monitoring is desired over long periods of time. The the 16-bit capacity is exceeded. Rollover should be
average voltage drop determines the time to rollover in avoided, however, because with rollover, the gas gauge
the gas gauge register pair (see below). An average volt- threshold and the last capacity values may be difficult or
age drop of 70 m V results in rollover after 20 hours of impossible to use. At the optimum sense resistor drop, 70
active monitoring, and an average voltage drop of 140 m V, the gas gauge rolls over after 20 hours. If the inputs
mV results in rollover after 10 hours. to Equation 1 or 2 define the current drain profile, the
maximum capacity measured without rollover is about
The measurement error associated with the voltage drop lAIRs amp-hours, where Rs is the sense resistor value in
during EMU-controlled discharge may be considered ohms.
separately, depending on system strategy for such dis-
charge. Typically this discharge only applies to a small Last Capacity Register Pair
portion of the capacity.
The last capacity register pair contains the gas gauge
value when the last EDCV threshold was reached. This
Capacity-Monitoring Software Design value should be qualified by the battery replaced bit, BR
The system software can determine the secondary bat- (see the capacity reference management discussion
tery condition whenever Vcc is supplied to the EMU. below). When a battery is monitored from full charge to
The EMU provides the following capacity and diagnostic full discharge (final EDV), the value recorded in the last
information for use in capacity monitoring: capacity register represents the measured capacity of
that battery.
• Capacity removed
Gas Gauge Threshold Register Pair and GGN
• Gas gauge threshold notification
The gas gauge threshold register pair provides the sys-
• Last capacity measured tem with a convenient method of monitoring battery con-
sumption. When the threshold is met or exceeded, an
• End-of-discharge voltage status interrupt is generated and GGN is set.
• Secondary battery fault

3-37
Designing With the EMU

Options include: • Nickel-metal hydride 0.9 to 1.0 volts/cell

• Selection of a specific critical notification threshold. The EDV threshold may be repeatedly adjusted during
system operation to provide remaining capacity informa-
• Interrupt-driven capacity monitoring. Each time tion. For example, a specific NiCd battery type may be
the threshold is reached and GGN is set, the characterized so that the user is provided one or more
threshold is incremented by a fixed amount. This early warnings at reasonable times prior to the final, or
allows the processor to easily note the usage of forced reset, voltage. EDV may also be used to manage
fixed capacity amounts. the capacity reference, as discussed below. The last
capacity registers are rewritten after each EDV decision.
End-of-Discharge Voltage Status, EDV The software may need to monitor the gas gauge
The end-of-discharge voltage status bit, EDV; is a voltage capacity usage between EDV thresholds.
monitor of the battery capacity. When this bit is 1, the
Before the system is shut down, the final EDCV should
per-cell voltage of the secondary battery is below the be programmed. This is required when the EMU is
value in the EDCV register. When EDV becomes 1, the programmed for a DC-input-initiated charge action that
EMU generates an interrupt, and loads the last capacity includes a discharge phase.
register pair.
Adjustments in discharge rate affect the battery voltage.
Figure 4 shows a typical discharge for a NiCd battery.
After an EDCV threshold has been reached, a decrease
The rapid decline of the voltage toward the end of dis-
or cutoff of the battery discharge may allow the voltage
charge points out the critical nature of EDV. The system
to recover to above the threshold. This should not typi-
must be warned when the voltage drops into the dis-
cally impact decisions based on reaching this threshold.
charge knee so that the user can take action. The value
Appendix A describes factors affecting the secondary bat-
in EDCV determines the per cell voltage that activates tery voltage.
EDV. "C" is the battery capacity, and is commonly used
to express charge and discharge per-hour rates. Secondary Battery Faults
Typical final end-of-discharge voltages are: A secondary battery fault indicates that the battery is
• NiCd 0.9 to 1.0 volts/cell not capable of sustaining system operation. Such faults
are monitored using the EDV threshold and the secon-
• Lead-acid 1.6 to 1.8 volts/cell dary battery fault bit, SBF.
EDV sensing may be used by appropriately program-
ming EDCV and using EDV as a general-purpose voltage
monitor.
EDV may be used to monitor for shorted cells and for
voltage depression. A single shorted cell causes the bat-
1.4 tery voltage to drop by a one-cell increment. EDV may be
~ used on power-up and power-down to verify battery volt-
age. If the battery voltage is one cell voltage or more
~ i:::-=
~ ~ t==: r::-- .- 1200 mAh
~
<II
en
~
1.2
- r---F::'"" "'" ----...,
below the final EDV threshold, charging may be dis-
abled and the user should be notified. If the battery
voltage of a newly charged battery (GGNV=O, gas
~
1
1\ 1\ gauge=O) is one cell voltage or more below nominal,
a; charging should be disabled, and the user should be
(J notified.

II Voltage depression, a NiCd phenomonen colloquially

.a referred to as "memory effect," may cause an early EDV.
'----l.-.
ac 4C 1C 0.2C
Voltage depression is characterized by an early step
0 20 40 60 ao 100 120 down in voltage during discharge (see Figure 10). This
voltage decrease may be misinterpreted as full discharge
Discharge Capacity (%)
Source: Senyo G·3 by the system. The tendency toward voltage depression
varies with different batteries, but generally is caused by
repeated shallow discharge/charge cycles. Conditioning
(discussed in Appendix D) may restore the battery
capacity. The system may consider it a probable voltage
Figure 4. Cell Voltage Versus Capacity at depression fault when the expected capacity is only par-
Various Discharge Rates tially consumed but the final EDV threshold is reached.

3-38
 Designing With the EMU

The secondary battery fault bit, SBF, may indicate an In all cases, the system may select an EDCV that will
open or short within the secondary battery. SBF is set to provide the user with an early EDV warning well before
1 when the input to SB is less than 0.5 V per cell. The the final EDV.
EMU prohibits charging, and the system should notify
the user. EDV may also be used within a parallel capacity
monitoring routine, particularly for occasions when
Capacity Reference Management GGNV=l. The EDV threshold may be repeatedly
reprogrammed to provide a best approximation of
When using the gas gauge register information, the sys- capacity monitoring. EDV capacity monitoring is most
tem must subtract the capacity used from an appropriate effective for batteries characterized by a sloping voltage
capacity reference. The base reference may be the profile during discharge, such as lead acid. This ap-
measured capacity of the specific battery, a nominal bat-
tery capacity, or a user-defmed capacity. The base refer-
ence may be adjusted to take into account self-discharge.
proach may still be of value for batteries such as NiCd,
because it may be able to determine full charge. This is
indicated by a rapid voltage drop to a stable voltage
III
above EDV (see the early discharge voltage region curves
When the measured battery capacity is used, a in Figure 4).
reasonable guardband should be selected to account for
the probability that the present charge/discharge cycle EDV Capacity Monitoring Procedure
conditions differ from the conditions during the measure-
ment cycle. The amount of guardband depends on the 1. Increment EDCVby 10 mV.
battery specifications, the previous and present system 2. Check EDV status. If 0, then go to 1.
use conditions, and the precision and variety of the
capacity reference adjustments to be undertaken (dis- 3. Appropriately interpret and store the EDCV
cussed below). value and store the gas gauge value.
The base capacity reference in use, precisely measured 4. Decrement EDCV by 10 mY. If EDCV is less
capacities for one or more batteries, and capacity adjust- than or equal to the EDCV indicating low
ments may be stored in the 32 nonvolatile general- capacity, then go to 9.
purpose storage registers.
5. Wait on EDV interrupt.
Secondary Battery Replaced (BR) and Gas Gauge
6. On EDV interrupt, interpret voltage.
Not Valid (GGNV) Interpretation
7. Compare current gas gauge value to last
The system uses these two bits to decide on a base recorded value.
capacity reference, and possibly to implement parallel
monitoring routines. See Table 2. 8. Record difference; then go to step 3. For NiCd-
like batteries, a difference smaller than a critical
BR=1 indicates that the secondary battery may have value may indicate discharge at the full charge
been replaced. This may invalidate use of the value in or full discharge ends of the discharge curve.
the last capacity register pair as the basis of the capacity
reference. 9. Enter end-of-capacity EDV routine.
GGNV=1 indicates that the gas gauge value is not Capacity Reference Adjustment
measured against a battery fully charged under EMU
control. Regardless of the base reference, the system may use a
calculated capacity adjustment factor in addition to the
actual measured discharge. Self-discharge, discharge
rate, and temperature may all be significant factors.
Table 2. BR and GGNV Capacity Reference
For a NiCd battery, room temperature self-discharge is
about 1% per day. When the battery has not been
Capacity EDV Early removed or charged, self-discharge is readily calculated
SR GGNV Reference Warning by summing the periods of time the system is off and
0 0 Last capacity register Optional calculating the appropriate adjustment factor. One
or previous capacity means to monitor system-off time is for the power-down
reference routine to place a "time stamp" into the general-purpose
nonvolatile registers, for later retrieval and comparison
1 0 Nominal capacity Optional within the power-up routine.

X 1 User-selected or Recom- For precise self-discharge estimates, the system may

estimated using EDV mended monitor the temperature during power-down periods, at
very slight current drains. The designer should be aware
that very slight current drains are more additive than

3-39
Designing With the EMU

substitutive for the self-drain. The few electrode charge Fast charging rates require an active charging method.
sites supporting the active load are not self-discharging, When a battery is undergoing a fast charge, the early
but the many electrode sites not being worked continue full-charge detection and charge current adjustment are
to self-discharge. required to prevent severe damage. The sensitivity of the
full-charge detection is also critical because cumulative
A second base reference adjustment to consider is the overcharging reduces the life of a battery.
discharge rate. For example, a 0.2C NiCd discharge
provides approximately 110% of the capacity of a 1C Conditioning may be applied to a battery to recover from
NiCd discharge. An application with discharge at a very certain kinds of operational degradation, including the
fast rate has less available capacity than an application voltage depression effect.
discharging at a much lower rate (see Figure 4). Rate of
discharge may be readily monitored by adding a fixed The EMU provides the system designer with flexible and
increment to the gas gauge threshold following each efficient methods allowing battery conditioning and fast
GGN interrupt. charge control with minimal overcharge.

Two last considerations are the charge temperature and The EMU controls a constant current charger, and can
discharge temperature, which affect battery capacity in be used to control the charging of any type of recharge-
a moderately deterministic manner. able battery, including NiCd, nickel-metal hydride, lead
acid, and lithium. For some chemistries, the voltage
Capacity References for Multiple Batteries must be limited to avoid permanent electrolyte disas-
sociation.
Implementing some method of battery identification
allows actual measured capacity to be used as the refer-
ence for more than the one battery discharged and Battery Charging Hardware DeSign
charged within the system. The 32 general-purpose non- The hardware design should support all aspects of charg-
volatile registers or other nonvolatile storage may be ing including non-operational discharge and trickle
used to maintain precise capacity references for multiple charge. The EMU charge action hardware consists of:
batteries. Identification may be manual (user input) or
automatic. • Charging power supply
Automatic ID may be implemented similar to the DIN
code on film. (Three electrical or optical contacts would
• Charge control FET

allow management of eight unique batteries.) Resistive • Voltage doubler components

ID is another option.
• Discharge FET
The system could store the last measured capacity for
Charging Power Supply
each battery, as well as calculate a self-discharge decre-
ment to be considered for application each time the bat- The charging power supply provides the required current
tery is reinstalled but not recharged. and voltage for battery charging. The EMU monitors the
charging supply availability on the DC input pin. A
As an added benefit, such a battery ID system might also
valid DC input is from 4.5V to 18V. The supply must
allow identification of battery type (manufacturer,
provide voltages within these limits and sufficient to
nominal capacity, battery chemistry, etc.) to allow the
charge the battery, while under the applicable loads.
system to adjust the EMU program as needed. Cycle
history might also be maintained to determine condition- Charge Control FET and Voltage Doubler
ing requirements.
The charging control is provided by the charge control
pin, CC. This pin is an open-drain output that provides
Battery Charging and the signal polarity to control an n-channel MOSFET.
Conditioning The gate voltage for the MOSFET can be provided by the
EMU voltage doubler. This provides voltages of twice the
Many methods are available for charging batteries (see DC input. The voltage doubler requires three external
Appendix B). The most common methods are passive and components-two diodes, and one capacitor with values
rely on battery manufacturers to build batteries that similar to:
tolerate overcharging. These types of charging may have 1000pF,50V
• Capacitor
lower charger cost, but this small savings advantage
must be considered along with the incompatibility of • Diodes IN914
such chargers for fast charge, and with the excess over-
charge leading to premature death of the rechargable
battery.

3-40
 Designing With the EMU

The CC pin is connected to the cathode end of the output A reasonable maximum time should always be
diode as shown in Figure 1. The CC pin is also connected programmed, if only as a fail-safe measure.
to the gate of the n-channel MOSFET used for charge
control. Table 3 lists recommended MOSFETs. A maximum time of 0 may be programmed to cause
immediate entry into trickle charge mode.
The MOSFETs listed in Table 3 are all logic-level
devices, requiring 5V gate-to-source to turn full on. The Maximum Voltage Termination
voltage doubler output provides the required gate-to-
The maximum voltage per cell termination is based on
source voltage.
the average voltage per cell from the SB input voltage
and the number of cells indicated in CSR1. The maxi-
Table 3. Charge Control n-Channel MOSFET mum value for the maximum voltage per cell is 2.55V,

Charge
Current
Suggested
Part Numbers
and the minimum value must be above O.5Y. Per-cell
values below O.5V do not allow a charge action to start. 1:11
A reasonable maximum voltage should always be
<lA IRLD024 programmed, if only as a fail-safe measure.

<lOA IRLR024, IRLU024 A reasonable maximum voltage is also important in

applications where multiple batteries are to be charged
<20A IRLZ34,IRLZ44 with the system off, with the continous presence of
charging current. If a battery is removed, the charging
supply open circuit voltage should exceed the maximum
voltage, ensuring charge action termination. Charge ter-
Discharge FET mination due to full charge of the battery in the system
The discharge FET is controlled by the discharge control or due to reaching maximum voltage after the battery is
pin, CD (see Figure 1). The CD pin is an open-drain removed resets the charge action state. When the bat-
output that is controlled by the EMU during tery is replaced, the charge action initiates as
programmed discharge and during the discharge inter- programmed (and BR and GGNV are set to 1).
val of "burp" charging. The control polarity is correct for
an n-channel MOSFET. The designer must provide the -IN Termination
proper current-limiting device in the discharge path. The secondary battery voltage at SB is used to determine
The limiting device should be sized for continuos dissipa- -/';.y' The -/';.V termination occurs when three consecutive
tion if EMU-controlled conditioning or capacity dischar- voltage samples indicate decreasing battery voltage.
ges are to be used.
The system designer should consider the noise level at
Consideration should also be given to whether discharg- SB. The -/';.V termination is sensitive to noise, as is any
ing occurs during system operation. If EMU-controlled other differentiating method.
discharge periods occur while the system is operational,
the discharge current should be limited so as to not A suitable RC filter can be used on the SB input pin.
greatly alter the measured capacity. For NiCd batteries The SB input impedance is 500K ohms. A RC filter with
at discharge rates above O.2C, the available capacity a 1K ohm input resistor and a 10 ~F capacitor should be
may decrease from 5 to 7 percent for every doubling of adequate for most noise problems. If very low-frequency
the discharge rate (see Figure 4). « 1 Hz) noise is a problem, however, the system may
require other changes.
Charge Termination on Full Charge
Battery Charging Software Design
The EMU full-charge determination is on the first of:
maximum elapsed time, maximum voltage per cell, or The EMU provides very flexible charging and condition-
-flY determination. The system designer must define ing ability. The system programs the EMU to provide the
these limits. Appendix C provides additional information desired charging and conditioning routine. System con-
on full-charge determination. trol allows an adaptive approach to battery manage-
ment.
Maximum Elapsed Time
Charge Action Selection
The maximum time termination presumes the battery
reaches full charge before the programmed maximum A charge action consists of an optional discharge phase
charge time expires. The maximum value for maximum followed by a charge phase. The EMU must be
charge time is 34 hours. The time covers charge rates programmed to perform charging and conditioning. The
down to O.05C. initial defaults prevent charge or discharge. Program-

3-41
Designing With the EMU

ming the EMU control registers is described in the The battery capacity determination discharge brings the
microprocessor software design section. battery to full discharge. Each charge action begins with
a full discharge if the gas gauge value is greater than the
Discharge Method gas gauge threshold value and GGNV is O. This dis-
charge method discharges the battery to the end-of-dis-
The EMU discharge phase provides three different charge voltage. The termination of this discharge up-
services:
dates the last capacity register pair. With the
• Battery conditioning (see Appendix D) appropriate gas gauge threshold, this discharge method
provides a convienent measure of capacity by discharg-
• Battery capacity determination (described ing only when the battery is near the capacity limit.
previously)
A forced full discharge can be obtained using the first
• Depolarization (see Appendices A and B) method with a very high gas gauge threshold, or by
using the second method with a threshold below the cur-
The conditioning and capacity services take place as the rent value. In either case, the last capacity register is
discharge phase of a charge action, which precedes the written when the final EDV threshold is reached.
actual charge phase. The discharge phase is not per-
formed if GGNV is set to 1. Charge Method
The depolarization discharge occurs within the charge The EMU provides three different charge current
phase to improve charge efficiency. modulation methods:
A battery conditioning discharge procedure may be
programmed by: • Continous charge
• Pulsed charge
1. Writing the EMU discharge method field in
CSR1 to 01. • "Burp" charge
2. Writing the gas gauge threshold value above the These methods are programmed by writing the charge
gas gauge value. and discharge period registers to the appropriate value.
The principles behind these methods are discussed in
Recent depth-of-discharge-before-recharge values
Appendix B. Charging is only available when DC valid,
for the battery should be considered. If the depths
DCY, in register SR is 1 and charge action enable in
are shallow and repetitive, then the gas gauge
register CSR1 is written to 1.
threshold value should be written to a value above
the recent discharge gas gauge values. DC·lnitiated Charging
3. If the system is operational during this dis- DC-initiated charging occurs when the power switch
charge, the GGN interrupt may require special state bit, PS, in register SR is 0 and DCV becomes 1.
service. The charging is performed as previously programmed.
This method starts each charge action with a discharge The important parameters for DC initiated charging are:
phase if the gas gauge threshold value is above the cur- 1. Charge action enable written to 1 in CSR1.
rent gas gauge value and GGNV is O. This discharge
method discharges the battery to the gas gauge 2. -flY enable written to 1 in CSR2.
threshold value or to the end-of-discharge voltage,
whichever comes first. This discharge method saves time 3. -flY sample time is selected in CSR2:
compared to doing a full discharge and can prevent volt- The -flY sample time choice should be based on
age depression effects, or moves the effects out of the charge rate. For high rates, use 8-second sample
recent operating range of the battery. times. The sample time chosen should allow detec-
A capacity discharge or deep discharge conditioning may tion of a 10 m V per cell drop after full charge has
be programmed by: occurred.

1. Writing the EMU discharge method field in 4. Maximum cell voltage written to maximum cell
CSR1 to 10. voltage register, MCV.

2. Writing the gas gauge threshold value below the 5. Maximum charge time written to maximum
gas gauge value. charge time register, MCT.

3. Writing the final EDCV value. 6. Charge period written to CPR.

7. Discharge period written to DPR.

3-42
 Designing With the EMU

8. Discharge method chosen in CSR1: The termination of a command-initiated charge action is

similar to DC-initiated charging termination except the
Final end-of-discharge voltage written to EDCV. charge action can also be terminated by the abort com-
Appropriate gas gauge threshold value written to mand.
GGTH and GGTL.
System Software Strategy
9. Trickle charge enable set in register CSR2:
The EMU contains data RAM for use in managing the
Appropriate trickle charge period written to TPR. secondary battery system. This RAM is meant to provide
nonvolatile storage for battery reference data.
The DC-initiated charge action terminates on any of the
following:
• DCV in SR becomes 0; terminates with GGNV set
On system startup, the operating system should check
the status of the current secondary battery. The follow-
ing is an outline of one system startup strategy:
III
to 1.
1. Read SR from the EMU.
• BR in SR becomes 1; terminates with GGNV set to
1. 2. Retain the status of EDV and GGN.

• SBF in SR becomes 1; terminates with GGNV set

to 1.
3. If PS is 0, then toggle power switch input (low
then high).
4. If GGNV is 0, then go to 5; else:
• PS in SR becomes 1; terminates with GGNV set to
1. a. Enter capacity reference determination
• Charge time exceeds MCT value; terminates with
GGNV set to 0 and begins trickle charge if enabled.
routine.
b. IfBR is 1, then reset with an abort charge
command.
• SB voltage input exceeds MCV value; terminates
with GGNV set to 0 and begins trickle charge if c. Issue charge command. This might require
enabled. reduced current selection using an
optional EMU output.
• -I'N condition determined; terminates with GGNV
set to 0 and begins trickle charge if enabled. d. Go to 7.
Command-Initiated Charging 5. IfBR is 0, then go to 6; else:
The command-initiated charging allows the system to set a. Enter capacity reference determination
the charge action parameters so as not to interfere with routine.
normal system operation.
b. Reset BR to 0 with an abort charge com-
The system operation may cause charging current fluc- mand.
tuations. If this happens, the -I'N condition may be
satisfied erroneously. To prevent false full-charge deter- c. If charging is desired, issue charge com-
minations, the -I'N test should be disabled during the mand and go to 7. Otherwise go to 8.
transitions in charging current by clearing the -/),V
6. If the last capacity register value has not
enable bit to O. The system should reenable -/),V deter-
changed, then use prior capacity reference:
mination as soon as the charging current becomes stable.
a. Use time stamp to estimate self-discharge.
Another consideration is that a faster discharge occurs
when the system is operating under battery power and b. If gas gauge is below the shallow discharge
the discharge control is simultaneously actuated (see the threshold for this battery (25 percent of
Discharge FET section above). This impacts available capacity), then go to 9.
capacity.
c. Issue charge command. This might require
The initialization for command-initiated charging is reduced current selection using an
similar to the DC-initiated charging (described in the optional EMU output.
previous section). The exceptions are:
7. Set system to monitor charging activity.
• A charge action command is required before any
charge action can begin. A commanded charge
action begins when DCV is 1.
• The charge action command is ignored ifPS is O.

3-43
Designing With the EMU

a. If the charging current is to vary with sys- a. Writing discharge mode.

tem activity, then write -eN enable to 0
during charging current transitions. b. Writing EDCV value.

b. During the charging phase of a charge c. Writing gas gauge threshold value.
action, the end-of-discharge cell voltage d. Writing maximum cell voltage value.
can be set to provide interrupt notifica-
tion oflow voltage during charging; i.e., e. Writing maximum charge time value.
DC unavailable or fallen low (perhaps
due to excessive system load). f. Writing -/!,v enable to 1.

8. Save the current charge history. g. Writing GGNV-qualified charge bit (if
desired).
9. Monitor gas gauge using threshold notification.
4. Issue system power-off command.
10. Monitor end-of-discharge cell voltage.
After the system power-off command is issued, the EMU
11. Monitor power switch input, if used. enters the system-off state. This is indicated by PS set to
System shutdown should set the EMU to the desired
o. At this time, DCV = 1 initiates a charge.
unattended charging method. A suggested shutdown out-
line is: Backup Supply Management
1. Store the following information in EMU data
storage: The EMU requires a backup cell when the secondary
battery becomes unavailable. If the backup cell is not
Last capacity value. available, then nonvolatile memory and programmed
settings are lost. The EMU also provides a backup cell
Gas gauge and time stamp value. output regulated down from the secondary battery. See
Cycle life count. Figure 5.

2. If CHG is 1, then issue an abort charge com-

mand.
3. Configure EMU charging action by:

Backup Supply
to System
BC

bq2001
EMU
3V
Backup
Cell

Secondary
Battery
I
~
,.-~---1 SB
-l
l

Backup Cell

BD-12A

Figure 5. Backup Supply

3-44
 Designing With the EMU

Backup Supply Management Hardware Resource Management Hardware Design

Design System Power Control
The backup supply hardware design centers arround System power control is provided by the PS input and
proper choice of the backup cell or battery. The backup PSC output. The PS input is pulled to VBe by lOOK
cell supply output is on the BC pin. The maximum BC ohms. The EMU power control is activated when the PS
output current is 1 rnA for 3 V. The designer should limit input is brought to Vss. This action causes the EMU to:
the typical BC output current to values that will not
overdischarge the secondary battery. The system should 1. IfPS is 0:
supply at least a lOOK ohm load on the BC output. The
maximum capacitance on the BC pin should not exceed 1 a. Set PSC to 1.
~.

The backup cell is connected to BC, input. The backup

cell must provide at least 2.0V.
b.
b.
Activate the PSC output.
Discontinue charge action.
III
d. Activate INT.
The cell capacity requirements are set by the system
considerations: e. Set INTF to 1.

• Total 3V backup load (EMU, RTC, configuration

RAM,etc.)
2. IfPS is 1:
a. Activate INT.
• Time where the secondary battery can not provide
the system backup, i.e., during removal or b. Set INTF to 1.
depletion. The designer may use the PSC output to enable the sys-
The designer should be aware that the switch-over from tem power supply. The PSC output may also operate an
the secondary battery to the backup cell input occurs LED for system power indication. The PSC output
when the secondary battery regulated output drops remains active while PS in SR is 1.
below the backup cell input. The secondary battery may Annunciators
be brought to very deep discharge if the secondary bat-
tery is allowed to provide significant system backup The designer may configure the EMU to output the state
power over a very long period. The typical 3V backup of certain status bits. These outputs provide indicators
load should be extremely small-only a fraction of the and/or annunciators without system supervision. The
battery self-discharge. available status bits are:

Backup Supply Management Software • CRG

Design • EDV

The backup cell software issues concern the backup cell • BCL
low, BCL, status bit. This status bit is set to 1 when BC,
is below 2.1 V typical . This diagnostic should be reported • DCV
to the user so that the backup cell can be serviced. • GGN

• SBF
Resource Management Each of the status bits can control an open-drain output.
The EMU provides the system with a variety of resource Subsystem Control
management options. The system designer may choose to
use these options as best fits the system. The designer may choose host control of the EMU out-
puts. There are seven configurable open-drain outputs,
including six selectable between host control or status
bit control.

3·45
Designing With the EMU

Resource Management Software Design Appendix A

The software design issues for resource management Characteristics Impacting
include system-on and system-off operation. During the Secondary Battery Voltage
system-off operation, the EMU status bits control those
outputs configured for such control, while the system- Measurement
controlled outputs remain in their last programmed
state. During system-on operation, all outputs may be Cell voltage is affected by discharge rate, capacity reduc-
actively controlled by the system. tion, and temperature. Although this discussion refers to
NiCd, this can be generally applied to other chemistries
System Power Control with similar characteristics.
The system power control software should respond to The discharge rate affect on a NiCd cell is shown in
either a power-on or power-off request. If the EMU is Figure 4. The separations of the discharge curves are
providing the power switching function, the system need caused by the internal resistance of the cell.
only to respond to the power-off request. With EMU
power control, the system must issue a power off com- The internal resistance is itself a function of the dis-
mand to instruct the EMU to power the system down. charge current. Figure 6 shows the equivalent circuit of
The system response is discussed in the battery charg- a cell. The Ro in this circuit is a function of the cell
ing, system software strategy section. geometry, including effective electrode area and electrode
separation. Ro is also a function of the electrolyte con-
Even if the PSC output is not used, the PS bit should be ductivity, which depends on ion concentration and
controlled to reflect system power. If PS is 1, the EMU temperature.
charging action must be commanded by the system. If
PS is 0, any programmed charge action is initiated by The Rp in Figure 6 is a complex function of discharge
valid DC. rate. The higher the discharge rate, the greater the Rp.
Rp is the resistance due to polarization at the electrodes.
EMU Status Annunciators Polarization is a state where the ion concentration
within a battery varies across the plate separation. This
The EMU can support the six status bits listed above as polarization is shown in Figure 4 by comparing the volt-
outputs. The state of these outputs are indicated in SR. age separation between the initial lC and 4C rates and
The system enables the status bit control of its output to the 4C and SC separation. Figure 4 shows that the
through the mask register, MR. Writing a 1 to a MR bit voltage difference for a factor of 4 change in rate at the
selects status bit control of a particular open-drain out- lower discharge rates is about equal to the voltage dif-
put. If an output is under status bit control, the output is ference for a factor 2 change in rate at the higher rates.
controlled regardless of the system power state.
System-Controlled Outputs
System control of an output is selected by writing its bit
in MR to o. This action places an open-drain output
under the control of the output control register, OCR.
The system may set the bits in OCR to control certain
subsystems (i.e., fixed disk, floppy disk, back-lighting) or
to control an annunciator (LED). As the system controls
the operation of subsystems to minimize battery con-
sumption, the effect of changing available charge current
should be considered, as discussed in the command-
initiated charging section.
The system software should set the OCR bits to the
80-9
proper power-down state before issuing the power-down
command. If system power is off, the EMU maintains the
OCR-controlled outputs in their last programmed state. Figure 6. Battery Equivalent Circuit
If system power is on, the system may continue to con-
trol the outputs (independent of the PS bit status).

3-46
 Designing With the EMU

The Cp is the capacitance associated with polarization. The capacity-reduction effect is due to the change in con-
This term becomes important if the discharge is a pulse. centration/activity of the various ions within the
In a pulse discharge, Cp provides an effective reduction electrolyte as the cell is discharged. During the dis-
in the impedance due to polarization. charge of a cell, ion activity changes. This effect reduces
the open-circuit voltage during discharge, for a NiCd
Figure 7 shows the change in internal resistance as a typically by 100 to 200 mV (see Figure 4).
function of spent capacity for two different NiCd cells.
The internal resistance of NiCd cells is low, about 10 to Figure 8 shows the operating temperature effect on in-
20 milli-ohms, and fairly flat over a good range of spent ternal resistance. These curves are typical for the opera-
capacity. For lead-acid batteries, the electrolyte par- tive range of NiCd cells.
ticipates actively in the discharge reaction, so the inter-
nal resistance has a much larger change with spent Temperature effects on battery voltage are documented
capacity. by the battery manufacturers. Within the specified bat-
tery operation temperature range, the open-circuit volt-
age increases with temperature.
III
16 16
~
! I
II i / !
14 14
a- I _./ ~ I
I
: I
I a-
s.. 12
~--+---- -_. - --
.
-."
..
_ -
s..
12
------
600 mAh
._.-L_ . --._---..,
u 600mAh
c 10 ! u 10
co c
1ii I co I
..
'iii
a:
8
i
1ii
.
'iii
a:
8
I
iii 6 6
~
!
E I iii
.. /
!
.E 4
1200 mAh
i
.E
4 -- .. 1200 mAh
r-----i
2
I 2

oI o I
o 20 40 60 80 100 -20 o 20 40 60

Discharge Capacity (%) Cell Temperature eC)

Source: Sanyo G·4 Source: Sanyo G·s

Figure 7. NiCd Internal Resistance Versus Figure 8. NiCd Internal Resistance Versus
Discharge Capacity Cell Temperature

3-47
Designing With the EMU

Pulse trickle charging is another option to replenish self-

Appendix B discharge. Continuous trickle charging at low current
Battery Charging Methods tends to work the most accessible charge sites con-
tinuously. Pulse trickle charging with a periodic full cur-
Two basic supply types are used in chargers: rent efficiently exercises most of the charge sites and
allows a depolarization period in between.
• Constant current

• Constant potential Constant Potential

The actual charge provided to the battery is a modula- Constant potential (voltage regulated) charging is used
tion of the outputs from these supplies. primarily on systems where the battery is vented or
when voltage above a certain level causes permanent
Constant Current disassociation of the electrolyte, i.e., some rechargeable
lithium batteries. The regulated voltage charger
Constant current charging can be performed on any provides a constant potential to a battery and is current-
rechargeable battery, but requires an appropriate maxi- limited. When applicable, the constant voltage charger
mum voltage limit for those batteries where voltages provides a rapid charge in the early times. As the charg-
above a certain level cause permanent disassociation of ing progresses and the battery potential comes closer to
the electrolyte, i.e., some rechargeable lithium batteries. the charging potential, the rate of charge diminishes.
The constant current supply maintains the charge to the
The system designer has two primary input decisions
battery within a finite voltage range. Constant current
when designing a constant potential charger: the charg-
charging provides an efficient method because the
charge rate does not change due to the changes in inter- ing voltage and the current limit. The higher voltage
should be accompanied with a higher current limit. The
nal resistance or open cell voltage of the battery.
values of these two parameters determines the time that
Constant current charging methods require either a bat- the battery system charges at constant current. Initially,
tery designed for continous charging or a feedback due to the curreI}.t limit and the voltage applied, the
mechanism to determine the full-charge condition. For battery is charged at the current limit. As the battery
example, standard sealed NiCd cells may be charged voltage gets close to the charging potential, the charging
continuously at rates of O.05C to O.IC, and quick-charge current decreases. The fmal current is determined by the
batteries can handle rates of O.2C to O.33C. Fast-charge internal resistance and the open cell voltage of the bat-
batteries under feedback control may be charged at rates tery. This current is the maintenance charge or trickle
up to 4C. charge level for the battery.
Constant current charging does not have to be continous Using higher charging voltages results in a higher main-
over the charging period. Pulse charging may provide tenance current. This may reduce the life of the battery.
high charging efficiencies. Pulse charging provides a Due to decay in charging current toward the end of
period of high rate followed by a period of no current. charging, series cell batteries may experience loss of
The current duty cycle can be modulated so that the capacity unless the charge time is extended. Vented bat-
average charge rate does not exceed that allowable for a teries typically have a greater increase in internal resis-
particular battery. During the no-current period, the bat- tance at full charge compared to sealed batteries. This
tery recovers from the polarization due to high current. increased internal resistance reduces the trickle current
The pulse charge efficiency is achieved from the higher under constant potential charging.
charge rate voltage and the reduction in polarization.
Constant potential charging is not recommended for
"Burp" charging is an extension beyond pulse charging. sealed NiCd or nickel-metal hydride. These batteries are
This method uses a short period of discharge between designed to minimize polarization and consume the
charge pulses to aid in depolarization. This reduction in oxygen produced during over charging. This results in
polarization improves the charging efficiency, and is smaller increase in battery internal resistance during
used in very sophisticated battery maintenance charging as compared to the vented cells. Therefore the
chargers. There are claims that "burp" charging can constant potential maintenance charge may be too large
rehabilitate degraded cells. and may result in damage to the battery.
Constant current charging may be done at a low level,
C/20 to C/30. This type of charging, often called trickle
charging, is used to maintain charge by replacing the
capacity lost due to self-discharge.

3-48
 Designing With the EMU

uses the change in battery temperature to determine full

Appendix C charge. The ~T method requires two temperature sen-
Charge Termination sors, one for the battery and one for the ambient condi-
tion. When the difference between these temperatures
Full battery charge may be determined by several reaches a predetermined value (typically lOOe), the
methods. charging is terminated.

• Time The drawbacks of this approach are:

• Battery temperature • The continuing overcharge while the temperature

increase conducts to the sensor.
• Delta temperature, ~T
• The overcharge or undercharge error that may
•
•
Battery voltage
Negative delta voltage, -~V
result ifthe base battery temperature is below or
above the ambient temperature. III
Time Termination Voltage Termination
The battery voltage termination method can be used
Time termination may be applied to constant potential
only with constant current charging. The voltage across
or constant current charging. Time should not be used as
a battery is determined by the open-circuit battery volt-
the only termination control when charging at high
age and the voltage drop due to the charging current
rates. Such control results in overcharging of a partially
through the internal resistance of the battery (see Fig-
discharged battery. Time may, however, provide a fail- ure 6). The open-circuit battery voltage increases during
safe mechanism when using other charge-termination
charging due to the change in activity of the electrolyte
methods.
ions.

Temperature Termination The internal resistance of the battery changes due to

polarization, ion concentration, and temperature of the
Battery temperature may be used to terminate constant electrolyte. As polarization increases, the internal resis-
potential or constant current charging. The battery tance increases. Under constant current charging, as the
temperature increases due to the energy conversion by internal resistance increases so does the voltage across
the internal resistance of the battery. Other controlling the battery.
factors are:
The voltage termination method depends on the ability
• Temperature dissipation ability ofthe battery to choose a termination voltage that will be achieved
after the battery has become fully charged. This choice is
• Ambient temperature difficult to make considering the parameters that
• Thermal conductivity of the battery influence the battery charging voltage. If a voltage is
chosen such that full charge is not reached, the battery
• Thermal mass of the battery looses capacity. If full charge is exceeded, overcharging
occurs. Maximum battery charging voltage may, how-
When the temperature is measured on the outside of the ever, provide a good fail-safe termination.
battery, the lag due to the above list can result in over-
charging. A temperature that ensures full charge will
always involve some overcharge. Also, charging cold or Negative Delta Voltage
hot batteries can result, respectively, in either overcharg-
The -~V method is applicable only to constant current
ing or terminating before full charge. The ambient
charging. This method is equivalent to the ~T approach,
temperature presents a similar problem.
taking advantage of cell heating at full charge. The -~V
method has the benefits of faster response (no heat con-
Delta Temperature duction to a sensor) and no need for comparison to a
reference. Where the voltage termination method
The delta temperature method, ~T, is similar to the depends on the voltage increase during charging, the -~V
temperature cutoff method described above except that method uses the voltage decrease immediately after full
the ambient temperature effect is removed. This method charge.

3-49
Designing With the EMU

Ail the battery becomes fully charged, more and more mination. A significant charge may remain, but at too
energy is dissipated by the battery's internal resistance, Iowa voltage.
even as the voltage continues to rise. This energy raises
the temperature of the battery. As the temperature Continuous trickle charging above the maintenance level
increases, the internal resistance decreases. Immedi- for prolonged periods leads to overcharging and possibly
ately after full charge, this temperature effect overcomes voltage depression. High temperatures magnify this
the polarization effect, and the constant current problem.
charging voltage decreases (see Figure 9). The -flY Repetitive charge and shallow discharge cycles also lead
method uses this phenomena to determine full charge. to voltage depression. These cycles expose the non-
This method uses the temperature effect on the conduc- discharged electrode materials to repeated overcharge.
tivity of the electrolyte to predict end of charge. There- Conditioning may be done by one or more full discharge
fore, this method is similar to the ,1.T method but reacts and charge cycles. This action recovers the lost energy
to the internal temperature of the batteries, providing capacity. Periodically choosing an EDCV below the usual
faster response and not requiring the addition of operating EDCV removes the voltage depression that
precision temperature-sensing devices. develops near the usual operating EDCV. Implementing
The key difficulty of the -,1.V method is the risk of false a "burp" charge pattern may also result in recovery from
full-charge determination due to a voltage drop unre- voltage depression.
lated to full charge. This is a significant issue with Lead-acid batteries that are allowed to have the open-
charging during system operation ifthe charging current circuit voltage drop below 1.98V undergo sulfation. Sul-
fluctuates with subsystem activity. In such cases, -,1.V fation greatly increases the internal resistance of the
observations coincident with charging current decreases battery. If the open-circuit voltage does not go below
should be ignored. 1.8V, this sulfation may be reversed by charging the bat-
tery at constant current, O.05C, with an increased maxi-
mum voltage limit. This breaks down the lead sulfate
Appendix D crystals and returns the battery to normal internal resis-
Battery Conditioning tance.

The conditioning of rechargeable batteries is a corrective References:

action meant to restore the full-charge capacity of the
battery. 1. Gates Energy Products, Inc., Sealed Recharge-
able Batteries Application Manual.
A NiCd battery may exhibit a phenomena called "voltage
depression." Voltage depression is a reduction in avail- 2. Sanyo Electric Co., Ltd., CADNICA® Sealed
able voltage from the battery (see Figure 10). Voltage Type Nickel-Cadmium Batteries Engineering
depression, sometimes referred to as "memory effect," Handbook, SF-6336.
may cause a false end-of-discharge voltage (EDV) deter-

70r 1.6 I Initial

1.4 i---+---1---j- ___ 1st after 100 cycles

U I
60'

' ; 50r ~1.4

1.5
,ICell voltage
~ [\
r><' .,:' ..
I
2!
~
R'<::-+---I--+- ._._.-
~'"""'~ .. 'ce,,,... ,,,,~. ~·~l·-
2nd after 100 cycles _
3rd after 100 cycles

'I~
Cut off temperature ....

i"
40~ 1
II
1.3
k< ~ S.
::
1.2
r--
Cycle Conditions:
Charge:0.1CX10Hrs.
II

I i~~S
5~
I
Do : 0
30~ ~ 1.2
Cell temperature /'
1
. ~
1 r--
Discharge: 1 eX10 Mms ~
,j\
...
=
~
: CD
20r u 1. 1
i
.-/ ::c
''''''
10~
E
. -
~
~
Temperature: 4S'C
I I I

Discharge Characteristics Testing Conditions: ~

i
I 1

5 III Charge: 0.1 CX16 Hrs. L I I,

!:I '
lOr-

ol
1.0
Internal gas pressur~ ?
"- o
.5 .8 - Discharge: 1 C •
Temperature: 20 C
1 I !
I
":
10 20 30 40 50 60 70 60
- Fast·charge 1200 mAh Charge Time (Mlns.)
Source: Sanyo
o 10 20 30 40 SO 60 70
......... Standard 1200 mAh
Discharge Time (Mins.)
G·l
Source: Sanyo G·2

Figure 9. Rapid Charge Characteristics Figure 10. Voltage Depression

3-50
Static RAM Nonvolatile Controllers 4
~BENatMARQ bq2201
SRAM Nonvolatile Controller Unit
Features General Description During a power failure, the external
SRAM is switched from the Vee sup-
~ Power monitoring and switching The CMOS bq2201 SRAM Non- ply to one of two 3V backup supplies.
for 3 volt battery-backup volatile Controller Unit provides all On a subsequent power-up, the
applications necessary functions for converting a SRAM is write-protected until a
standard CMOS SRAM into non- power-valid condition exists.
~ Write-protect control volatile read/write memory.
The bq2201 is footprint- and timing-
~ 3 volt primary cell inputs A precision comparator monitors the compatible with industry standards
~ Less than 10 ns chip enable 5V Vee input for an out-of-tolerance with the added benefit of a chip
propagation delay condition. When out of tolerance is enable propagation delay of less
detected, a conditioned chip enable than 10 ns.
~ 5% or 10% supply operation output is forced inactive to write-
~ 8-pin plastic DIP or SOIC
protect any standard CMOS SRAM.
III
Pin Connections Pin Names
VOUT Supply output
BCl-BC2 3 volt primary backup cell inputs
THS Threshold select input
--C7 1
CE Chip enable active low input
V OUT [ 1 8 ~l Vee
CEcON Conditioned chip enable output
BC 2 L2 7~JBC1
THS [3 6 nCECON Vee +5 volt supply input

VssL 4 5
______ J
hCE Vss Ground

PN-17

Functional Description IfTHS is tied to Vss, power-fail detection occurs at 4.62V

typical for 5% supply operation. If THS is tied to VOUT,
An external CMOS static RAM can be battery-backed power-fail detection occurs at 4.37V typical for 10%
using the Vout and the conditioned chip enable output supply operation. The THS pin must be tied to Vss or
pin from the bq2201. As Vee slews down during a power VOUT for proper operation.
failure, the conditioned chip enable output CEeoN is
forced inactive independent ofthe chip enable input CEo If a memory access is in process during power-fail detec-
tion, that memory cycle continues to completion before
This activity unconditionally write-protects external the memory is write-protected_ If the memory cycle is not
SRAM as Vee falls to an out-of-tolerance threshold VPFD. terminated within time tWPT, the CEeoN output is uncon-
VPFD is selected by the threshold select input pin, THS. ditionally driven high, write-protecting the memory.

Sept. 1990 1/8

4-1
bq2201

As the supply continues to fall past VPFD, an internal A valid isolation signal requires CE low as Vee crosses
switching device forces VOUT to one of the two external both VPFD and Vso during a power-down. Between these
backup energy sources. CEeoN is held high by the VOUT two points in time, CE must be brought to (0.48 to 0.52)*
energy source. Vee and held for at least 700ns. The isolation signal is
invalid if CE exceeds 0.54*Vee at any point between Vee
During power-up, VOUT is switched back to the Vee crossing VPFD and Vso. See Figure 2.
supply as Vee rises above the backup cell input voltage
sourcing VOUT. The CEeoN output is held inactive for The appropriate battery is connected to VOUT immedi-
time teER (120 ms maximum) after the supply has ately on subsequent application and removal of Vee.
reached VPFD, independent of the CE input, to allow for
processor stabilization.
During power-valid operation, the CE input is fed
through to the CEeoN output with a propagation delay of
less than 10 ns. Nonvolatility is achieved by hardware
hookup as shown in Figure 1.

Energy Cell Inputs-BC1, BC2

Two primary backup energy source inputs are provided
on the bq2201. The BCl and BC2 inputs accept a 3V
primary battery, typically some type of lithium
chemistry. If no primary cell is to be used on either BCl
or BC2, the unused input should be tied to Vss.
If both inputs are used, during power failure the VOUT
output is fed only by BCl as long as it is greater than
2.5Y. If the voltage at BCl falls below 2.5V, an internal
isolation switch automatically switches VOUT from BCl CE - O.5Vcc
to BC2.
To prevent battery drain when there is no valid data to
retain, VOUT is internally isolated from BCl and BC2 by
either: FG-2

• Initial connection of a battery to BCl or BC2, or

• Presentation of an isolation signal on CE.

Figure 2. Battery Isolation Signal

+5V

Vcc VOUT Vcc

From Address Decoder CE
bq2201
BC 1 CMOS
3V CE CE SRAM
l
CON
THS
Primary BC 2 3V
Cell
Vss Primary
lcell

80-1

Figure 1. Hardware Hookup (5% Supply Operation)

2/8 Sept. 1990

4-2
 bq2201

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT~Vee+0.3
relative to Vss
TOPR Operating temperature o to 70 °C
TSTG Storage temperature -55 to 125 °C
TBIAS Temperature under bias -10 to 85 °C
TSOLDER Soldering temperature 260 °C For 10 seconds
VOUT current 200
lOUT

Note:
rnA

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
III
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods oftime may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes

4.75 5.0 5.5 V THS=Vss

Vee Supply voltage
4.50 5.0 5.5 V THS = VOUT
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vcc + 0.3 V
VBCl, Backup cell voltage 2.0 - 4.0 V
VBC2
THS Threshold select -0.3 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25°C, Vcc = 5V or VBC.

Sept. 1990 3/8

4-3
bq2201

DC Electrical Characteristics (TA = 0 to 70·C, VCC = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±1 IlA VIN = Vss to Vcc

VOH Output high voltage 2.4 - - V IOH = -2.0 rnA
VOHB VOH, BC supply VBC - 0.3 - - V VBC > Vcc, IOH = -101lA
VOL Output low voltage - - 0.4 V IOL = 4.0 rnA
Icc Operating supply current - 3 5 rnA No load on VOUT and
CECON.
4.55 4.62 4.75 V THS=Vss
VPFD Power-fail detect voltage
4.30 4.37 4.50 V THS = VOUT
Vso Supply switch-over voltage - VBC - V
VOUT data-retention
IcCDR Data-retention mode - - 100 nA current to additional
current memory not included.
Vcc - 0.2 - - V Vcc > VBC, loUT = 100rnA
VOUTl VOUT voltage
Vcc - 0.3 - - V Vcc > VBC, loUT = 150rnA
VOUT2 VOUT voltage VBC- 0.3 - - V Vcc < VBC, loUT = 1001lA
Active backup cell - VBC2 - V VBCl < 2.5V
VBC voltage
- VBCl - V VBCl> 2.5V
IOUTl VOUT current - - 160 rnA VOUT > Vcc - 0.3V
IOUT2 VOUT current - 100 - IlA VOUT > VBC - 0.2V

Note: Typical values indicate operation at TA = 25·C, Vcc = 5V or VBC.

4/8 Sept. 1990

4-4
 bq2201

Capacitance (TA = 2S·C, F = 1MHz, Vcc = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIN Input capacitance - - 8 pF Input voltage= OV
COUT Output capacitance - - 10 pF Output voltage = OV

Note: This parameter is sampled and not 100% tested.

AC Test Conditions

•
Parameter Test Conditions

Input pulse levels OVto3.0V

Input rise and fall times 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figure 3

9600

CE CON o---~------+

5100 100pF

OL-1

Figure 3. Output Load

Sept. 1990 5/8

4-5
bq2201

Power-Fail Control (TA = 0 to 70·C)

Symbol Parameter Minimum Typical Maximum Unit Notes

tPF Vee slew, 4.75V to 4.25V 300 - - ~s

tFs Vee slew, 4.25V to Vso 10 - - ~s

tpu Vee slew, 4.25Vto 4.75V 0 - - ~s

teED Chip enable propagation - 7 10 ns

delay
Time during which SRAM is
teER Chip enable recovery 40 80 120 ms write-protected after Vee
passes VPFD on power-up.
Delay after Vee slews down
tWPl' Write-protect time 40 100 150 ~s past VPFD before SRAM is
write-protected.

Note: Typical values indicate operation at TA = 25·C.

Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down Timing

Vee

Veo

CE

t WPT

CE CON

PD-1

6/8 Sept. 1990

4·6
 bq2201

Power-Up Timing

Vee

CE

CE eON V._
OHB
~---/r----.
____ '=
%___'=L
"'-__1 -
-
PU-1

Sept. 1990 7/8

4-7
bq2201

Ordering Information

bq2201

l Package Option:
PN =8-pin narrow plastic DIP
SN =8-pin narrow SOIC

-Device:
bq2201 Nonvolatile SRAM Controller

8/8 Sept. 1990

4-8
 ~ BENCHMARQ _ _ _ _ _ _ _ _b_q.....;;..2_2_0_4
X4 SRAM Nonvolatile Controller Unit
Features General Description During a power failure, the external
SRAMs are switched from the Yee
~ Power monitoring and switching The CMOS bq2204 SRAM Non- supply to one of two 3Y backup sup-
for 3 volt battery-backup volatile Controller Unit provides all plies. On a subsequent power-up, the
applications necessary functions for converting SRAMs are write-protected until a
up to four banks of standard CMOS power-valid condition exists.
~ Write-protect control SRAM into nonvolatile read/write
memory. During power-valid operation, a two-
~ 2-input decoder allows control for input decoder transparently selects
up to 4 banks of SRAM A precision comparator monitors the one of up to four banks ofSRAM.
~ 3 volt primary cell inputs 5Y Yee input for an out-of-tolerance
condition. When out of tolerance is
~ Less than 10 ns chip enable detected, the fouf conditioned chip
propagation delay enable outputs are forced inactive to
~

~
5% or 10% supply operation
16-pin plastic DIP or SOIC
write-protect up to four banks of
SRAM. III

Pin Connections Pin Names

yOUT Supply output

-"- V" BCl-BC2 3 volt primary backup cell inputs

VOUT 16 Vee THS Threshold select input
BC 2 15 BC1
CE Chip enable active low input
NC 14 CE
AI 13 CEeoN1 CEcONl- Conditioned chip enable outputs
12 CEcON4
CEeON2
11 CEeON3 A-B Decoder inputs
THS .lCE eON4 NC No connect
Vss NC
Yee +5 volt supply input
PN-18 Vss Ground

Functional Description
4.62Y typical for 5% supply operation. If THS is tied to
Up to four banks of CMOS static RAM can be battery- YOUT, power-fail detection occurs at 4.37V typical for
backed using the Yout and conditioned chip enable out- 10% supply operation. The THS pin must be tied to Yss
put pins from the bq2204. As Yee slews down during a or YOUT for proper operation.
power failure, the conditioned chip enable outputs If a memory access is in process to any of the four exter-
CEeoNl through CEeoN4 are forced inactive independent nal banks of SRAM during power-fail detection, that
of the chip enable input CE. memory cycle continues to completion before the memory
This activity unconditionally write-protects external is write-protected. If the memory cycle is not terminated
SRAM as Yee falls to an out-of-tolerance threshold YPFD. within time tWPI', all four chip enable outputs are uncon-
YPFD is selected by the threshold select input pin, THS. ditionally driven high, write-protecting the controlled
If THS is tied to Yss, the power-fail detection occurs at SRAMs.

Sept. 1990 1/8

4-9
bq2204

Ail the supply continues to fall past VPFD, an internal During power-valid operation, the CE input is passed
switching device forces VOUT to one of the two external through to one of the four CEeoN outputs with a
backup energy sources. CEeoNl through CEeoN4 are propagation delay of less than 10 ns. The CE input is
held high by the VOUT energy source. output on one of the four CEeoN output pins depending
on the level of the decode inputs at A and B as shown in
During power-up, VOUT is switched back to the 5V the Truth Table.
supply as Vee rises above the backup cell i~t voltage
sourcing VOUT. Outputs CEeoNl through CEeoN4 are The A and B inputs are usually tied to high-order
held inactive for time teER (120 ms maximum) after the address pins so that a large nonvolatile memory can be
power supply has reached VPFD, independent of the CE designed using lower-density memory devices. Non-
input, to allow for processor stabilization. volatility and decoding are achieved by hardware hookup
as shown in Figure 1.

+L Vee
VOUT

1- Vee I-Vee L Vee LVee

- A
bq2204 CMOS CMOS CMOS CMOS
-B SRAM SRAM SRAM SRAM
CE CON, - CE
iCE
CE ,- CE
From Address
Decoder- CE CE CON2
BC 2 CE C0N3
3~~
Primary l
Cell
-...b THS

Vss
CE C0N4
BC,
-- lav lprimary
Cel
-- BD-2

Figure 1. Hardware Hookup (5% Supply Operation)

2/8 Sept. 1990

4-10
 bq2204

Energy Cell Inputs-BC1, BC2

Two backup energy source inputs are provided on the
bq2204. The BCl and BC2 inputs accept a 3V primary
battery, typically some type of lithium chemistry. If no
primary cell is to be used on either BCl or BC2, the
unused input should be tied to Vss.
If both inputs are used, during power failure the VOUT Vso
output is fed only by BCl as long as it is greater than
2.5V. If the voltage at BCl falls below 2.5V, an internal
isolation switch automatically switches VOUT from BCl
to BC2.
Th prevent battery drain when there is no valid data to
retain, VOUT is internally isolated from BCl and BC2 by
either: - O.5Vcc

•
•
Initial connection of a battery to BCl or BC2, or
Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as Vee crosses
both VPFD and Vso dur~ a power-down. Between these
two points in time, CE must be brought to (0.48 to
0.52)*Vee and held for at least 700ns. The isolation sig-
nal is invalid if CE exceeds 0.54Vee at any point be-
FG-2 -
tween Vee crossing VPFD and Vso. See Figure 2.
Figure 2. Battery Isolation Signal
The appropriate battery is connected to VOUT immedi-
ately on subsequent application and removal of Vee.

Truth Table

Inputs Outputs

CE A B CECON1 CECON2 CECON3 CECON4

H X X H H H H
L L L L H H H
L H L H L H H
L L H H H L H
L H H H H H L

Sept. 1990 3/8

4-11
bq2204

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vcc DC voltage applied on Vcc relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vcc -0.3 to 7.0 V VT S; Vcc + 0.3
relative to Vss
--,
TOPR Operating temperature Oto 70 °C
TSTG Storage temperature -55 to 125 °C
TEIAS Temperature under bias -10 to 85 °C
TSOLDER Soldering temperature 260 °C For 10 seconds
lOUT VOUT current 200 rnA
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70°C)

Symbol Parameter Minimum Typical Maximum Unit Notes

4.75 5.0 5.5 V THS =Vss
Vcc Supply voltage
4.50 5.0 5.5 V THS =VOUT
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIH Input high voltage 2.2 - Vcc + 0.3 V
VBCl, Backup cell voltage 2.0 - 4.0 V
VBC2
THS Threshold select -0.3 - Vcc + 0.3 V
Note: Typical values indicate operation at TA =25°C, Vcc = 5V or VBC.

4/8 Sept. 1990

4-12
 bq2204

DC Electrical Characteristics (TA = 0 to 70·C, VCC = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

III Input leakage current - - ±1 ~ VIN = Vss to Vee

VOH Output high voltage 2.4 - - V IOH = -2.0 rnA
VOHB VOH, BC supply VBC - 0.3 - - V VBC > Vcc, IOH = -10~
VOL Output low voltage - - 0.4 V IOL = 4.0 rnA
Icc Operating supply current - 3 6 rnA No load on VOUT, and
CECONl-CEcON4.

-
4.55 4.62 4.75 V THS= Vss
VPFD Power-fail detect voltage
4.30 4.37 4.50 V THS =VOUT
Vso Supply switch-over voltage - VBC - V
Data-retention mode VOUT data-retention
IccDR current - - 100 nA current to additional
memory not included.
Vcc - 0.2 - - V Vcc > VBC, loUT = 100rnA
VOUTl VOUT voltage
Vcc - 0.3 - - V Vcc > VBC, loUT = 150rnA
VOUT2 VOUT voltage VBC - 0.2 - - V Vcc < VBC, loUT = 100~

Active backup cell - VBC2 - V VBCl < 2.5V

VBC voltage
- VBCl - V VBCl > 2.5V
louTl VOUT current - - 160 rnA VOUT > Vee - 0.3V
IOUT2 VOUT current - 100 - ~ VOUT > VBC - 0.2V
Note: Typical values indicate operation at TA = 25"C, Vcc = 5V or VBC.

Capacitance (TA = 25·C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

Cm Input capacitance - - 8 pF Input voltage = OV
COUT Output capacitance - - 10 pF Output voltage = OV
Note: This parameter is sampled and not 100% tested.

Sept. 1990 5/8

4-13
bq2204

AC Test Conditions

Parameter Test Conditions

Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figure 3

9600

CE CON o-~~~~~~~--+

5100 100pF

OL-1

Figure 3. Output Load

Power-Fail Control (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes

tPF Vcc slew, 4.75Vto 4.25V 300 - - Il s
tFB Vcc slew, 4.25V to VBO 10 - - Il s
tpu Vcc slew, 4.25V to 4.75V 0 - - Il S
tCED Chip enable propagation - 7 10 ns
delay
tAB A,B set up to CE 0 - - ns
Time during which SRAM is
tCER Chip enable recovery 40 80 120 ms write-protected after Vcc
passes VPFD on power-up.
Delay after Vcc slews down
tWPr Write-protect time 40 100 150 Il s past VPFD before SRAM is
write-protected.
Note: Typical values indicate operation at TA = 25'C, Vcc = 5Y.

Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

6/8 Sept. 1990

4-14
 bq2204

Power-Down Timing

Vee

Vso

•
CE

t WPT

CE CON

PD-1

Power-Up Timing

Vee

CE

CEeoNV-~----------------~/

PU-1

Sept. 1990 7/8

4-15
bq2204

Address-Decode Timing

A,B

CE

cEco~- __________________________________t_cm
__1 _________t_c_m_l
CEco~ ---------
'---------
AD-1

Ordering Information

bq2204

1- Package Option:
PN = 16-pin narrow plastic DIP
SN =16-pin narrow SOIC

-Device:
bq2204 Nonvolatile SRAM Controller

8/8 Sept. 1990

4-16
Inlroauclion 1

Processor Managemenl 2

Energvllanagemenl :3

Iialic A'-M Non~olalile eonlrollers 'I

Aeal-Time Clocks 5

Nonvolalile Iialic A'-lis B

Package Drawings" ' J

~BENOtMARQ Preliminary bq3285
Real-Time Clock (RTC)
Features General Description
~ Direct clock/calendar ~ Time of day in seconds, minutes, The CMOS bq3285 is a low-power
replacement for IBM® and hours microprocessor peripheral providing
AT-compatible computers and - 12- or 24-hour format a time-of-day clock and 100-year
other applications calendar with alarm features and
- Optional daylight saving battery operation. Other features in-
~ Socket and functionally adjustment clude three maskable interrupt sour-
compatible with the DS1285 ces, square wave output, and 50
~ BCD or binary format for clock
- Closely matches MC146818A bytes of general nonvolatile storage.
and calendar data
pin configuration
The bq3285 write-protects the clock,
~ Programmable square wave
~ 160 ns cycle time allows fast bus calendar, and storage registers
output
operation during power failure. A backup bat-
~ Three individually maskable tery then maintains data and
~ Selectable Intel or Motorola bus operates the clock and calendar.
interrupt event flags:
timing
- Periodic rates from 122 ~s to The bq3285 is a fully compatible
~ Less than 0.5 IlA load under 500ms real-time clock for IBM AT-
battery operation compatible computers and other
- Time-of-day alarm once per
~ 14 bytes for clock/calendar and second to once per day
applications. The only external com- ~
control ponents are a 32.768 KHz crystal ...
- End-of-clock update cycle and a backup battery.
~ 50 bytes of general nonvolatile
~ 24-pin plastic DIP or SOIC and
storage 28-pinPLCC
~ Calendar in days, day of the
week, months, and years, with
automatic leap-year adjustment

Pin Connections Pin Names

ADo-AD? !Mul~lexed address/data
24-Pin DIP or SOIC 28-Pin PLCC mpu output
MOT B us type select input
CS Chip select input

::::
I- () s: AS Address strobe input
"-~ ~x~~;;,g~

~l''~w
DS Data strobe input
~ CD
"It C'II .....

0
IX)
'" '" '"
"
RiW Read/write input
ADo 5 RCL
AD 1L 5 20 BC
INT Interrupt request output
AD1 BC
AD 2 16 19 liNT AD2 7 INT RST Reset input
AD31 7 18 RST ADa RST SQW Square wave output
AD4f 8 17f1DS AD4 OS
AD5L9 16P Vss AD5 Vss RCL RAM clear input
ADe! 10 15IJR/W R/VII
NC BC 3V backup cell input
AD7fll 14~"'~ ~ ~ ;:! ~ ~ t::: $!
Vssl 12 13fCS
U DL.TTICTlTO- Xl,X2 Crystal inputs
- - - .. -~-

C' ~ -<
.;- :!ll~ ~ ~ NC No connect
-<
PN-13 PL·a Vee +5V supply
Vss Ground

Sept. 1990 1/18

5-1
bq3285 Preliminary

Block Diagram
X1 Time-
Baaa ;8 ->-- ;84 r-->-- ;84 -
X2 Oacillator

1 1 1 111 11 111

-
RST
rJ
Control/Status
I
~
18 .. MUX

sow
MO~ Registers
~ Generator saw

CS_--I I I
liP
I
R/W--I

AS~
AD O-AD 7

<
Bus

IIF
/L--
'r-
Clock Alarm and
Calendar Bytes

User Buffer
{] ----.
Interrupt
Generator
-
INT

J:=j
114 Byte"
DS - - I
~
------------ .I.
---y' Storage
Registers Cloak/Calendar
- 160 Bytes) Update
RCL
-
'I
CS
vCC
--=-------. Power- -VOUT
BC Fan
----t Control
- WRlTE-
PROTECT
BO-6

Pin Descriptions ADo-AD7 Multiplexed address/data inputJoutput

MOT Bus type select input The bq3285 bus cycle consists of two phases:
the address phase and the data-transfer
MOT selects bus timing for either Motorola phase. The address phase precedes the
or Intel architecture. This pin should be data-transfer phase. During the address
tied to Vee for Motorola timing or to Vss for phase, address placed on ADo-AD7 is
Intel timing (see Table 1). The setting latched into the bq3285 on the falling edge
should not be changed during system opera- of the AS signal. During the data-transfer
tion. MOT is internally pulled low by a 20K phase of the bus cycle, the ADo-AD7 pins
ohm resistor. serve as a bidirectional data bus.
AS Address strobe input
Table 1. Bus Setup
AS serves to demultiplex the address/data
Bus MOT OS R/Vii AS bus. The falling edge of AS latches the ad-
Type Level Equivalent Equivalent Equivalent dress on ADO-AD7. This demultiplexing
process is independent of the CS signal.
Motorola Vee DS,E,or RIW AS
<1>2
Intel Vss RD, WR, ALE
MEMR, MEMW,
or 1I0R orllOW

2/18 Sept. 1990

5-2
 Preliminary bq3285

DS Data strobe input RAM clear input

When MOT = Vee, DS controls data trans- A low level on the RCL pin causes the con-
fer during a bq3285 bus cycle. During a tents of each of the 50 storage bytes to be
read cycle, the bq3285 drives the bus after set to FF(hex). The contents of the clock
the rising edge on DS. During a write cycle, and control registers are unaffected. This
the falling edge on DS is used to latch write pin should be used as a user-interface input
data into the chip. (pushbutton to ground) and not connected to
the output of any active component. RCL
When MOT = Vss, the DS input is provided input is only recognized when held low for
a signal similar to RD, MEMR, or 1I0R in at least 100 ms in the presence of Vee when
an Intel-based system. The falling edge on the oscillator is running. Using RAM clear
DS is used to enable the outputs during a does not affect the battery load.
read cycle.
BC 3V backup cell input
Read/write input
BC should be connected to a 3V backup cell
When MOT = Vee, the level on R/W iden- for RTC operation and storage register non-
tifies the direction of data transfer. A high volatility in the absence of power. When
level on R/W indicates a read bus cycle, Vee slews down past VBe (3V typical), the
whereas a low on this pin indicates a write integral control circuitry switches the power
bus cycle. source to BC. When Vee returns above

--
VBC, the power source is switched to Vee.
When MOT = Vss, R/W is provided a signal
similar to WR, MEMW, or 1I0W in an Intel- Reset input
based system. The rising edge on R/W
latches data into the bq3285. The bq3285 is reset when RST is pulled low.
When reset, INT becomes high-impedance,
Chip select input and the bq3285 is not accessible. Table 4 in
the Control/Status Registers section lists
CS should be driven low and held stable the register bits that are cleared by a reset.
during the data-transfer phase of a bus
cycle accessing the bq3285. Reset may be disabled by connecting RST to
Vec. This allows the control bits to retain
Interrupt request output their states through power-downlpower-up
INT is an open-drain output. INT is cycles.
asserted low when any event flag is set and Xl,X2 Crystal input
the corresponding event enable bit is also
set. INT becomes high-impedance whenever The Xl, X2 inputs are provided for an exter-
register C is read (see the Control/Status nal 32.768Khz quartz crystal, Daiwa DT-
Registers section). 26S or equivalent. A trimming capacitor
may be necessary for extremely precise
SQW Square wave output time-base generation.
SQW may output a programmable fre-
quency square wave signal during normal
(Vee valid) system operation. Anyone of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square wave enable bit (SQE) in
register B is 0 (see the Control/Status
Registers section).

Sept. 1990 3/18

5-3
bq3285 Preliminary

date period (see Figure 2). The alarm flag bit may also
Functional Description be set during the update cycle.
Address Map The bq3285 copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
The bq3285 provides 14 bytes of clock and controVstatus written to the update transfer inhibit bit (UTI) in
registers and 50 bytes of general nonvolatile storage.
register B, the user copy of the clock and calendar bytes
Figure 1 illustrates the address map for the bq3285.
remains unchanged, while the local copy of the same
bytes continues to be updated every second.
Update Period
The update-in-progress bit (UIP) in register A is set tBUC
The update period for the bq3285 is one second. The time before the beginning of an update cycle (see Figure
bq3285 updates the contents of the clock and calendar 2). This bit is cleared and the update-complete flag (UF)
locations during the update cycle at the end of each up- is set at the end of the update cycle.

I"14
Byletl
0

18
Clock and
COntrol Stat...
Rogisters
00

OD
0

2
1 -
Second. Alarm

_eo
00

01

02

14 OE 3 Minutes Alarm 03

4 Hotn 04

6 Hour. Alarm 06
.,..
BCD
Binary
Formet
6 Day 01 w_ 06

7 Date 01 Month 07
150 Storage
Bytes Register. 8 Month 08

8 V ••r 08

10 FIogIster A OA

11 Regloter B OB
12 RogIstor C DC

18 Register 0 00
__ 3

Figure 1. Address Map

I1oI~-------- Update Period ---------.j~1

(1 sec)

UIP
____~Il~________________~Il~______
-..J J.- t UC (Update Cycle)
tauc -..J J.-
UIP-1

Figure 2. Update Period Timing and UIP

4/18 Sept. 1990

5-4
 Preliminary bq3285

Programming the RTe c. Write the appropriate value to the hour for-
mat (HF) bit.
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2). 2. Write new values to all the time, alarm, and
calendar locations.
These steps may be followed to program the time, alarm,
and calendar: 3. Clear the UTI bit to allow update transfers.

1. Modify the contents of register B: On the next update cycle, the RTC updates all 10 bytes
in the selected format.
a. Write a 1 to the UTI bit to prevent transfers
between RTC bytes and user buffer.
b. Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.

Table 2. Time, Alarm, and Calendar Formats

Range

Address RTC Bytes Binary·Coded

Decimal Binary Decimal

0 Seconds 0-59 00H-3BH 00H-59H

1 Seconds alarm 0-59 00H-3BH 00H-59H

2 Minutes 0-59 00H-3BH 00H-59H

3 Minutes alarm 0-59 00H-3BH 00H-59H

Hours, 12-hour format 1-12 01H-OCHAM; 01H-12HAM;

4 8lH-8CHPM 81H-92H PM

Hours, 24-hour format 0-23 00H-17H 00H-23H

Hours alarm, 12-hour format 1-12 01H-OCHAM; 01H-12HAM;

5 8lH-8CHPM 81H-92HPM
~-~- ---

Hours alarm, 24-hour format 0-23 00H-17H 00H-23H

6 Day of week (l=Sunday) 1-7 OlH-07H OlH-07H

7 Day of month 1-31 OlH-1FH OlH-3lH

8 Month 1-12 OlH-OCH 01H-12H

9 Year 0-99 00H-63H 00H-99H

Sept. 1990 5/18

5-5
bq3285 Preliminary

Square Wave Output • The update-ended interrupt, which occurs at the end
of each update cycle
The bq3285 divides the 32.768 KHz oscillator frequency
to produce the 1 Hz update frequency for the clock and Each of the three interrupt events is enabled by an in-
calendar. Thirteen taps from the frequency divider are dividual interrupt-enable bit in register B. When an
fed to a 16:1 multiplexer circuit. The output of this mux event occurs, its event flag bit in register C is set. If the
is fed to the SQW output and periodic interrupt genera- corresponding event enable bit is also set, then an inter-
tion circuitry. The four least significant bits of register rupt request is generated. The interrupt request flag bit
A, RSO-RS3, select among the 13 taps (see Table 3). The (INTF) of register C is set with every interrupt request.
square wave output is enabled by writing a 1 to the Reading register C clears all flag bits, including INTF,
square wave enable bit (SQE) in register B. and makes INT high-impedance.
Two methods can be used to process bq3285 interrupt
Interrupts events:
The bq3285 allows three individually selected interrupt • Enable interrupt events and use the interrupt
events to generate an interrupt request. These three request output to invoke an interrupt service routine.
interrupt events are:
• Do not enable the interrupts and use a polling
• The periodic interrupt, programmable to occur once routine to periodically check the status of the flag
every 122 Ils to 500 ms bits.
• The alarm interrupt, programmable to occur once per The individual interrupt sources are described in detail
second to once per day in the following sections.

Table 3. Square Wave Frequency/Periodic Interrupt Rate

Register A Bits Square Wave Periodic Interrupt

RS3 RS2 RS1 RSO Frequency Units Period Units

0 0 0 0 None None
0 0 0 1 256 Hz 3.90625 ms
0 0 1 0 128 Hz 7.8125 ms
0 0 1 1 8.192 KHz 122.070 IlS
0 1 0 0 4.096 KHz 244.141 Ils
0 1 0 1 2.048 KHz 488.281 Ils
0 1 1 0 1.024 KHz 976.5625 Ils
0 1 1 1 512 Hz 1.953125 ms
1 0 0 0 256 Hz 3.90625 ms
1 0 0 1 128 Hz 7.8125 ms
1 0 1 0 64 Hz 15.625 ms
1 0 1 1 32 Hz 31.25 ms
1 1 0 0 16 Hz 62.5 ms
1 1 0 1 8 Hz 125 ms
1 1 1 0 4 Hz 250 ms
1 1 1 1 2 Hz 500 ms

6/18 Sept. 1990

5-6
 Preliminary bq3285

Periodic Interrupt Update Cycle Interrupt

The mux output used to drive the SQW output also The update cycle ended flag bit (UF) in register C is set
drives the interrupt-generation circuitry. If the periodic to a 1 at the end of an update cycle. If the update inter-
interrupt event is enabled by writing a 1 to the periodic rupt enable bit (UIE) of register B is 1, and the update
interrupt enable bit (PIE) in register C, an interrupt transfer inhibit bit (UTI) in register B is 0, then an
request is generated once every 122~s to 500ms. The interrupt request is generated at the end of each update
period between interrupts is selected by the same bits in cycle.
register A that select the square wave frequency (see
Table 3).
Accessing RTC bytes
Alarm Interrupt Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
During each update cycle, the RTC compares the hours, calendar bytes without ambiguity are:
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm • Enable the update interrupt event to generate
interrupt event flag bit, AF in register C, is set to 1. If interrupt requests at the end of the update cycle.
the alarm event is enabled, an interrupt request is The interrupt handler has a maximum of 999ms to
generated. access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a "don't care" state. An alarm byte is set to a • Poll the update-in-progress bit (VIP) in register A. If
"don't care" state by writing a 1 to each of its two most- UIP =0, the polling routine has a minimum oftBue
significant bits. A "don't care" state may be used to time to access the clock bytes (see Figure 3).
select the frequency of alarm interrupt events as follows:
• Use the periodic interrupt event to generate _
• If none of the three alarm bytes is "don't care," the interrupt requests every tPI time, such that UIP = 1
frequency is once per day, when hours, minutes, and always occurs between the periodic interrupts. The
seconds match. interrupt handler will have a minimum of tpI/2 +
tBue time to access the clock bytes (see Figure 3).
• If only the hour alarm byte is "don't care," the
frequency is once per hour, when minutes and
seconds match. Oscillator Control
• If only the hour and minute alarm bytes are "don't When power is first applied to the bq32S5 and Vee is
care," the frequency is once per minute, when above VPFD, the internal oscillator and frequency divider
seconds match. are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of llX turns the oscillator on,
• If the hour, minute, and second alarm bytes are but keeps the frequency divider disabled. Any other pat-
"don't care," the frequency is once per second. tern to these bits keeps the oscillator off.

110-.------- 1 sec ---------01-1

UIP
----~~~------------~~~----­
taue --I {~tue

PF

UF ________~Ilm~~____________~Ilm~~_
UIP-2

Figure 3. Update-Ended/Periodic Interrupt Relationship

Sept. 1990 7/18

5-7
bq3285 Preliminary

Power-Down/Power-Up Cycle RSO-RS3 - Frequency Select

The bq3285 continuously monitors Vee for out-of- 7 6 5 4 1 o

tolerance. During a power failure, when Vee falls below RSI RSO
VPFD (4.37V typical), the bq3285 write-protects the clock
and storage registers. When Vee is below VBe (3V typi-
cal), the power source is switched to BC. RTC operation These bits select one of the 13 frequencies for the SQW
and storage data are sustained by a valid backup energy output and the periodic interrupt rate, as shown in Table 3.
source. When Vee is above VBe, the power source is
Vee. Write-protection continues for tesR time after Vee OSO-OS2 • Oscillator Control
rises above VPFD.
7 3 2 1 o
Control/Status Registers
The four control/status registers of the bq3285 are acces-
sible regardless of the status of the update cycle (see These three bits control the state of the oscillator and
Table 4). divider stages. A pattern of 010 enables RTC operation
by turning on the oscillator and enabling the frequency
Register A divider. A pattern of llX turns the oscillator on, but
keeps the frequency divider disabled. When 010 is writ-
Register A programs: ten, the RTC begins its first update after 500ms.

Reaister A Bits UIP • Update Cycle Status

7 161 5 I 4 I 3 121 1 I 0
UIP I OS2 I OSl I OSO I RS3 I RS2 I RSI I RSO 6 5 4 3 2 1 o

• The frequency of the square wave and the periodic

event rate. This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
• Oscillator operation. UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI) bit
Register A provides:
in register B is 1.
• Status of the update cycle.

Table 4. Control/Status Registers

Loc. Bit Name and State on Reset

Reg. (Hex) Read Write
7 (MSB) 6 5 4 3 2 1 o (LSB)
A OA Yes Yes! VIP na OS2 na OS2 na OSO na RS3 na RS2 na RSI na RSO na
B OB Yes Yes UTI na PIE 0 AlE 0 UIE 0 SQWE 0 DF na HF na DSE na
C OC Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - 0 - 0 - 0
D OC Yes No VRT na - 0 - 0 - 0 - 0 - 0 - 0 - 0

Notes: na = not affected.

1. Except bit 7.

8/18 Sept. 1990

5-8
 Preliminary bq3285

Register B SQWE • Square Wave Enable

Reaister B Bits 7 6 5 4 2 1 o

UTI I PIE I AlE I VIE ISQWE I DF I HF I DSE

This bit enables the square wave output:
Register B enables:
1 = Enabled
• Update cycle transfer operation
o = Disabled and held low
• Square wave output
UIE • Update Cycle Interrupt Enable
• Interrupt events
• Daylight saving adjustment 7 6 5 3 2 1 o
Register B selects:
• Clock and calendar data formats This bit enables an interrupt request due to an update
ended interrupt event:
All bits of register B are read/write.
1 = Enabled
DSE • Daylight Saving Enable
0= Disabled

-
2 1
The UIE bit is automatically cleared when the UTI bit
equals 1.

This bit enables daylight-saving time adjustments when AlE· Alarm Interrupt Enable
written to 1:
• On the last Sunday in October, the first time the 7 6 4 3 2 1 o
bq3285 increments past 1:59:59 AM, the time falls
back to 1:00:00 AM.
• On the first Sunday in April, the time springs This bit enables an interrupt request due to an alarm
forward from 2:00:00 AM to 3:00:00 AM. interrupt event:
1 = Enabled
HF • Hour Format
0= Disabled
7 6 5 4 3 2 1 o
HF PIE· Periodic Interrupt Enable

7 5 4 3 2 1 o
This bit selects the time-of-day and alarm hour format:
1 = 24-hour format
o = 12-hour format This bit enables an interrupt request due to a periodic
interrupt event:
OF • Data Format 1 = Enabled
7 6 5 4 3 2 1 o
0= Disabled
DF

This bit selects the numeric format in which the time,

alarm, and calendar bytes are represented:
1 = Binary
O=BCD

Sept. 1990 9/18

5-9
bq3285 Preliminary

UTI· Update Transfer Inhibit PF • Periodic Event Flag

This bit inhibits the transfer of RTC bytes to the user
buffer: 7 5 4 3 2 1 o

5 4 3 2 1 o
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RSO-RS3 in register A.
Reading register C clears this bit.
1 = Inhibits transfer and clears VIE
INTF . Interrupt Request Flag
o = Allows transfer
6 5 4 3 1 o
Register C
This flag is set to a 1 when any of the following is true:
Reaister C Bits
AIE= landAF= 1
7 161 5 141 3 I 2 I 1 I 0
0 PIE=landPF=l
INTFI PF I AF I VF I I 0 I 0 I 0
VIE = 1 and VF = 1
Register C is the read-only event status register.
Reading register C clears this bit.
Bits 0-3 . Unused Bits
Register D
7 5 3 2 1 o
o o o o Reaister 0 Bits
7 I 6 I 5 I 4 I 3 I 2 I 1 I 0
These bits are always set to O. VRT I 0 I 0 I 0 I 0 I 0 I 0 I 0

UF • Update Event Flag Register D is the read-only data integrity status register.

7 6 5 3 2 1 0 Bits 0-6 • Unused Bits

[ [ ;F [ [
- [

7 6 5 4 3 2 1 0
[ [ [
0 0 0 0 0 0 0
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
These bits are always set to O.
AF • Alarm Event Flag
VRT • Valid RAM and Time
7 6 4 3 2 1 0
- 6 5 4 3 2 1 0
I!I I I I
I;TI I - I
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit. 1 = Valid backup energy source
o = Backup energy source is depleted
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.

10/18 Sept 1990

5-10
 Preliminary bq3285

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT:O;Vee+0.3
relative to Vss
TOPR Operating temperature o to +70 °C
TSTG Storage temperature -55 to +125 °C

TRIAS Temperature under bias -10 to +85 °C

TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

Ell
Recommended DC Operating Conditions (TA = 0 to 70°C)
Symbol Parameter Minimum Typical Maximum Unit

Vee Supply voltage 4.5 5.0 5.5 V

Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V
VBe Backup cell voltage 2.0 - 4.0 V

Note: Typical values indicate operation at TA = 25°C.

Sept. 1990 11/18

5-11
bq3285 Preliminary

DC Electrical Characteristics (TA = 0 to 70'C, VCC = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

lu Input leakage current - - ±1 ~ VIN = Vss to Vee

Iw Output leakage current - - ±1 ~ ADo-AD7, INT, and SQW
in high impedance,
VOUT = Vss to Vee
VOR Output high voltage 2.4 - - V lOR = -2.0 rnA
VOL Output low voltage - - 0.4 V 10L =4.0 rnA
Icc Operating supply current - 7 15 rnA Min. cycle, duty = 100%,
lOR = OrnA, 10L = OmA
Vso Supply switch-over voltage - VBe - V
leeB Battery operation current - 0.3 0.5 ~ VBe = 3V, TA = 25'C
VPFD Power-fail-detect voltage 4.30 4.37 4.45 V
IReL Input current when RCL = Vss. - - 550 ~ Internal 20K pull-up
IMOTH Input current when MOT = Vee - - -550 ~ Internal 20K pull-down

Note: Typical values indicate operation at TA = 25'C, Vee = 5Vor VBe = 3Y.

Crystal Specifications (DT-26S or Equivalent)

Symbol Parameter Minimum Typical Maximum Unit

fo Oscillation frequency - 32.768 - KHz

CL Load capacitance - 6 - pF
Tp Temperature turnover point 20 25 30 'C
k Parabolic curvature constant - - -0.042 ppm!'C
Q Quality factor 40,000 70,000 -

Rl Series resistance - - 45 KQ

Co Shunt capacitance - 1.1 1.8 pF

CoICl Capacitance ratio - 430 600
DL Drive'level - - 1 IlW
Mlfo Aging (first year at 25'C) - 1 - ppm

12/18 Sept. 1990

5-12
 Preliminary bq3285

Capacitance (TA = 25·C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions
CliO Input/output capacitance - - 7 pF VOUT= OV

CIN Input capacitance - - 5 pF VIN = OV

Note: This parameter is sampled and not 100% tested.

AC Test Conditions
Parameter Test Conditions
Input pulse levels o to 3.0 V
Input rise and fall times 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 4 and 5 III

+5V +5V

9600
For all outputs 1.15Ko
except INT
o-----~--------~

I
INT 0 - - - - - - - - - - - - - - 1

5100 50pF
'''pF

OL-10 OL-l1

Figure 4. Output Load A Figure 5. Output Load B

Sept. 1990 13/18

5-13
bq3285 Preliminary

Read/Write Timing (TA = 0 to 70·C, vcc = 5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit
tcyc Cycle time 160 - - ns
tDSL DS low or RDIWR high time 80 - - ns
tDSH DS high or RDIWR low time 55 - - ns
tRWH RIW hold time 0 - - ns
tRWS RIW setup time 10 - - ns
tcs Chip select setup time 5 - - ns
tCH Chip select hold time 0 - - ns
tDHR Read data hold time 0 - 25 ns
tDHW Write data hold time 0 - - ns
tAS Address setup time 20 - - ns
tAR Address hold time 5 - - ns
tDAS Delay time, DS to AS rise 10 - - ns
tAsw Pulse width, AS high 30 - - ns
tASD Delay time, AS to DS rise (RD/WR fall) 35 - - ns
tOD Output data delay time from DS rise (RD fall) - - 35 ns
tDW Write data setup time 30 - - ns

14/18 Sept. 1990

5-14
 Preliminary bq3285

Motorola Bus Read/Write Timing

AS

OS

- - - + - - . - - - t DSH ----+I

R/W

III
CS

RC-4

Sept. 1990 15/18

5-15
bq3285 Preliminary

Intel Bus Read Timing

RC-5

Intel Bus Write Timing

t cvc

AS (ALE) j~ "l, }
io-- t DAS -II--- t ASW t ASD --I

OS (RD) k'
./

tD8L t DSH ------

./ ~ ""-
R/W (WRI ./k'

~tcs +- tCH -I

CS
""'-"'-"'-"'- "'- ,,~ ~ tAH -I
;;Ik' / /~

~ tAS--I

V
'" )-( "
/

~tDW-{ tDHW --0

WC-5

16/18 Sept. 1990

5-16
 Preliminary bq3285

Power-Down/Power-Up Timing
Symbol Parameter Minimum Typical Maximum Unit Conditions
tF Vee slew from 4.5V to OV 300 - - ~s

tR Vee slew from OV to 4.5V 100 - - ~s

Internal write-protection
tesR CS at VIR after power-up 20 - 200 ms period after Vee passes VPFD
on power-up.

Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

III

Vee

tes~ .

CS _~XXX~~~X~XX~X~XX~>OK=-~_-_-_
PD-4A

Sept 1990 17/18

5-17
bq3285 Preliminary

Interrupt Delay Timing

Symbol Parameter Minimum Typical Maximum Unit
tRSW Reset pulse width 5 - - ~s

trRR INT release from RST - - 2 ~s

tIRD INT release from DS - - 2 ~s

Interrupt Delay Timing

RD/WR (Intel) ,-----------~,~/---------------------------

os (Mot) '-----------~,~/~--------------------------
t R8w

RST

INT

tAD

INT-1

Ordering Information
bq3285

T_Package Option:
P = 24-pin plastic DIP (0.600)
S =24-pin SOIC (0.300)
Q =28-pin quad PLCC

Device:
bq3285 Real-Time Clock with 50 bytes of
general storage

18/18 Sept 1990

5-18
I4l BENOtMARQ _ _pre_'im_in_ary_bq....;;;.,3_2_B_7_/b_q...;;;..3_2_B_7_A
Real-Time Clock (RTC) Module
Features General Description
~ Direct clock/calendar ~ Time of day in seconds, minutes, The CMOS bq3287/bq3287 A is a
replacement for IBM® and hours low-power microprocessor peripheral
AT-compatible computers and - 12- or 24-hour format providing a time-of-day clock and
other applications 100-year calendar with alarm fea-
- Optional daylight saving tures and battery operation. Other
~ Pin-compatible with the adjustment features include three maskable
DS1287IDS1287A and interrupt sources, square wave out-
MC1468l8A ~ BCD or binary format for clock
put, and 50 bytes of general non-
and calendar data
~ Integral lithium cell and crystal volatile storage. The bq3287A ver-
~ Programmable square wave sion is identical to the bq3287, with
~ 160 ns cycle time allows fast bus output the addition of the RAM clear input.
operation
~ Three individually maskable The bq3287 write-protects the clock,
~ Selectable Intel or Motorola bus interrupt event flags: calendar, and storage registers
timing during power failure. The integral
- Periodic rates from 122 ~s to backup energy source then main-

-
~ 14 bytes for clock/calendar and 500ms tains data and operates the clock
control and calendar.
- Time-of-day alarm once per
~ 50 bytes of general nonvolatile second to once per day
The bq3287 is a fully compatible
storage - End-of-clock update cycle real-time clock for IBM AT-
~ Calendar in days, day ofthe compatible computers and other
~ Better than one minute per
week, months, and years with applications.
month clock accuracy
automatic leap-year adjustment As shipped from Benchmarq, the
backup cell is electrically isolated
from the memory. Following the first
application of Vee, this isolation is
broken, and the backup cell provides
data retention on subsequent power-
Pin Connections Pin Names downs.
ADo-AD7 Multiplexed address/data
input/output
I CJ MOT Bus type select input
MOT c:
1 24
~ Vee

~
2 23 SQW CS Chip select input
NC 3 22 . NC AS Address strobe input
NC
ADo 4 21 b NC/RCL
DS Data strobe input
AD 1 5 20 fJ NC
AD2 . 6 19 o INT R/W Read/write input
~
:g,~
7 18 RST
8 17 OS INT Interrupt request output
4
ADs 9 16 P NC RST Reset input
ADs 10 15 J R/W
SQW Square wave output
AD7 11 14 bAS
Vss~2 l~JJ CS RCL RAM clear input (bq3287 A
only)
PN-14 NC No connect
Vee +5V supply
Vss Ground
Sept. 1990 1/17

5-19
bq3287Ibq3287A Preliminary

Block Diagram

---'-- Time-
D
-,--
Base
OscIlator
f8 f--o-- f64 f--~ f64 r-

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

-
RST

MO~
n r-
ControilStatus
Reglstars
l
16 01 MUX

f----t saw
Generator saw

aJ'=:'j
CS_- - - - I I I
~
liP
R/W----I
/L-- Clock Alarm and
AS~ Bus Calendar Bytaa Interrupt
'I[- Generator
AD O-AD 7 ~ -
INT
< IIF Uaer Buffer
~
----I
v
~
114 Bytas)
------------ .
Storage
~ Raglsters CIock/Calendar
-
RCL 160 Byte,) ~ VI Update

cs
VCC
SV ~--=----. Power- -VOUT
UTHIU~ Fall
CELL -=r:::.... Control f--
WRITE-
- PROTECT
80-6

Pin Descriptions ADo-AD7 Multiplexed address/data input/output

MOT Bus type select input The bq3287 bus cycle consists of two phases:
the address phase and the data-transfer
MOT selects bus timing for either Motorola phase. The address phase precedes the
or Intel architecture. This pin should be data-transfer phase. During the address
tied to Vee for Motorola timing or to Vss for phase, address placed on ADo-AD7 is
Intel timing (see Table 1). The setting latched into the bq3287 on the falling edge
should not be changed during system opera- of the AS signal. During the data-transfer
tion. MOT is internally pulled low by a 20K phase of the bus cycle, the ADo-AD7 pins
ohm resistor. act as a bidirectional data bus.
AS Address strobe input
Table 1. Bus Setup AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
Bus MOT os R/W AS dress on ADo-·AD7. This demultiplexing
Type Level Equivalent Equivalent Equivalent process is independent of the CS signal.

Motorola Vee DS, E,or RIW AS

<ll2
Intel Vss _ RD, WR, ALE
MEMR, MEMW,
orIlOR orIlOW
2/17 Sept. 1990

5-20
 Preliminary bq3287/bq3287 A

DS Data strobe input SQW Square wave output

When MOT = Vee, DS controls data trans- SQW may output a programmable fre-
fer during a bq3287 bus cycle. During a quency square wave signal during normal
read cycle, the bq3287 drives the bus after (Vee valid) system operation. Anyone of
the rising edge on DS. During a write cycle, the 13 specific frequencies may be selected
the falling edge on DS is used to latch write through register A. This pin is held low
data into the chip. when the square wave enable bit (SQE) in
register B is 0 (see the Control/Status
When MOT = Vss, the DS input is provided Registers section).
a signal similar to RD, MEMR, or IIOR in
an Intel-based system. The falling edge on RAM clear input (bq3287A only)
DS is used to enable the outputs during a
read cycle. A low level on the RCL pin causes the con-
tents of each of the 50 storage bytes to be
Read/write input set to FF(hex). The contents of the clock
and control registers are unaffected. This
When MOT = Vee, the level on RIW iden- pin should be used as a user-interface input
tifies the direction of data transfer. A high (pushbutton to ground) and not connected to
level on RlWR indicates a read bus cycle, the output of any active component. RCL is
whereas a low on this pin indicates a write recognized when held low for at least 100
bus cycle. ms in the presence of Vee when the oscil-
lator is running. Using RAM clear does not
When MOT = Vss, RIW is provided a signal affect the battery load. This pin is a no con-
similar to WR, MEMW, or IIOW in an Intel-
based system. The rising edge on RIW
latches data into the bq3287.
nect on the bq3287.
Reset input
III
Chip select input The bq3287 is reset when RST is pulled low.
When reset, INT becomes high-impedance,
CS should be driven low and held stable and the bq3287 is not accessible. Table 4 in
during the data-transfer phase of a bus the Control/Status Registers section lists
cycle accessing the bq3287. the register bits that are cleared by a reset.
Interrupt request output Reset may be disabled by connecting RST to
INT is an open-drain output. INT is Vee. This allows the control bits to retain
asserted low when any event flag is set and their states through power-down/power-up
the corresponding event enable bit is also cycles.
set. INT becomes high-impedance whenever
register C is read (see the Control/Status
Registers section).

Sept. 1990 3/17

5-21
bq3287/bq3287 A Preliminary

Functional Description locations during the update cycle at the end of each
update period (see Figure 2). The alarm flag bit may
The bq3287 A differs from the bq3287 only by the also be set during the update cycle.
presence of RCL on pin 21. Otherwise, the two devices
are identical. The bq3287 copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in
Address Map register B, the user copy of the clock and calendar bytes
The bq3287 provides 14 bytes of clock and control/status is frozen, while the local copy of the same bytes con-
registers and 50 bytes of general nonvolatile storage. tinues to be updated every second.
Figure 1 illustrates the address map for the bq3287. The update-in-progress bit (DIP) in register A is set tBUC
time before the beginning of an update cycle (see Figure
Update Period 2). This bit is cleared and the update-complete flag (UF)
is set at the end of the update cycle.
The update period for the bq3287 is one second. The
bq3287 updates the contents of the clock and calendar

I 14
0
Clock and
COntrol Statu.
00 0

1
Seconds

Seooncte Alarm
00

01
Byla. Registers
13 00 2 Minutes 02

14 OE 3 Minutes Alarm 03

4 Hours 04
SCD
S Hours Alarm OS 0'
Bin.y
Format
e Day 01 Weak OS

7 Date of Month 07
50 Storags
Bytes Rsgiat.,.. 8 M_ OB

9 Vee' 09

1
10 Register It. Olt.

n Register S OB

12 Register C OC

SF 13 Register D 00

_-3

Figure 1. Address Map

~r------- Update Period

(1 sec)
--------.1-1
UIP
____~Il~__________________~Il~_______
~ I--- t UC (Update Cycle)
tauc ~ I---
UIP-1

Figure 2. Update Period Timing and UIP

4/17 Sept. 1990

5-22
 Preliminary bq3287/bq3287 A

Programming the RTC c. Write the appropriate value to the hour

format bit (HR).
The time-of-day, alarm, and calendar bytes can be
written in either the BCD or binary format (see Table 2). 2. Write new values to all the time, alarm, and
calendar locations.
3. Clear the UTI bit to allow update transfers.
These steps may be followed to program the time, alarm,
and calendar: On the next update cycle, the RTC updates all 10 bytes
in the selected format.
1. Modify the contents of register B:
a. Write a 1 to the UTI bit to prevent transfers
between RTC bytes and user buffer.
b. Write the appropriate value to the data
format bit (DF) to select BCD or binary
format for all clock and calendar bytes.

Table 2. Time, Alarm, and Calendar Formats

Range
III
Address RTC Bytes Binary-Coded
Decimal Binary Decimal

0 Seconds 0-59 00H-3BH 00H-59H

1 Seconds alarm 0-59 00H-3BH 00H-59H

2 Minutes 0-59 00H-3BH 00H-59H

3 Minutes alarm 0-59 00H-3BH 00H-59H

Hours, 12-hour format 1-12 OlH-OCHAM; OlH-12HAM;

4 8lH-8CHPM 8lH-92HPM

Hours, 24-hour format 0-23 00H-17H 00H-23H

Hours alarm, 12-hour format 1-12 OlH-OCHAM; OlH-12HAM;

5 8lH-8CHPM 8lH-92HPM

Hours alarm, 24-hour format 0-23 00H-17H 00H-23H

6 Day of week (1=Sunday) 1-7 OlH-07H OlH-07H

7 Day of month 1-31 01H-1FH OlH-3lH

8 Month 1-12 OlH-OCH OlH-12H

9 Year 0-99 00H-63H 00H-99H

Sept. 1990 5/17

5-23
bq3287/bq3287 A Preliminary

Square Wave Output • The update-ended interrupt, which occurs at the end
of an RTC update cycle
The bq3287 divides the 32.768 KHz oscillator frequency
to produce the 1 Hz update frequency for the clock and Each of the three interrupt events is enabled by an in-
calendar. Thirteen taps from the frequency divider are dividual interrupt-enable bit in register B. When an
fed to a 16:1 multiplexer circuit. The output of this mux event occurs, its event flag bit in register C is set. If the
is fed to the SQW output and periodic interrupt genera- corresponding event enable bit is also set, then an inter-
tion circuitry. The four least-significant bits of register rupt request is generated. The interrupt request flag bit
A, RSO-RS3, select among the 13 taps (see Table 3). The (INTF) of register C is set with every interrupt request.
square wave output is enabled by writing a 1 to the Reading register C clears all flag bits, including INTF,
square wave enable bit (SQE) in register B. and makes INT high-impedance.
Two methods can be used to process bq3287 interrupt
Interrupts events:
The bq3287 allows three individually selected interrupt • Enable interrupt events and use the interrupt
events to generate an interrupt request. These three request output to invoke an interrupt service routine.
interrupt events are:
• Do not enable the interrupts and use a polling
• The periodic interrupt, programmable to occur once routine to periodically check the status of the flag
every 122 ~s to 500 ms bits.
• The alarm interrupt, programmable to occur once per The individual interrupt sources are described in detail
second to once per day in the following sections.

Table 3. Square Wave Frequency/Periodic Interrupt Rate

Register A Bits Square Wave Periodic Interrupt

RS3 RS2 RS1 RSO Frequency Units Period Units

0 0 0 0 None None
0 0 0 1 256 Hz 3.90625 ms
0 0 1 0 128 Hz 7.8125 ms
0 0 1 1 8.192 KHz 122.070 ~s

0 1 0 0 4.096 KHz 244.141 ~s

0 1 0 1 2.048 KHz 488.281 ~s

0 1 1 0 1.024 KHz 976.5625 ~s

0 1 1 1 512 Hz 1.953125 ms
1 0 0 0 256 Hz 3.90625 ms
1 0 0 1 128 Hz 7.8125 ms
1 0 1 0 64 Hz 15.625 ms
1 0 1 1 32 Hz 31.25 ms
1 1 0 0 16 Hz 62.5 ms
1 1 0 1 8 Hz 125 ms
1 1 1 0 4 Hz 250 ms
1 1 1 1 2 Hz 500 ms

6/17 Sept. 1990

5-24
 Preliminary bq3287/bq3287 A

Periodic Interrupt Update Cycle Interrupt

The mux output used to drive the SQW output also The update cycle ended flag bit (UF) in register C is set
drives the interrupt-generation circuitry. If the periodic to a 1 at the end of an update cycle. If the update inter-
interrupt event is enabled by writing a 1 to the periodic rupt enable bit (DIE) of register B is 1, and the update
interrupt enable bit (PIE) in register C, an interrupt transfer inhibit bit (UTI) in register B is 0, then an
request is generated once every 12211s to 500ms. The interrupt request is generated at the end of each update
period between interrupts is selected by the same bits in cycle.
register A that select the square wave frequency (see
Table 3). Accessing RTC bytes
Alarm Interrupt Time and calendar readings may be in error. Three
methods to access the RTC bytes without ambiguity are
During each update cycle, the RTC compares the hours, available:
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm • Enable the update interrupt event to generate
interrupt event flag bit, AF in register C, is set to 1. If interrupt requests at the end of the update cycle.
the alarm event is enabled, an interrupt request is The interrupt handler has a maximum of 999ms to
generated. access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a "don't care" state. An alarm byte is set to a • Poll the update-in-progress bit (UIP) in register A. If
"don't care" state by writing a 1 to each of its two most- UIP = 0, the polling routine has a minimum oftBuc
significant bits. A "don't care" state may be used to time to access the clock bytes (see Figure 3).
select the frequency of alarm interrupt events as follows:
• Use the periodic interrupt event to generate _
• If none ofthe three alarm bytes is "don't care," the interrupt requests every tPI time, such that UIP = 1
frequency is once per day, when hours, minutes, and always occurs between the periodic interrupts. The
seconds match. interrupt handler will finish accessing the clock bytes
in tpr/2 + tBUC time (see Figure 3).
• If only the hour alarm byte is "don't care," the
frequency is once per hour, when minutes and
seconds match. Oscillator Control
• If only the hour and minute alarm bytes are "don't The bq3287 is shipped from Benchmarq with its internal
care," the frequency is once per minute, when oscillator turned off. The internal oscillator and fre-
seconds match. quency divider are turned on by writing a 010 pattern to
bits 4 through 6 of register A. A pattern of llX turns the
• Ifthe hour, minute, and second alarm bytes are oscillator on, but keeps the frequency divider disabled.
"don't care," the frequency is once per second. Any other pattern to these bits keeps the oscillator off.

1 0-.------- 1 sec ----------.!'I

UIP ____~r_l~____________~r_l~____
I J ~tuc
tBUC~ l-
PF

UF ______.__~Ilffi~~____________~Ilffi~~_
UIP-2

Figure 3. Update-Ended/Periodic Interrupt Relationship

Sept. 1990 7/17

5-25
bq3287Ibq3287A Preliminary

Power-Down/Power-Up Cycle RSO-RS3 - Frequency Select

The bq3287 continuously monitors Vee for out-of- 6 5 4 2

tolerance. During a power failure, when Vee falls below
RS2
VPFD (4.37V typical), the bq3287 write-protects the clock
and storage registers. When Vee is below Vso (3V typi-
cal), the power source is switched to the internal lithium These bits select one of the 13 frequencies for the SQW
cell. RTC operation and storage data are sustained by a output and the periodic interrupt rate, as shown in Table 3.
valid backup energy source. When Vee is above Vso, the
power source is Vee. Write-protection continues for tcSR OSO-OS2 - Oscillator Control
time after Vee rises above VPFD.

Control/Status Registers
The four control/status registers of the bq3287 are acces-
sible regardless of the status of the update cycle (see These three bits control the state of the oscillator and
Table 4). divider stages. A pattern of 010 enables RTC operation
by turning on the oscillator and enabling the frequency
Register A divider. A pattern of llX turns the oscillator on, but
keeps the frequency divider disabled. The bq3287 is
Reaister A Bits shipped from Benchmarq with its oscillator turned off.
When 010 is written, the RTC begins its first update
7 I 6 I 5 I 4 I 3 I 2 I 1~ after 500ms.
VIP I OS2 I OSl I OSO I RS3 I RS2 I RS1 I RSO-
UIP - Update Cycle Status
Register A programs:
• The frequency of the square wave and the periodic
event rate.
• Oscillator operation. This read-only bit is set prior to the update cycle. When
Register A provides: UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
• Status of the update cycle. is also cleared when the update transfer inhibit (UTI) bit
in register B is 1.

Table 4. Control/Status Registers

Loc. Bit Name and State on Reset

Reg. (Hex) Read Write ~-

7 (MSB) 6 5 4 3 2 1 o (LSB)
A OA Yes Yes! VIP na OS2 na OSl na OSO na RS3 na RS2 na RS1 na RSO na
--
B OB Yes Yes UTI na PIE 0 AlE 0 VIE 0 SQWE
c_
0 DF na HF na DSE na
----
C OC Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - 0 - 0 - 0
D OC Yes No VRT na - 0 - 0 - 0 - 0 - 0 - 0 - 0

Notes: na = not affected.

1. Except bit 7.

8/17 Sept. 1990

5-26
 Preliminary bq3287/bq3287 A

Register B SQWE - Square Wave Enable

716151413121110
Reaister B Bits
L-7_-,--_~f_~_L--_4--,-1=::>c.:..3
SQWE :..=.J1L--2_-,-_1_-,--_0--,
UTI I PIE I AlE I DIE I SQWE I DF_~JI~~P~~
This bit enables the square wave output:
Register B enables:
1 = Enabled
• Update cycle transfer operation
o = Disabled and held low
• Square wave output
UIE - Update Cycle Interrupt Enable
• Interrupt events
• Daylight saving adjustment
Register B selects:
• Clock and calendar data formats
This bit enables an interrupt request due to an update
All bits of register B are read/write. ended interrupt event:
DSE - Daylight Saving Enable 1 = Enabled
0= Disabled

FEI 6 5 4 3 2 1
The UIE bit is automatically cleared when the UTI bit
equals 1.

This bit enables daylight-saving time adjustments when AlE - Alarm Interrupt Enable
written to 1:
• On the last Sunday in October, the first time the 7 6 4 3 2 1 o
bq3285 increments past 1:59:59 AM, the time falls
back to 1:00:00 AM.
• On the first Sunday in April, the time springs This bit enables an interrupt request due to an alarm
forward from 2:00:00 AM to 3:00:00 AM. interrupt event:
1 = Enabled
HF - Hour Format
0= Disabled
7 6 5 4 3 2 1
HF l!l PIE - Periodic Interrupt Enable

7 5 4 3 2 1 o
This bit selects the time-of-day and alarm hour format:
1 = 24-hour format
o = 12-hour format This bit enables an interrupt request due to a periodic
interrupt event:
DF - Data Format 1 = Enabled
7 6 5 4 3 2 0= Disabled
DF

This bit selects the numeric format in which the time,

alarm, and calendar bytes are represented:
1 = Binary
O=BCD
Sept. 1990 9/17

5-27
bq3287Ibq3287A Preliminary

UTI - Update Transfer Inhibit PF - Periodic Event Flag

~I_u~~_I+I~6~~5~+-~4~~~3__~2~+-~1~~0~1 ~I_7~+I_p~~~~1_5~+-~4~~~3__~~2-+~1~~0~

This bit inhibits the transfer of RTC bytes to the user This bit is set to a 1 every tPI time, where tPI is the time
buffer: period selected by the settings of RSO-RS3 in register A.
Reading register C clears this bit.
1 = Inhibits transfer and clears UIE
o = Allows transfer INTF - Interrupt Request Flag

Register C
This flag is set to a 1 when any of the following is true:
Reaister C Bits AIE = 1 and AF = 1
7 1 6 1 5 1 4 1 3 1 2 1 1 1 0
PIE = 1 and PF = 1
INTFI PF I AF I UF I 0 I 0 I 0 I 0
VIE = 1 and UF = 1
Register C is the read-only event status register.
Reading register C clears this bit.
Bits 0-3 - Unused Bits
Register D
,----------------------------------------,
Reaister D Bits
7 1 6151413121110
These bits are always set to O. VRT I 0101010101010

UF - Update-Event Flag Register D is the read-only data integrity status register.

These bits are always set to O.

AF - Alarm Event Flag

~~7~--6~+I-A~~--rl~4~ ~3 r-=2~ 1~+-~0~11~_vR~R:_~~I_a_Ii:~R+A_M~:~n_drT_i~~_e~~3 r-=2~ 1~+-~0~

__ __ __ __ __

This bit is set to a 1 when an alarm event occurs. Read-

ing register C clears this bit. 1 = Valid backup energy source
o =Backup energy source is depleted
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.

10/17 Sept. 1990

5-28
 Preliminary bq3287/bq3287A

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions
Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V
VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT S; Vee + 0.3
relative to Vss
TOPR Operating temperature o to +70 °C

TSTG Storage temperature -40 to +70 °C

TRIAS Temperature under bias -10 to +70 °C

TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70°C)

Symbol Parameter Minimum Typical Maximum Unit
Vee Supply voltage 4.5 5.0 5.5 V
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIH Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25°.

DC Electrical Characteristics (TA =0 to 70°C, VCC =5V ± 10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes
ILl Input leakage current - - ±1 !!A VIN = Vss to Vee
ILO Output leakage current - - ±1 !!A ADo-AD7, INT and SQW
in high impedance
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA
VOL Output low voltage - - 0.4 V IOL = 4.0 rnA
Icc Operating supply current - 7 15 rnA Min. cycle, duty = 100%,
IOH = OrnA, IOL = OrnA
Vso Supply switch-over voltage - 3.0 - V
VPFD Power-fail-detect voltage 4.30 4.37 4.45 V
IReL Input current when RCL = Vss - - 550 !!A Internal 20K pull-up
(bq3287A only)
IMOTH Input current when MOT = Vee - - -550 !!A Internal20K pull-down

Note: Typical values indicate operation at TA = 25°C, Vee = 5V.

Sept. 1990 11/17

5-29
bq3287/bq3287A Preliminary

Capacitance (TA =2S"C, F =1 MHz, VCC = S.oV)

Symbol Parameter Minimum Typical Maximum Unit Conditions
CIIO Input/output capacitance - - 7 pF Vom = OV
CIN Input capacitance - - 5 pF VIN=OV
Note: This parameter is sampled and not 100% tested.

AC Test Conditions
Parameter Test Conditions
Input pulse levels o to3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 4 and 5

+5V

9600 1.15Ko
For all outputs
except INT
>
o-----~------~
INT 0 - - - - - - - 1

5100 50pF

OL-10 OL-11

Figure 4. Output Load A Figure 5. Output Load B

12117 Sept. 1990

5-30
 Preliminary bq3287Ibq3287 A

Read/Write Timing (TA =0 to 70 e, vee =5V ± 10%)

o

Symbol Parameter Minimum Typical Maximum Unit

tCYC Cycle time 160 - - ns

tDSL DS low or RDIWR high time 80 - - ns
tDSH DS high or RDIWR low time 55 - - ns
tRWH RIW hold time 0 - - ns
tRWS RIW setup time 10 - - ns
tcs Chip select setup time 5 - - ns
tCH Chip select hold time 0 - - ns
tDHR Read data hold time 0 - 25 ns
tDHW Write data hold time 0 - - ns
tAS Address setup time 20 - - ns

-
tAR Address hold time 5 - - ns
tDAS Delay time, DS to AS rise 10 - - ns
tASW Pulse width, AS high 30 - - ns
tASD Delay time, AS to DS rise (RDIWR fall) 35 - - ns
tOD Output data delay time time from DS - - 35 ns
rise (RD fall)
tDW Write data setup time 30 - - ns

Sept. 1990 13117

5-31
bq3287/bq3287 A Preliminary

Motorola Bus Read/Write Timing

AS

OS

- - t - - - - t 4 - - - - t DSH ----oj

R/W

CS

RC-4

14/17 Sept. 1990

5·32
 Preliminary bq3287/bq3287A

Intel Bus Read Timing

~--------------tc~--------------

AS (ALE)

t ASD

DS (Ao)

tOSL --1----_.
.1---- t OSH

R/W (WR)

tes tCH

CS

tAH
tAS tDHR

AD o -AD 7
III
RC-5

Intel Bus Write Timing

10--------------- t eye
AS (ALE)

DS (RD)

R/W (WR)

tes +----------oi

CS

tOHW

WC-5

Sept. 1990 15/17

5-33
bq3287Ibq3287A Preliminary

Power-Down/Power-Up Timing
Symbol Parameter Minimum Typical Maximum Unit Conditions

tF Vee slew from 4.5V to OV 300 - - J.1s

tR Vee slew from OV to 4.5V 100 - - J.1s
tesR CS at Vrn after power-up 20 - 200 ms Internal write-protection
period after Vee passes VPFD
on power-up.
tDR Data-retention and 10 - - years TA = 25°C
timekeeping time be-
tween charges

Note: Clock accuracy is better than ± 1 minute per month at 25°C for the period oftDR.
Caution: Negative undershoots below the absolute maximum rating of ·O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

Vee

CS

PD-4

16/17 Sept. 1990

5-34
 Preliminary bq3287/bq3287 A

Interrupt Delay Timing

Symbol Parameter Minimum Typical Maximum Unit

tRSW Reset pulse width 5 - - Ils

tIRR INT release from RST - - 2 Ils
tIRD INT release from DS - - 2 Ils

Interrupt Delay Timing

RO/WR (Intel) r-----------~,~/---------------------------

OS (Mot) '-----------~,~/~--------------------------
t R8w

RST

INT
-
INT-1

Ordering Information

bq3287 MT

I L Package Option:
MT =T-type module

RAM Clear Option:

A = RAM clear on pin 21
no mark = No connect on pin 21

-Device:
bq3287 Real-Time Clock Module

Sept. 1990 17/17

5-35
Notes

5-36
 Advance Information bq3385
Real-lime Clock (ATC) With 4Kx8 RAM
Features General Description
~ Direct clock/calendar ~ Time of day in seconds, minutes, The CMOS bq3385 is a low-power
replacement for IBM® and hours microprocessor peripheral providing
AT-compatible computers and - 12- or 24-hour format a time-of-day clock and 100-year
other applications calendar with alarm features and
- Optional daylight saving battery operation. Other features of
~ 160 ns cycle time allows fast bus adjustment the bq3385 include three maskable
operation interrupt sources, square wave out-
~ BCD or binary format for clock
~ Less than 1.0 ~ load under put, 50 bytes of general nonvolatile
and calendar data
battery operation storage, and an additional 4K x 8 of
~ Three individually maskable user-programmable nonvolatile
~ 14 bytes for clock/calendar and interrupt event flags: SRAM.
control
- Periodic rates from 122 Ils to The bq3385 write-protects the clock,
~ 50 bytes of general nonvolatile 500ms calendar, storage registers, and
storage RAM during power failure. An ex-
- Time-of-day alarm once per
second to once per day ternal backup battery then main-
~ Additional 4K x 8 nonvolatile tains data and operates the clock
SRAM, accessed using RAM - End-of-clock update cycle and calendar.

~
control pins
Programmable square wave
~ 24-pin plastic DIP or SOIC and
28-pinPLCC
The bq3385 is a fully compatible
real-time clock for IBM AT-
III
output compatible computers and other
~ Calendar in days, day of the applications. The only external com-
week, months, and years, with ponents are a 32.768 KHz crystal
automatic leap-year adjustment and a backup battery.

Pin Connections Pin Names

24-Pin DIP or SOIC 28-Pin PLCC ADo-AD? ~ul~lexed address/data
mpu output
CS RTC chip select input
ALE RTC address strobe input
OER Vee ]a: ();: I~
X1 saw ",~WO()OI/) RD RTC read enable input
xxOZ>1/) <
X2 ASRO WE RTC write enable input
... '" N .,... re ~ CD
ADo ASR1 0 '" INT Interrupt request output
AD 1 BC ADo ASR1 SQW Square wave output
AD2 AD1 BC
INT AD2 BC Backup cell input
INT
AD3 WER AD3 WER Xl,X2 Crystal inputs
AD4 RD AD4 RD
NC OER RAM output enable
AD5 AD5 NC
ADs WE NC WE WER RAM write enable
AD7 ALE $l! ~ ::t ~ ~ t:: \!! ASRO-ASRI RAM address strobe
VSS CS '" 0 ... ~ II/) W 0 NC No connect
~z~>0Ci!z
PL-4 Vee +5V supply
PN-15 Vss Ground

Sept. 1990 112

5-37
bq3385

Block Diagram

RO
1 J SOW
WE INT
ALE RTC
CS
(84 BYTES)
lcs
\== v T
VOUT

7
~ Power-
L-LATCH To Latches Fal ~
And Control
~ O~ SRAM
00 AO WRITE- ~ BC
r 07 PROTECT
- CK
07 A7

H-LATCH
4Kx8 SRAM

~ 00 00 ;L-
00 A8
r o~ 07
03 A11
ASR1 CK
OER OE
WER WE

~
-
CE

PROTECT BO-26

212 Sept. 1990

5-38
~ BENOIMARQ Advance Information bq3387
Real-lime Clock Module With 4Kx8 RAM
Features General Description
~ Direct clock/calendar ~ Time of day in seconds, minutes, The CMOS bq3387 is a low-power
replacement for IBM® and hours microprocessor peripheral providing
AT-compatible computers and - 12- or 24-hour format a time-of-day clock and 100-year
other applications calendar with alarm features and in-
- Optional daylight saving tegrated battery operation. Other
~ 160 ns cycle time allows fast bus adjustment features of the bq3387 include three
operation maskable interrupt sources, square
~ BCD or binary format for clock
~ 14 bytes for clock/calendar and wave output, 50 bytes of general
and calendar data
control nonvolatile storage, and an addition-
~ Better than one minute per al 4K x 8 of user-programmable non-
~ 50 bytes of general nonvolatile month clock accuracy volatile SRAM.
storage
~ Programmable square wave The bq3387 write-protects the clock,
~ Additional 4K x 8 nonvolatile output calendar, storage registers, and
SRAM, accessed using RAM RAM during power failure. An in-
control pins ~ Three individually maskable ternal lithium backup battery then

-
interrupt event flags maintains data and operates the
~ Integral lithium cell and crystal clock and calendar.
~ 24-pin plastic clock module
~ Calendar in days, day of the The bq3387 is a fully compatible
week, months, and years, with real-time clock for IBM AT-
automatic leap-year adjustment compatible computers and other
applications.
As shipped from Benchmarq, the
backup cell is electrically isolated
Pin Connections Pin Names from the memory. Following the first
application of Vee, this isolation is
ADo-AD? Multiplexed address/data broken, and the backup cell provides
input/output data retention on subsequent power-
CS RTC chip select input downs.
ALE RTC address strobe input
OER 1 24 Vee
2 23 saw RD RTC read enable input
NC
NC 3 22 ASRO WE RTC write enable input
ADo 4 21 ASR1 INT Interrupt request output
AD 1 5 20 NC
AD2 6 19 INT SQW Square wave output
AD3 7 18 WER OER RAM output enable
AD4 8 17 RD
WER RAM write enable
ADs 9 16 NC
ADs 10 15 WE ASRO- RAM address strobe
AD7 11 14 ALE ASRI
Vss 12 13 CS NC No connect
Vee +5V supply
PN-16
Vss Ground

Sept.1990 112

5-39
bq3387

Block Diagram

rD~ SOW
INT
RTC

A ~
(64 BYTES)
lcs
Y-
7
0
-y
T
VOUT

~ Power-
L-LATCH To Latche. FaU ~
And Control
~ DO SRAM
Lithium
00 AO WRITE- ~elI
v 07 PROTECT
ASRO - CK
07 A7 .- l
-
H-LATCH
RAM·4Kx8
DO
~
DO
00 AS
IJI--
v 07 I~
07
03 A11
CK
OE
WE

~
PROTECT
CE

80-26

212 Sept. 1990

5·40
~ 8EN0tMARQ _ _ _ _ _A_dv,_an_c_e_'n_fo_rm_a_tio_n_b_q--.;;;...3_4_B_5_
Real-lime Clock (RTC) With 8Kx8 RAM
Features General Description
~ Direct clock/calendar ~ Calendar in days, day of the The CMOS bq3485 is a low-power
replacement for IB~ week, months, and years, with microprocessor peripheral providing
AT-compatible computers and automatic leap-year adjustment a time-of-day clock and 100-year
other applications calendar with alarm features and
~ Time of day in seconds, minutes, battery operation. Other features of
~ Density upgrade of the bq3385R and hours the bq3485 include three maskable
~ 160 ns cycle time allows fast bus - 12- or 24-hour format interrupt sources, square wave out-
operation put, 50 bytes of general nonvolatile
- Optional daylight saving
storage, and an additional 8K x 8 of
adjustment
~ Less than 1.0 IJA load under user-programmable nonvolatile
battery operation ~ BCD or binary format for clock SRAM.
and calendar data
~ 14 bytes for clock/calendar and The bq3485 write-protects the clock,
control ~ Three individually maskable calendar, storage registers, and
interrupt event flags: RAM during power failure. A back-
~ 50 bytes of general nonvolatile up battery then maintains data and
storage - Periodic rates from 122 !J.s to operates the clock and calendar.
500ms
~ Additional 8K x 8 nonvolatile
- Time-of-day alarm once per
The bq3485 is a fully compatible ~
SRAM, accessed using RAM real-time clock for IBM AT- ...-
control pins second to once per day
compatible computers and other
~ 3 volt battery-backup input - End-of-clock update cycle applications. The only external com-
ponents are a 32.768 KHz crystal
~ 24-pin plastic DIP or SOIC and
~ Programmable square wave and a backup battery.
output 28-pinPLCC

Pin Connections Pin Names

24-Pin DIP or SOIC 28-Pin PLCC ADo-AD? ~ult%lexed address/data
mput output
CS RTC chip select input
ALE RTC address strobe input
OER
X1
Vee
saw ",~wt.) UJ
XXOZ>UJ c(
III: 000~1~ RD
WE
RTC read enable input
RTC write enable input
X2 ASRO
ADo ASR1 ... '" N .... CO"""

'" '" '"

U)

INT Interrupt request output

ADo 0 ASR1
AD 1 BC SQW Square wave output
ADI BC
AD2 INT AD2 BC Backup cell input
INT
AD3 WER AD3 WER Xl,X2 Crystal inputs
AD4 RD AD4 RD
AD5 NC OER RAM output enable
AD5 NC
ADs WE NC WE WER RAM write enable
~ ~ :!: ~ ~ t:: $1
AD7 ALE ASlill- RAM address strobe
ASRI
VSS CS ~~
c(
c ~ I~ <~ ~
c(> NC No connect
PL-4
PN-15 Vee +5V supply
Vss Ground

Sept.1990 112

5-41
bq3485

Block Diagram

l t SOW
INT
RTC

lee
r-
A ~

r ,.
(84 BYTES)
VOUT
7
l Power-
Fal It--
L-LATCH To Latche8
And Control
SRAM
~ O~
BC
QO AO WRITE- It--
r 07 PROTECT
Q7 A7
- CK

H-LATCH
8Kx8 SRAM
DO
~ DO
qo A8
Vt-
r o~ 07 I ~
04 A12
ASR1 CK
OER oe
WER WE

~
PROTECT
CE

80-24

2J2 Sept. 1990

5-42
~ BENCHMARQ Advance Information bq3487
Real-lime Clock Module With 8Kx8 RAM
Features General Description
>- Direct clock/calendar >- Time of day in seconds, minutes, The CMOS bq3487 is a low-power
replacement for IBM® and hours microprocessor peripheral providing
AT-compatible computers and - 12- or 24-hour format a time-of-day clock and 100-year
other applications calendar with alarm features and in-
- Optional daylight saving tegrated battery operation. Other
>- Density upgrade of the bq3387 adjustment features of the bq3487 include three
>- maskable interrupt sources, square
160 ns cycle time allows fast bus >- BCD or binary format for clock
wave output, 50 bytes of general
operation and calendar data
nonvolatile storage, and an addition-
>- 14 bytes for clock/calendar and >- Better than one minute per al 8K x 8 of user-programmable non-
control month accuracy volatile SRAM.
>- 50 bytes of general nonvolatile >- Programmable square wave The bq3487 write-protects the clock,
storage output calendar, storage registers, and
RAM during power failure. An in-
>- Additional 8K x 8 nonvolatile >- Three individually maskable ternal backup battery then main-

•
SRAM, accessed using RAM interrupt event flags tains data and operates the clock
control pins and calendar.
>- 24-pin plastic clock module
>- Integral lithium cell and crystal The bq3487 is a fully compatible
>- Calendar in days, day of the real-time clock for IBM AT-
week, months, and years, with compatible computers and other
automatic leap-year adjustment applications.
As shipped from Benchmarq, the
backup cell is electrically isolated
from the memory. Following the first
application of Vee, this isolation is
Pin Connections Pin Names broken, and the backup cell provides
data retention on subsequent power-
ADo-AD? Multiplexed address/data downs.
input/output
CS RTC chip select input
OER Vee ALE RTC address strobe input
NC saw RD RTC read enable input
NC ASRO
ADo ASRl WE RTC write enable input
AD 1 NC INT Interrupt request output
AD2 INT
SQW Square wave output
ADs WER
AD4 RD OER RAM output enable
ADs NC
WER RAM write enable
ADs WE
AD7 ALE ASRO- RAM address strobe
ASRI
VSS CS
NC No connect
PN-16 Vee +5Vsupply
Vss Ground

Sep1.1990 112

5-43
bq3487

Block Diagram

~Dh SOW
INT
RTC

A ~ lcs
<;= v
(84 BYTES)
T
YOUT
07
L-LATCH

DO
l
To Latches
And
SRAM
Power-
Fal
Control - Lithium

v 07
00 AO WRITE-
PROTECT T'en
- CK
07 A7 l-
-
H-LATCH
8Kx8 SRAM
~ DO
DO
QO
fl-
A8
07 07
04 A12
ASR1 CK
OER OE
WER WE

~
PROTECT
CE

BO-27

212 Sept. 1990

5-44
Introduction 1

Processor Management 2

Energy Management 3

Static RAM Nonvolatile Controllers 4

Real-Time Clocks 5

Nonvolatile Static RAMs 6

Package Drawings "'l

Sales Offices and Distributors 8

ltl BENCHMARQ _ _ _ _b......::,q_40_1_0_/b----=q=---40_1_0_Y
8Kx8 Nonvolatile SRAM
General Description At this time the integral energy
Features source is switched on to sustain the
~ Data retention in the absence of The CMOS bq4010 is a nonvolatile memory until after Vcc returns
power 65,536-bit static RAM organized as valid.
8,192 words by 8 bits. The integral
~ Automatic write-protection The bq4010 uses an extremely low
control circuitry and lithium energy
during power-up/power-down source provide reliable nonvolatility standby current CMOS SRAM,
cycles coupled with the unlimited write coupled with a small lithium coin
cycles of standard SRAM. cell to provide nonvolatility without
~ Industry-standard 28-pin 8K x 8 long write cycle times and the write
pinout The control circuitry constantly cycle limitations associated with
~ Conventional SRAM operation; monitors the single 5V supply for an EEPROM.
unlimited write cycles out-of-tolerance condition. When
Vcc falls out of tolerance, the SRAM The bq4010 requires no external cir-
~ 10-year minimum data retention is unconditionally write-protected to cuitry and is socket-compatible with
in absence of power prevent inadvertent write operation. industry-standard SRAMs and most
EPROMs and EEPROMs.
~ Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

Ao-AI2 Address inputs

U DQo-DQ7 Data input/output

NC
A'2
Vee
WE ~ Ao -A'2

CE Chip enable input 8K x 8

A7 NC - SRAM
Block
Ae
A.
Ae
A. OE Output enable input ~ ~DQ7.
An
A,
Aa
A2
OE
A,o
WE Write enable input
Power r -
CE CON

A, CE Vee +5 volt supply input -

Power-
Ao
DO o
D0 7
DOe Vss Ground ~ Fail ~
Control
DO, DO.
D0 2 DO,
Vss DO a 1 Lithium
--I- Cell
- BO-40
PN-6

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4010 -85 85 -5% bq40lOY -85 85 -10%
bq4010 -150 150 -5% bq4010Y -150 150 -10%
bq4010 -200 200 -5% bq4010Y -200 200 -10%

Sept. 1990 119

6-1
bq401 O/bq401 OY

Functional Description As Vee falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4010 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4010 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4010 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4010Y
monitors for VPFD =4.37V typical for use in systems with The internal coin cell used by the bq4010 has an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cell is
become high impedance, and all inputs are treated as electrically isolated from the memory. (Self-discharge in
"don't care." If a valid access is in process at the time of this condition is approximately 0.5% per year.) Following
power-fail detection, the memory cycle continues to com- the first application of Vee, this isolation is broken, and
pletion. If the memory cycle fails to terminate within the lithium backup cell provides data retention on
time twPr, write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE 1/0 Operation Power
Not selected H X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DoUT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions
Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V
VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT:5 Vee + 0.3
relative to Vss
ToPR Operating temperature o to +70 ·C
TSTG Storage temperature -40 to +70 ·C

TBIAS Temperature under bias -10 to +70 ·C

TSOLDER Soldering temperature +260 ·C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

2/9 Sept. 1990

6-2
 bq401 O/bq401 OY

Recommended DC Operating Conditions (TA = 0 to 70·C)

Symbol Parameter Minimum Typical Maximum Unit Notes

4.5 5.0 5.5 V bq4010Y
Vee Supply voltage
4.75 5.0 5.5 V bq4010
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA = 0 to 70·C, VCCmin ~ VCC ~ VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±1 ~ VIN = Vss to Vee

Iw Output leakage current - - ±1 ~ CE = VIR or OE = VIR or
WE =VIL
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA

-
VOL Output low voltage - - 0.4 V IOL = 2.1 rnA
ISBl Standby supply current - 4 7 rnA CE =VIH
CE ~ Vee - 0.2V,
ISB2 Standby supply current - 2.5 4 rnA OV ~ VIN ~ 0.2V,
or VIN ~ Vee - 0.2V
lee Operating supply current - 65 75 rnA Min. cycle, duty = 100%,
CE = VIL, 1110 = OmA
4.55 4.62 4.75 V bq4010
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4010Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3V.

Capacitance (TA = 25·C, F = 1 MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CliO Input/output capacitance - - 10 pF Output voltage = OV

CIN Input capacitance - - 10 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept. 1990 3/9

6-3
bq401 O/bq401 OY

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVt03.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

o OUT o OUT
1K n 100pF 1Kn 5pF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70'C, VCCmin S; VCC S; VCCmax)

-85 -150 -200

Symbol Parameter Unit Conditions
Min. Max. Min. Max. Min. Max.
tRC Read cycle time 85 - 150 - 200 - ns
tAA Address access time - 85 - 150 - 200 ns Output load A
tACE Chip enable access time - 85 - 150 - 200 ns Output load A
toE Output enable to output valid - 45 - 70 - 90 ns Output load A
tcLZ Chip enable to output in low Z 5 - 10 - 10 - ns Output load B
toLZ Output enable to output in low Z 5 - 5 - 5 - ns Output load B
tCHZ Chip disable to output in high Z 0 40 0 60 0 70 ns Output load B
toHZ Output disable to output in high Z 0 30 0 50 0 70 ns Output load B
tOH Output hold from address change 10 - 10 - 10 - ns Output load A

4/9 Sept. 1990

6·4
 bq401 O/bq401 OV

Read Cycle No.1 (Address Access) 1,2

~---------tRC----------~

Address

1~-------------tAA------------~
/4-.-- - - - - t OH ----------.j

DOUT Previous Data Valid Data Valid

-----------------~

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

RC-2
III
Read Cycle No.3 (OE Access) 1,5

--->1<-- tAC
Address

OE
i tAA .1

~-- t OE - - - . - j
tOLZ

oOUT Hlgh-Z
Data Valid
Hlgh-Z
RC-3
Notes: 1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
Sept. 1990 5/9

6·5
bq401 O/bq401 OV

Write Cycle (TA = 0 to 70'C, VCCmln :5 VCC :5 VCCmax)

-85 -150 -200 Conditionsl

Symbol Parameter Units Notes
Min. Max. Min. Max. Min. Max.
twc Write cycle time 85 - 150 - 200 - ns
taw Chip enable to end of write 85 - 100 - 150 - ns (1)

tAW Address valid to end of write 75 - 90 - 150 - ns (1)

Measured from ad-

tAS Address setup time 0 - 0 - 0 - ns dress valid to begin-
ning of write. (2)
Measured from begin-
twp Write pulse width 75 - 90 - 130 - ns ning of write to end of
write. (1)
Write recovery time Measured from WE
tWRl (write cycle 1) 5 - 5 - 5 - ns going high to end of
write cycle. (3)
Write recovery time Measured from CE
tWR2 (write cycle 2) 15 - 15 - 15 - ns going high to end of
write cycle. (3)
Measured from first
tDW Data valid to end of write 35 - 50 - 70 - ns low-to-hi!fu.transition
of either CE or WE.
Data hold time Measured from WE
tDHl (write cycle 1) 0 - 0 - 0 - ns going high to end of
write cycle. (4)
Data hold time Measured from CE
tDH2 (write cycle 2) 10 - 10 - 10 - ns going high to end of
write cycle. (4)
twz Write enabled to output in 0 30 0 50 0 70 ns I/O pins are in output
highZ state. (5)
tow Output active from end of 5 - 5 - 5 - ns I/O pins are in output
write state. (5)

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin/i.!!!e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWRl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. !feE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-6
 bq401 O/bq401 OY

Write Cycle No.1 (WE-Controlled) 1,2,3

~----------------twe----------------~

Address

14-------------- tAW -------------tI<l--tWR1

~...._...............,..J~
14------------- tew ---------------.j ~..,.........,..........,..........,..---.,.____:.__'T
CE
1 + - - - - twp - - - - - . I
WE

1+---- tDW - - -___-

tow----j .
DOUT High-Z --K.X
. . . . .X~X"""'7'
WC-3

-
Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

Address

CE

1+----------twP---------------.j

WE
14---- tDW ---+1+---
------------~----------~
Data-in Valid

DOUT

WC-4
Notes: 1. CE or WE must be high during address transition.
2. Because 110 may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.
Sept.1990 7/9

6-7
bq401 O/bq401 OV

Power-Down/Power-Up Cycle (TA = 0 to 70'C)

Symbol Parameter Min. Typ. Max. Unit Conditions
tPF Vee slew, 4.75 to 4.25 V 300 - - Il S
tFS Vee slew, 4.25 to Vso 10 - - Ils
tpu Vee slew, Vso to VPFD (max.) 0 - - Ils
Time during which SRAM is
teER Chip enable recovery time 40 80 120 ms write-protected after Vee passes
VPFD on power-up.
tDR Data-retention time in 10 - - years TA = 25°C. (2)
absence of Vee
Delay after Vee slews down past
tWPT Write-protect time 40 100 150 Il s VPFD before SRAM is write-
protected.

Notes: Typical values indicate operation at TA = 25°C, Vee = 5V.

1.
2.
Battery is disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

Vee

CE

PD-B

8/9 Sept. 1990

 bq401 O/bq401 OV

Ordering Information
bq4010 MA-

L Speed Options:
85 = 85 ns
150 = 150 ns
200 = 200 ns

- Package Option:
MA = A-type module

Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

Device:
bq4010 8K x 8 NVSRAM

Sept. 1990 9/9

6-9
Notes

6-10
 ~ BENCHMARQ _ _ _ _b_q~4_0_11_/_bq__:;;..4_0_1_1_y
32Kx8 Nonvolatile SRAM
At this time the integral energy
Features General Description source is switched on to sustain the
.. Data retention in the absence of The CMOS bq4011 is a nonvolatile memory until after Vee returns
power 262,144-bit static RAM organized as valid.
32,768 words by 8 bits. The integral
.. Automatic write-protection control circuitry and lithium energy The bq4011 uses an extremely low
during power-up/power-down source provide reliable nonvolatility standby current CMOS SRAM,
cycles coupled with the unlimited write coupled with a small lithium coin
cycles of standard SRAM . cell to provide non volatility without
.. Industry-standard 28-pin 32K x
long write cycle times and the write
8 pinout The control circuitry constantly cycle limitations associated with
.. Conventional SRAM operation; monitors the single 5V supply for an EEPROM .
unlimited write cycles out-of-tolerance condition. When
Vee falls out of tolerance, the SRAM The bq4011 requires no external cir-
.. 10-year minimum data retention is unconditionally write-protected to cuitry and is socket-compatible with
in absence of power prevent inadvertent write operation. industry-standard SRAMs and most
EPROMs and EEPROMs .
.. Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

Ao-AI4 Address inputs
A'4 1 "'.J 28 Vee DQo-DQ7 Data input/output
A'2 2 27 WE OE
, Ao-A'4
A7 3 26 A'3 CE Chip enable input 32K X 8

------
SRAM
Aa 4 25 As WE., Block 000 -007
OE Output enable input
A5 5 24 Ag
A4 6 23 A" WE Write enable input
A3 7 22 OE Po werT TCE CON
A2 8 21 AlO Vee +5 volt supply input
A,
Ao
00 0
9
10
11
20
19
18
CE
00 7
DO a
Vss Ground
.
CE Power-
Fail
Control
Vee

DO, 12 17 00 5
00 2 13 16 , 004 _1 Lit hium
15 ! 1D0 3 T Cell
Vss
BO-4'

PN-7

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4011 -100 100 -5% bq401l Y -100 100 -10%
bq4011-150 150 -5% bq4011 Y -150 150 -10%
bq4011 -200 200 -5% bq4011 Y -200 200 -10%

Sept. 1990 1/9

6-11
bq4011 Ibq4011 V

Functional Description As Vee falls past VPFD and approaches 3Y, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4011 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4011 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4011 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4011Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cell used by the bq4011 has an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cell is
become high impedance, and all inputs are treated as electrically isolated from the memory. (Self-discharge in
"don't care." If a valid access is in process at the time of this condition is approximately 0.5% per year.) Following
power-fail detection, the memory cycle continues to com- the first application of Vee, this isolation is broken, and
pletion. If the memory cycle fails to terminate within the lithium backup cell provides data retention on
time twPr, write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE 1/0 Operation Power
Not selected H X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DOUT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions
Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V
VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT~Vee+0.3
relative to Vss
ToPR Operating temperature o to +70 'C
TSTG Storage temperature -40 to +70 'C
TBIAS Temperature under bias -10 to +70 'C
TSOLDER Soldering temperature +260 'C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods oftime may affect device reliability.

2!9 Sept. 1990

6-12
 bq4011/bq4011 V

Recommended DC Operating Conditions (TA = 0 to 70"C)

Symbol Parameter Minimum Typical Maximum Unit Notes
4.5 5.0 5.5 V bq4011Y
Vee Supply voltage
4.75 5.0 5.5 V bq4011
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIH Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA = 0 to 70"C, VCCmin ::;; VCC ::;; VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±1 J.I.A VIN = Vss to Vee
lLO Output leakage current - - ±1 J.I.A CE = VIH or OE = VIH or
WE =VIL
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA
VOL Output low voltage - - 0.4 V IOL = 2.1 rnA
ISB! Standby supply current - 4 7 rnA CE =VIH

ISB2 Standby supply current - 2.5 4 rnA

CE 2': Vee - 0.2V,
OV ::;; VIN ::;; 0.2V,
III
or VIN 2': Vee - 0.2V
lee Operating supply current - 55 75 rnA Min. cycle, duty = 100%,
CE = VIL, !rIO = OmA
4.55 4.62 4.75 V bq4011
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4011Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3Y.

Capacitance (TA = 25"C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions
CIIO Input/output capacitance - - 10 pF Output voltage = OV
CIN Input capacitance - - 10 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept. 1990 3/9

6-13
bq4011 Ibq4011 Y

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

J+SV

:> 1.9Ko 1.9Ko

Dour Dour o-----~----------~

1Ko SpF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (T A = 0 to 70'e, VeCmin ~ vee ~ VCemax)

·100 ·150 ·200

Symbol Parameter Unit Conditions
Min. Max. Min. Max. Min. Max.

tRC Read cycle time 100 - 150 - 200 - ns

tAA Address access time - 100 - 150 - 200 ns Output load A
tACE Chip enable access time - 100 - 150 - 200 ns Output load A
tOE Output enable to output valid - 50 - 70 - 90 ns Output load A
tCLZ Chip enable to output in low Z 5 - 10 - 10 - ns Output load B
tOLZ Output enable to output in low Z 5 - 5 - 5 - ns Output load B
tcHZ Chip disable to output in high Z 0 40 0 60 0 70 ns Output load B
tOHZ Output disable to output in high Z 0 35 0 50 0 70 ns Output load B
tOH Output hold from address change 10 - 10 - 10 - ns Output load A

4/9 Sept. 1990

6·14
 bq4011 Ibq4011 V

Read Cycle No.1 (Address Access) 1,2

~--------------------tRC--------------------~

Address

Dour
14-----1: -tAA--;t
~-----------toH----------l~
------p-r-e-vi-o-Us-D-at-a-V-a-I-id-----~XX --O-a-ta-V-a-lid---

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

°OUT

Read Cycle No.3 (OE Access) 1,5

RC-2

-
Address

OE
1 + - - - t OE --~

tOLZ

Dour Data Valid

High-Z High-Z

RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.

Sept. 1990 5/9

6-15
bq4011 Ibq4011 V

Write Cycle (TA = 0 to 70"C, VCCmin s VCC s VCCmax)

-100 -150 -200 Conditions/

Symbol Parameter Units Notes
Min. Max. Min. Max. Min. Max.
twc Write cycle time 100 - 150 - 200 - ns
tcw Chip enable to end of write 90 - 100 - 150 - ns (1)

tAW Address valid to end of write 80 - 90 - 150 - ns (1)

Measured from ad-

tAS Address setup time 0 - 0 - 0 - ns dress valid to begin-
ning of write. (2)
Measured from begin-
twp Write pulse width 75 - 90 - 130 - ns ning of write to end of
write. (1)
Write recovery time Measured from WE
tWRl (write cycle 1) 5 - 5 - 5 - ns going high to end of
write cycle. (3)
Write recovery time Measured from CE
tWR2 (write cycle 2) 15 - 15 - 15 - ns going high to end of
write cycle. (3)
Measured from first
tDW Data valid to end of write 40 - 50 - 70 - ns low-to-hilili.,transition
of either CE or WE.
Data hold time Measured from WE
tDHl (write cycle 1) 0 - 0 - 0 - ns going high to end of
write cycle. (4)
Data hold time Measured from CE
tDH2 (write cycle 2) 10 - 10 - 10 - ns going high to end of
write cycle.(4)
twz Write enabled to output in 0 35 0 50 0 70 ns 110 pins are in output
highZ state. (5)
tow Output active from end of 5 - 5 - 5 - ns VO pins are in output
write state. (5)

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWRl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-16
 bq4011 Ibq4011 V

Write Cycle No. 1 (WE-Controlled) 1,2,3

~-----------------twe----------------~

Address

~--------------- tAW --------------tj4--twR1

~~~~___. ~------------- tew ------------~ /"~~~_r__r~~~"'T
CE

~------twp------~
WE

1+-----tDW - - - - - . . -

DIN

t ow - ,
DOUT High-Z -K"<"'"XX....,...........,.X~

WC-3

-
Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

Address

----
t tAW
twe

---------------1:~I~-~R~-----
t AS ~.I~t--------- t ew ------------~-.
=t
CE

~------------twp------------·~

WE

~---tDW --+14---

------------~------------~
DIN Data-in Valid

DOUT

WC-4
Notes: 1. CE or WE must be high during address transition.
2. Because VO may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept.1990 7/9

6-17
bq4011/bq4011Y

Power-Down/Power-Up Cycle (TA =0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Conditions
tPF Vee slew, 4.75 to 4.25 V 300 - - /ls
-~

[----

tFS Vee slew, 4.25 to Vso 10 - - /ls

r--- ~~------------- [----------- -------- -----
tpu Vee slew, Vso to VPFD (max.)
".~-
0 - -
-"-----
/ls
Time during which SRAM
teER Chip enable recovery time 40 80 120 ms is write-protected after Vee
---_.
passes VPFD on power-up.
[--------- ~~----------- c---~~-- -----~- -~

tDR Data-retention time in 10 - - years TA= 25·C (2)

absence of Vee
---- "-------
Delay after Vee slews down
tWPT Write-protect time 40 100 150 /ls past VPFD before SRAM is
write-protected.

Notes: 1. Typical values indicate operation at TA = 25'C, Vee = 5V.

2. Battery is disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

4.75

Vee

ktpu
~
tFS
14------~ tOR ~ t eER

CE ======t=WPTxxxxxx XXX
PD-B

8/9 Sept 1990

6-18
 bq4011 Ibq4011 V

Ordering Information
bq4011 MA-
L Speed Options:
100 = 100 ns
150 = 150 ns
200 = 200 ns

Package Option:
MA = A-type module

- Supply Tolerance:

l
no mark = 5% negative supply tolerance
y = 10% negative supply tolerance

Device:
bq4011 32K x 8 NVSRAM

Sept. 1990 919

6-19
Notes

6-20
~ BENOtMARQ _ _ _b---.;q~4_01_1_H_/b_q...;;...4_0_1_1_H_Y
32Kx8 Nonvolatile Fast SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
>- Data retention in the absence of The CMOS bq4011H is a nonvolatile memory until after Vee returns
power 262,144-bit fast static RAM valid.
organized as 32,768 words by 8 bits.
>- Access/cycle times of 35 and 45 ns The integral control circuitry and The bq4011H uses an extremely low
lithium energy source provide reli- standby current CMOS SRAM,
>- Automatic write-protection
coupled with a small lithium coin
during power-up/power-down able nonvolatility coupled with the
unlimited write cycles of standard cell to provide non volatility without
cycles
SRAM. Access times as fast as 35 ns long write cycle times and the write
>- !ndustry-standard 28-pin 32K x are available. cycle limitations associated with
8 pinout EEPROM.
The control circuitry constantly
>- Conventional SRAM operation; monitors the single 5V supply for an The bq4011H requires no external
unlimited write cycles out-of-tolerance condition. When circuitry and is socket-compatible
Vee falls out of tolerance, the SRAM with industry-standard SRAMs and
>- lO-year minimum data retention is unconditionally write-protected to most EPROMs and EEPROMs.
in absence of power prevent inadvertent write operation.
>- Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

A14
A12
1
2
-\.:)
28
27
Vee
WE
Ao-Al4

DQo-DQ7
Address inputs

Data input/output
OE Ao-A14
~-~
III
A7 3 26 A13 ------~

CE Chip enable input 32K X 8

As 4 25 As - - SRAM
A5[ 5 24 Ag WE Block 000 -007
OE Output enable input ------>
A4 6 23 ] A11
A3
A2
7
8
22
21
010
1 A10
WE Write enable input Power I ! CE CON

Al 9 20 CE Vee +5 volt supply input

Power-
Ao[ 10 19 DQ7
CE
--------0 Fail ~~cc
Vss Ground Control
DQ o I 11 18 DQs
DQ 1 12 17 1 DQ5
DQ 2 13 16 DQ 4 _L Lithium
I Cell
Vss 14 15 DQ3 --- BO-41
---- --------

PN-7

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4011H -35 35 -5% bq40lIHY -35 35 -10%
bq4011H -45 45 -5% bq40lIHY -45 45 -10%

Sept 1990 1/9

6-21
bq4011 H/bq4011 HV

Functional Description As Vee falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4011H operates as a stand- which provides data retention until valid Vee is applied.
ard CMOS SRAM. During power-down and power-up
cycles, the bq4011H acts as a nonvolatile memory, auto- When Vee returns to a level above the internal backup
matically protecting and preserving the memory con- cell voltage, the supply is switched back to Vee. Mter
tents. Vee ramps above the VPFD threshold, write protection
continues for a time teER (120 ms maximum) to allow for
Power-down/power-up control circuitry constantly processor stabilization. Normal memory operation may
monitors the Vee supply for a power-fail-detect threshold resume after this time.
VPFD. The bq4011H monitors for VPFD = 4.62V typical
for use in systems with 5% supply tolerance. The The internal coin cell used by the bq4011H has an
bq4011HY monitors for VPFD = 4.37V typical for use in extremely long shelf life and provides data retention for
systems with 10% supply tolerance. more than 10 years in the absence of system power.

When Vee falls below the VPFD threshold, the SRAM As shipped from Benchmarq, the integral lithium cell is
automatically write-protects the data. All outputs electrically isolated from the memory. (Self-discharge in
become high impedance, and all inputs are treated as this condition is approximately 0.5% per year.) Following
"don't care." If a valid access is in process at the time of the first application of Vee, this isolation is broken, and
power-fail detection, the memory cycle continues to com- the lithium backup cell provides data retention on
pletion. If the memory cycle fails to terminate within subsequent power-downs.
time tWPT, write-prot.ection takes place.

Truth Table
Mode CE WE OE I/O Operation Power

Not selected H X X HighZ Standby

r------------------- c--- f--- I-----~------

Output disable L H H HighZ Active

r---------------- 1 - - - - - - - - - - -1-------------c----- -.-

Read L H L DOUT Active

--- r------------
Write L L X DIN Active

Absolute Maximum Ratings

.---~--- -~-----------

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to---_.

7.0__.
V
1-------- -----"--- - - - - - - - - - - ------
VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT~Vee + 0.3
relative to Vss
------ -----------.--~------------

TOPR Operating temperature o to +70

--------~-
°C

TSTG Storage temperature -40 to +70 °C

-- -
TBIAS Temperature under bias -10 to +70 °C
- - - ------
TsoLDER Soldering temperature +260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

2/9 Sept. 1990

6-22
 bq4011H/bq4011HY

Recommended DC Operating Conditions (TA =0 to 70·C)

Symbol Parameter Minimum Typical Maximum Unit Notes

4.5 5.0 5.5 V bq4011HY

Vee Supply voltage
4.75 5.0 5.5 V bq4011H
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA =0 to 70"C, VCCmin $; Vcc $; VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±2 ~ VIN =Vss to Vee

ILO Output leakage current - - ±2 ~ CE = VIR or OE = VIR or
WE = VIL, VOUT = Vss to Vee
VOR Output high voltage 2.4 - - V lOR =-4.0 rnA
VOL Output low voltage - - 0.4 V IOL = 8.0 rnA
ISB1

ISB2

Ice
Standby supply current

Standby supply current

Operating supply current

-

-
-
18

2.5

65 125
34

4
rnA

rnA

rnA
CE =VIR
CE ~ Vee - 0.2V,
OV $; VIN $; 0.2V,
or VIN ~ Vee - 0.2V
Min. cycle, duty = 100%,
CE = VIL, Ivo = OmA
-
4.55 4.62 4.75 V bq4011H
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4011HY
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe =3Y.

Capacitance (TA = 25"C, F = 1 MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

Cvo Input/output capacitance - - 10 pF Output voltage = OV

CIN Input capacitance - - 8 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept. 1990 3/9

6-23
bq4011 H/bq4011 HY

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

Dour Dour

1Ko 100pF 1Ko 5pF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70°C, VCCmin ~ VCC ~ VCCmax)

-35 -45
Symbol Parameter Unit Conditions
Min. Max. Min. Max.
tRC Read cycle time 35 - 45 - ns
tAA Address access time - 35 - 45 ns Output load A
tACE Chip enable access time - 35 - 45 ns Output load A
tOE Output enable to output valid - 12 - 15 ns Output load A
tCLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 0 - 0 - ns Output load B
tcHZ Chip disable to output in high Z 0 22 0 25 ns Output load B
tOHZ Output disable to output in high Z 0 12 0 15 ns Output load B
tOH Output hold from address change 5 - 5 - ns Output load A

4/9 Sept. 1990

6-24
 bq4011 H/bq4011 HY

Read Cycle No.1 (Address Access) 1,2

~~~~~~~~~~--tRC--~~~~~~~~~~

Address

~ tOH tAA --~-------+I

-----------p-r-e-vi-O-us--D-at-a-v-a-h-.d---------~)«~----D-a-ta--V-a-lid-----
14---1:

DOUT

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

o OUT

RC-2

Read Cycle No.3 (OE Access) 1,5

~*~~~~~~~_tR_c~~~~~~~l_ _ _ _ _ __ _
Address

~14~~~~-tAA--------~
OE
1 4 - - - t OE --~

DOUT Data Valid

High-Z High-Z

RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.

Sept. 1990 5/9

6-25
bq4011 H/bq4011 HY

Write Cycle (TA = 0 to 70°C, VCCmin ~ VCC ~ VCCmax)

-35 -45
Symbol Parameter Units Notes
Mino Maxo Mino Maxo
twc Write cycle time 35 - 45 - ns
tcw Chip enable to end of write 30 - 40 - ns (1)

tAw Address valid to end of write 20 - 30 - ns (1)

Measured from address

tAS Address setup time 0 - 0 - ns valid to beginning of
write. (2)
Measured from begin-
twp Write pulse width 25 - 30 - ns ning of write to end of
write. (1)
Write recovery time Measured from WE
tWRl (write cycle 1) 0 - 0 - ns going high to end of
write cycle. (3)
Write recovery time Measured from CE
tWR2 (write cycle 2) 10 - 10 - ns going high to end of
write cycle. (3)
Measured from first low-
tDW Data valid to end of write 12 - 15 - ns to-high transition of
either CE or WE.
Data hold time Measured from WE
tDHl (write cycle 1) 0 - 0 - ns going high to end of
write cycle. (4)
Data hold time Measured from CE
tDH2 (write cycle 2) 10 - 10 - ns going high to end of
write cycle. (4)
twz Write enabled to output in 0 15 0 15 ns I/O pins are in output
high-Z state. (5)
tow Output active from end of 5 - 5 - ns I/O pins are in output
write state. (5)

Notes: 1. A write ends at the earlier transition ofCE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWRl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. IfCE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-26
 bq4011 H/4011 HY

Write Cycle No. 1 (WE-Controlled) 1,2,3

twe

Address )~
tAW t WR1 .....

""",,'i.
tew
CE /~/ / / / / / /
/.-- t AS ---- twp
WE
~I'\." ,,~ /~
" L
tDW tDH1

DIN
>k
\.--t wz
Data-in Valid

I---tow

WC-3

Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

Address
_ t,tt :'A.
AS - - - - . - - - - - tew
'_we --'-:r
-----__.1-.
w-J-----
CE
~---------twp-----------.I

WE
14---- tDW - - -.....-
------------~----------~ Data-in Valid

Dour
WC-4
Notes: 1. CE or WE must be high during address transition.
2. Because 1/0 may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the 1/0 pins remain in a state of high impedance.
4. Either tWRl or twR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept. 1990 7/9

6-27
bq4011 H/4011 HY

Power-Down/Power-Up Cycle (TA = 0 to 70·C)

Symbol Parameter Min. Typ. Max. Unit Conditions
tPF Vee slew, 4.75 to 4.25 V 300 - - I1S
tFS Vee slew, 4.25 to Vso 10 - - I1s
tpu Vee slew, Vso to VPFD
(max.)
0 - - I1s

Time during which SRAM is

tcER Chip enable recovery time 40 80 120 ms write-protected after Vee passes
VFPD on power-up.
tDR Data-retention time in
absence of Vee
10 - - years TA = 25·C (2)

Delay after Vee slews down past

tWPT Write-protect time 40 100 150 I1s VPFD before SRAM is write-
protected.

Note: 1. Typical values indicate operation at TA = 25°C, Vee = 5V.

2. Battery is disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

Vee

CE

PD-B

8/9 Sept. 1990

6-28
 bq4011 H/bq4011 HY

Ordering Information
bq4011H MA-

L Speed Options:
35 = 35 ns
45=45ns

- Package Option:
MA = A-type module

Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

Device:
bq4011H Fast 32Kx8 NVSRAM

III

Sept. 1990 9/9

6-29
Notes

6-30
 Advance Information Addendum

~ BENCHMARQ _ _ _ _
bq-=..40_1_1HI_b.....:.q40_1_1_H_Y
High-Speed 32Kx8 Nonvolatile SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
~ Access/cycle times of 20 and 25 ns The CMOS bq4011H is a nonvolatile memory until after Vee returns
262,144-bit fast static RAM valid.
~ Data retention in the absence of organized as 32,768 words by 8 bits.
power The integral control circuitry and The bq4011H uses an extremely low
lithium energy source provide reli- standby current CMOS SRAM,
~ Automaticwrite-protection
able nonvolatility coupled with the coupled with a small lithium coin
during power-up/power-down
unlimited write cycles of standard cell to provide nonvolatility without
cycles long write cycle times and the write
SRAM. Access times as fast as 20 ns
~ Industry-standard 28-pin 32K x are available. cycle limitations associated with
8 pinout EEPROM.
The control circuitry constantly
~ Conventional SRAM operation; monitors the single 5V supply for an The bq4011H requires no external
unlimited write cycles out-of-tolerance condition. When circuitry and is socket-compatible
Vee falls out of tolerance, the SRAM with industry-standard SRAMs.
~ 10-year minimum data retention is unconditionally write-protected to
in absence of power prevent inadvertent write operation.
~ Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

Address inputs
A14 1
u 28 Vee
Ao-AI4

2 27 WE DQo-DQ7 Data input/output OE ..---~ Ao-A14

A12
A7 3 26 A13 CE Chip enable input 32K X a

---
SRAM
Ae 4 25 Aa WE aleck DO 0 -DO 7
As 5 24 Ae DE Output enable input
A4 6 23 All
A3 7 22 bE WE Write enable input Power CE eON
A2 8 21 A10
Vee +5 volt supply input
Al 9 20 CE CE Power- Vee
Fail
Ao 10 19 DQ7 Vss Ground Control
DQ o 11 18 DQ e
DQ 1 12 17 DQs Lithium
DQ 2 13 16 DQ 4 --I... Cell
Vss 14 15 DQ3 BO-41

PN-7

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4011H -20 20 -5% bq40lIHY -20 20 -10%
bq4011H -25 25 -5% bq4011HY ··25 25 -10%

Sept. 1990 1/1

6-31
Notes

6-32
 ~ BENOIMARQ _ _ _ _b---:;q_40_1_3_/b----=q=---40_1_3_Y
128Kx8 Nonvolatile SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
~ Data retention in the absence of The CMOS bq4013 is a nonvolatile memory until after Vee returns
power 1,048,576-bit static RAM organized valid.
as 131,072 words by 8 bits. The
~ Automatic write-protection The bq4013 uses an extremely low
integral control circuitry and
during power-up/power-down lithium energy source provide reli- standby current CMOS SRAM,
cycles able nonvolatility coupled with the coupled with a small lithium coin cell
unlimited write cycles of standard to provide nonvolatility without long
~ Industry-standard 32-pin 128K x
SRAM. write cycle times and the write cycle
8 pinout
limitations associated with
~ Conventional SRAM operation; The control circuitry constantly EEPROM.
unlimited write cycles monitors the single 5V supply for an
out-of-tolerance condition. When The bq4013 requires no external cir-
~ 10-year minimum data retention Vee falls out of tolerance, the SRAM cuitry and is socket-compatible with
in absence of power is unconditionally write-protected to industry-standard SRAMs and most
prevent inadvertent write operation. EPROMs and EEPROMs.
~ Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

-.:::::J Ao-A16 Address inputs
NC. 1 32 VCC
A 16 2 31 A1s DQo-DQ7 Data input/output
A14 3 30 NC
Chip-enable input
-
OE
A12 - 4 29 WE
CE .~ ~~--
128K x 8
A7 5 28 A13 Output-enable input
OE ~
SRAM
A6 [ 6 27 A8 WE Block DOo -DO 7
As[ 7 26 Ae WE Write-enable input
I----~~ ..
A4
A3
8
9
25
24
All
OE NC No connect Power rr CE CON
A2 10 23 A 10
Vee +5 volt supply input CE Power-
Al 11 22 CE Fail ~VCC
Ao 12 21 C07 Vss Ground Cont'ol
COo 13 20 C0 6
Cal L 14 19 cas J Lithium
CO 2 15 18 C0 4 I Cell
16 17 C0 3 - 80-42
~

vss __.___ ._____.____----.J

PN-8

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4013-85 85 -5% bq4013Y -85 85 -10%
bq4013 -120 120 -5% bq4013Y -120 120 -10%

Sept. 1990 1/9

6-33
bq4013/bq4013Y

Functional Description As Vee falls past VPFD and approaches 3Y, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4013 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4013 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. Mter
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4013 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4013Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cell used by the bq4013 has an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cell is
become high impedance, and all inputs are treated as electrically isolated from the memory. (Self-discharge in
"don't care." If a valid access is in process at the time of this condition is approximately 0.5% per year.) Following
power-fail detection, the memory cycle continues to com- the first application of Vee, this isolation is broken, and
pletion. If the memory cycle fails to terminate within the lithium backup cell provides data retention on
time twPI', write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE 1/0 Operation Power
Not selected H X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DouT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VTsVee+0.3
relative to Vss
TOPR Operating temperature o to +70 °C

TSTG Storage temperature -40 to +70 °C

TBIAS Temperature under bias -10 to +70 °C

TsoLDER Soldering temperature +260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

2/9 Sept. 1990

6-34
 bq4013/bq4013V

Recommended DC Operating Conditions (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Notes
4.5 5.0 5.5 V bq4013Y
Vee Supply voltage
4.75 5.0 5.5 V bq4013
------- - --
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
----- - - r----
VIR Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA =0 to 70'C, VCCmin 2 VCC 2 VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±1 IlA VIN = Vss to Vee

ILO Output leakage current - - ±1 IlA CE = VIR or OE = VIR or
WE =VIL
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA
VOL Output low voltage - - 0.4 V IOL = 2.1 rnA
ISBl Standby supply current - 4 7 rnA CE = VIR
CE 2 Vee - 0.2V,
IS:!l2 Standby supply current - 2.5 4 rnA OV:O; VIN:O; 0.2V,
orVIN2 Vee - 0.2V
lee Operating supply current - 75 105 rnA Min. cycle, duty = 100%,
CE = VIL, IIIo = OmA
4.55 4.62 4.75 V bq4013
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4013Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3V.

Capacitance (TA = 2S'C, F = 1MHz, VCC = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIIO Input/output capacitance - - 10 pF Output voltage = OV

CIN Input capacitance - - 10 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept. 1990 3/9

6-35
bq4013/bq4013Y

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

+5V

1.9Kn

_1-
D OUT o~---~ .~-----+ DOUT

1Kn - -= 100pF 1Kn 5pF

---------_..-

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70'C, VCCmin 2: VCC 2: VCCmax)

-85 -120
Symbol Parameter Unit Conditions
Min. Max. Min. Max.
tRC Read cycle time 85 - 120 - ns
tAA Address access time - 85 - 120 ns Output load A
tACE Chip enable access time - 85 - 120 ns Output load A
tOE Output enable to output valid - 45 - 60 ns Output load A
tcLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 0 - 0 - ns Output load B
tcHZ Chip disable to output in high Z 0 35 0 45 ns Output load B
tOHZ Output disable to output in high Z 0 25 0 35 ns Output load B
tOH Output hold from address change 10 - 10 - ns Output load A

4/9 Sept. 1990

6-36
 bq4013/bq4013Y

Read Cycle No.1 (Address Access) 1,2

~--------- tRe ----------~

) ~, ________________________________________- -)

-tAA---;l
Address _ _ _ _ _ _J ' (
' -_ __ _

~.------toH-----1~
1+---1:

DOUT -------p-re-v-io-u-s-D-a-ta-V-ali-·d-------~XX ---o-a-ta-V-a-li-d----

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

DouT

RC-2
III
Read Cycle No.3 (OE Access) 1,5

---l--
~
tRe

Address

tM ~I

OE

~-- t OE - - - . j

Dour Data Valid

High-Z High-Z

RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE=VIL.
5. Device is continuously selected: CE = VIL.

Sept. 1990 5/9

6-37
bq4013/bq4013Y

Write Cycle (TA = 0 to 70·C, VCCmin ~ VCC ~ VCCmax)

-85 -120 Conditionsl

Symbol Parameter Units Notes
Min. Max. Min. Max.

twc Write cycle time 85 - 120 - ns

tcw Chip enable to end of write 75 - 100 - ns (1)

tAW Address valid to end of write 75 - 100 - ns (1)

tAS Address setup time 0 - 0 - ns Measured from address valid to

beginning of write. (2)
twp Write pulse width 65 - 85 - ns Measured from beginning of write to
end of write. (1)
tWRl Write recovery time 5 - 5 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (3)
tWR2 Write recovery time 15 - 15 - ns Measured from CE going high to end
(write cycle 2) of write cycle. (3)
tDW Data valid to end of write 35 - 45 - ns Measured to first low-to-high transi-
tion of either CE or WE.
tDHl Data hold time 0 - 0 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (4)
tDH2 Data hold time 10 - 10 - ns Measured from CE going high to end
(write cycle 2) of write cycle. (4)
twz Write enabled to output in 0 30 0 40 ns 110 pins are in output state. (5)
highZ
tow Output active from end of 0 - 0 - ns 1/0 pins are in output state. (5)
write

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either twnl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. IfCE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-38
 bq4013/bq4013Y

Write Cycle No.1 (WE-Controlled) 1,2,3

~----------twc----------~

Address

~-------- tAW ---------.!4-tWR1

~~~~~~-------tcw-------~,~--r_~_r~~r_~
CE

WE

14-----tDW ----...f--

tow---j .
oOUT High-Z -1<~XX~"7X~

WC-3

Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

III
Address

CE

~-------twp-------~

WE

____________-L____________~ 1+--- tDW ----+1+--

Data-in Valid

DOUT

WC-4
Notes: L CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept. 1990 7/9

6-39
bq4013/bq4013V

Power-Down/Power-Up Cycle (T A = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Conditions
tPF Vcc slew, 4.75 to 4.25 V 300 - - ~s

tFS Vcc slew, 4.25 to Vso 10 - - ~s

tpu Vcc slew, Vso to VPFD (max.) 0 - - ~s

Time during which

tCER Chip enable recovery time 40 80 120 ms SRAM is write-
protected after Vee pas-
ses VFPD on power-up.
tDR Data-retention time in 10 - - years TA = 25'C (2)
absence of Vee
Delay after Vee slews
twPr Write-protect time 40 100 150 ~s down past VPFD before
SRAM is write-
protected.

Note: 1. Typical values indicate operation at TA = 25'C, Vee = 5V.

2. Battery is disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

4.75

Vcc

Vso Vso

~
tFS
14----- tOR ktpu ~
t CER

CE
=======tW=PTXXXXXX XXX
PD-B

8/9 Sept. 1990

6-40
 bq4013/bq4013V

Ordering Information

bq4013 MA-

L Speed Options:
85 = 85 ns
120 = 120 ns

Package Option:
MA = A-type module

Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

Device:
bq4013 128K x 8 NVSRAM

III

Sept. 1990 9/9

6-41
Notes

6-42
~ BENOiMARQ _ _p_re_lim_ina_ry_b_q..;;......4_0_14_/_bq~4_0_1_4_Y
256Kx8 Nonvolatile SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
~ Data retention in the absence of The CMOS bq4014 is a nonvolatile memory until after Vee returns
power 2,097,152-bit static RAM organized valid.
as 262,144 words by 8 bits. The
~ Automatic write-protection The bq4014 uses extremely low
integral control circuitry and
during power-up/power-down lithium energy source provide reli- standby current CMOS SRAMs,
cycles able nonvolatiIity coupled with the coupled with small lithium coin cells
unlimited write cycles pf standard to provide nonvolatiIity without long
~ Industry-standard 32-pin 256K x
SRAM. write cycle times and the write cycle
8 pinout
limitations associated with
~ Conventional SRAM operation; The control circuitry constantly EEPROM.
unlimited write cycles monitors the single 5V supply for an
out-of-tolerance condition. When The bq4014 requires no external cir-
~ 10-year minimum data retention Vee falls out of tolerance, the SRAM cuitry and is compatible with the
in absence of power is unconditionally write-protected to industry-standard 2Mb SRAM
prevent inadvertent write operation. pinout.
~ Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

A('r-Al7 Address inputs
u 6
III
NC 1 32 Yee
DQ('r-DQ7 Data input/output
Ale 2
A14 - 3
31 A 15
30 ] A17 CE Chip-enable input
~
OE
... 2x12SKxS
~'}~_~6 __

A12 [ 4 29 WE SRAM
Block
A7 5 28 A 13 DE Output-enable input WE~ DOo -DO 7
~~-.--- ~
6 27
Ae
A5
A4[ 8
7 26
25
As
A9
A11
WE
NC
Write-enable input
No connect
power12 TCE eON

A3 9 24 :I OE
CE Power-
10 23 ] Al0 .vee
A2 Vee +5 volt supply input Fail
Control
Al 11 22 1 CE A17
--
Ao 12 21 007 Vss Ground
00 0 13 20 DOe I Lithium
T Cell
001 14 19 00 5
60-43
D0 2 L 15
1!JID0 4
Yss 16 17 J 003
---

PN-9

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4014 -85 85 -5% bq4014Y -85 85 -10%
bq4014 -120 120 -5% bq4014Y -120 120 -10%

Sept 1990 1/9

6-43
bq4014/bq4014 V Preliminary

Functional Description As Vee falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4014 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4014 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4014 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4014Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cells used by the bq4014 have an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cells
become high impedance, and all inputs are treated as are electrically isolated from the memory. (Self-discharge
"don't care." If a valid access is in process at the time of in this condition is approximately 0.5% per year.) Follow-
power-fail detection, the memory cycle continues to com- ing the first application of Vee, this isolation is broken,
pletion. If the memory cycle fails to terminate within and the lithium backup provides data retention on
time tWPI', write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE 1/0 Operation Power
Not selected H X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DouT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT => Vee +0.3
relative to Vss
TOPR Operating temperature o to +70 'C
TSTG Storage temperature -40 to +70 'C
TRIAS Temperature under bias -10 to +70 'C
TsoLDER Soldering temperature +260 'C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operatior
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods oftime may affect device reliability.

219 Sept. 1990

6-44
 Preliminary bq4014/bq4014 Y

Recommended DC Operating Conditions (TA = 0 to 70·C)

Symbol Parameter Minimum Typical Maximum Unit Notes
4.5 5.0 5.5 V bq4014Y
Vee Supply voltage
4.75 5.0 5.5 V bq4014
f---------.-- r---- - -- - - - - -- - -
Vss Supply voltage 0 0 0 V
r--- --- --- -.-~--.

VIL Input low voltage -0.3 - 0.8 V

VlH Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25°C.

DC Electrical Characteristics (TA =0 to 70·C, VCCmin ~ Vcc ~ VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±2 IlA VIN = Vss to Vee

ILO Output leakage current - - ±2 IlA CE = VIR or OE = Vrn or
WE =VIL
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA
1-----
VOL Output low voltage - - 0.4 V IOL = 2.1 rnA

-
ISBI Standby supply current - 5 12 rnA CE =Vrn
CE ~ Vee - 0.2V,
ISB2 Standby supply current - 2.5 4 rnA OV ~ VIN ~ 0.2V,
or VIN ~ Vee - 0.2V
f--
lee Operating supply current - 75 110 rnA Min. cycle, duty = 100%,
CE = VIL, 11/0 = OmA
- -- -
4.55 4.62 4.75 V bq4014
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4014Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25°C, Vee = 5V or VBe = 3Y.

Capacitance (TA =2S·C, F =1 MHz, VCC =S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CI/O Input/output capacitance - - 20 pF Output voltage = OV

CIN Input capacitance - - 20 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept.1990 3/9

6-45
bq4014/bq4014 Y Preliminary

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto 3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2
--

+5V

1.9Kn 1.9Kn

DOUT O------~---------4 D OUT 0------.--

1Kn 100pF 1Kn

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70"C, VCCmin ~ VCC ~ VCCmax)

-85 -120
Symbol Parameter Unit Conditions
Min. Max. Min. Max.

tRC Read cycle time 85 - 120 - ns

tAA Address access time - 85 - 120 ns Output load A J

tACE Chip enable access time - 85 - 120 ns Output load A

toE Output enable to output valid - 45 - 60 ns Output load A
tcLz Chip enable to output in low Z 5 - 5 - ns Output load B
toLz Output enable to output in low Z 0 - 0 - ns Output load B
tCHz Chip disable to output in high Z 0 35 0 45 ns Output load B
tOHZ Output disable to output in high Z 0 25 0 35 ns Output load B
tOH Output hold from address change 10 - 10 - ns Output load A

4/9 Sept. 1990

6-46
 Preliminary bq4014/bq4014 V

Read Cycle No.1 (Address Access) 1,2

~------------------tRC------------------~

Address

1:=: =-=--tOH-=-_tAA=-=;-~~
Dour ------p-re-v-iO-u-s-D-a-ta-V-al-id-----bm--o-a-ta-v-a-li-d--

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

Read Cycle No.3 (OE Access) 1,5

RC-2

-
Address

OE

~---t OE -----+I

D~ _ _ _ _~~~----~ Data Valid

High-Z High-Z
RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = DE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. DE = VIL.
5. Device is continuously selected: CE = VIL.
Sept. 1990 5/9

6-47
bq4014/bq4014Y Preliminary

Write Cycle (TA = 0 to 70'C, VCCmin ~ VCC ~ VCCmax)

-85 -120 Conditions!

Symbol Parameter Units Notes
Min. Max. Min. Max.
twc Write cycle time 85 - 120 - ns
tcw Chip enable to end of write 75 - 100 - ns (1)

tAW Address valid to end of write 75 - 100 - ns (1)

tAS Address setup time 0 - 0 - ns Measured from address valid to

beginning of write. (2)
twp Write pulse width 65 - 85 - ns Measured from beginning of write to
end of write. (1)
tWRl Write recovery time 5 - 5 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (3)
tWR2 Write recovery time 15 - 15 - ns Measured from CE going high to end
(write cycle 2) of write cycle. (3)
tDw Data valid to end of write 35 - 45 - ns Measured to first low-to-high transi-
tion of either CE or WE.
tDHl Data hold time 0 - 0 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (4)
tDH2 Data hold time 10 - 10 - ns Measured from CE going high to end
(write cycle 2) of write cycle. (4)
twz Write enabled to output in 0 30 0 40 ns 1/0 pins are in output state. (5)
highZ
tow Output active from end of 0 - 0 - ns UO pins are in output state. (5)
write

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWRI or tWR2 must be met.
4. Either tDHI or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-48
 Preliminary bq4014/bq4014Y

Write Cycle No.1 (WE-Controlled) 1,2,3

~------------------twe----------------~

Address

~------------- tAW -----------------Il4-tWR1

~.,.__~~......... [4------------------ tew ---------------*1 ,--..,~.,,__""7""_r__..,~.,,__""7
CE

14------twp------~
WE

-tDW----..-

tow ----j "

oOUT High-Z ----K~X"7X~X...-?"

WC-3

-
Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

Address

CE

14------------twp------------~

WE
[4--------t DW - -....-
------------~------------~
Data-in Valid

oOUT
WC-4
Notes: 1. CE or WE must be high during address transition.
2" Because 110 may be active COE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the 1/0 pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept. 1990 7/9

6-49
bq4014/bq4014V Preliminary

Power-Down/Power-Up Cycle (TA = 0 to 70"C)

Symbol Parameter Minimum Typical Maximum Unit Conditions
tPF Vee slew, 4.75 to 4.25 V 300 - - IlS
tFS Vee slew, 4.25 to Vso 10 - - Ils
tpu Vee slew, Vso to VPFD (max.) 0 - - Ils
Time during which
teER Chip enable recovery time 40 80 120 ms SRAM is write-pro-
tected after Vee passes
VFPD on power-up.
tDR Data-retention time in 10 - - years TA = 25"C (2)
absence of Vee
Delay after Vee slews
tWPr Write-protect time 40 100 150 Il S down past VPFD before
SRAM is write-
protected.

Note: 1. Typical values indicate operation at TA = 25"C, Vee = 5V.

2. Batteries are disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Cautiou: Negative undershoots below the absolute maximum rating of -O"3V in battery-backup mode
may affect data integrity"

Power-Down/Power-Up Timing

Vee

CE

PD-B

8/9 Sept. 1990

6-50
 Preliminary bq4014/bq4014 V

Ordering Information
bq4014 MB-

L Speed Options:
85= 85ns
120 = 120 ns

- Package Option:
MB =B-type module
- Supply Tolerance:
no mark =5% negative supply tolerance
Y = 10% negative supply tolerance

Device:

-
bq4014 256K x 8 NVSRAM

Sept. 1990 9/9

6-51
Notes

6·52
~ BENCHMARQ _ _P_rel_im'_'nar_
y _b.......;q~4_01_5_/b_q~4_0_1_5y_

512Kx8 Nonvolatile SRAM

Features General Description At this time the integral energy
source is switched on to sustain the
>- Data retention in the absence of The CMOS bq4015 is a nonvolatile memory until after Vee returns
power 4,194,304-bit static RAM organized valid.
as 524,288 words by 8 bits. The
>- Automatic write-protection integral control circuitry and The bq4015 uses extremely low
during power-up/power-down lithium energy source provide reli- standby current CMOS SRAMs,
cycles able nonvolatility coupled with the coupled with small lithium coin cells
unlimited write cycles of standard to provide nonvolatility without long
>- Industry-standard 32-pin 512K x write cycle times and the write cycle
8 pinout SRAM.
limitations associated with
>- Conventional SRAM operation; The control circuitry constantly EEPROM.
unlimited write cycles monitors the single 5V supply for an
out-of-tolerance condition. When The bq4015 requires no external cir-
>- 5-year minimum data retention Vee falls out of tolerance, the SRAM cuitry and is compatible with the
in absence of power is unconditionally write-protected to industry-standard 4Mb SRAM
prevent inadvertent write operation. pinout.
>- Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

Ao-AI8 Address inputs

-
1
CJ 32
A 18 Vee
DQo-DQ7 Data input/output
AlB
A14
A12
2
3
4
31
30
29
AIS
A17
WE
CE Chip-enable input
OE
--- .. 4x128Kx8
SRAM
..AE~~16_

A7 5 28 A 13 OE Output-enable input Block

Ae 6 27 A8 ~ 000 -007

As . 7 26 Ag WE Write-enable input
A4 8 25 All Power 14 { CE CON
Vee +5 volt supply input
A3 9 24 OE -
10 23 A10 Power-
A2
11 22 CE
Vss Ground ~.... Fail ~
Al Control
AlrA18
Ao 12 21 D0 7 .. -.:::..
13 20
DO o
14 19
DOe I Lithium
Cell
DOl DOs _L
D0 2 15 18 D0 4 - BO·44
Vss 16 17 D03

PN-10

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4015 -85 85 -5% bq4015Y -85 85 -10%
bq4OJ5 -120 120 -5% bq4OJ5Y ·120 120 -10%

Sept. 1990 1/9

6-53
bq4015/bq4015Y Preliminary

Functional Description As Vee falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4015 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4015 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4015 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4015Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cells used by the bq4015 have an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 5 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cells
become high impedance, and all inputs are treated as are electrically isolated from the memory. (Self-discharge
"don't care." If a valid access is in process at the time of in this condition is approximately 0.5% per year.) Follow-
power-fail detection, the memory cycle continues to com- ing the first application of Vee, this isolation is broken,
pletion. If the memory cycle fails to terminate within and the lithium backup provides data retention on
time twPr, write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE 1/0 Operation Power
Not selected Ii X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DoUT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to 7.0 V VT ~ Vee + 0.3
relative to Vss
ToPR Operating temperature o to +70 ·C
TSTG Storage temperature -40 to +70 ·C

TBIAS Temperature under bias -10 to +70 ·C

TSOLDER Soldering temperature +260 ·C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

2/9 Sept. 1990

6-54
 Preliminary bq4015/bq4015Y

Recommended DC Operating Conditions (TA = 0 to 70"C)

Symbol Parameter Minimum Typical Maximum Unit Notes
4.5 5.0 5.5 V bq4015Y
Vee Supply voltage
4.75 5.0 5.5 V bq4015
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA = 0 to 70"C, VCCmin ~ VCC ~ VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±4 ~ VIN = Vss to Vee

ILO Output leakage current - - ±4 ~ CE = VIH or OE = VIR or
WE =VIL
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA
VOL Output low voltage - - 0.4 V IOL= 2.1 rnA
ISBl Standby supply current - 7 17 rnA CE=VIH

ISB2 Standby supply current - 2.5 5 rnA

CE ~ Vee - 0.2V,
OV ::;; VIN ::;; 0.2V,
or VIN ~ Vee - 0.2V
III
lee Operating supply current - 75 115 rnA Min. cycle, duty = 100%,
CE = VIL, lIla = OmA
4.55 4.62 4.75 V bq4015
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4015Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3Y.

Capacitance (TA = 2S"C, F = 1MHz, VCC = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIIO Input/output capacitance - - 40 pF Output voltage = OV

CIN Input capacitance - - 40 pF Input voltage = OV

Note: These parameters are sampled and not 100% tested.

Sept. 1990 3/9

6-55
bq4015/bq4015Y Preliminary

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

DOUT

1Kn 100pF 1Kn 5pF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA =0 to 70·C, VCCmin ~ VCC ~ VCCmax)

·85 ·120
Symbol Parameter Unit Conditions
Min. Max. Min. Max.
tRC Read cycle time 85 . 120 - ns
tAA Address access time - 85 - 120 ns Output load A
tACE Chip enable access time - 85 - 120 ns Output load A
tOE Output enable to output valid - 45 - 60 ns Output load A
tCLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 0 - 0 - ns Output load B
tcHZ Chip disable to output in high Z 0 35 0 45 ns Output load B
tOHz Output disable to output in high Z 0 25 0 35 ns Output load B
tOH Output hold from address change 10 - 10 - ns Output load A

4/9 Sept. 1990

6-56
 Preliminary bq4015/bq4015Y

Read Cycle No.1 (Address Access) 1,2

Address
~------------------t~------------------~
---=--_-tOH=_tAA=-=-----.t~
:=-1:

DOUT
------P-re-y-io-u-s-D-a-ta-Y-alid-·- - - -....bm--D-at-a-Y-a-lid---

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

DOUT

Read Cycle No.3 (OE Access) 1,5

RC-2

-
Address

OE

~--- tOE -----.t

D~ _________ --------~
Data YaRd
High-Z High-Z

RC-3
Notes: 1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE=VIL.
5. Device is continuously selected: CE = VIL.

Sept. 1990 5/9

6-57
bq4015/bq4015Y Preliminary

Write Cycle (TA = 0 to 70'C, VCCmin ~ VCC ~ VCCmax)

-85 ·120 Conditions!
Symbol Parameter Units Notes
Min. Max. Min. Max.

twc Write cycle time 85 - 120 - ns

tcw Chip enable to end of write 75 - 100 - ns (1)

tAW Address valid to end of write 75 - 100 - ns (1)

tAS Address setup time 0 - 0 - ns Measured from address valid to
beginning of write. (2)
twp Write pulse width 65 - 85 - ns Measured from beginning of write to
end of write. (1)
tWRl Write recovery time 5 - 5 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (3)
tWR2 Write recovery time
(write cycle 2)
15 - 15 - ns Measured from CE going high to end
of write cycle. (3)
tDW Data valid to end of write 35 - 45 - ns Measured to first low-to-high transi-
tion of either CE or WE.
tDHl Data hold time 0 - 0 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (4)
tDH2 Data hold time
(write cycle 2)
10 - 10 - ns Measured from CE going high to end
of write cycle. (4)
twz Write enabled to output in 0 30 0 40 ns I/O pins are in output state. (5)
highZ
tow Output active from end of 0 - 0 - ns I/O pins are in output state. (5)
write

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs durin~e overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWRl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-58
 Preliminary bq4015/bq4015Y

Write Cycle No. 1 (WE-Controlled) 1,2,3

~----------------twe----------------~

Address

~------------- tAW ------------~t-tWR1

~~.........___TL.._... ~------------ tew - - - - - - - - - - - - . 1 r--r--r""""'7'---........,r-"7"""""""7"

CE
~--- twp - - - - - - - . j
WE

tow----j .
DOUT High-Z --K~XXX~~'"7'

WC-3

Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

III
Address

---t.M-I~~I~___t~~_we ____ -.to:I~f-_~----

CE

~----------twp----------~

WE

~--- tow ----.--

------------~----------~
Data-in Valid

I~ ~
oOUT <-,~X~X""7'x:~:-Da'7'O:;,-Un"..,~-..,diij
.....fine-,~~("""71()(~><><><>a----~H~igh:--Z=------
WC-4
Notes: 1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept. 1990 719

6-59
bq4015/bq4015Y Preliminary

Power-Down/Power-Up Cycle (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tPF Vee slew, 4.75 to 4.25 V 300 - - J.lS

tFS Vee slew, 4.25 to Vso 10 - - J.ls
tpu Vee slew, Vso to VPFn (max.) 0 - - J.ls
Time during which
tcER Chip enable recovery time 40 80 120 ms SRAM is write-
protected after Vee pas-
ses VFPn on power-up.
tnR Data-retention time in 5 - - years TA = 25'C (2)
absence of Vee
Delay after Vee slews
tWPr Write-protect time 40 100 150 J.ls down past VPFn before
SRAM is write-
protected.

Note: 1. Typical values indicate operation at TA = 25'C, Vee =5V.

2. Batteries are disconnected from circuit until after Vee is applied for the first time. tnR is the
accumulated time in absence of power beginning when power is frrst applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.8V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

Vee

CE

PD-B

8/9 Sept. 1990

6-60
 Preliminary bq4015/bq4015Y

Ordering Information

l
bq4015 MB-

L Speed Options:
85= 85ns
120 = 120 ns

Package Option:
MB = B-type module

- Supply Tolerance:
no mark =5% negative supply tolerance
Y = 10% negative supply tolerance

Device:
bq4015 512K x 8 NVSRAM

Sept. 1990 9/9

6-61
Notes

6·62
~ BENOWARQ _ _pre_lim_in_ary_bq.-;;;.4_0_2_4_/b_q..;;;..-4_0_2_4Y_
128Kx16 Nonvolatile SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
> Data retention in the absence of The CMOS bq4024 is a nonvolatile memory until after Vee returns
power 2,097,152-bit static RAM organized valid.
as 131,072 words by 16 bits. The
> Automatic write-protection integral control circuitry and The bq4024 uses extremely low
during power-up/power-down lithium energy source provide reli- standby current CMOS SRAMs,
cycles able nonvolatility coupled with the coupled with small lithium coin cells
unlimited write cycles of standard to provide nonvolatility without long
> Industry-standard 40-pin 128K x write cycle times and the write cycle
16 pinout SRAM.
limitations associated with
> Conventional SRAM operation; The control circuitry constantly EEPROM.
unlimited write cycles monitors the single 5V supply for an
out-of-tolerance condition. When The bq4024 requires no external cir-
> 10-year minimum data retention Vee falls out of tolerance, the SRAM cuitry and is compatible with the
in absence of power is unconditionally write-protected to industry-standard 2Mb SRAM
prevent inadvertent write operation. pinout.
> Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

\j Ao--Al6 Address inputs
Ncr 1 40 J Vee
eEL 2 39 lWE DQo--DQlS Data input/output
DO,. r 3 38 lA 16
DE
'2X128KX8~
00 14 4 37 A,.
CE Chip-enable input
DO,. L 5 36 J A14
OQ 12 [. 6 35 J A 13 SRAM
OE Output-enable input WE Block
00,,[ 7 34 A"
00'0 r 8 33 JA 11 • I-
WE Write-enable input
DO.
DO.L
Vss [
S
10
11
32
31
30
JA 10
J A.
J Vss NC No connect
Pow er r r CEeoN
00 7 [- 12 29 1 A.
DO. 13 28 l A7 CE Power- Vee
DOsi 14 27 [ Ae Vee +5 volt supply input
• Fail
Control
DO. [ 15 26 J As
00.[ 16 25 l A. Vss Ground
00,[ 17 24 As
18 23 A,
1_ Lithiu m
DO,
[A,
Cell
DOD [ 19 22
OE r 20 21 [AD 80-45

PN-11

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4024 -85 85 -5% bq4024Y -85 85 -10%
bq4024 -120 120 -5% bq4024Y -120 120 -10%

Sept. 1990 1/9

6-63
bq4024/bq4024V Preliminary

Functional Description As Vee falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4024 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4024 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time tcER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4024 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4024Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cells used by the bq4024 have an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cells
become high impedance, and all inputs are treated as are electrically isolated from the memory. (Self-discharge
"don't care." If a valid access is in process at the time of in this condition is approximately 0.5% per year.) Follow-
power-fail detection, the memory cycle continues to com- ing the first application of Vee, this isolation is broken,
pletion. If the memory cycle fails to terminate within and the lithium backup provides data retention on
time twPr, write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE I/O Operation Power

Not selected H X X HighZ Standby

Output disable L H H HighZ Active
Read L H L DOUT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to7.0 V VT S; Vee + 0.3
relative to Vss
ToPR Operating temperature o to +70 'C
TSTG Storage temperature -40 to +70 'C
TBIAS Temperature under bias -10 to +70 'C
TSOLDER Soldering temperature +260 'C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

219 Sept. 1990

6-64
 Preliminary bq4024/bq4024 V

Recommended DC Operating Conditions (TA = 0 to 70·C)

Symbol Parameter Minimum Typical Maximum Unit Conditions
4.5 5.0 5.5 V bq4024Y
Vee Supply voltage
4.75 5.0 5.5 V bq4024
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIR Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25"C.

DC Electrical Characteristics (TA = 0 to 70·C, VCCmin :2: vcc :2: VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±2 J.LA VIN = Vss to Vee

lLO Output leakage current - - ±1 J.LA CE = VIR or OE = VIR or
WE = VIL, VOUT = Vss to
Vee
VOH Output high voltage 2.4 - - V IOH = -1.0 rnA

-
VOL Output low voltage - - 0.4 V IOL =2.1 rnA
ISBl Standby supply current - 5 11 rnA CE = VIR
CE :2: Vee - 0.2V,
ISB2 Standby supply current - 2.5 5 rnA OV::; VIN ::; 0.2V,
or VIN ~ Vee - 0.2V
lee Operating supply current - 95 200 rnA Min. cycle, duty = 100%,
CE = VIL, IIIo = OrnA
4.55 4.62 4.75 V bq4024
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4024Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25"C, Vee = 5V or VBe = 3V.

Capacitance (TA = 2S·C, F = 1MHz, vcc = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CIIO Input/output capacitance - - 10 pF Output voltage = OV

CIN Input capacitance - - 20 pF Input voltage = OV

Note: This parameter is sampled and not 100% tested.

Sept. 1990 3/9

6-65
bq4024/bq4024Y Preliminary

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 1 and 2

1.9Kn 1.9Kn

Dour Dour

1Kn 100pF 1Kn 5pF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70'C, VCCmin ;;:: VCC ;;:: VCCmax)

-85 -120
Symbol Parameter Unit Conditions
Min. Max. Min. Max.
tRC Read cycle time 85 - 120 - ns
tAA Address access time - 85 - 120 ns Output load A
tACE Chip enable access time - 85 - 120 ns Output load A
tOE Output enable to output valid - 45 - 60 ns Output load A
tCLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 0 - 0 - ns Output load B
tcHZ Chip disable to output in high Z 0 35 0 45 ns Output load B
tOHZ Output disable to output in high Z 0 25 0 35 ns Output load B
tOH Output hold from address change 10 - 10 - ns Output load A

4/9 Sept. 1990

6-66
 Preliminary bq4024/bq4024 V

Read Cycle No.1 (Address Access) 1,2

~------------------tRC--------------------~

-tAA---;l
Address

I~-----------toH----------1~
14---:

Dour ------p-re-v-io-u-s-D-a-ta-V-al-id-----~XX --D-a-ta-V-a-li-d--

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

Dour

RC-2
III
Read Cycle No.3 (OE Access) 1,5

t RC
Address

OE
1 tAA .1

~--- t OE ---~

Dour Data Valid

High-Z High-Z

RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE =VIL.
5. Device is continuously selected: CE = VIL.

Sept. 1990 5/9

6-67
bq4024/bq4024Y Preliminary

Write Cycle (T A = 0 to 70·C, VCCmin ~ VCC ~ VCCmax)

·85 ·120 Conditions/

Symbol Parameter Units Notes
Min. Max. Min. Max.

twc Write cycle time 85 - 120 - ns

tcw Chip enable to end of write 75 - 100 - ns (1)
tAW Address valid to end of write 75 - 100 - ns (1)

tAS Address setup time 0 - 0 - ns Measured from address valid to begin-

ning of write. (2)
twp Write pulse width 65 - 85 - ns Measured from beginning of write to
end of write. (1)
tWRl Write recovery time (write 5 - 5 - ns Measured from WE going high to end
cycle 1) of write cycle. (3)
tWR2 Write recovery time (write 15 - 15 - ns Measured from CE going high to end of
cycle 2) write cycle. (3)
tDW Data valid to end of write 35 - 45 - ns Measured to first low-to-high transi-
tion of either CE or WE.
tDHl Data hold time 0 - 0 - ns Measured from WE going high to end
(write cycle 1) of write cycle.(4)]
tDH2 Data hold time 10 - 10 - ns Measured from CE going high to end of
(write cycle 2) write cycle. (4)
twz Write enabled to output in 0 30 0 40 ns I/O pins are in output state. (5)
high-Z
tow Output active from end of 0 - 0 - ns 110 pins are in output state. (5)
write

Notes: l. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overla~ a low CE and a low WE. A write begins at the later
transition of CE going low and WE going low.
3. Either tWRl or tWR2 must be met.
4. Either tDHl or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-68
 Preliminary bq4024/bq4024Y

Write Cycle No. 1 (WE-Controlled) 1,2,3

~----------------twc----------------~

Address

~------------- tAW ------------~l--tWR1

~_r_""T""~L.....,.. ~------------tcw -------~ ~_r_""7'".....,..___..".......,r_~~

CE
1 + - - - twp ------~
WE

1 + - - - tDW ---_.!+_-

tOW----1 .

High-Z ---K'"XX~"""'X"""'"
WC-3

Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

III
Address

CE
~------twP----------~

WE

1 + - - - tDW ---*_-

------------~----------~
Data-in Valid

oOUT
WC-4
Notes: L CE or WE must be high during address transition.
2. Because VO may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. HOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.

Sept. 1990 7/9

6-69
bq4024/bq4024Y Preliminary

Power-Down/Power-Up Cycle (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tPF Vee slew, 4.75 to 4.25 V 300 - - Its

tFS Vee slew, 4.25 to Vso 10 - - Its
tpu Vee slew, Vso to VPFD (max.) 0 - - Its
Time during which
tcER Chip enable recovery time 40 80 120 ms SRAM is write-pro-
tected after Vee passes
VPFD on power-up.
tDR Data-retention time in 10 - - years TA=25'C (2)
absence of Vee
Delay after Vee slews
tWPl' Write-protect time 40 100 150 Its down past VPFD before
SRAM is write-
protected.

Note: 1. Typical values indicate operation at TA = 25"C, Vee = 5V.

2. Batteries are disconnected from circuit until after Vee is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

Vee

CE

PD-B

8/9 Sept. 1990

6-70
 Preliminary bq4024/bq4024V

Ordering Information
bq4024

-I L
MA-

Speed Options:
85 = 85 ns
120 = 120 ns

- Package Option:
MA =A-type module

- Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

Device:
bq4024 128K x 16 NVSRAM

Sept. 1990 9/9

6-71
Notes

6-72
 Preliminary bq4025/bq4025Y
256Kx16 Nonvolatile SRAM
Features General Description At this time the integral energy
source is switched on to sustain the
~ Data retention in the absence of The CMOS bq4025 is a nonvolatile memory until after Vee returns
power 4,194,304-bit static RAM organized valid.
as 262,144 words by 16 bits. The
~ Automatic write-protection The bq4025 uses extremely low
integral control circuitry and
during power-up/power-down lithium energy source provide reli- standby current CMOS SRAMs,
cycles able nonvolatility coupled with the coupled with small lithium coin cells
unlimited write cycles of standard to provide nonvolatility without long
~ Industry-standard 40-pin 256K x
SRAM. write cycle times and the write cycle
16 pinout
limitations associated with
~ Conventional SRAM operation; The control circuitry constantly EEPROM.
unlimited write cycles monitors the single 5V supply for an
out-of-tolerance condition. When The bq4025 requires no external cir-
~ 5-year minimum data retention Vee falls out of tolerance, the SRAM cuitry and is compatible with the
in absence of power is unconditionally write-protected to industry-standard 4Mb SRAM
prevent inadvertent write operation. pinout.
~ Battery internally isolated until
power is applied

Pin Connections Pin Names Block Diagram

Ao-AI7 Address inputs
A17 Vee
CE 2 39 WE DQo-DQls Data input/output
DO,. 3 38 A16
DO,. 4 37 A,. CE Chip-enable input
00'3 5 36 A,.
DO,. 6 35 A'3 OE Output-enable input
DO" 7 34 A,.
DOlO 8 33 Al1 WE Write-enable input
DOs 9 32 A,o
DO a 10 31 Ag Vee +5 volt supply input
Vss 11 30 Vss
00 7 [ 12 29 Aa
Vss Ground
DOe 13 28 A7
DO. 14 27 As
DO. 15 26 A.
00 3 16 25 A. Lithium
00 2 17 24 A3 ~ Cell
DO, 18 23 A. BO-46
00 0 19 22 A,
OE 20 21 Ao
-----.---

PN-12

Selection Guide
Minimum Negative Minimum Negative
Part Access Supply Part Access Supply
Number Time (ns) Tolerance Number Time (ns) Tolerance
bq4025 -85 85 -5% bq4025Y -85 85 -10%
bq4025 -120 120 -5% bq4025Y -120 120 -10%

Sept. 1990 1/9

6-73
bq4025/bq4025Y Preliminary

Functional Description As Vee falls past VPFD and approaches 3Y, the control
circuitry switches to the internal lithium backup supply,
When power is valid, the bq4025 operates as a standard which provides data retention until valid Vee is applied.
CMOS SRAM. During power-down and power-up cycles,
the bq4025 acts as a nonvolatile memory, automatically When Vee returns to a level above the internal backup
protecting and preserving the memory contents. cell voltage, the supply is switched back to Vee. After
Vee ramps above the VPFD threshold, write-protection
Power-down/power-up control circuitry constantly continues for a time teER (120 ms maximum) to allow for
monitors the Vee supply for a power-fail-detect threshold processor stabilization. Normal memory operation may
VPFD. The bq4025 monitors for VPFD = 4.62V typical for resume after this time.
use in systems with 5% supply tolerance. The bq4025Y
monitors for VPFD = 4.37V typical for use in systems with The internal coin cells used by the bq4025 have an
10% supply tolerance. extremely long shelf life and provides data retention for
more than 5 years in the absence of system power.
When Vee falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs As shipped from Benchmarq, the integral lithium cells
become high impedance, and all inputs are treated as are electrically isolated from the memory. (Self-discharge
"don't care." If a valid access is in process at the time of in this condition is approximately 0.5% per year.) Follow-
power-fail detection, the memory cycle continues to com- ing the first application of Vee, this isolation is broken,
pletion. If the memory cycle fails to terminate within and the lithium backup provides data retention on
time twPr, write-protection takes place. subsequent power-downs.

Truth Table
Mode CE WE OE I/O Operation Power
Not selected H X X HighZ Standby
Output disable L H H HighZ Active
Read L H L DoUT Active
Write L L X DIN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

Vee DC voltage applied on Vee relative to Vss -0.3 to 7.0 V

VT DC voltage applied on any pin excluding Vee -0.3 to7.0 V VT~Vee+0.3
relative to Vss
ToPR Operating temperature o to +70 °C

TSTG Storage temperature -40 to +70 °C

TRIAS Temperature under bias -10 to +70 °C

TSOLDER Soldering temperature +260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

2/9 Sept. 1990

6-74
 Preliminary bq4025/bq4025Y

Recommended DC Operating Conditions (TA = 0 to 70'C)

Symbol Parameter Minimum Typical Maximum Unit Conditions
4.5 5.0 5.5 V bq4025Y
Vee Supply voltage
4.75 5.0 5.5 V bq4025
Vss Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIH Input high voltage 2.2 - Vee + 0.3 V

Note: Typical values indicate operation at TA = 25'C,

DC Electrical Characteristics (TA = 0 to 70'C, VCCmin ~ VCC ~ VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILl Input leakage current - - ±4 ItA VIN = Vss to Vee

ILO Output leakage current - - ±2 ItA CE = VIH or OE = VIH or
WE=VIL
VOH Output high voltage 2.4 - - V IOH= -1.0 rnA
VOL Output low voltage - - 0.4 V IOL = 2.1 rnA
ISB! Standby supply current - 7 18 rnA CE =VIH

ISB2 Standby supply current - 2.5 5 rnA

CE ~ Vee - 0.2V,
OV:S; VIN :S; 0.2V,
III
or VIN ~ Vee - 0.2V
Icc Operating supply current - 95 200 rnA Min. cycle, duty = 100%,
CE = VIL, II/o = OmA
4.55 4.62 4.75 V bq4025
VPFD Power-fail-detect voltage
4.30 4.37 4.50 V bq4025Y
Vso Supply switch-over voltage - 3 - V

Note: Typical values indicate operation at TA = 25'C, Vee = 5V or VBe = 3V.

CapaCitance (TA = 2S'C, F = 1MHz, VCC = S.OV)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CI/O Input/output capacitance - - 20 pF Output voltage = OV

CIN Input capacitance - - 40 pF Input voltage = OV

Note: This parameter is sampled and not 100% tested.

Sept. 1990 3/9

6-75
bq4025/bq4025V Preliminary

AC Test Conditions
Parameter Test Conditions
Input pulse levels OVto3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope andjig) See Figures 1 and 2

+5V

1.9Kn 1.9Kn

DOUT

1Kn 100pF 1Kn 5pF

OL-12 OL-13

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = 0 to 70·C, VCCmin <: VCC <: VCCmax)

-85 -120
Symbol Parameter Unit Conditions
Min. Max. Min. Max.
tRC Read cycle time 85 - 120 - ns
tAA Address access time - 85 - 120 ns Output load A
tACE Chip enable access time - 85 - 120 ns Output load A
tOE Output enable to output valid - 45 - 60 ns Output load A
tCLZ Chip enable to output in low Z 5 - 5 - ns Output load B
tOLZ Output enable to output in low Z 0 - 0 - ns Output load B
tcHZ Chip disable to output in high Z 0 35 0 45 ns Output load B
tOHZ Output disable to output in high Z 0 25 0 35 ns Output load B
tOH Output hold from address change 10 - 10 - ns Output load A

4/9 Sept. 1990

6-76
 Preliminary bq4025/bq4025Y

Read Cycle No.1 (Address Access) 1,2

~------------------tRC------------------~

Address

-tAA
~.-----------toH----------1~
14----------1: -~
DOUT ------p-re-v-io-u-s-D-a-ta-Va-li-·d----.... *ZXX --o-at-a-V-a-lid---

RC-1

Read Cycle No.2 (CE Access) 1,3,4

CE

oOUT

RC-2
III
Read Cycle No.3 (OE Access) 1,5

Address

OE
14----- t OE ---~
tOLZ

DOUT -----...,,,.....,...-=------1(
High-Z
Data Valid
High-Z

RC-3

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE = DE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. DE =VIL.
5. Device is continuously selected: CE =VIL.

Sept. 1990 5/9

6-77
bq4025/bq4025Y Preliminary

Write Cycle (TA = 0 to 70'C, VCCmin ~ VCC ~ VCCmax)

-85 ·120 Conditions!
Symbol Parameter Units Notes
Min. Max. Min. Max.

twc Write cycle time 85 - 120 - ns

tcw Chip enable to end of write 75 - 100 - ns (1)

tAW Address valid to end of write 75 - 100 - ns (1)

tAB Address setup time 0 - 0 - ns Measured from address valid to begin-

ning of write. (2)
twp Write pulse width 65 - 85 - ns Measured from beginning of write to
end of write. (1)
tWRl Write recovery time (write 5 - 5 - ns Measured from WE going high to end
cycle 1) of write cycle. (3)
tWR2 Write recovery time (write 15 - 15 - ns Measured from CE going high to end of
cycle 2) write cycle. (3)
tDW Data valid to end of write 35 - 45 - ns Measured to first low-to-high transi-
tion of either CE or WE.
tDHl Data hold time 0 - 0 - ns Measured from WE going high to end
(write cycle 1) of write cycle. (4)
tDH2 Data hold time 10 - 10 - ns Measured from CE going high to end of
(write cycle 2) write cycle. (4)
twz Write enabled to output in 0 30 0 40 ns 110 pins are in output state. (5)
high-Z
tow Output active from end of 0 - 0 - ns 1/0 pins are in output state. (5)
write

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overla~ a low CE and a low WE. A write begins at the later
transition of CE going low and WE going low.
3. Either twRl or twR2 must be met.
4. Either tDHl or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.

6/9 Sept. 1990

6-78
 Preliminary bq4025/bq4025Y

Write Cycle No. 1 (WE-Controlled) 1,2,3

~----------------twe----------------~

Address

~------------- tAW ------------~l--tWR1

~......._"T""_..._J""""' ~------------ tew - - - - - - - - - - - - - - . j ,..--,---.,..-r----r-""'........,.--7

CE
1 4 - - - - twp ------.j

WE

14----tDW - - - -....-

D..

DOUT
HiQh-ZX
tow =6
WC-3

Write Cycle No.2 (CE-Controlled) 1,2,3,4,5

III
Address

--t.U-"'~14f---_t~:~_w_e- -=- - =- - =-~-*-j. '-}~-

CE

~-----twp----------~

WE

~--tDW - - - - . . - -
------------~----------~
Data-in Valid

DOUT

WC-4
Notes: l. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. IfOE is high, the I/O pins remain in a state of high impedance.
4. Either tWRl or tWR2 must be met.
5. Either tDHl or tDH2 must be met.
Sept. 1990 7/9

6-79
bq4025/bq4025Y Preliminary

Power-Down/Power-Up Cycle (TA = 0 to 70·C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tPF Vee slew, 4.75 to 4.25 V 300 - - I.ls

tFs Vee slew, 4.25 to Vso 10 - - I.ls
tpu Vee slew, Vso to VPFD (max.) 0 - - I.ls
Time during which SRAM is
tcER Chip enable recovery time 40 80 120 ms write-protected after Vee
passes VPFD on power-up.
tDR Data-retention time in 5 years TA = 25°C (2)
absence of Vee
Delay after Vee slews down
tWPI' Write-protect time 40 100 150 I.ls past VPFD before SRAM is
write-protected.

Note: 1. Typical values indicate operation at TA = 25°C, Vee = 5V.

2. Batteries are disconnected from circuit until after Vee is applied for the fIrst time. tDR is the
accumulated time in absence of power beginning when power is fIrst applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -O.3V in battery-backup mode
may affect data integrity.

Power-Down/Power-Up Timing

4.75

Vee

t-sr~ t~j
CE

========~
PD-B

8/9 Sept. 1990

6·80
 Preliminary bq40251bq4025Y

Ordering Information

bq4025 MB-

Lspeed Options:
85= 85ns
120 = 120 ns

Package Option:
MB = B-type module

Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

-Device:
bq4025 256K x 16 NVSRAM

III

Sept. 1990 9/9

6-81
Notes

6·82
Introduction 1

Processor Management 2

Energy Management 3

Static RAM Nonvolatile eontrollers 4

Real-Time Clocks £)

Nonvolatile Static RAMs 6

Package Drawings 7

Sales Offices and Distributors 8

~ BENCHMARQ _ _ _ _p_ac_ka---=g::..-e_D_rawl
__ ·n~g=_s

MA: 28-Pin A-Type Module

28-pin MA (A-type module)
o '--'

1
o
Dimension Minimum Maximum
A
Al
B
C
0.365
0.015
0.017
0.008
0.375
-
0.023
0.013
Units
inches
inches
inches
inches
D 1.470 1.500 inches
E 0.710 0.740 inches
e 0.590 0.630 inches
G 0.090 0.110 inches
L 0.120 0.150 inches
S 0.075 0.110 inches

-
MA: 32-Pin A-Type Module
32-pin MA (A-type module)
o'CJ
Dimension Minimum Maximum Units
A 0.365 0.375 inches
Al 0.015 - inches
B 0.017 0.023 inches
o C 0.008 0.013 inches
D 1.670 1.700 inches
E 0.710 0.740 inches
e 0.590 0.630 inches
G 0.090 0.110 inches
L 0.120 0.150 inches
S 0.075 0.110 inches

7-1
Package Drawings

MA: 40-Pin A-Type Module

40-pin MA (A-type module)
o '-./

1
Dimension Minimum Maximum Units
A 0.365 0.375 inches
A1 0.015 - inches
B 0.017 0.023 inches
C 0.008 0.013 inches
D
D 2.070 2.100 inches
E 0.710 0.740 inches
e 0.590 0.630 inches
G 0.090 0.110 inches
L 0.120 0.150 inches
S 0.075 0.110 inches

MB: 32-Pin B-Type Module

Package dimensions to be determined; contact sales office or factory.

7-2
 Package Drawings

MB: 40-Pin B-Type Module

Package dimensions to be determined; contact sales office or factory.

-
MT: 24-Pin T-Type Module
24-pin MT (T-type module)
o '-J Dimension Minimum Maximum Units
A 0.360 0.375 inches
Al 0.015 - inches
B 0.015 0.022 inches
o C 0.008 0.013 inches
D 1.320 1.335 inches
E 0.685 0.700 inches
e 0.590 0.620 inches
G 0.090 0.110 inches
L 0.120 0.130 inches
S 0.100 0.120 inches

7-3
Package Drawings

SN: a-Pin SOIC Narrow

8-pin SOIC Narrow (SN)
e
~

BH
Dimension Minimum Maximum Units

t
[l
A 0.060 0.070 inches
0 Al 0.004 0.010 inches
B 0.013 0.020 inches
t C 0.007 0.010 inches

~ ~
E
t D 0.185 0.200 inches
E 0.150 0.160 inches
e 0.045 0.055 inches
H H 0.225 0.245 inches
L 0.015 0.035 inches

A
C
A1 t
L~ i
t t 10.004 1
~~ L

SN: 16-Pin SOIC Narrow

16-pin SOIC Narrow (SN)
Dimension Minimum Maximum Units
A 0.060 0.070 inches
Al 0.004 0.010 inches
B
B 0.013 0.020 inches
C 0.007 0.010 inches
D 0.385 0.400 inches
E 0.150 0.160 inches
e 0.045 0.055 inches
H 0.225 0.245 inches
L 0.015 0.035 inches

A
C A1 :
t ~-=-==F=-+.----r~_
t II \0.004\
-j~L

7-4
 Package Drawings

S: 24-Pin sOle
24-pin sOle (S)
Dimension Minimum Maximum Units
A 0.095 0.105 inches
B Al 0.004 0.012 inches
B 0.013 0.020 inches
C 0.008 0.013 inches
D 0.600 0.615 inches
E 0.290 0.305 inches
e 0.045 0.055 inches
H 0.395 0.415 inches
L 0.020 0.040 inches
E
H
A
C

i !
A1
L~ ~
t t 10.0041
~~ L

PN: 8-Pin DIP Narrow

-
8-pin DIP Narrow (PN)
Dimension Minimum Maximum Units
A 0.160 0.180 inches
Al 0.015 0.040 inches
B 0.015 0.022 inches
B1 0.055 0.065 inches
C 0.008 0.013 inches
D 0.350 0.380 inches
E 0.300 0.325 inches
E1 0.230 0.280 inches
e 0.300 0.370 inches
G 0.090 0.110 inches
L 0.115 0.150 inches
S 0.020 0.040 inches

7-5
Package Drawings

PN: 16-Pin DIP Narrow

16-pin DIP Narrow (PN)
Dimension Minimum Maximum Units
A 0.160 0.180 inches
A1 0.015 0.040 inches
B 0.015 0.022 inches
B1 0.055 0.065 inches
C 0.008 0.013 inches
D 0.740 0.770 inches
E 0.300 0.325 inches
E1 0.230 0.280 inches
e 0.300 0.370 inches
G 0.090 0.110 inches
L 0.115 0.150 inches
S 0.020 0.040 inches

PN: 24-Pin DIP Narrow

24-pin DIP Narrow (PN)
Dimension Minimum Maximum UnIts
A 0.160 0.190 inches
A1 0.015 0.040 inches
B 0.015 0.022 inches
B1 0.045 0.055 inches
C 0.008 0.013 inches
D 1.240 1.280 inches
E 0.300 0.325 inches
E1 0.250 0.300 inches
e 0.300 0.370 inches
G 0.090 0.110 inches
L 0.115 0.150 inches
S 0.070 0.090 inches

7-6
 Package Drawings

P: 24-Pin DIP
24-pin DIP (P)
Dimension Minimum Maximum Units
A 0.160 0.190 inches
Al 0.015 0.040 inches
B 0.015 0.022 inches
B1 0.045 0.065 inches
C 0.008 0.013 inches
D 1.240 1.280 inches
E 0.600 0.625 inches
E1 0.530 0.570 inches
e 0.600 0.670 inches
G 0.090 0.110 inches
L 0.115 0.150 inches
S 0.070 0.090 inches

-
P: 28-Pin DIP
28-pin DIP (P)
(0 '-J
(
Dimension Minimum Maximum Units
A 0.160 0.190 inches
Al 0.015 0.040 inches
B 0.015 0.022 inches
o B1 0.045 0.065 inches
C 0.008 0.013 inches
D 1.440 1.480 inches
E 0.600 0.625 inches
E1 0.530 0.570 inches
e 0.600 0.670 inches
G 0.090 0.110 inches
r-- L 0.115 0.150 inches
S 0.070 0.090 inches

7-7
Package Drawings

P: 40-Pin DIP
40-pin DIP (P)
Dimension Minimum Maximum Units
A 0.160 0.190 inches
Al 0.015 0.040 inches
B 0.015 0.022 inches
B1 0.045 0.055 inches
C 0.008 0.013 inches
D 2.040 2.080 inches
E 0.600 0.625 inches
E1 0.530 0.570 inches
e 0.600 0.670 inches
G 0.090 0.110 inches
L 0.115 0.150 inches
S 0.070 0.090 inches

Q: 28-Pin Quad PLCC

28-pin Quad PLCC (Q)
Dimension Minimum Maximum Units
A 0.165 0.180 inches
L·045 Al 0.020 - inches

-'-:D~
~1
f
DIE 81
~ ====+i'
D2/E2
B
B1
0.012
0.025
0.021
0.033
inches
inches
C 0.008 0.012 inches
t D 0.485 0.495 inches

~~e
B
D1 0.445 0.455 inches
D2 0.390 0.430 inches
E 0.485 0.495 inches
E1 0.445 0.455 inches

tmrnm~J~~.------.
E2 0.390 0.430 inches
e 0.045 0.055 inches

10.0041If
A1

7-8
 Package Drawings

Q: 44-Pin Quad PLCC

44-pin Quad PLCC (Q)
Dimension Minimum Maximum Units
A 0.165 0.180 inches
Al 0.020 - inches
B 0.012
--_.- .- 0.021 inches
Bl 0.025 0.033 inches
C 0.008 0.012 inches
D 0.685 0.695 inches
D1 0.645 0.655 inches
D2 0.590 0.630 inches
E 0.685 0.695 in_~
El 0.645 0.655 inches
E2 0.590 0.630 inches
e 0.045 0.055 inches
Al

7-9
Notes
Introduction 1

Processor Management 2

Energy Management 3

Static R~M Nonvolatile ~ontrolters 4.

Real·Time ~Iocks 5

Nonvolatile Static R~Ms 6

Package Drawings 7;

Sales Offices and Distributors 8

~ BENOWARQ Sales Offices and Distributors

Sales Offices Colorado

Straube Associates Mountain States, Inc.
Alabama 7970 Sheridan Blvd., Suite C
Westminster, CO 80003
The Novus Group (303) 426-0890
2905 Westcorp Blvd., Suite 120 FAJe(303) 426-0896
Huntsville, AL 35805
(205) 534-0044
FAJe(205)534-0186 Connecticut
CompRep Associates Inc.
Arizona 117 Church Street
Wallingford, CT 06492
Quatra Associates, Inc. (203) 269-1145
4645 South Lakeshore Drive, Suite #1 FAJe(203) 269-2819
Tempe, AZ 85281
(602) 820-7050
FAJe(602)820-7054
Delaware
Tritek Sales Inc.
Arkansas 21 East Euclid Avenue
Haddonfield, NJ 08033
Mil-Rep Associates, Inc. (609) 429-1551
1701 N. Greenville Ave., Suite 1008 FAJe (609) 429-4915
Richardson, TX 75081
(214) 644-6731
FAJe (214) 644-8161
District of Columbia
New Era Sales
California (North) 678 Ritchie Highway
Severna Park, MD 21146
Criterion Sales Inc. (301) 544-4100
3350 Scott Blvd., Building #44 FAJe(301) 544-6092
Santa Clara, CA 95054
(408) 988-6300
FAJe(408)986-9039 Florida
Sales Engineering Concepts, Inc.
California (South) 776 S. Military Trail
Deerfield Beach, FL 33442
H-Technical Sales II (305) 426-4601
25201 Paseo de Alicia, Suite 106 FAJe(305) 427-7338
Laguna Hills, CA 92653
(714) 583-1488 Sales Engineering Concepts, Inc.
FAJe(714)583-9284 901 Douglas Avenue, Suite 200
Altamonte Springs, FL 32714
Addem (407) 682-4800
1015 Chestnut Avenue, Suite F2 FAJe(407) 682-6491
Carlsbad, CA 9208 (San Diego)
(619) 729-9216
FAJe(619)729-6408

8-1
Sales Offices and Distributors

Sales Engineering Concepts, Inc. Kansas

11902 Racetrack Road
Tampa, FL 33625 Advanced Technical Sales
(407) 682-4800 601 N. Mur-Len
Suite 8
Olathe, KS 66062
Georgia (913) 782-8702
FlLK(913) 782-8641
The Novus Group
6115-A Oakbrook Parkway
Norcross, GA 30093 Kentucky
(404) 263-0320
FlLK(404) 263-8946 Rathsburg Associates Inc.
34605 Twelve Mile Road
Farmington Hills, MI 48331-3263
Illinois (North) (313) 489-1500
FlLK(313) 489-1480
Micro Sales, Inc.
901 Hawthorn Drive
Itasca, IL 60143 Louisiana (North)
(708) 285-1000
FlLK(708) 285-1008 Mil·Rep Associates, Inc.
1701 N. Greenville Ave.
Suite 1008
Illinois (South) Richardson, TX 75081
(214) 644-6731
Advanced Technical Sales FlLK(214) 644-8161
1810 Craig Road
Suite 213
St. Louis, MO 63146 Louisiana (South)
(314) 878-2921
FlLK(314) 878-1994 Mil·Rep Associates, Inc.
6111 FM 1960 W.
Suite 213
Indiana Houston, TX 77069
(713) 444-2557
Rathsburg Associates Inc. FlLK(713) 444-2751
7706 Madden Drive
Fishers, IN 46038
(317) 577-4500 (Indiana phone #) Maine
FlLK(317) 578-0727
CompRep Associates Inc.
100 Everett Street
Iowa Westwood, MA 02090
(617) 329-3454
Advanced Technical Sales FlLK (617) 329-6395
375 Collins Road, N.E.
Cedar Rapids, IA 52402
(319) 393-8280 Massachusetts
FlLK(319) 393-8273
CompRep Associates Inc.
100 Everett Street
Westwood, MA 02090
(617) 329-3454
FlLK(617) 329-6395
 Sales Offices and Distributors

Maryland Nebraska
New Era Sales Advanced Technical Sales
678 Ritchie Highway 601 N. Mur-Len
Severna Park, MD 21146 Suite 8
(30l) 544-4100 Olathe, KS 66062
FAJe(301)544-6092 (913) 782-8702
FAJe(913) 782-8641

Michigan
Nevada (North)
Rathsburg Associates Inc.
34605 Twelve Mile Road Criterion Sales Inc.
Farmington Hills, MI 48331-3263 3350 Scott Blvd.
(313) 489-1500 Bldg. #44
FAJe(313)489-1480 Santa Clara, CA 95054
(408) 988-6300
FAJe (408) 986-9039
Minnesota
Vector Component Sales Nevada (Clark County)
310 1 Old Highway 8
Suite 202 Quatra Associates, Inc.
Roseville, MN 55113 4645 South Lakeshore Drive, Suite #1
(612) 631-1334 Tempe, AZ 85281
FAJe(612)631-1329 (602) 820-7050
FAJe(602) 820-7054

Mississippi
New Hampshire
The Novus Group
2905 Westcorp Blvd. CompRep Associates Inc.
Suite 120 100 Everett Street
Huntsville, AL 35805 Westwood, MA 02090
(205) 534-0044 (617) 329-3454
FAJe(205)534-0186 FAJe (617) 329-6395

Missouri (East) New Jersey (North)

Advanced Technical Sales
1810 Craig Road
Suite 213
St. Louis, MO 63146
(314) 878-2921
FAJe(314)878-1994
Metro Logic Corporation
271 Route 48 West
SuiteD202
Fairfield, NJ 07006
(201) 575-5585
FAJe(201) 575-8023
-
Missouri (West) New Jersey (South)
Advanced Technical Sales Tritek Sales Inc.
601 N. Mur-Len 21 East Euclid Avenue
Suite 8 Haddonfield, NJ 08033
Olathe, KS 66062 (609) 429-1551
(913) 782-8702 FAJe(609) 429-4915
FAJe (913) 782-8641

8-3
Sales Offices and Distributors

New Mexico North Dakota

Quatra Associates, Inc. Vector Component Sales
9704 Admiral Dewey NE 3101 Old Highway 8
AJbuquerque,Nrnd 87111 Suite 202
(505) 821-1455 Roseville, MN 55113
(612) 631-1334
FAJ{(612) 631-1329
New York
Metro Logic Corporation Ohio
271 Route 48 West
Suite D202 Rathsburg Associates Inc.
Fairfield, NJ 07006 34605 Twelve Mile Road
(201) 575-5585 Fannington Hills, MI 48331-3263
FAJ{(201) 575-8023
Rathsburg Associates Inc.
Tri-Tech Electronics Inc. Cleveland
300 Main Street (216) 582-9550
East Rochester, NY 14445 FAJ{(216) 582-9547
(716) 385-6500
FAJ{(716) 385-7655
Rathsburg Associates Inc.
Columbus
Tri-Tech Electronics Inc. (614) 866-2490
3215 E. Main Street FAJ{ (614) 866-9041
Endwell, NY 13760
(607) 754-1094
FAJ{ (607) 785-4557 Oklahoma
Tri-Tech Electronics Inc. Mil-Rep Associates, Inc.
6836 E. Genesee Street 1701 N. Greenville Avenue
Fayetteville, NY 13066 Suite 1008
(315) 446-2881 Richardson, TX 75081
FAJ{ (315) 446-3047 (214) 644-6731
FAJ{(214) 644-8161
Tri-Tech Electronics Inc.
14 Westview Drive
Fishkill, NY 12524 Oregon
(914) 897-5611
FAJ{(914) 897-5611 Electra Technical Sales
6700 SW 105th Avenue
Suite 300
North Carolina Beaverton, OR 97005
(503) 643-5074
The Novus Group FAJ{ (503) 526-2055
102-L Commonwealth Court
Cary, NC 27511
(919) 460-7771 Pennsylvania (West)
FAJ{ (919) 460-5703
Rathsburg Associates Inc.
34605 Twelve Mile Road
Fannington Hills, Ml48331-3263
(313) 489-1500
FAJ{(313) 489-1480

8-4
 Sales Offices and Distributors

Pennsylvania (East) Mil-Rep Associates, Inc.

6111 FM 1960 w., Suite 213
Tritek Sales Inc. Houston, TX 77069
21 East Euclid Avenue (713) 444-2557
Haddonfield, NJ 08033 FAJ{ (713) 444-2751
(609) 429-1551
FAJ{(609)429-4915 Mil-Rep Associates, Inc.
1701 N. Greenville Avenue
Suite 1008
Rhode Island Richardson, TX 75081
(214) 644-6731
CompRep Associates Inc. FAJ{(214) 644-8161
100 Everett Street
Westwood, MA 02090
(617) 329-3454 Utah
FAJ{(617)329-6395
Straube Associates Mountain States, Inc.
3509 South Main
South Carolina Salt Lake City, UT 84115
(80l) 263-2640
The Novus Group FAJ{ (801) 261-5846
102-L Commonwealth Court
Cary, NC 27511
(919) 460-7771 Vermont
FAJ{(919)460-5703
CompRep Associates Inc.
100 Everett Street
South Dakota Westwood, MA 02090
(617) 329-3454
Vector Component Sales FAJ{(617) 329-6395
3101 Old Highway 8, Suite 202
Roseville, MN 55113
(612) 631-1334 Virginia
FAJ{(612)631-1329
New Era Sales
678 Ritchie Highway
Tennessee Severna Park, MD 21146
(301) 544-4100
The Novus Group FAJ{(301) 544-6092
6115-A Oakbrook Parkway
Norcross, GA 30093
(404) 263-0320
FAJ{(404)263-8946
Washington III
Electra Technical Sales
11411 NE 124th Street, Suite 285
Texas Kirkland, WA 98034
(206) 821-7442
Mil-Rep Associates, Inc. FAJ{(206) 821-7289
11615 Angus, Suite 112A
Austin, TX 78759
(512) 346-6331 West Virginia
FAJ{(512)346-1975
Rathsburg Associates Inc.
34605 Twelve Mile Road
Farmington Hills, MI 48331-3263
(313) 489-1500
FAJ{(313) 489-1480

8-5
Sales Offices and Distributors

Wisconsin (Southeast) North American Distributor

Micro Sales, Inc.
16800 West Greenfield Avenue, Marshall Industries (all locations)
Brookfield, WI 53005
(414) 786-1403
FAJe(414) 786-1813 Los Angeles (EI Monte), CA
(Headquarters)
Canada 9320 Telstar Avenue
EI Monte, CA91731
Vitel Electronics (818) 407-4100
2235 Gagnon FAJe(818) 307-6187
Lachine, Quebec
Canada H8T 9Z7 Huntsville, AL
(514) 636-5951 (205) 881-9235
FAJe(514) 636-5626
Phoenix,AZ
Vitel Electronics (602) 496-0290
300 March Road
Suite #301 Tucson,AZ
Kanata, Ontario (602) 790-5887
Canada K2K 2E3
(613) 592-0090 Irvine, CA
FAJe(613) 592-0182 (714) 458-5301

Vitel Electronics Sacramento, CA

5925 Airport Road (916) 635-9700
Suite #610
Mississauga, Ontario
Canada L4V lWl San Diego, CA
(416) 676-9720 (619) 578-9600
FAJe (416) 676-0055
San Francisco, CA
Vitel Electronics (408) 942-4600
4211 Kingsway Road
Suite #314 Denver, CO
Burnaby, British Columbia (303) 451-8383
Canada V5M lZ6
(604) 439-1136 Connecticut
FAJe(604) 682-3139 (203)-285-3822

Ft. Lauderdale, FL
Europe (305) 977-4880
Contact Factory
Orlando, FL
(407) 767-8585

Asia/Pacific Tampa,FL
(813) 573-1399
Contact Factory
Atlanta, GA
(404) 923-5750

Chicago, IL
(708) 490-0155
 Sales Offices and Distributors

Indianapolis, IN Dallas, TX
(317) 297-0483 (214) 233-5200

Kansas City, KS EIPaso, TX

(913) 492-3121 (915) 593-0706

Boston,MA Houston, TX
(508) 658-0810 (713) 895-9200

Maryland San Antonio, TX

(301) 622-1118 (512) 734-5100

Michigan Salt Lake City, UT

(313) 525-5850 (801) 485-1551

Minneapolis, MN Seattle, WA
(612) 559-2211 (206) 488-5747

St. Louis, MO Milwaukee, WI

(314) 291-4650 (414) 797-8400

Raleigh,NC In Canada: G.S. Marshall Co.

(919) 878-9882

New Jersey Montreal

(514) 694-8142
(201) 882-0320

Binghamton, NY Ottawa
(613) 564-0166
(607) 798-1611

Long Island, NY Toronto

(416) 458-8046
(516) 273-2424

Rochester, NY Vancouver
(604) 436-0068
(716) 235-7620

-
Cleveland, OH Western Canada
(800) 465-6640
(216) 248-1788

Dayton,OH
(513) 898-4480

Portland, OR
(503) 644-5050

Philadelphia, PA
(609) 234-9100

Pittsburgh, PA
(412) 788-0441

Austin, TX
(512) 837-1991

8-7
~ BENCHMARQ Sales Offices and Distributors

a-a
 ~
BENCHMARQ

2611 Westgrove Drive

Suite 101
Carrollton, Texas 75006
Fax: (214) 407-9845
Tel: (214) 407-0011