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The document discusses the design of an energy efficient 4-bit unsigned hybrid divider using 65nm CMOS technology. It aims to minimize power consumption through optimization at all levels of design including system, algorithm, architecture, and circuit levels. The divider is implemented using hybrid techniques like CMOS, GDI, PTL, and 3TXOR to take advantage of each technique's performance while reducing leakage losses and power consumption.

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33 views1 page

Basepaper Divider

The document discusses the design of an energy efficient 4-bit unsigned hybrid divider using 65nm CMOS technology. It aims to minimize power consumption through optimization at all levels of design including system, algorithm, architecture, and circuit levels. The divider is implemented using hybrid techniques like CMOS, GDI, PTL, and 3TXOR to take advantage of each technique's performance while reducing leakage losses and power consumption.

Uploaded by

sumathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Design of Energy Efficient 4-bit Unsigned Hybrid Divider using

65nm CMOS Technology


ABSTRACT

Power consumption is one of the most importantparameters considered in circuit


design. To minimize thisparameter, optimization at all levels of design abstractionincluding
system, algorithm, architecture, and circuit levels isrequired. Several efforts have been made
to reduceenergy consumption at the circuit level. Some hybrid structuresproposed here for
power and area optimization.using these structures complex circuits can be implemented with
a lownumber of transistors, low area and low power consumption. Due to their special
topologies and technique, these may significantly reduces leakage losses. In modern
technologies by loweringthreshold voltages, the leakage loss is becoming the mainpart of the
total loss; so, the reduction of this loss leads to asignificant reduction of power consumption.
An Unsigned Divider is chosen here with hybrid techniques like CMOS, GDI, PTL,
3TXOR. Each logic has its own advantage in such a way that it bounces back with good
performance. The application is chosen to implement a full custom level layout to implement
at post layout simulation. The design constraints along with the module architecture were
compared to elevate the suitable architecture for high speed applications. The simulation part
is done by using Microwind 3.5.

Under the guidance of

Mrs. V. Krishna Sree, Mr. K. Naresh Submitted By,


G.PUNYALAXMI

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