EFFICIENT DESIGN OF 8-BIT RESTORING DIVIDER USING 65nm
CMOS TECHNOLOGY
ABSTRACT PUN is to provide a connection between the output
and VDD anytime the output of the logic gate is
meant to be 1 (based on the inputs). Similarly the
Power consumption is one of the most important parameters function of the PDN is to connect the output to VSS
considered in circuit design. To minimize this parameter,
optimization at all levels of design abstraction including system,
when the output is meant to be 0. Static logic retains
algorithm, architecture, and circuit levels is required. Several its output level as long as the power is applied.
efforts have been made to reduce energy consumption at the
circuit level. Some hybrid structures proposed here for power
and area optimization. Using these structures complex circuits GDI (Gate Diffusion Input) - a new technique of low
can be implemented with a low number of transistors, low area power digital circuit design is described. This
and low power consumption. Due to their special topologies and technique allows reducing power consumption, delay
technique, these may significantly reduce leakage losses. In
modern technologies by lowering threshold voltages, the leakage
and area of digital circuits, while maintaining low
loss is becoming the main part of the total loss; so, the reduction complexity of logic design.
of this loss leads to a significant reduction of power
consumption. Pass transistor logic (PTL) describes several logic
An Unsigned Divider is chosen here with hybrid techniques like families used in the design of integrated circuits. It
CMOS, GDI, PTL, 3TXOR. Each logic has its own advantage in reduces the count of transistors used to make
such a way that it bounces back with good performance. The different logic gates, by eliminating redundant
application is chosen to implement a full custom level layout to
implement at post layout simulation. The design constraints transistors. Transistors are used as switches to
along with the module architecture were compared to elevate the pass logic levels between nodes of a circuit, instead
suitable architecture for high speed applications. The simulation of as switches connected directly to supply voltages.
part is done by using Micro wind 3.5. [1]
This reduces the number of active devices, but has
the disadvantage that the difference of the voltage
between high and low logic levels decreases at each
1. INTRODUCTION stage.
The efficient design of 8-bit restoring divider using
65nm CMOS Technology and the simulation results
show that the proposed techniques offer low power,
high speed and with high performance than the 2. LITERATURE SURVEY ON
existing designs CMOS and PTL. Non-Restoring and
restoring array divider circuits have been designed EXISTING MODULE
using adder cell and subtractor cell respectively. The
8bit adder cell consists of 16 transistors and mixed Clock Gating:
Shannon based adder cell consists of 12 transistors
compared to CPL28 transistors and CMOS-28 This was by far one of the first techniques to save
transistors. The two different (Non-Restoring and power (and it also results in saving some area due to
Restoring array) 8bit divider circuits have been sharing, however, it makes the design slightly
simulated. Various parameters such as propagation difficult for timing and DFT). The thought here is
delay, power dissipation, PDP have been determined that if a common clock signal is going to hundreds
from array dividers layout of feature size 65nm of flops, a lot of them are retaining their old value,
technology. then we can gate off the clock to such flip flops and
they still retain their old value. This gating off
A static CMOS gate is a combination of two results in lesser toggling in the clock path cells and
networks, the pull up network (PUN) which is thus saves dynamic power. Nowadays, synthesis
constructed using PMOS devices and the pull-down tools identify chunks of flip flops that have a
network (PDN) is constructed using NMOS devices. common structure and common enable of loading
The primary reason for this choice is that NMOS data and covert all such structures into clock gating
transistors produce “strong zeroes” and PMOS cells.
devices generate “strong ones”. The function of the
Power Gating: special scenarios, where one needs a fast wake up of
the Gated domain and wants to avoid reconfiguring
In a practical device/ application, a large portion of the Gated domain. In comparison to other techniques,
the ICs is not in use for a reasonable amount of this method has the fastest wake-up time with state
time. If the power to such a portion of the IC can be machine data being retained.
switched off, it can save a lot of power. This saves
static (leakage) power and can save some dynamic
power as well where the clock was not gated off.
Following are considerations that have to be taken 3. TYPES OF POWER
for such a technique:
a. Complexity for Application Development: One
CONSUMPTION:
of the penalties here is that portion being switch
off shall need to be re-configured by software 3.1 Dynamic (switching) power
after power is switched on power. consumption:
As the name suggests, dynamic power has got
b. Complexities in power Backend Flow: Power something to do with some changes that are
Grid Design, Synthesis, Placement, Clock Tree, occurring in the circuit. There are many nodes in the
Static Timing Analysis c. Complexity in logic circuit that are changing from high to low voltage or
design: Isolation cells, Power Off scheme and low to high voltage. Let’s suppose we consider a
Power on the scheme for the logic going off. node that corresponds to the output of
a CMOS inverter gate.
Dynamic Voltage and Frequency Scaling:
3.2 Short circuit power consumption:
The portion of the circuit requiring higher frequency
can be taken to a higher voltage for the time the A new CMOS short-circuit power consumption is
high-performance mode is required. If the voltage the gate-driving signal of the output pull-up (pull-
levels are different then, one shall need level shifter down) transistor is fed back to the output pull-down
cells in between when the signal crosses a domain. (pull-up) transistor to get tri-state output
Physically, the power grid of each voltage island has momentarily, eliminating the short-circuit power
to be done separately. A careful sequence has to be consumption, The HSPICE simulation results
followed as the voltage and frequency are changed. verified the operation of the proposed buffer and
A safe approach shall be to keep a frequency fixed showed the power-delay product is about 15%
and increase voltage first. After Voltage is smaller than conventional tapered CMOS buffer.
increased, then the frequency canbe increased.
Timing fixes shall need to be done for both voltage 3.3 Static (leakage) power consumption:
scenarios. Nowadays, almost all laptops use similar
techniques to increase performance when connected
with the mains by default. Normally the default Static Power Consumption The static
power saving options, also reduce the performance power dissipation is due to the leakage currents.
level to save battery life (when the device is The static or steady state power dissipation of the
operated in battery mode). circuit is given by, Pstat = Ileakage VDD where I
leakage is the leakage current that flows between
VDD and ground in the absence of switching
RPG:
activity.
This technique has an advantage over Power Gating
that, one can retain the value of the state machine in
the Gated Power domain. However, this is a more 4. PROPOSED DESIGN:
complex technique and requires higher overhead in
terms of area and implementation. In this case,
special flip flops are used in the Power Gated As the proposed techniques reduce the power delay
domain. These flip flops, in addition to the power of product toa larger extent, these circuits can be used
the Gated domain, shall have continuous power as as the building blocks of DSP processors for higher
well. Also, they have logic internally to store the state energy efficiency. As we are going to ultra deep sub-
of the flip flop when the power is switched off. Due micron technology and nano-technology, where
to area and routing overheads, this is used in very leakage power is significant, leakage power must be
considered, as in these technologies leakage power is 6.1 DESIGN MODULES:
higher than the dynamic power dissipation. Other
scope is to investigate the effect of PVT (Process,
voltage & temperature)variations
ontheproposedcircuitsandtobuildvariationresilientcirc MULTIPLEXER CIRCUIT DESIGN:
uits.Various parameters such as propagation delay,
power dissipation,PDP have been determined from The multiplexer is a combinational logic circuit
array dividers layout of feature size 65nm designed to switch one of several input lines to a
technology. The efficient design of 8-bit restoring single common output line. Multiplexing is the
divider using 65nm CMOS Technology and the generic term used to describe the operation of
simulation results show that the proposed techniques sending one or more analogue or digital signals over
offer low power, high speed and with high a common transmission line at different times or
performance than the existing designs CMOS and speeds and as such, the device we use to do just that
PTL. Restoring array divider circuits have been is called a Multiplexer. Multiplexers, or MUX’s,
designed using adder cell and subtract or cell can be either digital circuits made from high speed
respectively. The efficient design of 8 bit restoring logic gates used to switch digital or binary data or
divider using 65nm CMOS Technology has been they can be analogue types using transistors,
simulated. MOSFET’s or relays to switch one of the voltage or
current inputs through to a single output.
Conventional efficient design of 8 bit restoring
dividers require various divider hardware
configurations to achieve distinct energy–quality
trade-off points, which decreases the hardware
flexibility, especially for modern embedded
systems. READ accomplishes energy efficiency
while meeting the dynamically varying accuracy
requirements of the targeted application. READ uses
reconfigurable subtractor cells that can work in
either accurate or approximate mode using Fig6.1: Multiplexer Circuit Design.
subtractor cell controller logic. The logic is used in
the circuits basically affect the speed, area,
capacitance and delays and complexity of the 6.2 MULTIPLEXER SWITCHING
circuit. Two important characteristics of CMOS are DESIGN:
high noise immunity and static low static power
consumption. Since one transistor of the pair is
The rotary switch, also called a wafer switch as each
always off, the series combination draws significant
layer of the switch is known as a wafer, is a
power only momentarily during switching between
mechanical device whose input is selected by rotating
on and off states.
a shaft. In digital electronics, multiplexers are also
known as data selectors because they can “select”
each input line, are constructed from individual
Analogue Switches encased in a single IC package as
opposed to the “mechanical” type selectors such as
normal conventional switches and relays.
Generally, the selection of each input line in a
multiplexer is controlled by an additional set of
inputs called control lines and according to the binary
condition of these control inputs, either “HIGH” or
“LOW” the appropriate data input is connected
directly to the output. Normally, a multiplexer has an
even number of 2n data input lines and a number of
“control” inputs that correspond with the number of
data inputs.
Fig: Efficient Conventional Design of 8bit Restoring Divider
Fig.6.2: Multiplexing Switch Design
MULTIPLEXER TRUTH TABLE: Fig 6.2.1: Subtract or with Multiplexer Switching
Design.
6.3 CMOS DIVIDER CIRCUIT:
CMOS divider circuits were used for these elements
to maintain a compact design. A 4.8–6.8GHz phase-
locked loop with power optimized design
methodology for dividers before applying to CMOS
divider circuits.
Fig.6.2.1: Simulation of Multiplexer
6.2.1 SUBTRACTOR WITH
MULTIPLEXER
SWITCHING DESIGN:
Generally, the selection of each input line in a
multiplexer is controlled by an additional set of
inputs called control lines and according to the binary Fig 6.3: CMOS Divider Circuit.
condition of these control inputs, either “HIGH” or
“LOW” the appropriate data input is connected
directly to the output. Normally, a multiplexer has an 6.4 GDI (GATE DIFFUSION INPUT):
even number of 2n data input lines and a number of
“control” inputs that correspond with the number of GDI technique that can be used to design fast, low
data inputs. Encoders are able to switch an n-bit input power circuits using only a few transistors.
pattern to multiple output lines that represent the The GDI cell is similar to a CMOS inverter
binary coded (BCD) output equivalent of the active structure. In a CMOS inverter the source of the
input. PMOS is connected to VDD and the source of
NMOS is grounded. But in a GDI cell this might not
necessarily occur.
Fig 6.4: Gate Diffusion Input Circuit Design.
6.5 GATE DIFFUSION INPUT BASED
Fig6.6: Exact cell Divider Circuit Design.
MULTIPLEXER:
Gate Diffusion Input (GDI) is a new technique of a 6.7 EXACTCELL CMOS DESIGN:
low-power digital combinatorial circuit design. This
allows reducing power consumption, propagation To generate the exact minimum cell transistor
delay, and area of digital circuits while maintaining placement, our approaches are the first exact method
low complexity of logic design. Performance which can be applied to CMOS cells with any types
comparison with traditional CMOS and various of structure.The cell formation problem (CFP)
pass-transistor logic design techniques is presented. consists in an optimal grouping of the given
machines and parts into cells, so that machines in
every cell process as much as possible parts from
this cell (intra-cell operations) and as less as
possible parts from other cells (inter-cell
operations). The grouping efficacy is the objective
function for the CFP which simultaneously
maximizes the number of intra-cell operations and
minimizes the number of inter-cell operations.
Currently there are no exact approaches suggested
for solving the CFP with the grouping efficacy
objective.
Fig 6.5: Gate Diffusion Input Based Multiplexer
6.6 EXACTCELL DIVIDER CIRCUIT DESIGN:
In Exact cell Divider Circuit Design; non dual
CMOS cells occupy a major Part of an industrial
standard-cell library. To generate the exact
minimum cell transistor placement, our approaches
are the first exact method which can be applied to
CMOS cells with any types of structure.
Fig6.7.1: Exact cell CMOS Design
incompatible features for small errors. By processing
of existing techniques, we can take the area problem,
area, power consumption.
6. CONCLUSION AND FUTURE
SCOPE:
As the proposed techniques reduce the power delay
product toa larger extent, these circuits can be used
Fig6.7.2: Design of Exact cell CMOS as the building blocks of DSP processors for higher
energy efficiency. As we are going to ultra deep sub-
6.8 PTL (PASS TRANSISTOR LOGIC) micron technology and nano-technology, where
leakage power is significant, leakage power must be
considered, as in these technologies leakage power is
PTL SUBTRACTOR: higher than the dynamic power dissipation. Other
scope is to investigate the effect of PVT (Process,
Pass Transistor Subtract or (PTL) technique voltage & temperature)variations
consumes less power. The PTL Subtractor circuit is ontheproposedcircuitsandtobuildvariationresilientcirc
designed and simulated using DSCH 3.1 and Micro uits.Various parameters such as propagation delay,
wind 3.1 on 120nm. The power estimation and power dissipation,PDP have been determined from
simulation of layout has been done for the proposed array dividers layout of feature size 65nm
PTL Subtractor design. This has been proven power technology. The efficient design of 8-bit restoring
efficient as compared to design the efficient Pass divider using 65nm CMOS Technology and the
Transistor logic design. simulation results show that the proposed techniques
offer low power, high speed and with high
performance than the existing designs CMOS and
PTL. Restoring array divider circuits have been
designed using adder cell and subtractor cell
respectively. The efficient design of 8 bit restoring
divider using 65nm CMOS Technology has been
simulated.
The proposed Shannon adder based Non-Restoring
array divider circuit has a reduced power dissipation
of 82.77%, a reduced propagation delay of 44.12%
and a reduced PDP of 90.37% compared with
Fig 6.8: PTL Subtractor design CMOS based array divider circuits due to lower
critical path in the proposed adder cell. Similarly,
Restoring array divider circuit has a reduced power
dissipation of 66.09%, a reduced propagation delay
5. PROBLEM STATEMENT: of 28.88% and a reduced PDP of 75.98% compared
with CMOS based array divider circuits. As the
Every application doesn’t need an accurate proposed techniques reduce the power delay product
computation unless it is very sensitive to errors. Old to a larger extent, these circuits can be the proposed
computers have memory problems but they are Shannon adder based Non-Restoring array divider
reduced by present day computers but still there is a circuit has a reduced power dissipation of 82.77%, a
problem occurred here which, is Energy reduced propagation delay of 44.12% and a reduced
Consumption. Complex designs require more space PDP of 90.37% compared with CMOS based
in the implementation process for accurate designs; array divider circuits due to lower critical path in
area can be tradeoff for small errors in the design the proposed adder cell. Similarly, Restoring array
which may not affect the functionality. By using divider circuit has a reduced power dissipation of
these, every application does not need an accurate 66.09%, a reduced propagation delay of 28.88% and
computation and using these accurate designs, area a reduced PDP of 75.98% compared with CMOS
can be a balance achieved between two desirable but based array divider circuits.
