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Ncku-Es Introduction To Digital IC Design Fall 2017

This document provides instructions for a lab assignment on implementing a multiply and accumulate (MAC) circuit. Students are asked to design a MAC module that takes in two 4-bit inputs, multiplies them, and accumulates the results over multiple cycles. The design must include inputs for the two operands, a clock, reset, and control signals to indicate valid input values. It must output an 11-bit accumulated result and a signal to indicate a valid output after 8 MAC operations. Pipeline registers should be added to improve timing. Students must submit their Verilog code, testbench, waveform analysis, and screenshots in a compressed folder by the given deadline.

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69 views

Ncku-Es Introduction To Digital IC Design Fall 2017

This document provides instructions for a lab assignment on implementing a multiply and accumulate (MAC) circuit. Students are asked to design a MAC module that takes in two 4-bit inputs, multiplies them, and accumulates the results over multiple cycles. The design must include inputs for the two operands, a clock, reset, and control signals to indicate valid input values. It must output an 11-bit accumulated result and a signal to indicate a valid output after 8 MAC operations. Pipeline registers should be added to improve timing. Students must submit their Verilog code, testbench, waveform analysis, and screenshots in a compressed folder by the given deadline.

Uploaded by

devi noor endrawati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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NCKU-ES

Introduction to Digital IC Design


Fall 2017

Lab4

Multiply and Accumulation

Professor : Wen-Long Chin


TA : Cheng-Chieh Chang、
Chieh-sheng Cheng
VLSI signal processing LAB

1
 Objectives

 To implement the basic circuits of DSP operation

 LAB contents
 LAB4: Multiply and Accumulation

2
 Design Description
 Please design a Multiply and Accumulation(MAC) with two 4-
bits inputs.
 Block Diagram

4 11

 Specifications
 Top module name : mac (File name: mac.v)
 Input pins: in_a[3:0], in_b[3:0], in_valida, in_validb, reset, clk
 Output pins: mac_out[10:0], out_valid,
 All inputs and outputs are synchronized at clock positive edge.
 It is synchronous-reset architecture, both outs become 0 when the
reset equal to 1.
 Note that in_a, in_b are 4-bits signed integer number. Please
design the circuit without overflow.
 The two operands are valid when the control signals “in_valida”
and “in_validb” are 1, respectively.
 After 8 MACs, output the result and assert the “out_valid” signal
 Note that two control signals are in a “one-to-one” manner, so you
do not have to buffer the operands.

3
 In order to decrease the critical path, insert a retiming D-
FF(introduce one more pipeline stage) at the output of the
multiplier.
 Note

 本測驗提供測試程式(testbench)，各位同學之作業需能通過

testbench 的驗證

 書面報告(report.doc）需包含：
(請詳細描述原理及分析波型)
1. 設計原理(Design principle)
2. 架構設計(Architecture)
3. 波型(Waveform)分析
4. 通過測試的截圖，如下

 書面報告請勿手寫

 評分標準依是否達到題目要求各事項，未達到要求依項扣分

 繳交的作業資料夾組織與命名請與下頁圖示相同

 作業繳交至 Moodle

 上傳截止日期: 2017/11/22(三) 23:55

請務必於上傳截止日期前繳交作業

4
 Directory Organization

學號_LAB4_v 版本編號（壓縮檔）
Ex:E94991344_LAB4_v1.rar

LAB4 report.doc

mac.v、mac_tb.v、pattern_in、
golden.dat

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