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Secondary PG Routing Using NanoRoute

The document provides recommendations for improving secondary power grid routing (SPGR) quality by controlling resistance, NanoRoute settings, and route robustness. It suggests using the least resistive metal layers for SPGR, specifying via lists and wire shapes in NanoRoute, and controlling the AON power net source and fanout. It also provides guidance for placing AON buffers/inverters and validating SPGR quality by summing wire lengths.

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pragya mita
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1K views2 pages

Secondary PG Routing Using NanoRoute

The document provides recommendations for improving secondary power grid routing (SPGR) quality by controlling resistance, NanoRoute settings, and route robustness. It suggests using the least resistive metal layers for SPGR, specifying via lists and wire shapes in NanoRoute, and controlling the AON power net source and fanout. It also provides guidance for placing AON buffers/inverters and validating SPGR quality by summing wire lengths.

Uploaded by

pragya mita
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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5/27/2019 Secondary PG Routing Using NanoRoute

Secondary PG Routing Using NanoRoute

Problem
Secondary power grid routing (SPGR) is critical to design scenarios of nested power domains where always-on buffers/
inverters are added at every stage of optimization. Standard cell libraries having always-on buffers/inverters with
secondary power pins need to be hooked up to the corresponding the power net as per power intent provided in
1801/CPF format. This article is about recommendations/guidelines to improve the SPGR quality.

Solution
Strategy: Resistance Requirement, NanoRoute Settings and Route Robustness

Take into account resistance of each metal layer to be used for eg. if M2,M3,M4, M5 and M6 are going to be used
for SPGR, identify one horizontal and one vertical layer with least resistance that will constitute majority of wires
connecting AON power source to the secondary power pin of standard cell.
User can specify the choice of VIA list through add_ndr command and associate with NanoRoute setting to use
VIA stack from, say, M4 to M1/M2 and WIRE shapes on M6 and M5.
add_ndr -name spg_ndr -width {m5:m6 width} -spacing {m5:m6 width} -via {VIA LIST}

setAttribute -net <AON-net> -top_routing_layer M6 -bottom_routing_layer M5 -


preferred_routing_layer_effort high -pattern trunk -stack_distance 0.001 -
min_stack_layer 4 -non_default_rule spg_ndr

Controlling the source stripe - You can use following setting to specify AON power net source is on top metal M6 :
setNanoRouteMode -routeStripeLayerRange {6:6}

Controlling number of AON connections from single source tap – fanout of one being most robust :
routePGPinUseSignalRoute -nets <AON-net> -pattern trunk -maxFanout <fanout>

It is recommended to do one round of SPGR connections before the design enters into route stage, as, plenty of
routing resources are available.
To retain SPGR shapes from being modified through PnR, below command set can be used:
deselectAll

editSelect -net <AON-net-name> -status routed -type Regular

editSelectVia -net <AON-net-name> -status routed -type Regular

editSelect -net <AON-net-name> -status routed -type Patch

editChangeStatus -to FIXED

deselectAll

As secondary PG routing wires are fixed, it is recommended to mark the related AON cells also as fixed. Use
the following command to mark the instances related to a given secondary PG net as fixed:
dbSet [dbget top.insts.pgCellTerms.name <secondary-power-pin-name> -p2].pStatus
fixed

Guidance for AON buffers/inverters for DRC sensitive design

Free movement of AON buffers/inverters is not possible in quite a few design.


We can perform the guided placement of AON buffers/inverters through constraints on the corresponding library
cells. Following constraint avoids any AON buffer/inverter to be placed within few microns away from AON-net
stripe of the layer metal6

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5/27/2019 Secondary PG Routing Using NanoRoute
specify_pg_keepout -cell <AON-libcell-name> -pin <secondary-power-pin-name> -layer
m6 -top <w> –bottom <w>

However there are cases where robust connections need only one connection per source-tap. In such cases the
density of the AON buffers need to controlled.
The density control is specific and directly depends to maximum number of connections one can me make in a
given window without causing any DRC/congestion issues
specifyCellPad <AON-libcell-name> –right <number-of-row-units> -left <number-of-
row-units>

Validation of SPGR quality

It indeed would be demanding for IR signoff to be run iteratively while arriving at SPGR recipe
In order to have an early feel of SPGR quality, one can sum up the length of the metal wires involved
A sample script here does the same, which can be used as indicative of the resistance of a SPG connection
set m6sum 0 ; set m5sum 0

foreach c [dbget [dbget [dbget top.pgNets.name <AON-net-name> -p].wires.layer.name


m6 -p2].length ] { set m6sum [expr $m6sum + $c] }

foreach c [dbget [dbget [dbget top.pgNets.name <AON-net-name> -p].wires.layer.name


m5 -p2].length ] { set m5sum [expr $m5sum + $c]}

set m6shapes [llength [dbget [dbget [dbget top.pgNets.name <AON-net-name> -


p].wires.layer.name m6 -p2].length ]]

set m5shapes [llength [dbget [dbget [dbget top.pgNets.name <AON-net-name> -


p].wires.layer.name m5 -p2].length ]]

puts "Total M5 <AON-net-name> \nTotal length : $m5sum | Shapes : $m5shapes |


Average : [format {%f} [expr $m5sum/$m5shapes] ]"

puts "Total M6 <AON-net-name> \nTotal length : $m6sum | Shapes : $m6shapes |


Average : [format {%f} [expr $m6sum/$m6shapes] ]"

The script can be extended further to report mode/median of the length-wise wire distribution of SPGR or as
desired by the user requirements.

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