Zilog

zaooo CPU User's

Reference Manual
 Z8000 CPU User's

.-
Reference Manual
. . -III

Prentice-Hall, Inc., Englewood Cliffs, New Jersey 07632

Library 01 Congress Cataloging in Publication Data
Main entry under Iitle:
Z8000 CPU user's reference man'"al.
I. Zilog Model Z8000 (Computer) 1. Zilog, Inc.
II. Title: Z8000 C.P.U. user's reference manual.
QA76.8.Z55Z15 00 1. 64's 81-21043
ISBN 0-13-983908-9 AACR2
ISBN 0-13-983890-2 (pbk.)

Editorial/production supervision by Lori Opre

Manufacturing buyer: Gordon Osbourne

This is a technical manuaL The information contained

herein is subject to change.

All rights reserved. No part of this publication may be reproduced, stored in a retrievel system,
or transmitted, in any form or by any means, electric, mechanical, photocopying,
recording, or otherwise, without the prior written permission of Zilog and the publisher.

Zilog assumes no responsibility for the use of any circuitry other

than circuitry embodied in a Zilog product. No other circuit patent
licenses are implied.

1982, 1981, and 1980 by Zilog, Inc.

This book was previously published under the

title,~cruTechnical~

Printed in the United States of America

10987654321

ISBN 0-13-983908-9

ISBN 0-13-983890-2 {pbk.}

Prentice-Hall International, Inc., London

Prentice-Hall of Australia Pty. Limited, Sydney
Prentice-Hall of Canada, Ltd., Toronto
Prentice-Hall of India Private Limited, New Delhi
Prentice-Hall of Japan, Inc_, Tokyo
Prentice-Hall of Southeast Asia Pte. Ltd., Singapore
Whitehall Books Limited, Wellington, New Zealand
Table of CODleDls
1.1 Introduction 3 Z8000 Processor
1.2 General Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 Overview
1.3 Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
General-Purpose Register File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4
4
I
Data Types................................................... 4
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4
Multiple Memory Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
System/Normal Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
Separate I/O Address Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5
Multi-Processing 6
Large Address Space of the 28001 6
Segmented Addressing of the 28001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Management ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6
1.4 Benefits of the Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
Code Density........... . 7
Compiler Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
Support for Many Types of Data Structures. . . . . . . . . . . . . . . . . . . . . .. 8
Two CPU Versions: 28001 and 28002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8
1.5 Extended Instruction Facility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8
1.6 Summary .......... 8

2.1 Introduction . 11 Architecture

2.2 General Organization ................... 11
2.3 Hardware Interface. . . .. .. . .
Address/Data Lines
. 13
13
2
Segment Number (28001 only) .................. 13
Bus Timing . . . . . . . . . . . 13
Status. . . . . . . . . . . . f3
CPU Control. . . . . . . . . . . . . .. . . . .. . . . . 14
Bus Control ................ .......... 14
Interrupts . . . . . . . . . . . . .. 14
Segment Trap Request (28001 only) 14
Multi-Micro Control 14
System Inputs . . . .. . 14
2.4 Timing............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14
2.5 Address Spaces ...................... 14
Memory Address Space ............... . . . . . . . . . . . . . . . . . . . . . .. 14
I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 General-Purpose Registers.. . . . . . . .. . . .. . . . . . . . .. . . . . ... 15
2.7 Special-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Status Registers . . . . . . ............ ........... 17
Program Status Area Pointer 17
Refresh Counter . . . . . . ..................................... 17
2.8 Instruction Execution... ................ 17
2.9 Instructions.................................................... 17
Instruction Formats 18
2.lOData Types.......... 18
2.11 Addressing Modes . . . . ................ ............. 18
2.12 Extended Processing Architecture 18

v
Table of Conlenls (Continued)

2.13 Exceptions 19 Architecture

Reset '" 19 (Continued)
Traps 19
Interrupts
Trap and Interrupt Service Procedures
19
19
2
3.1 Introduction 23 Address Spaces
3.2 Types of Address Spaces 23
3.3
3.4
I/O Address Space
Memory Address Spaces
23
24
3
Addressable Data Elements 24
Segmented and Nonsegmented Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
Segmentation and Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25

4.1 Introduction 29 CPU Operation

4.2 Operating States 29
Running State
Stop/Refresh State
29
29
4
Bus-Disconnect State 29
Effect of Reset 29
4.3 Instruction Execution 30
Running-State Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Segmented and Nonsegmented Modes . . . . . . . .. 30
Normal and System Modes 31
4.4 Extended Instructions 32

5.1 Introduction ., ,.. 35 Addressing Modes

5.2 Use of CPU Registers .................................. . .. 36
5.3
5.4
Addressing Mode Descriptions
Descriptions and Examples (28002 and 28001 Nonsegmemed Mode)
36
37
5
Register (R) 37
Immediate (lM) ................................ 37
Indirect Register OR) ............ ........................... 37
Direct Address (DA) . 38
Index (X) .... . . . . . ..................................... 38
Relative Address (RA) 38
Base Address (BA) 39
Base Index (BX) 40
5.5 Descriptions and Examples (Segmented 28001) 40
Register (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Immediate OM) 40
Indirect Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 41
Direct Address (DA) 41
Index (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 42
Relative Address (RA) . 42
Base Address (BA) .............................. 43
Base Index (BX) .. . . . . .. ................... 44

vi
6.1 Introduction 47 Instruction Set
6.2 Functional Summary 47
Load and Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 48
Arithmetic Instructions 48
6
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 49
Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 49
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50
Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50
Block Transfer and String Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .. 51
Input/Output Instructions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52
CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52
Extended Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 53
6.3 Processor Flags..................................................... 53
6.4 Condition Codes 54
6.5 Instruction Interrupts and Traps " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 54
6.6 Notation and Binary Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
6.7 28000 Instruction Descriptions and Formats , 57
6.8 EPA Instruction Templates. . . . . . . . . . . . . . . . . . . . . . . . . . .. 213

7.1 Introduction 219 Exceptions

7.2 Interrupts 219
Non-Maskable Interrupt (NMI) . ..
Vectored Interrupt (VI)
.219
219
7
Nonvectored Interrupt (NVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3 Traps 219
Extended Instruction Trap 219
Privileged Instruction Trap . . . . . . . . . . . . . . . . . . . . . 219
System Call Trap 219
Segment Trap 219
7.4 Reset . , 220
7.5 Interrupt Disabling 220
7.6 Interrupt and Trap Handling. . . . . . . . . . . . . . . . . . . . . . . . 220
Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Status Saving 220
Loading New Program Status 221
Executing the Service Routine 222
Returning from an Interrupt or Trap 222
7.7 Priority 222

8.1 Introduction 225 Refresh

8.2 Refresh Cycles 225
8.3
8.4
Periodic Refresh
Stop-State Refresh
225
225
8

vii
Table of Conlenls (Continued)

9.1 Introduction 229 External Interface

9.2 Bus Operations. . . . . . . . . . . . . . . . . . . . 229
9.3 CPU Pins. . . . . . . . . . . . . . .
Transaction Pins . . . . . . . . .
.
................ .
230
230
9
Bus Control Pins . . ........................ . 230
Interrupt/Trap Pins ....................... . 230
Multi-Micro Pins 231
CPU Control ......... ................................ 231
9.4 Transactions......... ........................ . 231
WAIT............................. . 232
Memory Transactions . . . . . . . . . . . . . . . . 232
I/O Transactions ............. . 234
EPU Transfer Transactions . . . . 235
Interrupt/Trap Acknowledge Transactions .. 236
Internal Operations and Refresh Transactions ... 236
9.5 CPU and Extended Processing Unit Interaction ................ 238
9.6 Requests .......... 238
Interrupt/Trap Request 239
Bus Request . . . . . ......... .... 239
Resource Request .............. . 240
Stop Request 240
9.7 Reset.... .. . .. .. .. .. .. 241

Hardware Information 245 Appendix

A
28000 Family Speciiicalions 249 Appendix

B
Programmers Quick Reference 265 Appendix

C
Glossary of Terms .. 287 Appendix

Vlll
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ix
zaooo CPU User's
Reference Manual
 I
.-
 Chapter 1
Z8000 Processor Overview
1.1 Intro- This chapter provides a summary description overview of the architecture is provided in
duction of the advanced architecture of the 28000 Chapter 2, with detailed descriptions of the
Microprocessor, with special attention given to various aspects of the processor provided in
those architectural features that set the 28000 succeeding chapters.
CPU apart from its predecessors. A complete

1.2 General 2ilog's 28000 microprocessor has been benefits that result from these features are
Organization designed to accommodate a wide range of code density, compiler efficiency and support for
applications, from the relatively simple to the typical operating system operations, and complex
large and complex. The 28000 CPU is offered data structures. These topics are treated in
in three versions: the 28001, 2, and 3. The Section 1.3.
28003 is discussed in the 28003 CPU User's The CPU has been designed so that a power-
Manual. Each CPU comes with an entire family of ful memory management system can be used to
support components: a memory management improve the utilization of the main memory
unit, a DMA controller, serial and parallel I/O and provide protection capabilities for the
controllers, and extended processing units-all system. This is discussed in Section 1.3.12.
compatible with 2ilog's 2-Bus. Together with other Although memory management is an optional
28000 Family components, the advanced CPU capability-the 28000 CPU is an extremely
architecture provides in an LSI microprocessor sophisticated processor without memory
design the flexibility and sophisticated features management-the CPU has explicit features to
usually associated with mini- or mainframe facilitate integrating an external memory
computers. management device into a 28000 system con-
The major architectural features of the 28000 figuration.
CPU that enhance throughput and processing Finally, care has been taken to provide a
power are a general purpose register file, very general mechanism for extending the
system and normal modes of operation, multi- basic instruction set through the use of extern-
ple addressing spaces, a powerful instruction al devices (called Extended Processing
set, numerous addressing modes, multiple Units---EPUs). In general, an EPU is dedicated
stacks, sophisticated interrupt structure, a rich to performing complex and time-consuming
set of data types, separate 1/0 address spaces tasks so as to unburden the CPU. Typical tasks
and, for the 28001, a large address space and for speCialized EPUs include floating-point
segmented memory addressing. Each of these arithmetic, data base search and maintenance
! __ L ~_ ~_ ...... _.&. ...... ......J ~ ...... ....J. ...... +~;l .; ..... +'h ...... ,....,.t':~:YV~ c.cu..... tlr"\n onerations. network interfaces, and many
1.3 Architec- 1.3.1 General-Purpose Register File. The The majority of operations deal with byte,
tural Features heart of the 28000 CPU architecture is a file of word, or long-word operands, thereby pro-
(Continued) sixteen 16-bit general-purpose registers. These viding a high degree of regularity. Also
general-purpose registers give the 28000 its included in the instruction set are compact,
power and flexibility and add to its regular one-word instructions for the most frequently
instruction structure. used operations, such as branching short
General-purpose registers can be used as distances in a program.
accumulators, memory pointers or index reg- The instruction set contains some notable
isters. Their major advantage is that the partic- additions to the standard repertoire of earlier
ular use to which they are put can vary during microprocessors. The Load and Exchange
the course of a program as the needs of the group of instructions has been expanded to
program change. Thus, the general-purpose support operating system functions and con-
register file avoids the critical bottlenecks of version of eXisting microprocessor programs.
an implied or dedicated register architecture, The usual arithmetic instructions can now deal
which must save and restore the contents of with higher-precision operands, while hard-
dedicated registers when more registers of a ware multiply and divide instructions have also
particular type are needed than are supplied been added. The Bit Manipulation instructions
by the processor. can use calculated values to specify the bit
The 28000 CPU register file can be position within a byte or word as well as to
addressed in several ways: as 16 byte registers specify the position statically in the instruc-
(occupying one half of the file) or as 16 word tion. The Rotate and Shift instructions are con-
registers or, by using the register pairing Siderably more flexible than those in previous
mechanism, as eight long-word (32-bit) reg- microprocessors. The String instructions are
isters or as four quadruple-word (64-bit) useful in translating between different char-
registers. Because of this register fleXibility, it acter codes. Multiple-processor configurations
is not necessary (for example) for a 28000 user are supported by special instructions.
to dedicate a 32-bit register to hold a byte of
1.3.3 Data Types. Many data types are sup-
data. Registers can be used efficiently in
ported by the 28000 architecture. A data type
the 28000.
is supported when it has a hardware represen-
1.3.2 Instruction Set. A powerful instruction tation and instructions which directly apply to
set is one of the distinguishing characteristics it. New data types can always be simulated in
of the 28000. The instruction set is one terms of basic data types, but hardware sup-
measure of the fleXibility and versatility of a port provides faster and more convenient
computer. Having a given operation imple- operations. The basic data type is the byte,
mented in hardware saves memory and which is also the basic addressable element.
improves speed. In addition, completeness of The architecture also supports the follOWing
the operations available on a particular data data types: words (16 bits), long words (32
type is frequently more important than addi- bits), byte strings, and word strings. In
tional, esoteric instructions, which are unlikely addition, bits are fully supported and
to affect performance significantly. The 28000 addressed by number within a byte or word.
CPU prOVides a full complement of arithmetic, BCD digits are supported and represented as
logical, branch, I/O, shift, rotate, and string two 4-bit digits in a byte. Arrays are supported
instructions. In addition, special instructions by the Indexed addressing mode (see 1.3.4
have been included to facilitate multiprocess- and Chapter 5). Stacks are supported by the
ing, multiple processor configurations, and instruction set and by an external device (the
typical high level language and operating Memory Management Unit, MMU) available
system functions. The general philosophy of with the 28001.
the instruction set is two-operand register- 1.3.4 Addressing Modes. The addressing
memory operations, which include as a special mode, which is the wayan operand is speci-
subset register-register operations. However, fied in an instruction, determines how an
to improve code density, a few memory- address is generated. The 28000 CPU offers
memory operations are used for string manipu- eight addressing modes. Together with the
lation. The two-address format reflects the most large number of instructions and data types,
frequently occurring operations (such as they improve the processing power of the
A - A + B). Also, haVing one of the CPU. The addressing modes are Register,
operands in a rapidly accessible general- Immediate, Indirect Register, Direct Address,
purpose register facilitates the use of inter- Index, Relative Address, Base Address, and
mediate results generated during a Base Index. Several other adcressing modes
calculation. are implied by specific instructions, including
autoincrement. The first five modes listed

4
1.3 Architec- above are basic addressing modes that are mode and the individual users write their pro-
tural Features used most frequently and apply to most grams to run in normal mode.
(Continued) instructions having more than one addressing To further support the system/normal mode
mode. (In the 28002, Base Address and Index dichotomy, there are two copies of the stack
modes are identical, and in the 28001, Base pointer-one for a system mode stack and
Addressing capabilites can be simulated with another for a normal mode stack. These two
all instructions, using Based Addressing or the stacks facilitate the task sWitching involved
Memory Management Unit and the Direct or when interrupts or traps occur. To insure that
Indexed Addressing mode.) the normal stack is free of system information,
the information saved on the occurrence of
1.3.5 Multiple Memory Address Spaces. The interrupts or traps is always pushed on to the
28000 CPU facilitates the use of multiple system stack before the new program status is
address spaces. When the 28000 CPU loaded.
generates an address, it also outputs signals
indicating the particular internal activity which 1.3.7 Separate 110 Address Spaces. The
led to the memory request: instruction fetch, 28000 Architecture distinguishes between
operand reference, or stack reference. This memory and I/O spaces and thus requires
information can be used in two ways: to specific I/O instructions. This architectural
increase the memory space available to the separation allows better protection and has
processor (for example, by putting programs in more potential for extension. The use of
one space and data in another); or to protect separate I/O spaces also conserves the limited
portions of the memory and allow only certain 28002 data memory space. There are in fact
types of accesses (for example, by allOWing two separate I/O address spaces: Standard I/O
only instruction fetches from an area desig- and Special I/O. The main advantage of these
nated to contain proprietary software). The two spaces is to prOVide for two types of
Memory Management Unit (MMU) has been peripheral support chips-Standard I/O pe-
designed to provide precisely these kinds of ripherals and Special I/O peripherals-devices
protection features by using the CPU- such as the 28010 Memory Management Unit
generated status information. that do not respond to Standard I/O com-
1.3.6 System/Normal Mode of Operation. mands. A second advantage of these two
The 28000 CPU can run in either system mode spaces is that they allow 8-bit peripherals to
or normal mode. In system mode, all of the attach to the low-order eight bits (Standard
instructions can be executed and all of the I/O) or to the high-order eight bits (Special
CPU registers can be accessed. This mode is I/O) of the processor Address/Data bus.
intended for use by programs performing The increased speed requirements of future
operating system functions. In normal mode, microprocessors are likely to be achieved by
Ql'lrn.o. inc:trl1f"tiflnc::. rnAV n(")t h.o. Aypr"tprl (p rr tailorinq memory and I/O references to their
1.3 Architec- The 28000 has implemented a priority system address calculation (by indeXing, for exam-
tural Features for handling interrupts. Vectored interrupts ple). This corresponds to the way memory is
(Continued) have higher priority than non-vectored inter- typically used by a program-one portion of
rupts. This priority scheme allows the efficient the memory is set aside to hold instructions,
control of many peripheral devices in a 28000 another for data. In a segmented address
system. space, the instructions could reside in one seg-
An interrupt causes information relating to ment (or several different modules in different
the currently executing program (program segments), and each data set could reside in a
status) to be saved on a special system stack separate segment. One advantage of segmenta-
with a code describing the reason for the tion is that it speeds up address calculation
switch. This allows recursive task switches to and relocation. Thus, segmentation allows the
occur while leaving the normal stack undis- use of slower memories than linear addressing
turbed by system information. The program schemes allow. In addition, segments prOVide
state to handle the interrupt (new program a convenient way of partitioning memory so
status) is loaded from a special area in that each partition is given particular access
memory, the .program status area, designated attributes (for example, read-only). The Z8000
by a pointer resident in the CPU. approach to segmentation (simultaneous access
The use of the stack and of a pointer to the to a large number of segments) is necessary if
program status area is a specific choice made all the advantages of segmentation are to be
to allow architectural compatibility if new realized. A system capable of directly access-
interrupts or traps are added to the ing only, say, four segments would lack the
architecture. needed fleXibility and would be constrained by
address space limitations.
1.3.9 Multi-Processing. The increase in micro-
processor computing power that the 28000 1.3.12 Memory Management. Memory
represents makes simple the design of management consists primarily of dynamic
distributed processing systems having many relocation, protection, and sharing of memory.
low-cost microprocessors running dedicated It offers the follOWing advantages: prOViding a
processes. logical structure to the memory space that is
The 28000 prOVides some basic mechanisms independent of the actual physical location of
that allow the sharing of address spaces among data, protecting the user from inadvertent
different microprocessors. Large segmented mistakes, preventing unauthorized access to mem-
address spaces and the support for external ory resources or data, and protecting the operat-
memory management make this possible. Also, ing system from disruption by the users.
a resource request bus is prOVided which, in The addresses manipulated by the program-
conjunction with software, prOVides the exclu- mer, used by instructions, and output by the
sive use of shared critical resources. These segmented 28000 CPU are called logical
mechanisms, and new peripherals such as the addresses. The external memory management
Z-FIO, have been designed to allow easy asyn- system takes the logical addresses and trans-
chronous communication between different forms them into physical addresses required
CPUs. for accessing the memory. This address trans-
formation process is called relocation, which
1.3.10 Large Address Space for the Z8001. makes user software independent of the physi-
For many applications, a basic address space cal memory. Thus, the user is freed from
of 64K bytes is insufficient. A large address specifying where information is actually
space increases the range of applications of a located in the physical memory.
system by permitting large, complex programs The segmented 28000 CPU supports memory
and data sets to reside in memory rather than management both with segmented addressing
be partitioned and swapped into a small and with program-status information. A seg-
memory as needed. A large address space mented addressing space allows individual
greatly simplifies program and data manage- segments to be treated differently.
ment. In addition, large address spaces and Program status information generated by the
memories reduce the need for minimizing pro- CPU permits an external memory management
gram size and permit the use of higher level device to monitor the intended use of each
languages. The segmented version of the memory access. Thus, illegal types of access
Z8000 generates 23-bit addresses, for a basic can be suppressed and memory segments pro-
address space of 8 megabytes (8M or 8,388, tected from unintended or unwanted modes of
608 bytes). use. For example, system tables could be pro-
1.3.11 Segmented Addressing of the Z8001. tected from direct user access. This added pro-
The segmented version of the 28000 CPU tection capability becomes more important as
divides its 23-bit addresses into a 7-bit seg- microprocessors are applied to large, complex
ment number and a 16-bit segment offset. The tasks.
segment number serves as a logical name of a
segment; it is not altered by the effective

6
1.4 Benefits of The features of the 28000 Architecture com- ing modes and data types. Access to
the Architec- bine to provide several significant benefits: parameters and local variables on the pro-
ture improvements in code density, compiler effi- cedure stack is supported by the "Index With
ciency, operating system support, and support Short Offset" addressing mode, as well as the
for high level data structures. Base Address and Base Index addressing
1.4.1 Code Density. Code density affects both modes. In addition, address arithmetic is aided
processor speed and memory utilization. Code by the Increment and Decrement instructions.
compaction saves memory space-an especial- Testing of data, logical evaluation, initializa-
ly important factor in smaller systems-and tion, and comparison of data are made possi-
improves processor speed by reducing the ble by the instructions Test, Test Condition
number of instruction words that must be Codes, Load Immediate Into Memory, and
fetched and decoded. The 28000 offers several Compare Immediate With Memory. Since com-
advantages with respect to code density. The pilers and assemblers frequently manipulate
most frequently used instructions are encoded character strings, the instructions Translate,
in single-word formats. Fewer instructions are Translate And Test, Block Compare, and Com-
needed to accomplish a given task and a con- pare String all result in dramatic speed
sistent and regular architecture further improvements over software simulations of
reduces the number of instructions required. these important tasks. In addition, any register
Code density is achieved in part by the use except RO can be used as a stack pointer by
of special "short" formats for certain instruc- the Push and Pop instructions.
tions which are shown by statistical analysis to 1.4.3 Operating System Support. Interrupt
be most frequently used. A "short offset" and task-switching features are included to
mechanism has also been provided to allow a 2- improve operating system implementations.
word segmented address to be reduced to a The memory-management and compiler-
single word; this format may be used by support features are also quite important.
assemblers and compilers. The interrupt structure has three levels: non-
The largest reduction in program size and maskable, non-vectored, and vectored. When
increase in speed results from the consistent an interrupt occurs, the program status is
.... -..-3 .................. 1............. -I- ............ .j.." ..... _ _ ~ .j..h_ :::I,....~h;+~,...+'l,...c:l. :::Inri . .
1.4 Benefit of 1.4.4 Support for Many Types of Data Struc- addition, two hardware stack pointers are used
the Architec- tures. A data structure is a logical organiza- to assign separate stacks to system and normal
ture tion of primitive elements (byte, word, etc.) operating modes, thereby further supporting
(Continued) whose format and access conventions are well- the separation of system and normal operating
defined. Common data structures include environments discussed earlier.
arrays, lists, stacks, and strings. Since data Byte strings are supported by the Translate and
structures are high-level constructs frequently Translate And Test instructions. Decimal strings
used in programming, processor performance use the Decimal Adjust instruction to do decimal
is significantly enchanced if the CPU provides arithmetic on strings of BCD data, packed two
mechanisms for efficiently manipulating them. characters per byte. The Rotate Digit instructions
The 28000 offers such mechanisms. also manipulate 4-bit data.
In many applications, one of the most fre-
quently encountered data structures is the 1.4.5 Two CPU Versions: Z8001 and Z8002.
array. Arrays are supported in the 28000 by The 28000 CPU is offered in two versions: the
the Index and Base Index Addressing modes 28001 48-pin segmented CPU and the 28002
and by segmented addressing. The Base Index 40-pin nonsegmented CPU. The main differ-
Addressing mode allows the use of pointers into ence between the two is addressing range. The
an array (i.e., offsets from the array's starting 28001 can directly address 8M bytes of
address). Segmented addressing allows an memory; the 28002 directly addresses 64K
array to be assigned to one segment, which bytes. The 28001 has a non-segmented mode of
can be referenced simply by segment number. operation which permits it to execute programs
Lists occur more frequently than arrays in written for the 28002.
business applications and in general data pro- Not all applications require the large
cessing. Lists are supported by Indirect Reg- address space of the 28001; for these appli-
ister and Base Address Addressing modes. The cations the 28002 is recommended. Moreover,
Base Index Addressing mode is also useful for many multiple-processor systems can be imple-
more complex lists. mented with one 28001 and several 28002s,
Stacks are used in all applications for nest- instead of exclusively using 28001s. Since
ing of routines, block structured languages, segmented 28000s can execute code gen-
and interrupt handling. Stacks are supported erated for nonsegmented CPUs, users can
by the Push and Pop instructions, and multiple buy only the power they require without hav-
stacks may be implemented based on the ing to worry about software incompatibility
general-purpose registers of the 28000. In between processors.

1.5 Extended The 28000 architecture has a mechanism for cessing Units-EPUs) as opcodes. Thus, by
Instruction extending the basic instruction set through the using appropriate EPUs, the instruction set of
Facility use of exte;-nal devices. Special opcodes have the 28000 can be extended to include special-
been set aside to implement this feature. When ized instructions.
the CPU encounters an instruction with these In general. an EPU is dedicated to perform-
opcodes in its instruction stream, it will per- ing complex and time-consuming tasks in
form any indicated address calculation and order to unburden the CPU. Typical tasks suit-
data transfer; otherwise, it will treat the able for specialized EPUs include floating-
"extended instruction" as being executed by point arithmetic, data base search and main-
the external device. Fields have been set aside tenance operations, network interfaces,
in these extended instructions which can be graphics support operations-a complete list
interpreted by external devices (Extended Pro- would include most areas of computing.

1.6 Summary The architectural sophistication of the 28000 architecture-code density, compiler support,
microprocessor is on a level comparable with and operating system support-greatly
that of the minicomputer. Features such as enhance the power and versatility of the CPU.
large address spaces, multiple memory spaces, The CPU features that support an external
segmented addresses, and support for multiple memory management system also enhance the
processors are beyond the capabilities of the CPU's applicability to large system
traditional microprocessor. The benefits of this environments.

8
 2
_-I!---
--'-l1li _
.,.: , ~----=:

17': '~.L1W
7;1,..,.
Zilog
 Chapter 2
Architecture

2.1 Intro- This chapter provides an overview of the and the segmented Z8001) are noted where
duction Z8000 CPU architecture. The basic hardware, appropriate. Most of the subjects covered here
operating modes and instruction set are all are also treated with greater detail in later
described. Differences between the two ver- chapters of the manual.
sions of the Z8000 (the nonsegmented Z8002

2.2 General Figure 2.1 contains a block diagram that • An exception-handling control, which pro-
Organization shows the major elements of the Z8000 CPU, cesses interrupts and traps.
namely: • A refresh control, which generates memory
• A 16-bit internal data bus, which is used to refresh cycles.
move addresses and data within the CPU. Each of these elements is explained in the
• A Z-Bus interface, which controls the inter- following sections. All of the elements are
action of the CPU with the outside world. common to both the Z8001 CPU and the Z8002
• A set of 16 general-purpose registers, which CPU. The differences between the two versions
is used to contain addresses and data. of the Z8000 are derived from the number of
bits in the addresses they generate. The Z8002
• Four special-purpose registers, which con- always generates a 16-bit linear address, while
trol the CPU operation. the Z8001 always generates a 23-bit segmented
• An Arithmetic and Logic Unit, which is address (that is, an address composed of a
used for manipulating data and generating 7-bit segment number and a 16-bit offset).
addresses.
• An instruction execution control, which
fetches and executes Z8000 instructions.

1--------------------1
I I

:l
+
I
GENERAL
PURPOSE I~
!y---y
ARITHMETIC
LOGIC
I REFRESH
CONTROL
I
REGISTERS UNIT
~ I
REFRESH
I COUNTER
I
it it
INTERNAL DATA BUS
it Z·BUS
A
Z·BUS
~

< > INTERFACE

~ y

L
it
I INSTRUCTION I
_B~~R_ J
it
PROGRAM I
itPSAP
I I
STATUS
REGISTERS
~ I
>---
INSTRUCTION
EXECUTION
CONTROL

t
- r----..,
f- - -ic;- - ~ -I EXCEPTION
HANDLING
CONTROL I- I
I
I
I
I
LZ8000C~ ~
I

Figure 2-1. ZSOOO CPU Functional Block Diagram

II
2.2 General Figure 2.2 gives a system-level view of the Management Units (MMUs) that offer sophis-
Organization Z8000. It is important to realize that the Z8000 ticated memory allocation and protection
(Continued) CPU comes with a whole family of support features.
components. The Z8000 Family has been • One or more Direct Memory Access (DMA)
designed to allow the easy implementation of controllers for high-speed data transfers.
powerful systems. The major elements of such
a system might include: • A large number of possible peripheral
devices interfaced to the Z-Bus through
• The Z-Bus, a multiplexed address/data Universal Peripheral Controllers (UPCs),
shared bus that links the components of the Serial Communication Controllers (SCCs),
system. Counter- Timer and Parallel I/O Controllers
• A Z8000 CPU. (CIOs) or other Z-Bus peripheral
• One or more Extended Processing Units controllers.
(EPUs), which are dedicated to performing • One or more FIFO I/O Interface Units
specialized, time-consuming tasks. (FIOs) for elastic buffering between the
• A memory sub-system, which in Z8001 CPU and another device, such as another
systems can include one or more Memory CPU in a distributed processing system.

PERIPHERALS

8 8EPU DMA

B< JJ
JJ
JJ Z·BUS

II &
U
>

'"00' 0'" {
8 MMU
<
Z·BUS

JJ MEMORY
il
I I
Figure 2-2. Z8000 System Configuration

12
2.3 Hardware Figure 2.3 shows the 28000 pins grouped
Interface according to function. The 28001 is packaged
in a 48-pin DIP and the 28002 is packaged in a
AD15
40-pin DIP. The eight additional pins on the AD14
BUS{
TIMING
28001 are the seven segment-number lines and AD 13
the segment trap. Except for those eight, all AD 12

'w~l
READIWRITE AD,1
pins on the two CPU versions are identical.
NORMAUSYSTEM AD,o
The 28000 is a 2-Bus CPU; thus, activity on BYTElWORD AD,
the pins is governed by the 2- Bus protocols AD, ADDRESS I
DATA BUS
(see The Z-Bus Summary). These protocols AD,
AD,
specify two types of activities: transactions, AD,
which cover all data movement (such as AD.

memory references or I/O operations), and

CONT~~~{
Z8001
requests, which cover interrupts and requests Z8002
AD,
CPU AD,
for bus or resource control. The following is a ADo
brief overview of the 28000 pin functions; com-
CONT=~~{ 1--

-r'=~
plete descriptions are found in Chapter 9. I SN,
SN,
I
2.3.1 Address/Data Lines. These 16 lines I
SN.
SEGMENT:
alternately carry addresses and data. The I
SN,
NUMBER I
SN,
addresses may be those of memory locations or I I
SN,
I/O ports. The bus timing signal lines I I
SNo
MULTI.MICRO{ I I
described below indicate what kind of informa- CONTROL
I
I SEGT SEGMENT
tion the Address/Data lines are carrying. L__ _~R~ _ _ -l
2.3.2 Segment Number (Z8001 only). These
seven lines encode the addresses of up to 128 t
+5 V GND elK
t
RESET
relocatable memory segments. The segment
signals become valid before the address offset
signals, thus supporting address relocation by
the memory managment system. Figure 2-3. Z8000 Pin Functions

2.3.3 Bus Timing. These three lines include to determine when the multiplexed Address/
Address Strobe (AS), Data Strobe (DS) and Data Bus holds addresses or data. The Memory
Memory Request (MREQ). They are used to Request signal can be used to time control
signal the beginning of a bus transaction and signals to a memory system.

Definition 2.3.4 Status. These lines function to indicate

the kind of transaction on the b~ (STo-ST3 ),
0000 Internal operation
whether it is a read or write (R/W, where High
000 I Memory refresh
00 I 0 1/0 reference is Read and Low is Write), whether it is on
001 I Special 1/0 reference byte or word data (B/W, High = byte,
0100 Segment trap acknowledge Low = word), and whether the CPU is
010 ] Non-maskable Interrupt acknowledge operating in normal mode or system mode
0] ] 0 Non-veciored interrupt acknowledge
0] ] ] Vectored interrupt acknowledge
(N/S, High = normal, Low = system). The
] 000 Data memory request STo-ST 3 lines also encode additional
] 00] Stack memory request characteristics of the bus transactions, as Table
] 0 ] 0 Data memory request (EPU) 2.1 shows. The availability of status information
] 0 ] ] Stack memory request (EPU) defining the type of bus transaction in advance
] ] 00 Instruciion space access
] ] 0 ] Instruciion fetch, first word
of data transmission allows bidirectional
] ] ] 0 CPU-EPA Transfer drivers and other external hardware elements
Ill] Test and Set Data Access (28003/4 only) to be enabled before data is transferred.

Table 2.1 Status Line Codes

13
2.3 Hardware 2.3.5 CPU Control. These inputs allow exter- enforce a priority among several external
Interface nal devices to delay the operation of the CPU. devices.
(Continued) The WAIT line, when active (Low), causes the 2.3.1 Interrupts. Three interrupt inputs are
CPU to idle in the middle of a bus transaction, provided: non-maskable interrupts (NMI), vec-
taking extra clock cycles until the WAIT line tored interrupts (VI) and non-vectored inter-
goes inactive; it is typically used by memory or rupts (NVI). These permit external devices to
I/O peripherals which operate more slowly suspend the CPU's execution of its current
than the CPU. The Stop (STOP) line halts program and begin executing an interrupt ser-
internal CPU operation when the first word of vice routine.
an instruction (or the second word of an EPA
instruction) has been fetched. This signal is 2.3.8 Segment Trap Request (Z8001
useful for single-step instruction execution dur- only). This input to the CPU is used by an
ing debugging operations and for enabling external memory-management system to indi-
Extended Processing Units to halt the CPU cate that an illegal memory access has been
temporarily. attempted.
2.3.6 Bus Control. These lines provide the 2.3.9 Multi-Micro Control. The Multi-Micro In
means for other devices, such as direct (MI) and Multi-Micro Out (MO) lines are used
memory access (DMA) controllers, to gain in conjunction with instructions such as MSET
exclusive use of the system bus, i.e., the signal and MREQ to coordinate multiple-CPU sys-
lines that are common to several devices in a tems. They allow exclusive use by one CPU of
system. The external device requesting control a shared resource in a multiple-CPU system.
of the bus inputs a bus request (BUSREQ); the 2.3.10 System Inputs. The four inputs shown
CPU responds with a bus acknowledge at the bottom of Figure 3 include + 5 V power,
(BUSACK) after three-stating, or electrically ground, a single-phase clock signal and a CPU
neutralizing, the Address/Data Bus, Bus Tim- reset. The reset function is described in
ing lines, Status lines, and Control lines. The Chapter 7.
Z-Bus allows a daisy chain to be used to

2.4 Timing Figure 2.4 shows the three basic timing of AS and ending with a rising edge of DS. A
periods of the 28000: a clock cycle, a bus machine cycle covers one basic CPU operation
transaction, and a machine cycle. A clock and always starts with a bus transaction. A
cycle (sometimes called a T-state) is one cycle machine cycle can extend beyond the end of a
of the CPU clock, starting with a rising edge. transaction by an unlimited number of clock
A bus transaction covers a single data move- cycles.
ment on the CPU bus and will last for three or
more clock cycles, starting with a falling edge

BUS
MACHINE

TRANSACTION
CYCLE

CLOCK CYCLE
--1
11
I
CPU CLOCK

v
v
Figure 2-4. Basic Timing Periods

2.5 Address The 28000 supports two main address 2.5.1 Memory Address Space. Memory
Spaces spaces corresponding to the two different kinds address space can be further subdivided into
of locations that can be addressed: Program Memory address space, Data Memory
• Memory Address Space. This consists of the address space, and Stack Memory address
addresses of all locations in the main space, each for both normal and system
memory of the computer system. modes.
The particular space addressed is deter-
• 1/0 Address Space. This consists of the mined by the external circuitry from the code
addresses of all I/O ports through which appearing at the CPU's output status pins
peripheral devices are accessed. (STO-ST3) _and the state of the Normal/System
For more information on address spaces, con- signal (N/S pin). Data memory reference, stack
sult Chapter 3. memory reference, and program memory

14
2.5 Address reference each correspond to a different status independently of user addresses, allowing
Spaces code at the STo-ST3 outputs, allowing three better management of the memory resources
(Continued) address spaces to be distinguished for each of and sharing of data and programs.
two operating modes, giving six address The signals provided on the segmented
spaces in all. Each of the six address spaces 28001 CPU assist in implementing these
has a range as great as the addressing ability features, although additional software and
of the processor. For the nonsegmented 28002, external circuitry (such as the 28010 MMU) are
each address space can have up to 64K bytes generally required to take full advantage of
of directly addressable memory. The seg- them. Chapter 3 contains an extensive discus-
mented 28001, on the other hand, provides up sion of segmentation.
to 8M bytes of memory in each address space.
Segmentation is a means of partitioning 2.5.2 I/O Address Space. I/O addresses are
memory into variable-sized segments so that a represented as 16-bit words for both the 28001
variety of useful functions may be imple- and 28002.
mented, including: There are two I/O address spaces, Standard
I/O and Special I/O, which are both separate
from the memory address space. Each I/O
• Protection mechanisms that prevent a user
space is accessed through a separate set of I/O
from referencing data belonging to others,
instructions, which can be executed only when
attempting to modify read-only data or over-
the CPU is operating in system mode.
flowing a stack.
Standard I/O instructions transfer data
• Virtual memory, which permits a user to between the CPU and peripherals and Special
write functioning programs under the I/O instructions transfer data to or from exter-
assumption that the system contains more nal CPU support circuits such as the 28010
memory than is actually available. MMU. Access to Standard or Special I/O
• Dynamic relocating, which allows the place- space is distinguished by the status lines
ment of blocks of data in physical memory (ST o- ST3)·

2.6 General- The 28000 CPU contains 16 general-purpose RHO-RL7, which may be used as accumulators,
Purpose registers, each 16 bits wide. Any general- overlap the first eight word registers. Register
Registers purpose register can be used for any instruc- groupings for larger operands include eight
tion operand (except for minor exceptions double-word (32-bit) registers, RRO-RRI4, and
described at the beginning of Chapter 5). four quad-word registers, RQO-RQI2, which
Figure 2.5 shows these general-purpose reg- are used by a few instructions such as Mul-
isters. They allow data formats ranging from tiply, Divide, and Extend Sign.
bytes to quadruple words. The word registers As Figure 2.5 illustrates, the CPU has two
are speCified in assembly-language statements hardware stack pointers, one dedicated to each
as RO through R15. Sixteen byte registers, of the two basic operating modes, system and
Z8001 Z8002
Rol7 01 RO!7 01
000 ( RO.(
R1115 01 R1115 01
R2! R21
RR'( RR2 (
O'! R'!
0·1 R·I
RR'( R51 RR'( Rsl
0·1 ROI
RR.( RRO (
071 R71
01 Raj,S 01

I~
RsI15
RRS( ORO (
R91 ..I
RR10
( R101 RR10
( R1O!
R11 I R1,!

RR12
( R121 RR12
( R121

I I
R131 0131
SYSTEM STACK POINTER (SEG. NO.)
R1.R14 NORMAL STACK POINTER (SEG. NO.) RR14
R141R1S'
SYSTEM STACK POINTER
RR14
R1S' SYSTEM STACK POINTER (OFFSET) R15 NORMAL STACK POINTER
015 NORMAL STACK POINTER (OFFSen

Figure 2-50. Z8001 Segmented General-Purpose Figure 2-5b. Z8002 Nonsegmented General-Purpose
Registers (Register Address Space) Registers (Registers Address Space)

15
2.6 General- normal. The segmented zaOOl uses a two-word mode. The normal stack pointer is used for
Purpose stack pointer for each mode (R14'/R15' or subroutine calls in user programs. In normal-
Registers R14/R15), whereas the nonsegmented 28002 mode operation only the normal stack pointer
(Continued) uses only one word for each mode (R15' is accessible. In system mode, the system stack
or R15). pointer is directly accessed as a general-purpose
The system stack pointer is used for saving register. The normal mode stack pointer can be
status information when an interrupt or trap assessed as a special control register.
occurs and for supporting calls in system

2.7 Special- In addition to the general-purpose registers, Parity/Overflow (P/V), which is generally used
Purpose there are special-purpose registers. These to indicate either even parity (after logical
Registers include the Program Status registers, the Pro- operations on byte operands) or overflow (after
gram Status Area Pointer, and the Refresh arithmetic operations).
Counter; they are illustrated for both CPU ver- Decimal-Adjust (D), which is used in BCD
sions in Figure 2.6. Each register can be arithmetic to indicate the type of instruction
manipulated by software executing in system that was executed (addition or subtraction).
mode, and some are modified automatically by
certain operations. Half Carry (H), which is used to convert the
binary result of a previous addition or subtraction
2.7.1 Program Status Registers. These of BCD numbers into the correct decimal result.
registers include the Flag and Control Word
(FCW) and the Program Counter (PC). They
are used to keep track of the state of an exe- Section 6.3 provides more detail on these
cuting program. flags.
In the nonsegmented 28002, the Program The control bits, which occupy the high-
Status registers consist of two words: one each order byte of the FCW, are used to enable
for the FCW and the PC. In the segmented various interrupts or to control CPU operating
28001, there are four words: one reserved modes. The control bits are:
word, one word for the FCW and two words for Non-Vectored Interrupt Enable (NVIE), Vec-
the segmented PC. tored Interrupt Enable (VIE). These bits deter-
The low-order byte of the Flag and Control mine whether or not the CPU will accept non-
Word (FCW) contains the six status flags, from vectored or vectored interrupts (see Section
which the condition codes used for control of 2.13).
program looping and branching are derived.
The six flags are: SystemlNormaI Mode (SiN). When this bit is
set to one, the CPU is operating in system
Carry (C), which generally indicates a carry mode; when cleared to zero, the CPU is in
out of the high-order bit position of a register normal mode (see Section 2.8). The CPU out-
being used as an accumulator. put status line (NIS pm) IS the complement of
Zero (2), which is generally used to indicate this bit.
that the result of an operation is zero. Extended Processor Architecture (EPA)
Sign (S), which is generally used to indicate Mode. When this bit is set to one, it indicates
that the result of an operation is a negative that the system contains Extended Processing
number. Units, and hence extended instructions
15 , 15 ,

I 0 I 0 I 0 ! o! 0 ! 0 ! a ! 0 ! 0 ! 0 ! 0 ! 0 ! a ! 0 I 0 ! 0 I :_~~:~VEO I I~N I I
0 EPA VIE INVtE! a ! 0 I 0 I I I I I I I
c z s PrJ DA H 0 ! 0 I }~~~\:~~

Proaram Sta.tus Reqist~:rs

I ' I ~'GM~.TN~M.'~ I' ,It 1 ' 1 ' 1 ' 1 ' 1 ' 1 ' 1 PROGRAM
L:80Ud

r-------====---------,
I SEfMEN:OF7 ET I !
ICOUNTER

28001 Program Status Reglstt'rs

1', I SEGMENT NUMBER

! ! I I , , , ,
' 1 1 1 1 1 , 1 'I ,I I' UPPER POINTER
! ! !

I UPPER OFFSET
! ! I I ' 1
, , , ,
1 1 1 1
, 1
' 1
,I L8UUL Program Slaws Area P0lI11er

£:8001 Program ~tutus Arf..:u POlr;~c·r

RATE
I ! ! !
ROW
! j'R'1 RATE
1 I
ROW
!

28001 Rei resh 28002 Reiresh Ccun'er

Figure 2-6. CPU Special Registers

16
2.7 Special encountered in the CPU instruction stream are ister values are fetched from this area when an
Purpose executed (see Section 2.12). When this bit is interrupt or trap occurs. As shown in Figure
Registers cleared to zero, extended instructions are 2.6, the PSAP comprises either one word (non-
(Continued) trapped for software emulation. segmented 28002) or two words (segmented
Segmentation Mode (SEG). This bit is imple- 28001); for either configuration, the lower byte
mented only in the 28001; it is always cleared of the pointer must be zero. Refer to Chapter 7
in the nonsegmented 28002. When set to one, for more details about the Program Status Area
the CPU is operating in segmented mode, and and its layout.
when cleared to zero, the CPU is operating in 2.7.3 Refresh Counter. The CPU contains a
nonsegmented mode (see Section 2.8). programmable counter that can be used to
2.7.2 Program Status Area Pointer refresh dynamic memory automatically. The
(PSAP). The Program Status Area Pointer refresh counter register consists of a 9-bit row
points to an array of progam status values counter, a 6-bit rate counter and an enable bit
(FCWs and PCs) in main memory called the (Figure 2.6). Refer to Chapter 8 for details of
Program Status Area. New Program Status reg- the refresh mechanism.

2.8 Instruction In the normal course of events, the 28000 instructions. If it is executing instructions, the
Execution CPU will spend most of its time fetching 28000 can be in the system or normal execu-
instructions from memory and executing them. tion mode. In system mode, privileged instruc-
This process is called the running state of the tions (such as those which perform I/O) can be
CPU. The CPU also has two other states that it executed; in normal mode they cannot. This
occasionally enters. dichotomy allows the creation of operating
Stop/Refresh State. This is really one state, system software, which controls CPU resources
although it may be entered in two different and is protected from application program
ways: either automatically for a periodic action.
memory refresh; or when the STOP line is acti- In addition, the CPU will be in either seg-
vated. In this state, program execution is mented or nonsegmented mode. In segmented
temporarily suspended and the CPU makes use mode, which is available only on the 28001,
of the Refresh Counter to generate refreshes. the program uses 23-bit segmented addresses
For more information, consult Chapter 8. for memory accesses; in nonsegmented mode,
which is available on both CPUs, the program
Bus-Disconnect State. This is the state the uses 16-bit nonsegmented addresses for mem-
CPU enters when the DMA, or some other bus ory accesses.
requester, takes over the bus. Program execu- While executing instructions, the mode of
tion is suspended and the CPU disconnects the CPU is controlled by bits in the FCW (Sec-
itself from the bus. tion (2.7). While handling interrupts, the CPU
While the CPU is in the running state, it can is always in system mode and, for the 28001, in
either be handling interrupts or executing segmented mode.

2.9 Instructions The 28000 instruction set contains over 400 Rotate and Shift for bytes, words, or, for shifts
different instructions which are formed by only, long words within registers.
combining the 110 distinct instruction types
Block Transfer and String Manipulation for
(opcodes) with the various data types and
automatic memory-to-memory transfers of data
addressing modes. The complete set is divided
blocks or strings, including compare and
into the following groups:
translate functions.
Load and Exchange for register-to-register
Input/Output for transfers of data between I/O
and register-to-memory operations, including
ports and memory or registers.
stack management.
Extended for operations involving Extended
Arithmetic for arithmetic operations, including
Processing Units.
multiply and divide, on data in either registers
or memory. Compare, increment, and decre- CPU Control for accessing special registers,
ment functions are included. controlling the CPU operating state, synchro-
nizing multiple-processor operation, enabling/
Logical for Boolean operations on data in
disabling interrupts, mode selection, and
registers or memory.
memory refresh.
Program Control for program branching (con-
Chapter 6 contains details on the full instruc-
ditional or unconditional), calls, and returns.
tion set.
Bit Manipulation for setting, resetting and
testing individual bits of bytes or words in
registers or memory.

17
2.9 2.9.1 Instruction Formats. Formats of the A. COMPACT INSTRUCTION FORMAT
LOAD IMMEDIATE BYTE
Instructions instructions are shown in Figure 2.7. The two LDB 11 I 1 I 0 I 0 I I ;
(Continued) most significant bits in the instruction word
CALL RELATIVE
determine whether the compact instruction for- CALR 11 1
i 10 11 I Of/set'
mat (A) or the general instruction format (B) is JUMP RELATIVE
used. Compact formats encode the four most JR 11 1
I I 1 0 I I c~ , • 'Off~et
frequently used instructions into single words, DECREMENT AND JUMP ON NON·ZERO
thereby saving on instruction-memory usage DJNZ 11 i 1 I 1 I 1 I I ; I I I
W I I ol'se;
and increasing execution speed. As long as
the two most significant bits are not logic ones,
B. GENERAL INSTRUCTION FORMAT (FIRST WORD)
the general format applies. In the general for- addressing
mode
mat, the two most significant bits in conjunc- (

tion with the source-register field are sufficient

for specifying any of the five main addressing
modes. Source and destination fields are four
bits wide for addressing the 16 general-
purpose registers. Note: W indicates Word (1) or Byte (0)

Figure 2-7. Instruction Formats

2.10 Data The 28000 supports manipulation of eight • Unsigned byte decimal integer
Types data types. Five of these have fixed lengths;
• Dynamic-length string of byte data
the other three have lengths that can vary
dynamically. Each data type is supported by a • Dynamic-length string of word data
number of instructions which operate upon it • Dynamic-length stack of word data
directly. These data types are:
Bits can be manipulated in registers or
• Bit memory. Binary and decimal integers and
• Signed and unsigned byte, word, long logical values can be manipulated in registers,
word, or quadruple word binary integer although operands can be fetched directly from
memory. Addresses are manipulated only in
• Byte or word-length logical value registers, and strings and stacks are manipulated
• Word (nonsegmented) or long word only in memory.
(segmented) address

2.11 The information included in 28000 instruc- in the location whose address is the sum of the
Addressing tions consists of the function to be performed, contents of a 16-bit index value in a register
Modes the type and size of data elements to be ahd an address in the instruction.
manipulated, and the location of the data Relative Address Mode. The data element can
elements. Locations are designated using one be found in the location whose address is the
of the follOWing eight addressing modes: sum of the contents of the program counter
Register Mode. The data element is located in and a 16-bit displacement in the instruction.
one of the 16 general-purpose registers. Base Address Mode. The data element can be
Immediate Mode. The data element is located found in the location whose address is the sum
in the instruction. of a base address in a register and a
Indirect Register Mode. The data element can displacement in the instruction.
be found in the location whose address is in a Base Index Mode. The data element can be
register. found in the location whose address is the sum
Direct Address Mode. The data element can of a base address in a register and a displacement
be found in the location whose address is in in the instruction.
the instruction. Chapter 5 defines and illustrates the eight
Index Mode. The data element can be found addressing modes.

2.12 Extended An important feature of the 28000 CPU these extended instructions in its instruction
Processing architecture is the Extended Processing stream, it will either trap to a software trap
Architecture Architecture (EPA) facility. This facility pro- handler to process the instruction or it will
vides a mechanism by which the basic instruc- perform the data transfer portion of the
tion set of the CPU can be extended viaexter- instruction (leaving the data manipulation part
nal devices, called Extended Processing Units of the instruction to the EPU). Whether the
(EPUs). A special set of instructions, called CPU traps or transfers data depends on the
extended instructions, is used to control this setting of the EPA bit in the FCW.
feature. When the CPU encounters one of

18
2.12 Extended The underlying philosophy behind the EPA feature-the CPU fetches the instruction and
Processing feature is a view of the CPU as an instruction performs any address calculation that may be
Architecture processor-the CPU fetches instructions, needed. It also generates the timing signals for
(Continued) fetches data associated with the instruction, the memory access if data must be transferred
performs the operations and stores the result. between memory and the extended processor.
Extending the number of operations performed But the actual data manipulation is handled by
does not affect the instruction fetch and the EPU. The Extended Processing Architec-
address calculation portion of the CPU activi- ture is explained more fully in Chapter 4.
ty. The extended instructions exploit this

2.13 Three events can alter the normal execu- using an offset larger than the defined length
Exceptions tion of a 28000 program: hardware interrupts of the segment, can be made to cause an
that occur when a peripheral device needs ser- external memory management system to signal
vice, synchronous software traps that occur a segmentation trap. This can occur only with
when an error condition arises, and system the segmented 28001.
reset. Chapter 7 contains a detailed descrip- 2.13.3 Interrupts. Interrupts are asynchronous
tion of exceptions and how they are handled. events typically triggered by peripheral
Interrupt requests and segmentation trap re- devices needing attention. T~ three kinds of
quests are accepted after the completion of the interrupts associated with the three interrupt
instruction execution during which they were lines of the CPU are:
made. At the end of the instruction execution,
a spurious instruction fetch transaction is Non-maskable interrupts (NMI). These inter-
usually performed before the interrupt rupts cannot be disabled and are usually
acknowledge sequence begins, but the Pro- reserved for critical external events that
gram Counter is not affected by the spurious require immediate attention.
fetch. Vectored interrupts (VI). These interrupts
2.13.1 Reset. A system reset overrides all cause eight bits of the vector output by the
other operating conditions. It puts the CPU in interrupting device to be used to select a par-
a known state and then causes a new program ticular interrupt service procedure to which
status to be fetched from a reserved area of the program automatically branches.
memory to reinitialize the Flag and Control Non-vectored interrupts (NVI). These inter-
Word (FCW) and the Program Counter (PC). rupts are maskable interrupts which are all
2.13.2 Traps. Traps are synchronous events handled by the same interrupt procedure.
that are usually triggered by specific instruc- 2.13.4 Trap and Interrupt Service Pro-
tions and recur each time the instruction is cedures. Interrupts and traps are handled
executed with the same set of data and the similarly by the 28000 CPU. The 28000 CPU
same process or state. The four kinds of traps automatically acknowledges interrupts and
are: processes traps in system mode. In the case of
Extended instruction attempted in non-EPA the segmented 28001, the CPU uses the
mode. The current instruction is an EPU segmented mode regardless of its mode at the
instruction, but the system is not in EPA mode. time of interrupt or trap. The program status
This trap allows system software to either information in effect just prior to the interrupt
simulate instruction or abort the program. or trap is pushed onto the system stack. An ad-
ditional word, which serves as an identifier for
Privileged instruction attempted in normal the interrupt or trap, also is pushed onto the
mode. The current instruction is privileged system stack, where it can be accessed by the
(I/O for example), but the CPU is in normal interrupt or trap handler. The Program Status
mode. registers are loaded with new status informa-
System Call (SC) instruction. This instruction tion obtained from the Program Status Area of
provides a controlled access from normal-mode memory. Then control is transferred to the ser-
to system-mode operation. vice procedure, whose address is now located
Segmentation violation (supplied by external in the Program Counter. For details of inter-
circuit). A segmentation violation, such as rupt and trap handling, refer to Chapter 7.

19
 3
.-
 Chapter 3
Address Spaces
3.1 Intro- Programs and data may be located in the The CPU generates addresses during four
duction main memory of the computer system or in types of operations:
peripheral devices. In either case, the location • Instruction fetches, described in Chapter 4.
of the information must be specified by an
address of some sort before that information • Operand fetches and stores, described in
can be accessed. A set of these addresses is Chapter 5.
called an address space. • Exception processing, described in
The 28000 supports two different types of Chapter 7.
addresses and thus two categories of address
• Refreshes, desCribed in Chapter 8.
spaces:
Timing information concerning addresses is
• Memory addresses, which specify locations described in Chapter 9.
in main memory.
• I/O addresses, which specify the ports
through which peripheral devices are
accessed.

3.2 Types of Within the two general types of address • Data Spaces (status = 1000 or 1010), nor-
Address spaces (memory and I/O), it is possible to dis- mal mode (N/S = 1) or system mode
Spaces tinguish several subcategories. Figure 3.1 (NiS = 0). These spaces may be used to
shows the address spaces that are available on address the data that user or system pro-
both the 28001 and the 28002. grams operate on.
The difference between the 28001 and the • Stack Spaces (status = 1001 or 1011), nor-
28002 lies not in the number and type of mal mode (N/S = 1) or system mode
address spaces, but rather in the organization (N/S = 0). These spaces can be used to
and maximum size of each space. For the address the system and normal program
2800 I, each of the six memory address spaces stacks.
contains 8M byte addresses grouped into 128
segments, for a total memory addressing capa- • Standard I/O Space (status = 0010). This
bility of 48M bytes. For the 28002, each mem- space addresses all the I/O ports that are
ory space is a homogeneous collection of 64K used for 28000 peripherals.
byte addresses. In both the 28001 and the • Special I/O Space (status = 0011). This
28002, the I/O address spaces contain 64K port space addresses ports in CPU support chips
addresses. When an address is used to access (such as the 28010 Memory Management
data, the address spaces may be distinguished Unit).
by the state of the status lines (STo-ST3 ) (which
is determined by the way the address was
MEMORY ADDRESS SPACES I/O ADDRESS SPACES
generated) and by the value of the Normal!
System line (NiS) (which is determined by the SYSTEM MODE NORMAL MODE SYSTEM MODE

state of the SIN bit in the FCW).

INSTRUCTIONS INSTRUCTIONS STANDARD I/O
• Instruction Space (status = 1100 or 1101), DATA DATA
SPECIAL I/O
normal mode (NlS = 1) or system mode STACK STACK

(NlS = 0). These spaces typically address

memory that contains user programs (nor-
mal) or system programs (system). Figure 3-1. Address Spaces on the Z8001 and Z8002

3.3 I/O All I/O addresses are represented by 16-bit The address of a 16-bit port may be even or
Address words. Each of the ports addressed is either odd for both address spaces. In Standard I/O
Spaces eight or 16 bits wide. Transfer to or from 16-bit space, byte ports must have an odd address; in
ports always involves word data and, for 8-bit Special I/O space, byte ports must have an
ports, byte data. even address.

23
3.4 Memory Each memory address space in the 28002, or most significant. This is consistent with the
Address each segment in each memory address space convention that bit n corresponds to position
Spaces on the 28001, can be viewed as addressing a 2 n in the conventional representation of binary
string of 64K bytes numbered consecutively in numbers (see Figure 3.2).
ascending order. The 8-bit byte is the basic The address of a data type longer than one
addressable eleraent in 28000 memory address byte (word or long word) is the same as the
spaces. However, there are three other address of the byte with the lowest memory
addressable data elements: address within the word or long word (Figure
3.2). This is the leftmost, highest-order, or
• Bits, in either bytes or words.
most significant byte of the word or long word.
• 16-bit words. Word or long word addresses are always
• 32-bit long words. even-numbered. Low bytes of words are stored
3.4.1 Addressable Data Elements. The nature at odd-numbered memory locations and high
of the data element being addressed depends bytes at even-numbered locations. Byte
on the instruction being executed. As Chapter addresses can be either even- or odd-
6 explains in detail, different assembler numbered.
mnemonics are used for addressing bytes, Certain memory locations are reserved for
system-reset handling. These are described
words, and long words. Moreover, only certain
fully in Chapter 7. Except for these reserved
instructions can address bits.
locations, there are no memory addresses
A bit can be addressed by specifying a byte
specifically designated for a particular
or word address and the number of the bit
within the byte (0-7) or word (0-15). Bits are purpose.
numbered right-to-left, from the least to the
7 6 5 4 3 2 1 0

I I I I I I I BITS IN A BYTE

1514 13 121110 9 8 7 6 5 4 3 2 1 0

I I I I I I I I I I I I BITS IN A WORD

Address n

I , , BYTE

WORD

Address n

I ~PP~R ~OR~IUP~ER ~YTE,

rd',... 2n +

Figure 3-2. Addressable Data Elements

3.4.2 Segmented and Non-Segmented long word and thus can be stored in a long
Addresses. The two versions of the 28000 CPU word register (RRn) or a long word memory
generate two kinds of addresses with different element. There is a short encoding of
lengths. The 28002 generates a 16-bit address segmented addresses that appears in instruc-
specifying one of 64K bytes. The 28001 gener- tions and requires only 16 bits.
ates a 23-bit segmented address. A segmented It is important to realize that even though
address consists of a 7-bit segment number, the 28001 can operate in nonsegmented mode
which specifies one of 128 segments, and a (Chapter 4), it always generates segmented
16-bit offset, which specifies one of up to 64K addresses. In non-segmented mode the segment
bytes in the segment. Each segment is an inde- number is supplied by the program counter seg-
pendent collection of bytes; thus, instructions ment number.
and multiple byte data elements cannot cross Non-segmented Memory Address
segment boundaries. Some of the advantages (Z8002 Only)

of address segmentation are outlined in Sec-

tion 3.4.3.
ADDRESS
! I , , , ! , I
Segmented Memory Address
Figure 3.3 shows the format of segmented (Z80010nly)
and nonsegmented addresses. Nonsegmented
addresses are 16 bits long and thus can be I! ~
15 14

0 SEGMENT R
: : : :
8

?FFSE1
!
7
0 0
:
0
:
0
:
0
:
0
:
0
:
0

0 I
stored in word registers (Rn) or in memory as 15 0
word-length addressable elements. The 23-bit
Figure 3-3. Segmented and Non-Segmented
segmented addresses are embedded in a 32-bit
Address Formats

24
3.4 Memory 3.4.3 Segmentation and Memory Manage- • Hardware stack overflow protection.
Address ment. Addresses manipulated by the pro-
• Support for multiple, independently execut-
Spaces grammer/ used by instructions, and output by
ing programs that can share access to com-
(Continued) the 28001 are called "logical addresses." An
mon code and data.
external memory-management circuit can
translate logical addresses into physical • Protection from unauthorized or uninten-
(actual) memory addresses and perform certain tional access to data or programs.
checks to insure data and programs are prop- • Detection of obviously incorrect use of
erlyaccessed. memory by an executing program.
The 28010 Memory Management Unit (MMU)
• Separation of users from system functions.
performs this function for the segmented
addresses produced by the 28001 CPU. A Segmentation in the 28001 helps support
single MMU holds 64 descriptors. Each memory management in two ways:
descriptor tells where in physical memory the • By allowing part of an address (the segment
segment lies, how long the segment is, and number) to be output by the CPU early in a
what kind of accesses can be made to the memory cycle. This keeps access to the ad-
segment. The MMU uses these descriptors to dress descriptor in the MMU from adding to
translate logical segment numbers and offsets the basic access time of the memory.
into 24-bit physical addresses (as shown in
• By providing a standard, variable-sized unit
Figure 3.4). At the same time, the MMU of memory for the protection, sharing, and
checks for errors such as writing into a read- movement of data.
only segment or a system segment being
accessed by a nonsystem program. MMUs are In addition, segmentation is a natural
designed to be combined so that more than model for the support of modular programs
64 descriptors can be supported at once. The and data in a multi-programming environment.
CPU does not require MMUs; the segment It efficiently supports re-entrant programs by
providing data relocation for different tasks
number can be used directly as part of a
using common code.
physical address.
More information about the MMU and
Some of the benefits of the memory manage-
memory management can be found in An
ment features provided by the MMU are:
Introduction to the Z8010 MMU Memory
• Provision for flexible and efficient allocation Management Unit and in the Z8010 MMU
of physical memory resources during the Manual and the Z8015 Paged MMU User's
execution of programs. Manual.

LOGICAL
(virtual)
ADDRESSING
SPACE PHYSICAL
r--l MEMORY

t
Segments of physical
memory can be loaded
from peripheral devices
through the CPU or DMA.

Figure 3-4. Segmented Address Translation

25
 4
.-
 Chapter 4
CPU Operation

4.1 Intro- This chapter gives a fundamental description Z8000 operation are given in Chapter 7
duction of the operating states of the Z8000 CPU and (Exceptions) and Chapter 8 (Refresh). Chapter
the process of instruction execution. The 9 describes CPU operations as they are mani-
details of instruction execution are described fest on the external pins of the CPU.
in Chapters 5 and 6. Other detailed aspects of

4.2 Operating The Z8000 CPU has three operating states: • An external stop request pushes the CPU
States Running state, Stop/Refresh state, and Bus- into Stopped state.
Disconnect state. Running state is the usual • An external bus request pushes the CPU
state of the processor: the CPU is executing into Bus-Disconnect state.
instructions or handling exceptions. Stop/
Refresh state is entered when the STOP line is 4.2.2 Stop/Refresh State. While the CPU is in
asserted or the refresh counter indicates that a Stop/Refresh state, it generates a continuous
stream of refresh cycles (as discussed in Chap-
periodic refresh should be done. In this state,
ter 8) and does not perform any other func-
memory refresh transactions are generated
tions. This state provides for the generation of
continually (see Chapter 8). Bus-Disconnect
memory refreshes by the CPU and allows
state is entered when the CPU acknowledges a
external devices to suspend CPU operation.
bus request and gives up control of the system
This feature can be used to force single-step
bus. Figure 4.1 shows the three states and the
operation of the processor or to synchronize
conditions that cause state transitions.
the CPU with an Extended Processing Unit (as
4.2.1 Running State. While the CPU is in described in Section 4.4).
Running state, it is either executing instruc- The CPU enters Stop/Refresh state when the
tions (as described in Section 4.3) or handling refresh mechanism needs to do a refresh or
exceptions (as described in Chapter 7). The when the stop line is activated. It leaves Stop/
CPU is normally in Running state, but will Refresh state when neither of these conditions
leave this state in response to one of three con- holds or when a bus request causes the CPU to
ditions: enter Bus-Disconnect state.
• The refresh mechanism indicates that a 4.2.3 Bus-Disconnect State. While the CPU is
periodic refresh needs to be done, in which in Bus-Disconnect state, it does nothing. It
case the CPU temporarily enters Stop/ enters Bus-Disconnect state from either Run-
Refresh state. ning state or Stop/Refresh state when a bus
request has been received on BUSREQ and
STOP RELEASED. OR acknowledged on BUSACK (as described in
PERIODIC REFRESH
COMPLETED Chapter 9). While in this state, it disconnects
itself from the bus by 3-stating its output. It
BUSREQ RELEASED.
STOP INACTIVE STOP ASSERTED. OR leaves Bus-Disconnect state when the external
PERIODIC REFRESH
REQUESTED bus request has been released. Note that Bus-
Disconnect state is highesf in priority in that
the presence of a bus request will force the
CPU into this state, regardless of any con-
ditions indicating that a different state should
be entered.
4.2.4 Effect of Reset. Activation of the CPU's
RESET line puts the CPU in a nonoperational
state within five clock cycles, regardless of its
previous state or the states of its other inputs.
BUSREQ RELEASED. The CPU will remain in this state until RESET
STOP ACTIVE
is deactivated. When this occurs, the program
BUSREQ ASSERTED.
AND ACKNOWLEDGED ON enters one of the three operating states
ii'iJSACi<
described above, depending on the state of
BUSREQ and STOP inputs. Reset is more fully
Figure 4-1. Operating States and Transistions described in Chapters 7 and 9.

29
4.3 Instruction While the CPU is in Running state and exe- memory-to-register instructions, such as a
Execution cuting instructions, it is controlled by the Pro- value in memory being added to the value in a
gram Status registers (Figure 4.2). The Pro- general-purpose register. Part of each instruc-
gram Counter gives the address from which tion is fetched while the previous instruction
instructions are fetched, the flags control execution is being completed. This mechanism
branching (as described in Chapter 6), and provides faster execution speed than the
the control bits determine the mode in which typical alternative of fetching each instruction
the CPU operates and the interrupts that are only after the prior instruction has completed
masked (see Chapter 7). execution.
Instruction execution consists of the repeated After executing an instruction and in some
application of two steps: cases (explained in Chapters 6 and 7) during
• Fetch one or more words comprising a an instruction's execution, the CPU checks to
single instruction from the program memory see if there are any traps or interrupts pending
address space at the address specified by and not masked. If so, it temporarily suspends
the Program Counter (PC). instruction execution and begins a standard
exception-handling sequence. This sequence,
• Perform the operation specified by the which is described fully in Chapter 7, causes
instruction and update the Program Counter the value of the Program Status registers to be
and flags in the Program Status registers. saved and a new value loaded. Instruction exe-
The operation performed by an instruction cution then continues with a new PC value and
and the way the flags are updated depends on Flag and Control Word value. The effect is to
the particular instruction being executed and switch the execution of the CPU from one pro-
is described in Chapter 6. For most instruc- gram to another.
tions, the PC value is updated to point to the 4.3.1 Running-State Modes. While the CPU is
word immediately following the last word of the executing instructions, its mode will be con-
instruction. The effect of this is that instruc- trolled by three control bits in the FCW: the
tions are fetched sequentially from memory. System/Normal Mode bit (SiN), the Segmenta-
Exceptions to this are Branch, Call, Interrupt tion Mode bit (SEG), and the EPA Mode bit.
Return, Load Program Status, System Call, Halt, 4.3.2 Segmented and Nonsegmented
Decrement and Jump if Non-Zero, and Return in- Modes. The segmentation mode of the CPU
structions, which cause the PC to be set to a value (segmented or nonsegmented) determines the
generated by the instruction. This causes a transfer size and format of addresses that are directly
of control with execution continuing at the new manipulated by programs. In segmented mode
address in PC. The exact operation of these in- (SEG = 1), programs manipulate 23-bit seg-
structions is described in Chapter 6. mented addresses; in nonsegmented mode
The 28000 CPU is able to overlap the fetch- (SEG = 0), programs generate 16-bit nonseg-
mg of one instructIon with the operatIon of the mented addresses. There are also the follOWing
previous instruction. This facility, called differences in the address portions of instruc-
Instruction Look-Ahead, is illustrated in Figure tions, which are due to the difference in
4.3. This shows the execution of a series of
I
.. 0
,
•
I
13
,
D
,
0
I
0
I
•
!
0
I
0
!
0
!
0
I
0
,
0
!
0
I
•
!
0
.II........
WORD D
address size:
15

1 Ism IEP·IV1EINV'EI
0 0 IO! 0 I c I z Is IpNI I HID! I }~~~\~~
D 0
•

1-1"*1·..1 1....1• ¥E ! • ! • I I I I I IHI·

c z s PN D ! • Il~: IL......L.'......I.---I.1---l1--JI--I...'--l..'~DDR'SS I
......L.'......I.I---I.'---l--JI--l.-l.-.L.I.....J
lPROORAM
COUNTEFI

28002 Program S:atus RcgJs~(?rs

1·1
I I

28001 Program Slat us R<ocglS'ers

j". I SEQIIBITNtJIIBEA
, ! I j' UPPER POINTER
I ! I ! !

UPPER OFFSET 28002 Frogr"m Sratus Area Pomter

I I I

ZSOOI Program SI"tu, Are" PUInter

RATE
! I I I I ! I
ROW
! I j'R" , RATE
! ! ! ! ! I
ROW
!

28001 Refresh Counter 28002 Retresh CO'lrl'er

Figure .·2. Program StatWl Reglsten

30
4.3 Instruction • Indirect and Base Registers are 32-bit Stack Pointer. As shown in Figure 4.4, there
Execution registers in segmented mode and 16-bit are two Stack Pointer registers (Register 15 in the
(Continued) registers in nonsegmented mode. 28002 and Registers 14 and 15 in the 28001):
• Addresses embedded in instructions are one for normal mode and one for system mode.
always 16-bits in nonsegmented mode. They When in normal mode, a reference to the Stack
consist of a 7-bit segment number and either Pointer register by an instruction will access the
an 8-bit or 16-bit offset in segmented mode. normal Stack Pointer. When in system mode, an
access to the Stack Pointer register will reference
Segmented mode is available only on the the system Stack Pointer, unless the 28001 is run-
28001 CPU; on the 28002, the segment bit is
ning in nonsegmented system mode, in which case
always forced to zero, indicating nonseg-
a reference to R14 will access the normal mode
mented mode. Because the 28001 supports
R14. This is summarized in Table 4.l.
segmented and nonsegmented modes, it is
In normal mode, the system Stack Pointer is
possible to run programs written for the 28002
not accessible; in system mode the normal
on the 28001 without alteration. The reverse is Stack Pointer is accessed by using a special
not possible. The 28001 CPU always generates Load Control Register instruction (described in
segmented addresses, even when operating in Chapter 6).
nonsegmented mode. When a memory access The CPU switches modes whenever the Pro-
is made in nonsegmented mode, the offset of gram Status Control bits change. This can
the segmented address is the 16-bit address happen when a privileged load control instruc-
generated by the program, and the segment
tion is executed or when an exception (inter-
number is the value of the segment number rupt, trap, or reset) occurs. There is a special in-
field of the Program Counter. struction (System Call) whose sole purpose is
4.3.3 Normal and System Modes. The opera- to generate a special trap and thus provide a con-
tion mode of the CPU (system mode or normal trolled transition from normal to system mode.
mode) determines which instructions can be The distinction between normal/system mode
executed and which Stack Pointer register allows the construction of a protected operat-
is used. ing system. This is a program that runs in
In system mode (siN = 1), all instructions system mode and controls the system's
can be executed. While in normal mode, cer- resources, managing the execution of one or
tain privileged instructions that alter sensitive more application programs which run in nor-
parts of the machine state (such as I/O opera- mal mode. Normal and system modes, along
tions or changes to control registers) cannot be with Memory Protection, provide the basis for
executed. protecting the operating system from malfunc-
The second distinction between system and tions of application programs.
normal mode is access to the system or normal

Figure 4-3. Instruction Look-Ahead

Register System Mode Normal Mode

Referenced by - - - - - - - - - - - - - - - - - - - - - - -
Instruction Segmented Nonsegmented Segmented Nonsegmented
Rl4 System Rl4 Normal Rl4 Normal Rl4 Normal Rl4
Rl5 System Rl5 System Rl5 Normal Rl5 Normal Rl5
RRl4 System Rl4 Normal Rl4 Normal Rl4 Normal Rl4
System Rl5 System Rl5 Normal Rl5 Normal Rl5

Note: 28002 always runs In nonsegmented mode.

Table 4.1 Registers Accessed by References to R14 and RIS.

31
4.4 Extended The 28000 CPU supports seven types tion. If the instruction specifies the transfer of
Instructions of extended instructions, which can be exe- data, the CPU will generate the timing signals
cuted cooperatively by the CPU and an exter- for this transfer. The CPU will fetch and begin
nal Extended Processing Unit. The execution executing the next instruction in its instruction
of these instructions is controlled by the EPA stream. The Extended Processing Unit is
control bit in the FCW. expected to monitor the CPU's activity, partici-
When the EPA bit is zero, it indicates that pate in extended instruction data transfers
there is no Extended Processing Unit con- initiated by the CPU, and execute the
nected to the CPU and causes the CPU to trap extended instruction. While the Extended Pro-
(as explained in Chapter 7) when it encounters cessing Unit (EPU) is executing the instruction,
an extended instruction. This allows the opera- the CPU can be fetching and executing futher in-
tion of the extended instruction to be simulated structions. If the CPU fetches another extended
by software running on the CPU. instruction before the Extended Processing Unit is
If the EPA bit is set, it indicates that an finished executing a previous instruction, the
Extended Processing Unit is connected to the STOP line may be used by the EPU to delay the
CPU in order to process the operation encoded CPU until the previous instruction is complete
in the extended instruction. The CPU will fetch This process is described more fully in Chapters
the extended instruction and perform any 6 and 9.
address calculation required by that instruc-
Rol7 0:7 01
RROI
R1115
R'\
RR'I R31
A·I
AA·I
A51
A61
AA': A71
RailS 01
I·" GENERAL

AA·I

I
A'I
A101
I
I
AOB
PURPOSE
REGISTERS

RRlO
A111 I
I A121
RR12 1 R13!

R14 SYSTEM STACK POINTER (SEG, NO.) lAO"

A14 NORMAL STACK POINTER (SEQ. NO.)

AR"I
I
R15
Q1!!
SYSTEM STA.CK POINTER {OFFSETl
NORMAL STACK POINTEH IOFFSETl
I
I

Figure 4-4. General-Purpose Registers

32
 5
. -
--'-11I
17': , _~U
_
=_=
17':'~41W
7;1~,...
Zilog
 Chapter 5
Addressing Modes
5.1 Intro- This chapter describes the eight addressing (opcode). These operands may reside in CPU
duction modes used by instructions to access data in registers or memory locations. The modes by
memory or CPU registers. Separate sets of which references are made to operands are
examples for the nonsegmented and segmented called "addressing modes." Figure 5.1 illus-
modes of operation are given at the end of the trates these modes. Not all instructions can use
chapter. all addressing modes; some instructions can
An instruction is a consecutive list of one or use only a few, and some instructions use none
more words aligned at even-numbered byte at all. In Figure 5.1, the term "operand" refers
addresses in memory. Most instructions have to the data to be operated upon.
operands in addition to an operation code

Addressing Mode Operand Addressing Operand Value

In the Instruction In a Register In Memory

Register I REGISTER ADDRESS ~ The content of the

register

1M

Immediate In the instruction

*IR
The content of the location
Indirect
Register
I REGISTER ADDRESS ~I-------·I OPERAND I whose address is in the
register

DA
The content of the location
Direct ~f--------------".~ whose address is in the
Address instruction

*X The content of the loca-

tion whose address is the
Index address in the instruction
plus the content of the
register.

RA The content of the location

whose address is the
Relative content of the program
counter. offset by the
Address displacement in the
instruction

*BA The content of the location

Base whose address is the
address in the register.
Address offset by the displacement
in the instruction

*BX The content of the loca-

Base tion whose address is
Index the address in a register
plus the index value in
another register.

·Do not use RO or RRO as indirect. index. or base registers.

Figure 5-1. Addressing Modes

35
5.2 Use of The 16 general-purpose CPU registers can, address for an effective address calculation.
CPU Registers with the exceptions noted below, be used in The Program Counter normally is used only to
any of the following ways: keep track of the next instruction to be exe-
• As accumulators, where the data to be cuted; whenever an instruction is fetched from
manipulated resides within the register. memory, the PC is incremented to point to the
• As pointers, where the value in the register next instruction. For addressing purposes,
is the memory address of the operand, however, the updated PC serves as a base for
rather than the operand itself. In string and referencing an operand relative to the location
stack instructions, the pointers may be auto- of an instruction. Operands speCified by rela-
matically stepped either forward or back- tive addressing reside in the program address
ward through memory locations. space if the memory system distinguishes
between program and data or stack address
• As index or base registers, where the con-
spaces.
tents of the register and the word(s) follow-
ing the instruction are combined to produce Two of the addressing modes, Direct
the address of the operand. This allows effi- Address and Index, involve an I/O or memory
cient access to a variety of data structures. address as part of the instruction. I/O
addresses are always 16 bits long, as are non-
There are two exceptions to the above uses
segmented memory addresses (28002), so these
of general-purpose registers:
addresses occupy one word in the instruction.
• Register RO (or the double register RRO in Segmented addresses generated by the 28001
segmented mode) cannot be used as an are 23 bits long. Within an instruction, a seg-
indirect register, base register, index regis- mented address may occupy either two words
ter, or software stack pointer. (l6-bit long offset) or one word (8-bit short
• Register R15' (or the double register RRI4' offset).
in the Z8001) is used in acknowledging As Figure 5.2 illustrates, bit 7 of the seg-
interrupts and therefore can never be used ment number byte distinguishes the two for-
as an accumulator in system-mode opera- mats. When this bit is set, the long-offset
tion. The system-mode registers, Rl4' and representation is implied. When the bit is
R15', are automatically accessed when R14, cleared, the short-offset address representation
R15, or RR14 are referenced by instructions is implied. For a short-offset address, the
executed in system mode. 23-bit segmented address is reduced to 16 bits
In addition to the general-purpose use of by omitting the eight most significant bits of
28000 registers, the folloWing registers are the offset, which are assumed to be zero.
used for special purposes:
• Register R15 (or the double register RR 14 in 8 7 0
the 2800 I) is used as a stack pointer for
subroutine calls and returns. 15
• The byte register RH 1 is used in the
translate instructions (TRDB, TRDRB, I !
long offset
, ! I

TRIB, TRIRB) and the translate and

test instructions (TRTDB, TRTDRB, 15 8 7

short otfset
TRTIB, TRTIRB). ! ! ! !

• Register RO is used in extended instructions.

In Relative Address (RA) mode, the Program Figure 5-2. Segmented Memory Address
Counter (PC) is used instead of a general- Within Instruction.
NOTE: Shaded area is reserved.
purpose CPU register to supply the base

5.3 Addressing The following pages contain descriptions of The descriptions are grouped into two sec-
Mode the addressing modes of the 28000. Each tions-one for nonsegmented CPUs, the other
Descriptions description: for segmented CPUs. Users of the 28002 need
• Explains how the operand address is refer to the first section only; users of the
calculated, 28001 in nonsegmented mode should also refer
• Indicates which address space (Register, to the first section, while users of 28001 in
I/O, Special I/O, Data Memory, Stack segmented mode should refer to the second
Memory, or Program Memory) the operand section. In the examples, hexadecimal notation
is located in, is used for memory addresses and the contents
of registers and memory locations. The %
• Shows the assembly language format used to
symbol precedes hexadecimal numbers in
specify the addressing mode, and
assembly language text.
• Works through an example.

36
5.4 Descrip- In this section, the addressing modes of both After Execution
lions and the 28002 and the nonsegmented mode 2800 I
Examples and 28003 are described. R2 155891
(Z8002 and 5.4.1 Register (R). In the Register Addressing 5.4.3 Indirect Register (lR). In the Indirect
Z8001 Nonseg- mode the instruction processes data taken Register Addressing mode, the data processed
mented Mode) from a specified general-purpose register. is not the value in the speCified register.
Storing data in a register allows shorter Instead, the register holds the address of
instructions and faster execution than occur the data.
with instructions that access memory. 110 or
INSTRUCTION REGISTER MEMORY
INSTRUCTION REGISTER I OPERATION I REGISTER ~
I OPERATION I REGISTER ~I OPERAND I THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS IN
THE REGISTER.
THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER.

The operand is always in the register A single word register is used to hold the
address space. The register length (byte, address. Any general-purpose word register
word, register pair, or register quadruple) is can be used except RO.
specified by the instruction opcode. Depending on the instruction, the operand
Assembler language format: specified by IR mode will be located in either
Standard I/O address space (I/O instructions),
RHn, RLn Byte register Special I/O address space (Special I/O in-
Rn Word register structions), or data or stack memory address
RRn Double-word register spaces . For non -I/O references, the operand
RQn Quadruple-word register will be in stack memory space if the stack
Example of R mode: pointer (R15) is used as the indirect register;
LD R2, R3 !load the contents of! otherwise, the operand will be in data memory
!R3 into R2! space.
The Indirect Register mode may save space
Before Execution
and reduce execution time when consecutive
locations are referenced. This mode can also
R2iA6B81
R3 9A20 be used to simulate more complex addressing
modes, since addresses can be computed
before the data is accessed.
After Execution
Assembler language format (see also
R219A20
R3 9A20
I Chapter 6):
@Rn
5.4.2 Immediate (1M). The Immediate Address- Example of IR mode:
ing mode is the only mode that does not indi- LD R2,@R5 !load R2 with the!
cate a register or memory address as the !data addressed by the!
source operand. The data processed by the !contents of R5!
instruction is in the instruction.
Before Execution Data Memory
INSTRUCTION

OPERATION R2 030F
WORD(S) OPERAND R3 0005 170A A023
THE OPERAND VALUE IS IN THE INSTRUCTION. R4 2000 170C OBOE
R5 170C 170E lODO
Because an immediate operand is part of the
instruction, it is always located in the program
After Execution
memory address space. Immediate mode is
often used to initialize registers. The 28000 is R2 OBOE
optimized for this function, providing several R3 0005
short immediate instructions to reduce the
length of programs. R4 2000
R5 170C
Assembler language format (see also
Chapter 6):
#data
Example of 1M mode:
LDB RH2 #%55 !load hex 55 into RH2!
Before Execution

R2 167891

37
5.4 Descrip- 5.4.4 Direct Address (DA). In the Direct Assembler language format (see also
tions and Addressing mode, the data processed is found Chapter 6):
Examples at the address speCified in the instruction. address (Rn)
(Z8002 and INSTRUCTION
Z8001 Nonseg- Example of X mode:
mented Mode) LD R4,%231A(R3) !load into R4 the con-!
(Continued) !tents of the memory!
THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS IN
THE INSTRUCTION. !location whose!
!address is 231A +!
Depending upon the instruction, the oper- !the value in R3!
and speCified by DA mode will be either in Before Execution Data Memory
Standard I/O space (I/O instructions), in
Special I/O space (Special I/O instructions), or
in data memory space.
R3101FE I 2516 F3C2
R4 203A
This mode is also used by Jump and Call 2518 3DOE
instructions to specify the address of the next
instruction to be executed in program memory. 251A 7ADA
(Actually, the address serves as an immediate
value that is loaded into the Program Counter.) Address Calculation
Assembler language format (see also 231A
Chapter 6): +OIFE
address either memory, I/O, or 2518
Special I/O After Execution
Example of DA mode:
LDB RH2,%5E23 !load RH2 with the! R3io1FE
R4 3DOE
I
!data in address!
!5E23!
5.4.6 Relative Address (RA). In the Relative
Before Execution Addressing mode, the data processed is found
at an address relative to the current instruc-
R2 167891
tion. The instruction specifies a two's comple-
ment displacement which is combined with the
'-'~ ~.L __ ..l_ 1 LL_ ..l ..l _-l...l _
5.4 Descrip- Assembler language format (see also Before Execution Program Memory
tions and Chapter 6):
Examples R21AOFOI
address 0202
(Z8002 and PC 0202 3102 } Instruction
Z8001 Nonseg- Example of RA mode: (Note that the symbol 0204 0002
mented Mode) "$" is used for the value of the current pro-
0206 E801
(Continued) gram counter.)
0208 FFFE
LDR R2,$+ %6 !load into R2 the con-!
!tents of the memory!
!location whose! Address Calculation
!address is the current! 0206
!program counter! + 2
! + hex 6! 0208
Because the program counter will be advanced After Execution
to point to the next instruction when the
address calculation is performed, the constant R21FFFEI
that occurs in the instruction will actually PC 0206
be +2.

5.4.7 Base Address (BA). The Base Address- mode, allows random access to tables or other
ing mode is similar to Index mode in that a data structures where the displacement of an
base and offset are combined to produce the element within the structure is known, but the
effective address. In Base Addressing, how- base of the particular structure must be com-
ever, a register contains the base address, and puted by the program.
the displacement is expressed as a 16-bit value Any word register can be used for the base
in the instruction. The two are added and the address except RD.
resulting address points to the data to be pro- An operand specified by BA mode will be in
cessed. This addressing mode may be used stack memory space if the base register is the
only with the Load instructions. Base stack pointer (R15) and in data memory space
Addressing mode, as a complement to Index otherwise.

THE OPEHAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS THE
ADDRESS IN THE INSTRUCTION. OFFSET BY THE CONTENTS OF THE REGISTER.

Assembler language format (see also Address Calculation

Chapter 6): 20AA
Rn (#disp) + 18
20C2
Example of BA mode: After Execution Data Memory
LDL R5(#%18),RR2 !load the long word!
lin RR2 into the! RR2 R2 OAOO
!memory location! R3 1500 20CO OABE
!whose address is the! R4 3100 20C2 OAOO
!value in R5 + hex! R5 20AA 20C4 1500
!18!
20C6 BODI
Before Execution Data Memory
RR2 R2 OAOO
R3 1500 20CO OABE
R4 3100 20C2 F50D
R5 20AA 20C4 BADE
20C6 BODl

39
5.4 Descrip- 5.4.8 Base Index (BX). The Base Index Before Execution Data Memory
tions and addressing mode is an extension of the Base
R2 IF3A
Examples Addressing mode and may be used only with
(Z8002 and the Load instructions. In this case, both the R3 FFFE 14FE OlGl
Z8001 Nonseg- base address and index (displacement) are R4 0300 1500 BODE
mented Mode) held in registers. This mode allows access to R5 1502 1502 F732
(Continued) memory locations whose physical addresses
are computed at runtime and are not fully
known at assembly time. Address Calculation
Any word register can be used for either the 1502
base address or the index except RD. +FFFE
An operand specified by BX mode will be in 1500
stack memory space if the base register is the After Execution
stack pointer (RI5) and in data memory
otherwise. R2 BODE
Assembler language format (see also R3 FFFE
Chapter 6): R4 0300
Rn (Rm) R5 1502
Example of BX mode:
LD R2,R5(R3) !load into R2 the!
!value whose address!
lis the value in!
!R5 + the value in R3!

REGISTER

L--------11 DISPLACEMENT ~
THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE
ADDRESS IS THE CONTENTS OF REGISTER 1 OFFSET BY THE
DISPLACEMENT IN REGISTER 2.

5.5 Descrip- In this section, «nn» will often be used Before Execution
tions and to refer to segment number nn. RR2 R2 A6B8
Examples 5.5.1 Register (R). In the Register Addressing
R3 9A20
(Segmented mode, the instruction processes data taken
Z8001) from a specified general purpose register.Stor RR4 R4 38A6
ing data in a register allows shorter instruc- R5 745E
tions and faster execution than occurs with After Execution
instructions that access memory.
RR2 R2 38A6
INSTRUCTION REGISTER
R3 745E
I OPERATION I REGISTER ~
RR4 R4 38A6
THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER
R5 745E
The operand is always in the register
address space. The register length (byte, 5.5.2 Immediate (1M): The Immediate Address-
word, register pair, or register quadruple) is ing mode is the only mode that does not indi-
speCified by the instruction opcode. cate a register or memory address as the loca-
tion of the source operand. The data processed
Assembler language formats (see by the instruction is in the instruction.
also Chapter 6):
INSTRUCTION
RHn, RLn Byte register
OPERATION
Rn Word register
WORD(S) OPERAND
RRn Double-word register
THE OPERAND VALUE IS IN THE INSTRUCTION
RQn Quadruple-word
register
Example of R mode:
LDL RR2,RR4 !load the contents!
!of RR4 into RR2!
5.5 Descrip- Because an immediate operand is part of the Example of memory access using IR mode:
tions and instruction, it is always located in the program LD R2,@RR4 !load into R2 the!
Examples memory address space. Immediate mode is !value in the memory!
(Segmented often used to initialize registers. The Z8000 is !location addressed!
Z8001) optimized for this function, providing several ! by the contents of!
(Continued) short immediate instructions to reduce the JRR4J
length of programs.
Before Execution Data Memory
Assembler language format (see also
Chapter 6): RR2 R2 030F
#data R3 0005 ~20~170A A023
Example of 1M mode: RR4 R4 2000 170C OBOE
R5 170C 170E 10D3
LDB RH2,#%55 !load hex 55 into RH2!
Before Execution
After Execution
R2 167891 RR2 R2 OBOE
After Execution R3 0005
R2 155891 RR4 R4 2000
R5 170C
5.5.3 Indirect Register (IR). In the Indirect
Register Addressing mode, the data processed Example of I/O using IR mode:
is not the value in the speCified register. OUTB @Rl,RLO
Instead, the register holds the address of Before Execution
the data.
INSTRUCTION REGISTER
110 or
MEMORY
RO I0A231 Execution sends the
I OPERATION I REGISTER ~ Rl 0011 data "23" to the I/O
THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS IN
device addressed by
THE REGISTER.
"0011."
Depending upon the instruction, the oper- 5.5.4 Direct Address (DA). In the Direct
and specified by IR mode will be located in Addressing mode, the data processed is found
either I/O address space (I/O instructions). at the address speCified in the instruction.
Special I/O address space (Special I/O
instructions), or data or stack memory address
spaces. For non-I/O references, the operand INSTRUCTION
1/0 or
will be in stack memory space if the stack MEMORY

pointer (RR 14) is used as the indirect register, I OPERAND I

otherwise the operand will be in data memory THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS IN
THE INSTRUCTION.
space.
A 16- bit register is used to hold an I/O or Depending upon the instruction, the oper-
Special I/O address; a register pair is used to and speCified by the Direct Address (DA)
hold a memory address. Any general-purpose mode will be either in Standard I/O address
register or register pair may be used except RO space (Standard I/O instructions), Special I/O
or RRO. address space (Special I/O instructions), or in
The Indirect Register mode may save space data memory space. I/O addresses are one
and reduce execution time when consecutive word long; memory addresses can be either
locations are referenced. This mode can also one or two words long, depending on whether
be used to simulate more complex addressing the long or short format is used.
modes, since addresses can be computed This mode is also used by Jump and Call
before the data is accessed. instructions to specify the address of the next
Assembler language formats (see also instruction to be executed. (Actually, the
Chapter 6): address serves as an immediate value that is
loaded into the Program Counter.)
Contains I/O or
Special I/O address.
@RRn Contains memory
address.

41
5.5 Descrip- Assembler language format (see also Example of DA mode:
tions and Chapter 6): LDB RH2, 1« 15» %23 j!load RH2 with the!
Examples address either memory, I/O, or !value in memory!
(Segmented Special I/O where dou- !segment 15, dis-!
Z8001) ble angle brackets !placement 23 (hex)!
(Continued) "«" and "»"
enclose the segment Before Execution Data Memory
number, and vertical
R2 167891
lines "I" and "I"
enclose short-form «15» 00221 o;rn; I

memory addresses. 0024 0304

After Execution
R2 106891

5.5.5 Index (X). In the Index Addressing instruction. The segment number of the oper-
mode, the instruction processes data located at and address comes directly from the instruc-
an indexed address in memory. The indexed tion. (Any overflow is ignored-it neither sets
address is computed by adding the "index" the Overflow flag nor increments the segment
contained in a word register, to an address number.) Indexed addressing allows random
speCified in the instruction also speCified by access to tables or other complex data struc-
the instruction. tures where the address of the base of the table
The offset of the operand address is com- is known, but the particular element index
puted by adding the 16-bit index value to the must be computed by the program.
8 or 16-bit offset portion of the address in the

WORDlS)
....._---_....
THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDl'IESS IS THE
ADDRESS IN THE INSTRUCTION. OFFSET BY THE CONTENTS OF THE REGISTER.

Any word register can be used as the index Address Calculation

register except RD. The address in th.; instruc-
tion can be one or two words, depending on «5» %231A
whether a long or short offset is used in the + OIFE
address.
Operands speCified by X mode are always in «5» %2518
the data memory address space.
Assembler language format: After Execution
address(Rn) R31 OIFE I
Example of X mode: R4 3DOE

LD R4, «5» %231A(R3) !load into R4 the! 5.5.6 Relative Address (RA). In the Relative
!contents of the! Addressing mode, the data processed is found
!memory location! at an address relative to the current instruc-
!whose address is! tion. The instruction specifies a two's comple-
!segment 5,! ment displacement which is added to the offset
!displacement! of the Program Counter to form the target
!231A + the! address. The Program Counter setting used is
!value in R3! the address of the instruction following the
Before Execution Data Memory currently executing instruction. (The assem-
bler will take this into account in calculating
R3j OIFE
R4 203A
I «5» 2516 F3C2
the constant that is assembled into the
instruction. )
2518 3DOE
251A 7ADA
THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE
ADDRESS IS THE CONTENTS OF PC OFFSET BY THE DISPLACEMENT IN THE
INSTRUCTION.

42
5.5 Descrip- An operand specified by RA mode is always 5.5.7 Base Address (BA). The Base
tions and in the program memory address space. Addressing mode is similar to Index mode in
Examples As with the Direct Addressing mode, the that a base and displacement are combined to
(Segmented Relative Addressing mode is also used by cer- produce the effective address. In Base
Z8001) tain program control instructions to specify the Addressing, a register pair contains the 23-bit
(Continued) address of the next instruction to be executed. segmented base address and the displacement
For JR, the result of the addition of the Pro- is expressed as a 16-bit value in the instruc-
gram Counter offset value and the displace- tion. The displacement is added to the offset of
ment is loaded into the Program Counter; for the base address, and the resulting address
DJNZ or CALR instructions; the displacement points to the data to be processed. (The seg-
is then subtracted from the PC offset. Relative ment number is not changed.) This addressing
addressing allows short references forward or mode may be used only with the Load instruc-
backward from the current Program Counter tions. Base Addressing mode, as a complement
value and is used only for such instructions as to Index mode, allows random access to '
Jumps and Calls and special loads (LDR). Note records or other data structures where the
that because the segment number is unchang- displacement of an element within the struc-
ture is known, but the base of the particular
ed relative addresses are located in the same
structure must be computed by the program.
segment as the instruction.

Assembler language format (see also

Chapter 6): THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS
IS THE ADDRESS IN THE REGISTER, OFFSET BY THE DISPLACEMENT IN THE
INSTRUCTION,
address
Example of RA mode: Any double-word register can be used for
the base address except RRO. The Base
LDR R2,$ + 6 !load into R2 the con-J Address mode allows access to locations
!tents of the memory! whose segment numbers are not known at
!location whose! assembly time.
!address is the! An operand specified by BA mode will be in
!current program! stack memory space if the base register is the
!counter + 6! stack pointer (RR14) and in data memory space
Because the program counter will be advanced otherwise.
to point to the next instruction when the If the segment number is known when the
address calculation is performed, the constant program is assembled (or loaded, for example,
that occurs in the instruction will actually if the loader can resolve symbolic segment
be +2. numbers), the Index Addressing mode may
Before Execution Program Memory be used to simulate the Based Addressing
mode. For example, if R2 is known to hold seg-
R2 IAOFO I ment number IS, then the operand specified
«13» 0202 3102 } using the based address RR2 (#93) can also be
0002 Instruction referenced by the indexed address «IS»
0204
%93 (R3). The advantage of this simulation is
I
PC ODOQ
0202
I 0206
020S
ESOI
FFFE
that Index mode is supported for most
operations, whereas based is restricted to
LOAD and LOAD ADDRESS. Thus, using In-
Address Calculation dexed addressing is faster and leads to com-
« 13»0206 pact code.
+ 2 Assembler language format (see also
« 13»020S Chapter 6):
RRn(#disp) Add the immediate
After Execution value to the contents of
R2 IFFFE I RRn; the result is the
address of the operand,
PC IODOO I
0206

43
5.5 Descrip- Example of BA mode: Address Calculation
tions and LDL RR4(#%18),RR2 !load the long word! «31»20AA
Examples !in RR2 into the! + 18
(Segmented !memory location! «31» 20C2
Z8001) !whose address is!
(Continued) After Execution Data Memory
!the value of RR4!
! + hex 18! RR2 R2 OAOO
Before Execution Data Memory R3 1500 «31» 20CO OABE
RR4 R4 IFOO 20C2 OAOO
RR2 R2 OAOO
R5 20AA 20C4 1500
R3 1500 «31 » 20CO OABE
20C6 BODI
RR4 R4 IFOO 20C2 F50D
R5 20AA 20C4 BADE
20C6 BODI

5.5.8 Base Index (BX). The Base Index offset of the operand address. The segment
addressing mode is an extension of the Base number of the operand address is the same as
Addressing mode and may be used only with the base address. This mode allows access to
the LOAD and LOAD ADDRESS instructions. memory locations whose physical addresses
In this case, both the base address and index are computed at runtime and are not fully
are held in registers. The index value is added known at assembly time.
to the offset of the base address to produce the
REGISTERS

,--_AD_D_RE_ss---,~DATA MEMORY
REGISTER
+ I OPERAND I
'----------1 DISPLACEMENT

THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE

ADDRESS IS THE CONTENTS OF REGISTER 2 OFFSET BY THE
DISPLACEMENT IN REGISTER 1.

Any register pair can be used for the base Before Execution Data Memory
address except RRO. Any word register except
RR2 R2 3535
RO can be used for the index. Note that the
Short Offset format for base addresses is ille- R3 FFFE «13» 14FE 0101
gal in registers. RR4 R4 ODOO ]500 BODE
An operand specified by BX mode will be in R5 1502 1502 F732
stack memory space if the base register is the
stack pointer (RR14) and in data memory
otherwise. Address Calculation
«13» 1502
Assembler language format (see also + FFFE
Chapter 6): «13» 1 500
RRn(Rn) After Execution Data Memory
Example of BX mode: RR2 R2 BODE
LD R2,RR4(R3) !load into R2 the value!
!whose address is the!
R3 FFFE «13» 14FE oiol I I
!contents of RR4 +!
RR4 R4
R5
ODOO
1502
1500
1502
IBODE
F732
I
!the contents of R3!

44
 6
.-
 Chapter 6
Instruction Set

6.1 Intro- This chapter describes the instruction set of discussed in relation to the instruction set. This
duction the 28000. An overview of the instruction set is is followed by a section discussing interrupt-
presented first, in which the instructio.ns are ibility of instructions and a description of
divided into ten functional groups. The traps. The last part of this chapter consists of a
instructions in each group are listed, followed detailed description of each 28000 instruction,
by a summary description of the instructions. listed in alphabetical order. This section is
Significant characteristics shared by the intended to be used as a reference by 28000
instructions in the group, such as the available programmers. The entry for each instruction
addressing modes, flags affected, or inter- includes a description of the instruction,
ruptibility, are described. Unusual instructions addressing modes, assembly language mne-
or features that are not typical of predecessor monics, instruction formats, execution times
microprocessors are pointed out. and simple examples illustrating the use of the
Following the functional summary of the instruction.
instruction set, flags and condition codes are

6.2 Functional This section presents an overview of the The Load and Exchange group includes a
Summary 28000 instructions. For this purpose, the variety of instructions that provide for move-
instructions may be divided into ten functional ment of data between registers, memory, and
groups: the program itself (i.e., immediate data). These
• Load and Exchange instructions are supported with the widest
range of addressing modes, including the Base
• Arithmetic
(BA) and the Base Index (BX) mode which are
• Logical available here only. None of these instructions
• Program Control affect any of the CPU flags.
• Bit Manipulation The Load and Load Relative instructions
• Rotate and Shift transfer a byte, word, or long word of data
• Block Transfer and String Manipulation from the source operand to the destination
operand. A special one-word instruction, LDK,
• Input/Output
is also included to handle the frequent require-
• CPU Control ment for loading a small constant (0 to 15) into
• Extended Instructions a register.
6.2.1 Load and Exchange Instructions. These instructions basically provide one of
Instruction Operandlsl Name of Instruction the follOWing three functions:
CLR dst Clear • Load a register with data from a register or
CLRB a memory location.
EX dst, src Exchange • Load a memory location with data from a
EXB register.
lO ds!, src Load • Load a register or a memory location with
lOB immediate data.
lOL
dst, src
The memory location is speCified using any
lOA Load Address
of the addressing modes OR, DA, X, BA,
lOAR dst, src Load Address Relative
BX, RA).
lOK dst, src Load Constant The Clear and Clear Byte instructions can
lOM dst, src, num Load Multiple be used to clear a register or memory location
lOR dst, src Load Relative to zero. While this is functionally equivalent to
lORB a Load Immediate where the immediate data is
lORL zero, this operation occurs frequently enough
POP ds!, src Pop to justify a special instruction that is more
POPL compact and faster.
PUSH dst, src Push
PUSHL

47
6.2 Functional The Exchange instructions swap the contents The Arithmetic group consists of instructions
Summary of the source and destination operands. for performing integer arithmetic. The basic
(Continued) The Load Multiple instruction provides for instructions use standard two's complement
efficient saving and restoring of registers. This binary format and operations. Support is also
can significantly lower the overhead of pro- provided for implementation of BCD
cedure calls and context switches such as arithmetic.
those that occur at interrupts. The instruction Most of the instructions in this group per-
allows any contiguous group of 1 to 16 regis- form an operation between a register operand
ters to be transferred to or from a memory and a second operand designated by any of
area, which can be designated using the DA, the five basic addressing modes, and load the
IR or X addressing modes. (RO is considered to result into the register.
follow R15, e.g., one may save R9-R15 and The arithmetic instructions in general alter
RO-R3 with a single instruction.) the C, Z, Sand P/V flags, which can then be
Stack operations are supported by the tested by subsequent conditional jump instruc-
PUSH, PUSHL, POP, and POPL instructions. tions. The PIV flag is used to indicate arith-
Any general-purpose register (or register pair metic overflow for these instructions and it is
in segmented mode) may be used as the stack referred to as the V (overflow) flag. The byte
pointer except RO and RRO. The source version of these instructions generally alters
operand for the Push instructions and the the D and H flags as well.
destination operand for the Pop instructions The basic integer (binary) operations are
may be a register or a memory location, performed on byte, word or long word oper-
specified by the DA, IR, or X addressing ands, although not all operand sizes are sup-
modes. Immediate data can also be pushed ported by all instructions. Multiple precision
onto a stack one word at a time. Note that byte operations can be implemented in software
operations are not supported, and the stack using the Add with Carry, (ADC, ADCB),
pointer register must contain an even value Subtract with Carry (SBC, SBCB) and Extend
when a stack instruction is executed. This is Sign (EXTS, EXTSB, EXTSL) instructions.
consistent with the general restriction of using BCD operations are not provided directly,
even addresses for word and long word but can be implemented using a binary addi-
accesses. tion (ADC, ADCB) or subtraction (SUBB,
The Load Address and Load Address Rela- SBCB) followed by a decimal adjust instruc-
tive instructions compute the effective address tion (DAB).
for the DA, X, BA, BX and RA modes and The Multiply and Divide instructions perform
return the value in a register. They are use- signed two's complement arithmetic on word or
ful for management of complex data structures. long word operands. The Multiply instruction
(MULT) mutliplies two 16-bit operands and
6.2.2 Arithmetic Instructions
produces a 32-bit result, which is loaded into
Instruction Operand(s) Name of Instruction
the destination register pair. Similarly, Mult-
ADC dst, src Add with Carry iply Long (MULTL) multiplies two 32-bit oper-
ADCB
ands and produces a 64-bit result, which is
ADD dsl, HC Add loaded into the destination register quadruple.
ADDB
ADDL
An overflow condition is never generated by a
multiply, nor can a true carry be generated.
CP dsl, src Compare
CPB
The carry flag is used instead to indicate
CPL where the product has too many significant bits
DAB dst Decimal Adjust
to be contained entirely in the low-order half
of the destination.
DEC dst, src Decrement
DECB
The Divide instruction (DIV) divides a 32-bit
number in the destination register pair by a
DIV us!, src Divide
DIVL
16-bit source operand and loads a 16-bit quo-
tient into the low-order half of the destination
EXTS dst Extend Sign
EXTSB
register. A 16-bit remainder is loaded into the
EXTSL high-order half. Divide Long (DIVL) operates
INC dsl, src Increment
similarly with a 64-bit destination register
INCB quadruple and a 32-bit source. The overflow
MULT cist, src MultIply
flag is set if the quotient is bigger than the
MULTL low-order half of the destination, or if the
NEG cist Negate source is zero.
NEGB
SBC dst, src Subtract with Carry
SBCB
SUB dst, src Subtract
SUBB
SUBL

48
6.2 Functional 6.2.3 Logical Instructions. registers and memory are not altered except
Summary Instruction Operand(s) Name of Instruction for the processor stack pointer and the pro-
(Continued) AND dSI, src And cessor stack, which playa significant role in
AN DB procedures and interrupts. (An exception is
COM dst Complement Decrement and Jump if Not Zero (DJNZ), which
COMB uses a register as a loop counter.) The flags
OR dst, src Or are also preserved except for IRET which
ORB reloads the program status, including the
TEST dst Test flags, from the processor stack.
TESTB The Jump OP) and Jump Relative OR)
TESTL instructions provide a conditional transfer of
XOR dst, src Exclusive Or control to a new location if the processor flags
XORB statisfy the condition speCified in the condition
code field of the instruction. (See Section 6.4
The instructions in this group perform logi- for a description of condition codes.) Jump
cal operations on each of the bits of the oper- Relative is a one-word instruction that will
ands. The operands may be bytes or words; jump to any instruction within the range -254
logical operations on long word are not sup- to + 256 bytes from the current location. Most
ported (except for TESTL) but are easily imple- conditional jumps in programs are made to
mented with pairs of instructions. locations only a few bytes away; the Jump
The two-operand instructions, And (AND, Relative instruction exploits this fact to
ANDB), Or (OR, ORB) and Exclusive-Or improve code compactness and efficiency.
(XOR,XORB) perform the appropriate logical Call and Call Relative are used for calling
operations on corresponding bits of the desti- procedures; the current contents of the PC are
nation register and the source operand, which pushed onto the processor stack, and the effec-
can be designated by any of five basic ad- tive address indicated by the instruction is
dressing modes (R, IR, DA, 1M, X). The result loaded into the PC. The use of a procedure
is loaded into the destination register. address stack in this manner allows straight-
Complement (COM, COMB) complements forward implementation of nested and recur-
the bits of the destination operand. Finally, sive procedures. Like Jump Relative, Call
Test (TEST, TESTB, TESTL) performs the OR Relative provides a one-word instruction for
operation between the destination operand and calling nearby subroutines. However, a much
zero and sets the flags accordingly. The Com- larger range, -4092 to + 4098 bytes for CALR
plement and Test instructions can use four instruction, is provided since subroutine calls
basic addressing modes to specify the exhibit less locality than normal control
destination (Immediate mode is excluded.) transfers.
The Logical instructions set the Z and S flags
Both Jump and Call instructions are
based on the result of the operation. The byte
available with the indirect register, indexed
variants of these instructions also set the Parity
and relative address modes in addition to the
Flag (PIV) if the parity of the result is even,
direct address mode. These can be useful for
while the word instructions leave this flag
implementing complex control structures such
unchanged. The Hand D flags are not affected
as dispatch tables.
by these instructions.
The Conditional Return instruction is a com-
6.2.4 Program Control Instructions. panion to the Call instruction; if the condition
Instruction Operand(s) Name of Instruction speCified in the instruction is satisfied, it loads
CALL dSl Call Procedure the PC from the stack and pops the stack.
A special instruction, Decrement and Jump
CALR dSl Call Procedure Relative
if Not Zero (DJNZ, DBJNZ) , implements the
DJNZ r, ds! Decrement and lump if
control part of the basic PASCAL FOR loop in
DBJNZ No! Zero
a one-word instruction.
!RET Interrupt Return
System Call (SC) is used for controlled
IP CC, ds' lump access to facilities provided by the operating
JR CC, ds: I ump Relative system. It is implemented identically to a trap
RET cc Return from Procedure or interrupt: the current program status is
SC src System Call pushed onto the system processor stack fol-
lowed by the instruction itself, and a new pro-
This group consists of the instructions that
gram status is loaded from a dedicated part of
affect the Program Counter (PC) and thereby
control program flow. General-purpose

49
6.2 Functional the Program Status Area. An 8-bit immediate instruction. (See Section 5.6.1 for a list of con-
Summary source field in the instruction is ignored by the dition codes.) This may be used to control sub-
(Continued) CPU hardware. It can be retrieved from the sequent operation of the program after the
stack by the software which handles system flags have been changed by intervening
calls and interpreted as desired, for example instructions. It may also be used by language
as an index into a dispatch table to implement compilers for generating boolean values.
a call to one of the services provided by the 6.2.6 Rotate and Shift Instructions.
operating system. Instruction Operand(sl Name of Instruction
Interrupt Return (IRET) is used for returning
RL dst, src Rotate Left
from interrupts and traps, including system RLB
calls, to the interrupted routines. This is a
RLC dst, src Rotate Left through
privileged instruction. RLCB Carry
6.2.5 Bit Manipulation Instructions RLDB dst, src Rotate Left Digit
Instruction Operand(sl Name of Instruction
RR dst, src Rotate Right
BIT dst, src Bit Test RRB
BITB
RRC dst, src Rotate Right through
RES dst, src Reset Bit RRCB Carry
RESB Rotate Right Digit
RRDB dst, src
SET dst, src Set Bit Shift Dynamic Arithmetic
SDA dst, src
SETB
SDAB
TSET dst Test and Set ,SDAL
TSETB dst, src Shift Dynamic Logical
SDL
TCC cc, dst Test Condition Code SDLB
TCCB SDLL
The instructions in this group are useful for SLA dst, src Shift Left Arithmetic
manipulating individual bits in registers or SLAB
C:11I1
6.2 Functional 6.2.7 Block Transfer And String Manipula- using the value of each byte as the address of
Summary tion Instructions. its own replacement in a translation table. The
(Continued) Instruction Operand(s) Name of Instruction
more complex Translate and Test instructions
skip over a class of bytes specified by a
CPO dst, src, r, cc Compare and Decrement
CPDB
translation table, detecting bytes with values
of special interest.
CPDR ds!, src, r, cc Compare, Decrement and
C;PDRB Repeat
All the operations can proceed through the
data in either direction. Furthermore, the
CPI dst, src, r, cc Compare and Increment
CPIB
operations may be repeated automatically
while decrementing a length counter until it is
CPIR dst, src, r, cc Compare, Increment and
CPIRB Repeat
zero, or they may operate on one storage unit
per execution' with the length counter decre-
CPSD dst, src, r, cc Compare String and
CPSDB Decrement
mented by one and the source and destination
pointer registers properly adjusted. The latter
CPSDR dst, src, r, cc Compare String,
CPSDRB Decrement and Repeat
form is useful for implementing more complex
operations in software by adding other instruc-
CPSI dst, src, r, cc Compare String and
CPSIB Increment
tions within a loop containing the block
instructions.
CPSIR dst, src, r, cc Compare String,
CPSIRB Increment and Repeat
Any word register can be used as a length
counter in most cases. If the execution of the
LOD dst, src, r Load and Decrement
LODB
instruction causes this register to be decre-
mented to zero, the P/V flag is set. The auto-
LODR dst, src, r Load, Decrement and
LODRB Repeat
repeat forms of these instructions always leave
this flag set.
LDI dst, src, r Load and Increment
LOIB
The D and H flags are not affected by any of
these instructions. The C and S flags are
LDIR dst, src, r Load, Increment and
LOIRB Repeat
preserved by all but the compare instructions.
These instructions use the Indirect Register
TRDB dst, src, r Translate and Decrement
OR) addressing mode: the source and destina-
TRDRB dst, src, r Translate, Deciement and tion operands are addressed by the contents of
Repeat
general-purpose registers (word registers in
TRIB dst, src, r Translate and Increment nonsegmented mode and register pairs in seg-
TRIRB dst, src, r Translate, Increment and mented mode). Note that in the segmented
Repeat mode, only the low-order half of the register
TRTDB srcl, src2, r Translate, Test and pair gets increnented or decremented as with
Decrement all address arithmetic in the Z8000.
TRTDRB srcl, src2, r Translate, Test, The repetitive forms of these instructions are
Decrement and Repeat interruptible. This is essential since the repeti-
TRTIB srcl, src2, r Translate, Test and tion count can be as high as 65,536 and the
Increment instructions can take 9 to 14 cycles for each
TRTIRB srcl, src2, r Translate, Test, Increment iteration after the first one. The instruction can
ahd Repeat be interrupted after any iteration. The address
of the instruction itself, rather than the next
This is an exceptionally powerful group of
one, is saved on the stack, and the contents of
instructions that provides a full complement of
the operand pointer registers, as well as the
string comparison, string translation and block
repetition counter, are such that the instruc-
transfer functions. Using these instructions, a
tion can simply be reissued after returning
byte or word block of any length up to 64K
from the interrrupt without any visible dif-
bytes can be moved in memory; a byte or word
ference in its effect.
string can be searched until a given value is
found; two byte or word strings can be com-
pared; and a byte string can be translated by

51
6.2 Functional 6.2.8 Input/Output Instructions. are connected to bus lines ADs-AD I5. SpeCIal
Summary Instruction Operand(s) Name of Instruction I/O byte instructions use even addresses only.
(Continued) IN dst, src Input The instructions for transferring a single
INB byte or word (IN, INB, OUT, OUTB, SIN,
IND dst, src, r Input and Decrement SINB, SOUT, SOUTB) can transfer data
INDB between any general-purpose register and any
INDR dst, src, r Input, Decrement and port in either address space. For the Standard
INDRB Repeat I/O instructions, the port number may be
INI ds!, src, r Input and Increment specified statically in the instruction or dynam-
INIB ically by the contents of the CPU register. For
INIR dst, src, r Input, Increment and the Special I/O instructions the port number is
INIRB Repeat specified statically.
OTDR dst, src, r Output, Decrement and The remaining instructions in this group
OTDRB Repeat form a powerful and complete complement of
OTIR dst, src, r Output, Increment and instructions for transferring blocks of data
OTIRB Repeat between I/O ports and memory. The operation
OUT dst, src Output of these instructions is very similar to that of
OUTB the block move instructions described earlier,
OUTD dst, src, r Output and Decrement with the exception that one operand is always
OUTDB an I/O port which remains unchanged as the
OUTI dst, src, r Output and Increment address of the other operand (a memory loca-
OUTIB tion) is incremented or decremented. These
SIN dst, src Special Input instructions are also interruptible.
SINB All I/O instructions are privileged, i.e. they
SIND dst, src, r Special Input and can be executed only in system mode. The
SINDB Decrement single byte/word I/O instructions don't alter
SINDR dst, src, r Special Input, Decrement any flags. The block I/O instructions, includ-
SINDRB and Repeat ing the single iteration variants, alter the 2 and
SINI dst, src, r Special Input and PIV flags. The latter is set when the repetition
SINIB Increment counter is decremented to zero.
SINIR dst, src, r Special Input, Increment 6.2.9 CPU Control Instructions.
SINIRB and Repeat Instruction Operand(s) Name of Instruction
SOTDR dst, src, r Special Output, COMFLG flag Complement Flag
SOTDRB Decrement and Repeat
DI int Disable Interrupt
SOTIR dst, src, r Special Output,
SOTIRB Increment and Repeat EI in! Enable Interrupt

SOUT ds! src Special Output HALT Halt

SOUTB LDCTL dst, src Load Control Register
SOUTD dst, src, r Special Output and LDCTLB
SOUTDB Decrement LDPS src Load Program Status
SOUTI dst, src, r Special Output and MBIT Multi-Micro Bit Test
SOUTIB Increment
MREQ dst Multi-Micro Request
This group consists of instructions for trans- MRES Multi-Micro Reset
ferring a byte, word or block of data between MSET Multi-Micro Set
peripheral devices and the CPU registers or NOP No Operation
memory. Two separate I/O address spaces with
RESFLG flag Res~t Flag
l6-bit addresses are recognized, a Standard
I/O address space and a Special I/O address SETFLG flag Set Flag
space. The latter is intended for use with The instructions in this group relate to the
special 28000 Family devices, typically an CPU control and status registers (FCW, PSAP,
MMU. Instructions that operate on the REFRESH, etc.), or perform other unusual
Special I/O address space are prefixed with functions that do not fit into any of the other
the word "special." Standard I/O and Special groups, such as instructions that support multi-
I/O instructions generate different codes on microprocessor operation. Most of these
the CPU status lines. Normal 8-bit peripherals instructions are privileged, with the exception
are connected to bus lines AD o-AD7. Standard of NOP and the instructions operating on the
I/O byte instructions use odd addresses only. flags (SETFLG, RESFLG, COMFLG,
Special 8-bit peripherals such as the MMU, LDCTLB).
which are used with Special I/O instructions,

52
6.2 Functional 6.2.10 Extended Instructions. The 28000 memory and EPU; da ta transfers between EPU
Summary architecture includes a powerful mechanism and CPU; and data transfers between EPU flag
(Continued) for extending the basic instruction set through registers and CPU flag and control word. The
the use of external devices known as Extended last type is useful when the program must
Processing Units (EPUs). (See Section 2.12 for branch based on conditions determined by the
a more comprehensive presentation of the EPU. The action taken by the CPU upon
Extended Processor Architecture.) A group of encountering extended instructions is depen-
six opcodes, OE, OF, 4E, 4F, 8E and 8F (in dent upon the EPA control bit in the CPU's
hexadecimal), is dedicated for the implemen- FCW. When this bit is set, it indicates that the
tation of extended instructions using this facil- system configuration includes EPUs; therefore,
ity. The five basic addressing modes (R, JR, the instruction is executed. If this bit is clear,
DA, 1M and X) can be used by extended the CPU traps (extended instruction trap) so
instructions for accessing data for the EPUs. that a trap handler in software can emulate the
There are four types of extended instructions desired operation.
in the 28000 CPU instruction repertoire: EPU
internal operations; data transfers between

6.3 Processor The processor flags are a part Of the pro- The FLAGS register can be separately
Flags gram status (Section 2.7.1). They provide a loaded by the Load Control Register (LDCTLB)
link between sequentially executed instructions instruction without disturbing the control bits
in the sense that the result of executing one in the other byte of the FCW. The contents of
instruction may alter the flags, and the the flag register may also be saved in a reg-
resulting value of the flags may be used to ister or memory.
determine the operation of a subsequent The Carry (C) flag, when set, generally indi-
instruction, typically a conditional jump cates a carry out of or a borrow into the high-
instruction. An example is a Test followed by a order bit position of a register being used as
Conditional Jump: an accumulator. For example, adding the 8-bit
TEST R1 !sets 2 flag if R1 = O! numbers 225 and 64 causes a carry out of bit 7
JR 2, DONE !go to DONE if 2 flag is and sets the Carry flag:
set! Bit
4

225 o o o
+ 64 o o o
DONE:
289 1 0
The program branches to DONE if the TEST Carry flag
sets the 2 flag, i.e., if R1 contains zero.
The program status has six flags for the use The Carry flag plays an important role in the"
of the programmer and the 28000 processor: implementation of multiple-precision arithmetic
(see the ADC, SBC instructions). It is also
• Carry (C)
involved in the Rotate Left Through Carry
• 2ero (2) (RLC) and Rotate Right Through Carry (RRC)
• Sign (S) instructions. One of these instructions is used
to implement rotation or shifting of long strings
• Parity/Overflow (PIV)
of bits.
• Decimal Adjust (D) The 2ero (2) flag is set when the result reg-
• Half Carry (H) ister's contents are zero following certain
operations. This is often useful for deter-
The flags are modified by many instructions,
mining when a counter reaches zero. In addi-
including the arithmetic and logical
tion, the block compare instructions use the 2
instructions.
Appendix C lists the instructions and the flag to indicate when the specified comparison
flags they affect. In addition, there are 28000 condition is satisfied.
CPU control instructions which allow the pro- The Sign (S) flag is set to one when the most
grammer to set, reset (clear), or complement significant bit of a result register contains a
any or all of the first four flags. The Half-Carry one (a negative number in two's complement
and Decimal-Adjust flags are used by the notation) following certain operations.
28000 processor for BCD arithmetic correc-
tions. They are not used explicitly by the pro-
grammer.

53
6.3 Processor The Overflow (V) flag, when set, indicates The Block Move and String instructions and
Flags that a two's complement number in a result the Block I/O instructions use the PIV flag to
(Continued) register has exceeded the largest number or is indicate the repetition counter has decre-
less than the smallest number that can be mented to o.
represented in a two's complement notation. The Decimal-Adjust (D) flag is used for BCD
This flag is set as the result of an arithmetic arithmetic. Since the algorithm for correcting
operation. Consider the following example: BCD operations is different for addition and
Bit
subtraction, this flag is used to record whether
4 0 an add or subtract instruction was executed so
that the subsequent Decimal Adjust (DAB)
120 0 I 0 0 instruction can perform its function correctly
+ 105 0 0 0 I
(See the DAB instruction for further discussion
225 0 0 on the use of this flag).
Overflow flag set The Half-Carry (H) flag indicates a carry out
of bit 3 or a borrow into bit 3 as the result of
The result in this case (-31 in two's comple- adding or subtracting bytes containing two
ment notation) is incorrect, thus the overflow BCD digits each. This flag is used by the DAB
flag would be set. instruction to convert the binary result of a
The same bit acts as a Parity (P) flag follow- previous decimal addition or subtraction into
ing logical instructions on byte operands. The the correct decimal (BCD) result.
number of one bits in the register is counted Neither the Decimal-Adjust nor the Half-
and the flag is set if the total is even (that is, Carry flag is normally accessed by the pro-
P = 1). If the total is odd, the flag is reset grammer.
(P = 0). This flag is often referred to as the
PIV flag.

6.4 Condition The first four flags, C, Z, S, and P/V, are forms a part of all conditional instructions.
_. __ ..J .1. .L __ l .ll- ..... .L~ __ .... ! ...... _ ..... .L .... ~ ...... " ................. ...J. T~,", ................. ......l; ... ; ........................ ......l .......... :::l ..... ,..l tho tl=ar...- C'~++1T"\....,.C"
6.5 Instruction The 28000 CPUs implement four kinds of ware which is invoked by the Extended
Interrupts traps: Instruction trap.
and Traps _ Extended Instruction The Privileged Instruction trap serves to pro-
(Continued) tect the integrity of a system from erroneous or
_ Privileged Instruction in normal mode
unauthorized actions of arbitrary processes.
_ Addressing violation (Segment Trap in Certain instructions, called privileged instruc-
28001 and Address Trap in 28003) tions, can only be executed in system mode.
_ System Call An attempt to execute one of these instructions
in normal mode causes a Privileged Instruction
The Extended Instruction trap occurs when trap. All the 1/0 instructions and most of the
an Extended Instruction is encountered, but instructions that operate on the FCW are
the Extended Processor Architecture Facility is privileged, as are instructions like HALT
disabled, i.e., the EPA bit in the FCW is a and IRET.
zero. This allows the same software to be run The System Call instruction always causes a
on 28000 system configurations with or without trap. It is used to transfer control to system
EPUs. On systems without EPUs, the desired mode software in a controlled way, typically to
extended instructions can be emulated by so£1- request supervisor services.

6.6 Notation The rest of this chapter consists of detailed instruction recognized by the assembler. For
and Binary descriptions of each instruction, listed in example,
Encoding alphabetical order. This section describes the ADD Rd.#data
notational conventions used in the instruction
descriptions and the binary encoding for some represents a statement of the form
of the common instruction fields (e.g., register ADD R3,#35. The assembler will also accept
designation fields). variations like ADD TOTAL, #NEW-DELTA
The description of an instruction begins with where TOTAL, NEW and DELTA have been
the instruction mnemonic and instruction name suitably defined.
in the top part of the page. Privileged instruc- The follOWing notation is used for register
tions are also identified at the top. operands:
The assembler language syntax is then given Rd, Rs a word register in the
in a single generic form that covers all the range RO-RI5
variants of the instruction, along with a list of Rbd, Rbs: a byte register RHn or
applicable addressing modes. RLn where n = 0 - 7
RRd, RRs: a register pair RRO, RR2,
Example:
... RR14
AND dst, src dst: R RQd: a register quadruple
ANDB src: R, 1M, IR, DA, X RQO, RQ4, RQ8 or RQ12
The operation of the instruction is presented The "s" or "d" represents a source or destina-
next, followed by a detailed discussion of the tion operand. Address registers used in
instruction. Indirect. Base and Base Index addressing
The next part specifies the effect of the modes represent word registers in nonseg-
instruction on the processor flags. This is mented mode and register pairs in segmented
followed by a table that presents all the mode; this situation is flagged and a footnote
variants of the instruction for each applicable explains the situation.
addressing mode and operand size. For each
B. Instruction Format. The binary encoding of
of these variants, the follOWing information is
the instruction is given in each case for both
provided:
the nonsegmented and segmented modes.
A. Assembler Language Syntax. The syntax Where applicable, both the short and long
is shown for each applicable operand width forms of the segmented version are given (SS
(byte, word or long). The invariant part of the and SL).
syntax is given in UPPER CASE and must The instruction formats for byte and word
appear as shown. Lower case characters repre- versions of an instruction are usually com-
sent the variable part of the syntax, for which bined. A single bit, labeled "w," distinguishes
suitable values are to be substituted. The syn-
tax shown is for the most basic form of the

55
6.6 Notation them: a one indicates a word instruction, while Register Binary
and Binary a zero indicates a byte instruction. RII RL3 1011
Encoding Fields specifying register operands are RQI2 RRI2 RI2 RL4 1100
RI3 RL5 1101
(Continued) identified with the same symbols (Rs, RRd, RRI4 RI4 RL6 1110
etc.) as in Assembler Language Syntax. In RI5 RL7 IIII
some cases, only nonzero values are permitted
for certain registers, such as index registers. For easy cross- references, the same symbols
This is indicated by a notation of the form are used in the Assembler Language Syntax
"RS *- 0." and the instruction format. In the case of relative
The binary encoding for register fields is as addresses, the assembler format uses "address,"
follows: while the instruction format contains "displace-
Register Binary ment," indicating that the assembler has com-
RQO RRO RO RHO 0000
puted the displacement and inserted it as indicated.
Rl RHI 0001 A condition code is indicated by "cc" in
RR2 R2 RH2 0010 both the Assembler Language Syntax and the
R3 RH3 0011 instruction formats. The condition codes, the
RQ4 RR4 R4 RH4 0100
R5 RH5 0101 flag settings they represent, and the binary
RR6 R6 RH6 0110 encoding in the instruction are as follows:
R7 RH7 aliI
RQ8 RR8 R8 RLO 1000
R9 RLI 1001
RRIO RIO RL2 1010

Code Meaning Flag Setting Binary

F Always false 0000
Always true 1000
Z Zero Z = I 0110
N2 Not zero 2 = 0 1110
C Carry C=I 0111
NC No carry C = 0 IIII
PL Plus 5 = 0 1101
MI Minus 5 = I 0101
NE Not equal Z = 0 1110
EQ Equal 2 = I OlIO
OV Overflow V = I 0100
NOV No overflow V = a 1100
PE Parity even P = I 0100
PO Parity odd P = a 1100
GE Greater than (5 XOR V) = 0 1001
or equal
LT Less than (5 XOR V) = I 0001
GT Greater than (Z OR (5 XOR V)) = a 1010
LE Less than or (Z OR (5 XOR V)) = I 0010
equal
UGE Unsigned C = a III I
greater than
or equal
ULT Unsigned C = I 0111
less than
UGT Unsigned ((C = 0) AND (2 = 0)) 1011
greater than
ULE Unsigned less (C OR 2) = I 0011
than or equal

Note that some of the condition codes correspond to identical flag settings: i.e., Z-EQ, N2-NE,
NC-UGE, PE-OV, PO-NOV.

C. Cycles. This line gives the execution time D. Example. A short assembly language
of the instructions in CPU cycles. example is given showing the use of the
instruction.

56
6.7 Z8000
Instruction ADC
Descriptions
and Formats
Add With Carry
ADC dst, src dst: R
ADCB src: R

Operation: dst -- dst + src + c

The source operand, along with the setting of the carry flag, is added to the destina-
tion operand and the sum is stored in the destination. The contents of the source are
not affected. Two's complement addition is performed. In multiple precision arith-
metic, this instruction permits the carry from the addition of low-order operands to
be carried into the addition of high-order operands.

Flags: C: Set if there is a carry from the most significant bit of the result; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise
D: ADC-unaffected; ADCB-cleared
H: ADC-unaffected; ADCB-set if there is a carry from the most significant bit of
the low-order four bits of the result; cleared otherwise

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: ADC Rd, Rs
ADCB Rbd, Rbs ~ 5 ~ 5

Example: Long addition can be done with the following instruction sequence, assuming RO, Rl
contain one operand and R2, R3 contain the other operand:
ADD Rl,R3 !add low-order words!
ADC RO,R2 !add carry and high-order words!
If RO contains %0000, Rl contains %FFFF, R2 contains %4320 and R3 contains
%0001/ then the above two instructions leave the value %4321 in RO and %0000
in Rl.

57
ADD
Add
ADD dst, src dst: R
ADDB src: R, 1M, IR, DA, X
ADDL

Operation: dst ....- dst + src

The source operand is added to the destination operand and the sum is stored in the
destination. The contents of the source are not affected. Two's complement addition
is performed.

Flags: c: Set if there is a carry from the most significant bit of the result; cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise
D: ADD, ADDL-unaffected; ADDB-cleared
H: ADD, ADDL-unaffected; ADDB-set if there is a carry from the most significant
bit of the low-order four bits of the result; cleared otherwise

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: ADD Rd, Rs
ADDB Rbd, Rbs ~ 4 ~ 4

ADDL RRd, RRs

~1010ll0~ ~lol0llol~
I 8 8

1M: ADD Rd, #data 00\ 000001 \ 0000 I Rd 001000001 1 0000 \ Rd

7 7
data data

ADDB Rbd, #data Rbel 001000000 10000 \ Rbel

001000000 \00001
7 7
data \ data data I data

ADDL RRd, #data I

o 0 0 1 0 1 1 0 \ 0 0 0 0 \ RRd 001010110100001 RRd

31 data (high) 16 14 31 data (high) 16 14

15 data (low) 0 15 data (low) 0

IR: ADD Rd, @Rsl

ADDB Rbd, @Rsl
~oooooB Rs*O I Rd I 7 ~100000[!J RRs..o I Ad I 7

ADDL RRd, @Rsl

~010110~ 14 §I010l10f~ 14

58
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: ADD Rd, address

ADDB Rbd, address
101100000[wl 0000 1 Rd I 9
SS 01100000lwlooool Rd
10
I address I o 1 segment I offset

01100000lwlooool Rd
SL 11 segment I 00000000 12
offset

ADDL RRd, address

I0 1 I 0 1 0 1 1 0 I0 0 0 0 1 RRd I 15 SS
I
o1 0 10110 I 0 0 0 0 1 RRd 16
I address I o I segment 1 offset

o 1 1 0 1 0 1 1 0 10 0 0 0 I RRd
SL 11 segment I 00000000 18
offset

X: ADD Rd, addr(Rs)

I
ADDB Rbd, addr(Rs)
101100000lwi RHO 1 Rd I 10 SS
o 1100000lwi Rs*O Rd
10
I address I o I segment I offset

01100000lwi Rs*O I Rd

SL 11 segment I 00000000 13
offset

ADDL RRd, addr(Rs)

I0 1 I 0 1 0 1 1 0 I Rs * 0 I RRd I 16 SS
011 010110 1 Rs*O I RRd I 16
I address I o I segment I offset I
01 1 01 011 0 I Rs*O I RRd
SL 11 segment I 00000000 19
offset

Example: ADD R2, AUGEND !augend A located at % 1254!

Before instruction execution:
Memory R2

1252~
1254 0 6 4 4
~
1256

After instruction execution:

Memory R2

1252~
1254 0 6 4 4
~
1256

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

59
AND
And
AND dst, src dst: R
ANDB src: R, 1M, IR, DA, X

Operation: dst ...- dst AND src

A logical AND operation is performed between the corresponding bits of the source
and destination operands, and the result is stored in the destination. A one bit is
stored wherever the corresponding bits in the two operands are both ones; otherwise
a zero bit is stored. The source contents are not affected.

Flags: c: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
P: AND - unaffected; ANDB - set if parity of the result is even; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: AND Rd, Rs
ANDB Rbd, Rs
110 10 0 0 1 1 [Vi] Rs I Rd I 4 GOO0111 w l Rs
I Rd
I 4

1M: AND Rd, #dala 1001000111100001 Rd I 7

001000111100001 Rd
7
I data I data

ANDB Rbd, #dala o0 i 0 0 0 1 1 0 I 0 0 0 0 I

10 0 i 0 0 0 1 1 0 i 0 000 i Rbd I Rbd
7 7
I data I data
I data I data

1R: AND Rd, @Rsl

ANDB Rbd. @Rs! ~ 7 ~RRS*OI Rd
I 7

DA: AND Rd, address I011000111wl 0000 I Rd I o 1 10 0 0 1 11 w I 0 0 0 0 I Rd I

ANDB Rbd, address 9 55 10
I address I oI segment I offset I
011000111wl00001 Rd

5L 1 I segment I0 0 0 0 0000 12
offset

X: AND Rd, addr(Rs)

l Rs""O I
ANDB Rbd, addr(Rs)
101/000111 w Rd
I 10 55
01/000111wl RHOI Rd
I 10
I address I oI segment I offset
I
o 110001 11 w I Rs "" 0 I Rd
5L 1 I segment I0 0 0 0 0000 13
offset

60
Example: ANDB RL3, # %CE

Before instruction execution:

RL3 Flags
11100111 cz S PIV D H
czspdh

After instruction execution:

RL3 Flags
1000110 cz S PIV D H
c01 1 dh

Note I: Word register in nonsegmented mode, register pair in segmented mode.

61
BIT
Bit Test
BIT dst, src dst: R, IR, DA, X
BITB src: 1M
or
dst: R
src: R

Operation: Z .- NOT dst (src)

The specified bit within the destination operand is tested, and the Z flag is set to one
if the specified bit is zero; otherwise the Z flag is cleared to zero. The contents of the
destination are not affected. The bit number (the source) can be specified statically
as an immediate value, or dynamically as a word register whose contents are the bit
number. In the dynamic case, the destination operand must be a register, and the
source operand must be RO through R7 for BITB, or RO through R15 for BIT. The bit
number is a value from a to 7 for BITB, or a to 15 for BIT, with a indicating the least
significant bit. Note that only the lower four bits of the source operand are used to
specify the bit number for BIT, while only the lower three bits of the source operand
are used for BITB.

Flags: c: Unaffected
Z: Set if specified bit is zero; cleared otherwise
S: Unaffected
V: Unaffected
D: Unaffected
H: Unaffected

Bit Test Static

Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

BIT Rd, lib

~
R: B100111wl~ 4 4
BITB Rbd, lib

IR: 100110011~ ~
BIT @ Rd 1 , lib 8 8
BITB @ Rd1,#b
I
DA: BIT address, lib
BITB address, lib
101i100111w!0000i b I 10 SS
01!100111wiooool b
11
I address I o I segment I offset

01!10011I w !00001 b

SL 11 segment 10000 0000 13

offset

X: BIT addr(Rd), lib

1011100111wl Rd*O I b I 01!10011IwIRd*01 b
BITB addr(Rd), #b 11 SS 11
I address I O! segment I offset

01110011l w l Rd*O I b

SL 11 segment 10000 0000 14

offset

62
Bit rest Dynamic
Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: BIT Rd, Rs 100110011/w100001 Rs I 10 1001100111Wl00QOI Rs I 10

BITB Rbd, RS 2 100001 Rd 10000100001 100001 Rd 10000100001

Example: If register RH2 contains %B2 (0110010), the instruction

BITB RH2, #0
will leave the Z flag set to 1.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: Word registers 0-7 only.

63
CALL
Call
CALL dst dst: IR, DA, X

Operation: Nonsegmented Segmented

SP __ SP - 2 SP __ SP - 4
@SP -- PC @SP -- PC
PC -- dst PC -- dst

The current contents of the program counter (PC) are pushed onto the top of the
processor stack. The stack pointer used is R15 in nonsegmented mode, or RR14 in
segmented mode. (The program counter value used is the address of the first instruc-
tion following the CALL instruction.) The specified destination address is then
loaded into the PC and points to the first instruction of the called procedure.
At the end of the procedure a RET instruction can be used to return to original pro-
gram. RET pops the top of the processor stack back into the PC.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: CALL Q1Rdi

~011111~ 10 El011111~ 15

DA: CALL address

101101111110000100001 01101111110000100001
12 18
1 address 1
SS
0] segment I offset I
0110111111000010000

SL 1 I segment I0 0 0 0 0000 20
offset

X: CALL addr(Rd)
101/0111111 Rd*olooool
13
I
SS 0 1 0.1 1 1 1 1 I Rd'l'O I 0 0 0 0 1 18
1 address I oI segment I offset I
o1 I 0 1 1 1 1 1
I Rd'l'O I0 0 0 0
SL 1 I segment I 0 0 0 0 0 0 0 0 21
offset

Example: In nonsegmented mode, if the contents of the program counter are %1000 and the
contents of the stack pointer (RI5) are %3002, the instruction
CALL %2520
causes the stack pointer to be decremented to %3000, the value %1004 (the address
following the CALL instruction with direct address mode specified) to be loaded into
the word at location %3000, and the program counter to be loaded with the value
%2520. The program counter now points to the address of the first instruction in the
procedure to be executed.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

64
 CALR
Call Relative
CALR dst dst: RA

Operation: Nonsegmented Segmented

SP SP - 2 SP SP - 4
@SP PC @SP PC
PC PC + (2 x displacement) PC PC + (2 x displacement)

The current contents of the program counter (PC) are pushed onto the top of the
processor stack. The stack pointer used is R15 in nonsegmented mode, or RR14 in
segmented mode. (The program counter value used is the address of the first in-
struction following the CALR instruction.) The destination address is calculated and
then loaded into the PC and points to the first instruction of a procedure.
At the end of the procedure a RET instruction can be used to return to the original
program flow. RET pops the top of the processor stack back into the PC.
The destination address is the sum of twice the displacement in the instruction and
the current value of the PC. The displacement is a l2-bit signed value in the range
-2048 to +2047. Thus, the destination address must be in the range -4094 to
+ 4096 bytes from the start of the CALR instruction. In segmented mode, the PC
segment number is not affected. The assembler automatically calculates the dis-
placement by subtracting the PC value of the following instruction from the address
given by the programmer and dividing the result by 2.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: CALR address

E2J displacement
I 10 EI displacement
I 15

Example: In nonsegmented mode, if the contents of the program counter are % 1000 and the
contents of the stack pointer (R15) are %3002, the instruction
CALR PROC
causes the stack pointer to be decremented to %3000, the value %1002 (the address
following the CALR instruction) to be loaded into the word location %3000, and the
program counter to be loaded with the address of the first instruction in procedure
PROC.

65
CLR
Clear
CLR dst dst: R, IR, DA, X
CLRB

Operation: dst -- 0

The destination is cleared to zero.

Flags: No flags affected.

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: CLR Rd
CLRB Rbd
110 loo11 o lwl Rd 11000 I 7
~ 7

IR: CLR @Rdl

CLRB @Rdl ~ 8 Elo 01 1 0 B RRd#{) 11 000 I 8

DA: CLR address

CLRB address
I1
101100110 w 0000 110 0 0 I 11 55
0110011 olwl 00001 1000 I 12
I address I oI segment I offset I
I I
01100110 w 0000 110 0 0
5L 11 segment 10000 0000 14
offset

X: CLR addr(Rd)
101100110Iwi Rd*O 110001 I
01 1001101 w Rd*O 110 0 0 I
CLRB addr(Rd) 12 55 12
1 address 1 01 segment I offset 1

011001101wl Rd*O 11000

5L 1 I segment I0 0 0 0 0000 15
offset

Example: If the word at location %ABBA contains 13/ the statement

CLR %ABBA
will leave the value 0 in the word at location %ABBA.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

66
 COM
Complement
COM dst dst: R, IR, DA, X
COMB

Operation: (dst -- NOT dst)

The contents of the destination are complemented (one's complement); all one bits
are changed to zero, and vice-versa.

Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
P: COM-unaffected; COMB-set if parity of the result is even; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~
COMRd
COMB Rbd
7
~ 7

IR: COM (i.'Rdl

COMB (i.'Rdi
§10011 OI~Rd;" 0\ 0000 I 12 El 0 0 1 1 0 ~I RRd1'O 0 000 I I 12

DA: COM address

101100110lwl0000100001 0110011 olwl 0000 1 0000 I
COMB address 15 55 16
, I address
I o I segment I offset I
0110011 olwl 0000 0000 I
5L 1 I segment I 0 0 0 0 0000 18
offset

X: COM addr(Rd)
I0 1 10 0 1 10 Iw I Rd '" 0 I0 0 0 0 I I I
o 1 0 0 1 1 0 Wi Rd", 0 0 0 0 0 I I
16 55 16
COMB addr(Rd)
I address I o I segment I offset I
0110011 olwl Rd",O 10000
5L 1 I segment I0000 0000 19
offset

Example: If register Rl contains %2552 (0010010101010010), the statement

COM Rl
will leave the value %DAAD (101101010101101) in Rl.

Note 1: Word regIster In nonsegmented mode, reglsier palr In segmenred moce.

67
COMFLG
Complement Flag
COMFLG flag Flag: C, Z, S, P, V
FLAGS (4:7) .,.- FLAGS (4:7) XOR instruction (4:7)

Operation: Any combination of the C, Z, S, P or V flags is complemented (each one bit is

changed to zero, and vice-versa). The flags to be complemented are encoded in a
field in the instruction. If the bit in the field is one, the corresponding flag is com-
plemented; if the bit is zero, the flag is left unchanged. Note that the P and V flags
are represented by the same bit. There may be one, two, three or four operands in
the assembly language statement, in any order.

Flags: C: Complemented if specified; unaffected otherwise

Z: Complemented if specified; unaffected otherwise
S: Complemented if speCified; unaffected otherwise
P/V: Complemented if speCified; unaffected otherwise
D: Unaffected
H: Undefined

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

COMFLG flags
110001101~ 7 110001101 ~ 7

Example: If the C, Z, and S flags are all clear ( = 0), and the P flag is set ( = 1), the statement
COMFLG P, S, Z, C
wiil leave the C, Z, and S flags set ( = l), and the P flag cleared ( = 0).

68
 CP
Compare
CP dst, src dst: R
CPB src: R, IM, IR, DA, X
CPL or
dst: IR, DA, X
src: IM

Operation: dst - src

The source operand is compared to (subtracted from) the destination operand, and
the appropriate flags set accordingly, which may then be used for arithmetic and
logical conditional jumps. Both operands are unaffected, with the only action being
the setting of the flags. Subtraction is performed by adding the two's complement of
the source operand to the destination operand. There are two variants of this instruc-
tion: Compare Register compares the contents of a register against an operand
specified by any of the five basic addressing modes; Compare Immediate performs a
comparison between an operand in memory and an immediate value.

Flags: C: Cleared if there is a carry from the most significant bit of the result; set other-
wise, indicating a "borrow"
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of opposite signs
and the sign of the result is the same as the sign of the source; cleared otherwise
D: Unaffected
H: Unaffected

Compare Register
Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: CP Rd, Rs
CPB Rbd, Rbs ~ 4
~ 4

CPL RRd, RRs

E10100001~ 8 B010000~ 8

1M: CP Rd, #data

001001011 10000 I 001001011 10000 I Rd
Rd
7 7
data data

CPB Rbd, #data 0010010101000 0 1 Rbd o0 I 0 0 1 0 1 0 I 0 0 0 0 I Rbd

7 7
data I data data I data

CPL RRd, #data

o0 I 0 1 0 0 0 0 I 0 0 0 0 I RRd 001010000 i 0000 I RRd

31 data (high) 16 14 31 data (high) 16 14

15 data (low) 0 15 data (low) 0

IR:
~ ~
CP Rd, @Rsl
7 7
CPB Rbd, @Rsl
CPL RRd, @Rsl
B010000~ 14 B010000~ 14

69
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: CP Rd, address

CPB Rbd, address 1011001011wl 0000 I Ad I 9 55
011001011wl00001 Ad I 10
I address I oI segment 1 offset I
011001011wl00001 Ad

5L 1 I segment I0000 0000 12

offset

CPL RRd, address

1011010000100001 RAd I 15 55
011 010000 I 0000 I RRd I 16
I address
I o1 segment 1 offset I
011010000100001 Rd

5L 1 I segment 10 0 0 0 0 0 0 0 18
offset

X: CP Rd, addr(Rs)
I0 1 I0 0 10 11 w 1 As;O 0 1
ePB Rbd, addr(Rbs)
Ad I 10 55
0110010 11w l AHO I AAd I 10
I address I oI segment I offset I
o 1 10 0 1 0 11 w I As;O 0 I Ad

5L 1 I segment I0 0 0 0 0000 13
offset

ePL RRd, addr(Rs)

I
10 1 0 1 0 0 0 0 1As ;0 0 I AAd I 16 55
011010000 I As;OO I RAd I 16
I address I 0' segment I offset I
011010000 I Rs;OO! RAd I
_____.. . ...II~ SL 1
!

...
I

m'"~,,~tOO 0 0000 II-=-

I

Compare Immediate
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language I------------...-----+-----------~---
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: ep @Rdl, #data

11 11

ePB @Rdl, #data

11 11

70
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: CP address, #data

011 001 10IWI 0000 10001 01100110lw 00001 0001
address 14 55 01 segment offset 15
data data

01100110lw 000010001

11 segment 0000 0000

5L 17
offset
data

CPB address, #data 01100110lwl000 0 10001 01100110lw 00001 0001

address 14 55 01 segment offset 15
data I data data data

01\00110\W 0000\0001

11 segment 0000 0000

5L 17
offset

data data

X: CP addr(Rd), #data
o 1 I0 0 1 1 0 IW IRd '" 0 10 0 0 1 01 1001101 W Rd '" 0 10001
address 15 55 01 segment offset 15
data data

o 1 10 0 1 1 0 IW I
Rd", 0 0 0 0 1

11 segment 0000 0000

5L 18
offset

data

CPB addr(Rd), #data

o 1 I0 0 1 10 IW I Rd '" 0 I 0 0 0 1 01100110lw Rd",O 10001
address 15 55 01 segment offset 15
data I data data data

01100110lw Rd",O 10001

5L
11 segment 0000 0000
18
offset

data data

Example: If register R5 contains %0400, the byte at location %0400 contains 2, and the source
operand is the immediate value 3, the statement
CPB @R5,#3
will leave the C flag set, indicating a borrow the S flag set, and the Z and V flags
I

cleared.

Note 1: Word regisrer in nonsegmented mode, register pair In segmented mode.

71
CPD
Compare and Decrement
CPO dst, src, r, cc dst: R
CPOB src: IR

Operation: dst - src

AUTODECREMENT src (by 1 if byte, by 2 if word)
r -- r - 1
This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register are
compared to (subtracted from) the destination operand, and the Z flag is set if the
condition code specified by "cc" would be set by the comparison; otherwise the Z
flag is cleared. See Section 6.6 for a list of condition codes. Both operands are un-
affected.
The source register is then decremented by one if CPDB, or by two if CPD, thus
moving the pointer to the previous element in the string. The word register specified
by "r" (used as a counter) is then decremented by one. The source, destination,
and count registers must be separate and non-overlapping registers.

Flags: C: Undefined
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Undefined
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: CPD Rd, @RsJ, r, cc

11 01 1 1 01 IwIRS"" 0 110 0 0 1 11 0 1 1 1 01 IwI RRs*O 110 00 1
CPDB Rbd, @Rsl, r, cc 20 20
1
0000
1
r
I Rd I cc 1 10000 1
r I Rd I cc I

Example: If register RHO contains %FF, register R1 contains %4001, the byte at location
%4001 contains %00, and register R3 contains 5, the instruction
CPDB RHO, @R1, R3, EQ
will leave the Z flag cleared since the condition code would not have been "equal."
Register R1 will contain the value %4000 and R3 will contain 4. For segmented
mode, Rl must be replaced by a register pair.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

72
 CPDR
Compare, Decrement and Repeat
CPDR dst, src, r, cc dst: R
CPDRB src: IR

Operation: dst - src

AUTODECREMENT src (by 1 if byte; by 2 if word)
r.-r-l
repeat until cc is true or R = 0

This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register are
compared to (subtracted from) the destination operand, and the Z flag is set if the
cohdition code specified by "cc" would be set by the comparison; otherwise the Z
flag is cleared. See Section 6.6 for a list of condition codes. Both operands are unaf-
fected.
The source register is then decremented by one if CPDRB, or by two if CPDR, thus
moving the pointer to the previous element in the string. The word register specified
by "r" (used as a counter) is decremented by one. The entire operation is repeated
until either the condition is met or the result of decrementing r is zero. This instruc-
tion can search a string from 1 to 65536 bytes or 32768 words long (the value of r
must not be greater than 32768 for CPDR). The source, destination, and count
registers must be separate and non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted.

Flags: C: Undefined
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Undefined
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cydes2 Instruction Format Cydes2

IR: CPDR Rd, @Rsl, r, CC

1 1 011101 Iw IRs * 011100 I 11 01 1 1 01 IW IRRs *0 111 00 1
CPDRB Rbd, @Rsl, r, cc 11 +9n 11 +9n
100001 r I Rd I cc 1 100001 r I Rd I cc 1

Example: If the string of words starting at location %2000 contains the values 0, 2, 4, 6 and 8,
register R2 contains %2008, R3 contains 5, and R8 contains 8, the instruction
CPDR R3, @R2, R8, 8T
will leave the Z flag set indicating the condition was met. Register R2 will contain the
value %2002, R3 will still contain 5, and R8 will contain 2. For segmented mode, a
register pair would be used instead of R2.

Note I: Word register in nonsegmented mode, register pair m segmented mode.

Note 2: n = number of data elements compared.

73
CPI
Compare and Increment
CPI dst, src, r, cc dst: IR
CPIB src: IR

Operation: dst - src

AUTOINCREMENT src (by I if byte; by 2 if word)
r'" r - 1

This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register are
compared to (subtracted from) the destination operand and the Z flag is set if the
condition code specified by "cc" would be set by the comparison; otherwise the Z
flag is cleared. See Section 6.6 for a list of condition codes. Both operands are
unaffected.
The source register is then incremented by one if CPlB, or by two if CPl, thus
moving the pointer to the next element in the string. The word register specified by
"r" (used as a counter) is then decremented by one. The source, destination, and
counter registers must be separate and non-overlapping registers.

Flags: c: Undefined
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Undefined
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: CPI Rd, @Rsl, r, cc

CPIB Rbd, @Rsl, r, cc 11 0111 01 Iw IRI * 0 I00001 20
11 0 111 0 1 Iw iRRs*O I0000 1 20
1 0000 1
r
I Rd I cc 1 10000 1 r
I Rd I cc 1

74
Example: This instruction can be used in a "loop" of instructions that searches a string of data
for an element meeting the specified condition, but an intermediate operation on
each data element is required. The folloWing sequence of instructions (to be
executed in non-segmented mode) "scans while numeric," that is, a string is
searched until either an ASCII character not in the range "0" to "9" (see Appendix
C) is found, or the end of the string is reached. This involves a range check on each
character (byte) in the string. For segmented mode, RI must be changed to a
register pair.
LD R3, #STRLEN !initialize counter!
LDA RI, STRSTART !load start address!
LDB RLO,#,9' !largest numeric char!
LOOP:
CPB @RI,#'O' !test char < 'a'!
JR ULT,NONNUMERIC
CPIB RLO, @RI, R3, ULE !test char ~ 9!
JR NZ, NONNUMERIC
JR NOV, LOOP !repeat until counter a!
DONE:

NONNUMERIC: !handle non-numeric char!

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

75
CPIR
Compare, Increment and Repeat
CPIR dst, src, r, cc dst: R
CPIRB src: IR

Operation: dst - src

AUTOINCREMENT src (by 1 if byte; by 2 if word)
r +-r - 1
repeat until cc is true or R = 0

This instruction is used to search a string of data for an element meeting the
specified condition. The contents of the location addressed by the source register are
compared to (subtracted from) the destination operand, and the Z flag is set if the
condition code specified by "cc" would be set by the comparison; otherwise the Z
flag is cleared. See Section 6.6 for a list of condition codes. Both operands are
unaffected.
The source register is then incremented by one if CPIRB, or by two if CPIR, thus
moving the pointer to the next element in the string. The word register specified by
"r" (used as a counter) is then decremented by one. The entire operation is repeated
until either the condition is met or the result of decrementing r is zero. This instruc-
tion can search a string from 1 to 65536 bytes or 32768 words long (the value of r
must not be greater than 32768 for CPIR). The source, destination, and counter
registers must be separate and non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted.

Flags: C: Undefined
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Undefined
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: CPIR Rd, @Rsl, r, CC

11 01 1 1 01 IwI Rs * o! 01 00 1 11011101 I wI RRs 10 10 0 1
CPIRB Rbd,@Rsl, r, cc 11 +9n 11 +9n
1 0000 1 r I Rd I cc I 100001 r I Rd I cc 1

76
Example: The following sequence of instructions (to be executed in nonsegmented mode) can
be used to search a string for an ASCII return character. The pointer to the start of
the string is set, the string length is set, the character (byte) to be searched for is
set, and then the search is accomplished. Testing the Z flag determines whether the
character was found. For segmented mode, Rl must be changed to a register pair.
LDA R 1, STRSTART
LD R3, #STRLEN
LDB RLO, #% D !hex code for return is D!
CPIRB RLO, @Rl,R3, EQ
JR Z, FOUND

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements compared.

77
CPSD
Compare String and Decrement
CPSD dst, src, r, cc dst: IR
CPSDB src: IR

Operation: dst - src

AUTODECREMENT dst and src (by 1 if byte; by 2 if word)
r..-r-l

This instruction can be used to compare two strings of data until the speCified condi-
tion is true. The contents of the location addressed by the source register are com-
pared to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set if the condition code speCified by "cc" would be set by the
comparison; otherwise the Z flag is cleared. See Section 6.6 for a list of condition
codes. Both operands are unaffected.
The source and destination registers are then decremented by one if CPSDB, or by
two if CPSD, thus moving the pointers to the previous elements in the strings. The
word register speCified by "r" (used as a counter) is then decremented by one.
The source, destination, and count registers must be separate and non-overlapping
registers.
Flags: c: Cleared if there is a carry from the most significant bit of the result of the com-
parison; set otherwise, indicating a "borrow". Thus this flag will be set if the
destination is less than the source when viewed as unsigned integers.
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Set is the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

cPSD (Ii Rd i , ~, Rsi, r, cc

IR:
CPSDB (II Rdl ,(II Rsi ,r,cc
I
11 011 1 01 w 1Rs * 01 10 10 1 25
110111 011wlRRHol1 01 0 1
25
10000 1
r IRd * 01 cc 1 100001 r IRRd'FOI cc 1

Example: If register R2 contains %2000, the byte at location %2000 contains %FF, register R3
contains %3000, the byte at location %3000 contains %00, and register R4 contains
I, the instruction (executed in nonsegmented mode)
CPSDB @R2, @R3, R4, UGE
will leave the Z flag set to 1 since the condition code would have been "unsigned
greater than or equal", and the V flag will be set to 1 to indicate that the counter R4
now contains O. R2 will contain %IFFF, and R3 will contain %2FFF. For segmented
mode, R2 and R3 must be changed to register pairs.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

78
 CPSDR
Compare String. Decrement and Repeat
CPSDR cist, src,r, cc dst: IR
CPSDRB src: IR

Operation: dst - src

AUTODECREMENT dst and src (by I if byte; by 2 if word)
r +- r - I
repeat until cc is true or r = 0

This instruction is used to compare two strings of data until the specified condition is
true. The contents of the location addressed by the source register are compared to
(subtracted from) the contents of the location addressed by the destination register.
The Z flag is set if the condition code specified. by "cc" would be set by the compar-
ison; otherwise the Z flag is cleared. See Section 6.6 for a list of condition codes.
Both operands are unaffected.
The source and destination registers are then decremented by one if CPSDRB, or by
two if CPSDR, thus moving the pointers to the previous elements in the strings. The
word register specified by "r" (used as a counter) is then decremented by one. The
entire operation is repeated until either the condition is met or the result of decre-
menting r is zero. This instruction can compare strings from I to 65536 bytes or from
I to 32768 words long (the value of r must not be greater than 32768 for CPSDR).
The source, destination, and count registers must be separate and non-overlapping
registers.
This instruction can be interrupted after each execution of the basic operation. The
program counter of the start of this instruction is saved before the interrupt request
is accepted, so that the instruction can be properly resumed. Seven more cycles
should be added to this instruction's execution time for each interrupt request that is
accepted.

Flags: c: Cleared if there is a carry from the most significant bit of the result of the com-
parison; set otherwise, indicating a "borrow". Thus this flag will be set if the
destination is less than the source when viewed as unsigned integers
Z: Set if the conditon code generated by the comparison matches cc; cleared
otherwise
S: Setif the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: CPSDR@Rd1,@Rsl,r,cc
11 0 1 1 1 0 1 IwI Rs~ 11 1 1 0 ) 11 0 1 1 1 0 1 IwIRRs~ 11 1 1 0 I
CPSDRB@Rd1,@Hsl,r,cc 11 + 14n 11 + 14n
1 0000 I r I Rd~ 1 cc I 100001 r IRRd~1 eel

79
Example: If the words from location %1000 to %1006 contain the values 0, 2, 4, and 6, the
words from location %2000 to %2006 contain the values 0, I, 1,0, register R13 con-
tains %1006, register R14 contains %2006, and register RO contains 4, the instruc-
tion (executed in nonsegmented mode)
CPSDR @R13, @R14, RO, EQ
leaves the Z flag set to 1 since the condition code would have been "equal" (loca-
tions %1000 and %2000 both contain the value 0). The V flag will be set to 1 indi-
cating RO was decremented to O. R13 will contain %OFFE, R14 will contain %IFFE,
and RO will contain O. For segmented mode, R13 and R14 must be changed to
register pairs.

Note 1: Word register in nonsegmented mode, register pair in segmen;ed mode.

Note 2: n ~ number of data elements compared.

80
 CPSI
Compare String and Increment
CPSI dst, src, r, cc dst: IR
CPSIB src: IR

Operation: dst - src

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word)
r .... r - 1

This instruction can be used to compare two strings of data until the specified condi-
tion is true. The contents of the location addressed by the source register are com-
pared to (subtracted from) the contents of the location addressed by the destination
register. The Z flag is set if the condition code speCified by "cc" would be set by the
comparison; otherwise the Z flag is cleared. See Section 6.6 for a list of condition codes.
Both operands are unaffected.
The source and destination registers are then incremented by one if CPSIB, or by
two if CPSI, thus moving the pointers to the next elements in the strings. The word
register speCified by "r" (used as a counter) is then decremented by one.
The source, destination, and count registers must be separate and non-overlapping registers.

Flags: C: Cleared if there is a carry from the most significant bit of the result of the comparison;
set otherwise, indicating a "borrow". Thus this flag will be set if the destination is less
than the source when viewed as unsigned integers
Z: Set if the condition code generated by the comparison matches cc; cleared otherwise
S: Set is the result of the comparison is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: CPSI @Rd1,@Rsl,r,cc

cPSIB @Rdl,@Rsl,r,cc
11 0 1 1 1 0 1 Iw IRs * 0 I0 0 10 I
25
11 0111 01 IwIRRs * 0 I0010 I 25
1
0000
1
r IRd * 01 cc 1 1
0000
1
r IRRd *01 cc I

81
Example: This instruction can be used in a "loop" of instructions which compares two strings
until the specified condition is true, but where an intermediate operation on each
data element is required. The following sequence of instructions, to be executed in
nonsegmented mode, attempts to match a given source string to the destination
string which is known to contain all upper-case characters. The match should suc-
ceed even if the source string contains some lower-case characters. This involves a
forced conversion of the source string to upper-case (only ASCII alphabetic letters
are assumed, see Appendix C) by resetting bit 5 of each character (byte) to 0 before
comparison.

LDA Rl, SRCSTART !load start addresses!

LDA R2, DSTSTART
LD R3, #STRLEN !initialize counter!
LOOP:
RESB @Rl,#5 !force upper-case!
CPSIB @RI,@R2, R3, NE [compare until not equal!
JR Z, NOTEQUAL !exit loop if match fails!
JR NOV, LOOP !repeat until counter = O!
DONE: !match succeeds!

NOTEQUAL: !match fails!

In segmented mode, RI and R2 must both be register pairs.

Note I: Word register in nonsegmented mode. register pair in segmented mode.

82
 CPSIR
Compare String. Increment and Repeat
CPSIR dst, src, r, cc dst: IR
CPSIRB src: IR

Operation: dst - src

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word)
r+-r-l
repeat until cc is true or r = 0

This instruction is used to compare two strings of data until the specified condition is
true. The contents of the location addressed by the source register are compared to
(subtracted from) the contents of the location addressed by the destination register.
The Z flag is set if the condition code specified by "cc" would be set by the com-
parison; otherwise the Z flag is cleared. See Section 6.6 for a list of condition
codes. Both operands are unaffected. The source and destination registers are then
incremented by one if CPSIRB, or by two if CPSIR, thus moving the pointers to the
next elements in the strings. The word register specified by "r" (used as a counter) is
then decremented by one. The entire operation is repeated until either the condition
is met or the result of decrementing r is zero. This instruction can compare strings
from 1 to 65536 bytes or from 1 to 32768 words long (the value of r must not be
greater than 32768 for CPSIR). The source, destination, and counter registers must
be separate and non-overlapping registers.
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven cycles
should be added to this instruction's execution time for each interrupt request that is
accepted.

Flags: C: Cleared if there is a carry from the most significant bit of the result of the last
comparison made; set otherwise, indicating a "borrow". Thus this flag will be set
if the last destination element is less than the last source element when viewed as
unsigned integers.
Z: Set if the condition code generated by the comparison matches cc; cleared
otherwise
S: Set if the result of the last comparison made is negative; cleared otherwise
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: CPSIR @Rd1,i(.Rsl,r,ee

11011101 I wi Rs ,. 0 1 0110 I 11 01 1 1 01 Iwi RRs * 01 01 1 0 I
CPSIRB @Rdl ,@Rsl ,r,ce 11 + 14n 11 + 14n
1 0000 1
r IRd,. 0 I cc I 10000 1
r IRRd*Oi cc I

83
Example: The CPSIR instruction can be used to compare text strings for lexicographic order.
(For most common character encodings-for example, ASCII and EBCDIC-lexico-
graphic order is the same as alphabetic order for alphabetic text strings that do not
contain blanks.)
Let Sl and S2 be text strings of lengths Ll and L2. According to lexicographic
ordering, Sl is said to be "less than" or "before" S2 if either of the following is true:
• At the first character position at which Sl and
S2 contain different characters, the character
code for the S 1 character is less than the
character code for the S2 character.
• Sl is shorter than S2 and is equal, character for
character, to an initial substring of S2.
For example, using the ASCII character code, the following strings are in ascending
lexicographic order:
A
AA
ABC
ABCD
ABD
Let us assume that the address of Sl is in RR2, the address of S2 is in RR4, the
lengths Ll and L2 of Sl and S2 are in RO and Rl, and the shorter of Ll and L2 is in
R6. The the following sequence of instructions will determine whether Sl is less than
S2 in lexicographic order:
CPSIRB @RR2, @RR4, R6, NE !Scan to first unequal character!
!The following flags settings are possible:
Z = a, v = 1: Strings are equal through Ll
character (Z = 0, V = a cannot occur).
Z = I, V = a or 1: A character position was
found at which the strings are unequal.
C = 1 (S = a or 1): The character in the RR2
string was less (viewed as numbers from a to
255, not as numbers from -128 to + 127).
C = a (S = a or 1): The character in the RR2
string was not less!
JR Z, CHALCOMPARE !If Z = 1, compare the characters!
CP RO,Rl !Otherwise, compare string lengths!
JR LT, S l_IS_LESS
JR Sl-.NOT_LESS
CHALCOMPARE:
JR ULT, S l_IS_LESS !ULT is another name for C = I!
Sl_NOT LESS:

84
 DAB
Decimal Adjust
DAB dst dst: R

Operation: dst __ DA dst

The destination byte is adjusted to form two 4-bit BCD digits following a binary
addition or subtraction operation on two BCD encoded bytes. For addition (ADDB,
ADCB) or subtraction (SUBB, SBCB), the following table indicates the operation
performed:

Carry Bits 4-7 H Flag Bits 0-3 Number Carry

Before Value Before Value Added After
Instruction DAB (Hex) DAB (Hex) To Byte DAB

0 0-9 0 0-9 00 0
0 0-8 0 A-F 06 0
ADDB 0 0-9 1 0-3 06 0
ADCB 0 A-F 0 0-9 60 1
0 9-F 0 A-F 66 1
0 A-F 1 0-3 66 1
1 0-2 0 0-9 60 1
1 0-2 0 A-F 66 1

SUBB 0 0-9 0 0-9 00 0

SBCB 0 0-8 1 6-F FA 0
1 7-F 0 0-9 AO 1
1 6-F 1 6-F 9A 1

The operation is undefined if the destination byte was not the result of a binary
addition or subtraction of BCD digits.

Flags: c: Set or cleared according to the table above

Z: Set if the result is zero; cleared otherwise
5: Set if the most significant bit of the result is set; cleared otherwise
V: Unaffected
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: DAB Rbd
B1100ool~ 5 B1100001~ 5

85
Example: If addition is performed using the BCD values 15 and 27, the result should be 42.
The sum is incorrect, however, when the binary representations are added in the
destination location using standard binary arithmetic.
0001 0101
+ 0010 0111
0011 1100 = %3C
The DAB instruction adjusts this result so that the correct BCD representation is
obtained.
0011 1100
+ 0000 0110
0100 0010 42

86
 DEC
Decrement
DEC dst, src dst: R, IR, DA, X
DECB src: 1M

Operation: dst .- dst - src (where src = 1 to 16)

The source operand (a value from 1 to 16) is subtracted from the destination operand
and the result is stored in the destination. Subtraction is performed by adding the
two's complement of the source operand to the destination operand. The source
operand may be omitted from the assembly language statement and defaults to the
value 1.
The value of the source field in the instruction is one less than the actual value of the
source operand. Thus, the coding in the instruction for the source ranges from 0 to
15, which corresponds to the source values 1 to 16.

Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs,
and the sign of the result is the same as the sign of the source; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
DEC Rd, #n
4 4
DECB Rbd, #n

IR: DEC Ql RdJ, #n

DECB Ql Rd J , #n ~ 11 El1 0 1 0 1 B RRd*O I n - 1 I 11

DA: DEC address, #n

1011101011wl00001 n-11 01110101!w100001 n-1
13 14
DECB address, #n
I address I I
55 0 segment I
ollset

011101011wl 00001 n-1

5L 11 segment 10000 0000 16
ollset

X: DEC addr(Rd), #n
1011101011 w I Rd.-O I n - 1 I 011101011wl Rd.-ol n-1
DECB addr(Rd), #n 14 55 14
I address I o I segment I ollset

01!10101!wl Rd.-Oj n-1

5L 11 segment 10000 0000 17
ollset

Example: If register RlO contains %002A, the statement

DEC RlO
will leave the value %0029 in RlO.
Note 1: Word register in nonsegmented mode, register pair in segmented mode.

87
DJ Privileged Instruction
Disable Interrupt
OJ Int Int: VI, NVI

Operation: If instruction (0) o then NVI .- 0

If instruction (1) o then VI .- 0

Any combination of the Vectored Interrupt (VI) or Non-Vectored Interrupt (NVI)

control bits in the Flags and Control Word (FCW) are cleared to zero if the cor-
responding bit in the instruction is zero, thus disabling the appropriate type of inter-
rupt. If the corresponding bit in the instruction is one, the control bit will not be
affected. All other bits in the FCW are not affected. There may be one or two
operands in the assembly language statement, in either order.

Flags: No flags affected.

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

Dr in!
1011111001~ 7 101111100 Jooooool]l] 7

Example: If the NVI and VI control bits are set (1) in the FCW, the instruction:
DI VI
will leave the NVI control bit in the FCW set (1) and will leave the VI control bit in
the FCW cleared (0).

88
 DIV
Divide
DIV dst, src dst: R
DIVL src: R, 1M, IR, DA, X

Operation: Word: (dst is register pair, src is word):

dst (0:31) is divided by src (0: 15)
(dst (0:31) = quotient x src (0: 15) + remainder)
dst (0: 15) -- quotient
dst (16: 31) -- remainder
Long: (dst register quadruple, src is long word or register pair):
dst (0:63) is divided by src (0:31)
(dst (0:63) = quotient x src (0:31) + remainder)
dst (0: 31 ) -- quotient
dst (32: 63) -- remainder

The destination operand (dividend) is divided by the source operand (divisor), the
quotient is stored in the low-order half of the destination and the remainder is stored
in the high-order half of the destination. The contents of the source are not affected.
Both operands are treated as signed, two's complement integers and division is per-
formed so that the remainder is of the same sign as the dividend. For DIV, the
destination is a register pair and the source is a word value; for DIVL, the destina-
tion is a register quadruple and the source is a long word value.
There a four possible outcomes of the Divide instruction, depending on the division,
and the resulting quotient:
CASE 1. If the quotient is within the range -2 15 to 215 - 1 inclusive for DIV or
-231 to 231 - 1 inclusive for DIVL, then the quotient and remainder are left in the
destination register as defined above, the overflow and carry flags are cleared to
zero, and the sign and zero flags are set according to the value of the quotient.
CASE 2. If the divisor is zero, the destination register remains unchanged, the
overflow and zero flags are set to one and the carry and sign flags are cleared to
zero.
CASE 3. If the quotient is outside the range -2 16 to 2 16 - 1 inclusive for DIV or -232
to 232 -1 inclusive for DIVL, the destination register contains an undefined value,
the overflow flag is set to one, the carry and zero flags are cleared to zero, and the
sign flag is undefined.
CASE 4. If the quotient is inside the range of case 3 but outside the range of case
I, then all but the sign bit of the quotient and all of the remainder are left in the
destination register, the overflow and carry flags are set to one, and the sign and
zero flags are set according to the value of the quotient. In this case, the sign flag
can be replicated by subsequent instruction into the high-order half of the destina-
tion to produce the two's complement representation of the quotient in the same
precision as the original dividend.

Flags: c: Set if V is set and the quotient lies in the range from _2 16 to 2 16 -1 inclusive for
DIV or in the range from _232 to 232 -1 inclusive for DIVL; cleared otherwise
Z: Set if the quotient or divisor is zero; cleared otherwise
S: Undefined if V is set and C is clear (overflow); otherwise set if the quotient is
negative, cleared if the quotient is non-negative.
V: Set if the divisor is zero or if the computed quotient lies outside the range from
_2 15 to 2 15 - 1 inclusive for DIV or outside range from _231 to 231 - 1 inclusive
for DIVL; cleared otherwise
D: Unaffected
H: Unaffeded

89
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

ft: DIV RRd, Rs

B0110111~ 107 B0110111~ 107

DIVL ROd, RRs

B0110101~ 744 B0110101~ 744

1M: DIV RRd, #data

001011011100001 RRd RRd
001011011100001
107 107
data data

DIVL ROd, #data

001011010100001 RQd 001011010100001 RQd

31 data (high) 16 744 31 data (high) 16 744

15 data (low) 0 15 data (low) 0

1ft: DIV RRd, @Rsl

~011011~ ~011011~
107 107
DIVL ROd, @Rsl
§]011010[~ 8 011010 IRRs.=O I RQd I
DA: DIV RRd, address
I
o 1 0 1 1 0 1 1 10000 1 RRd
011011011100001 RRd
108 55 109
address o I segment 1 offset

o 11 0 1 1 0 1 1 I0 0 0 0 I RRd
111
5L 1 1 segment 10 0 0 0 0 0 0 0
offset

DIVL ROD, address RQd

0110110 10 100001 RQd 011011010100001
445 55 746
address o 1 segment I offset

011011010100001 RQd

5L 11 segment 10000 0000 748

offset

X: DIV RRd, addr(Rs)

1011 011011 I RHO I RRd 1 0110110111 Rs.=ol RRd
55
r address I
109
o 1 segment 1 offset
109

011 011011 1 Rs.=O 1 RRd

112
5L 11 segment 10000 0000
offset

DIVL RQd, addr(Rs)

1011 011010 I Rs.=O I RQd 1 011 011010 I Rs.=O I RQd I
746 55 746
I address I o 1 segment' 1 offset

011 011010 I Rs.=O I RQd

749
5L 11 segment 10000 0000
offset

90
Example: If register RRO (composed of word register RO and Rl) contains %00000022 and
register R3 contains 6, the statement
DIV RRO,R3
will leave the value %00040005 in RRO (Rl contains the quotient 5 and RO contains
the remainder 4).

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: The execution time for the instruction will be lower by 94 cycles for word, 714 for long word than in-
dicated for divide by zero and by 82 for word, 693 for long word for overflow conditions.

91
DJNZ
Decrement and Jump if Not Zero
DJNZ R, dst
DBJNZ dst: RA

Operation: R +- R - 1
If R *"
0 then PC +- PC - (2 X displacement)

The register being used as a counter is decremented. If the contents of the register
are not zero after decrementing, the destination address is calculated and then
loaded into the program counter (PC). Control will then pass to the instruction
whose address is pointed to by the PC. When the register counter reaches zero, con-
trol falls through to the instruction following DJNZ or DBJNZ. This instruction pro-
vides a simple method of loop control.
The relative addressing mode is calculated by doubling the displacement in the
instruction, then subtracting this value from the updated value of the PC to derive
the destination address. The updated PC value is taken to be the address of the
instruction following the DJNZ or DBJNZ instruction, while the displacement is a
7-bit positive value in the range 0 to 127. Thus, the destination address must be in
the range -252 to 2 bytes from the start of the DJNZ or DBJNZ instruction. In the
segmented mode, the PC segment number is not affected. The assembler automatic-
ally calculates the displacement by subtracting the PC value of the following instruc-
tion from the address given by the programmer and dividing the result by 2. Note
that DJNZ or DBJNZ cannot be used to transfer control in the forward direction, nor
to another segment in segmented mode operation.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: DJNZ R, address

DBJNZ Rb, address
11111 ! r Iwl disp 1 11 11111 1 r Iwl disp
1 11

Example: DJNZ and DBJNZ are typically used to control a "loop" of instructions. In this exam-
ple for nonsegmented mode, 100 bytes are moved from one buffer area to another,
and the sign bit of each byte is cleared to zero. Register RHO is used as the counter.
LDB RHO,#100 !initalize counter!
LDA Rl, SRCBUF !load start address!
LDA R2, DSTBUF
LOOP:
LDB RLO,@Rl !load source byte!
RESB RLO,#7 !mask off sign bit!
LDB @R2, RLO !store into destination!
INC Rl !advance pointers!
INC R2
DBJNZ RHO, LOOP !repeat until counter O!
NEXT:
For segmented mode, Rl and R2 must be changed to register pairs.

92
 Privileged Instruction EI
Enable Interrupts
EI int Int: VI, NVI

Operation: If instruction (0) o then NVI +- 1

If instruction (1) o then VI +- 1

Any combination of the Vectored Interrupt (VI) or Non-Vetored Interrupt (NVI) con-
trol bits in the Flags and Control Word (FCW) are set to one if the corresponding bit
in the instruction is zero, thus enabling the appropriate type of interrupt. If the cor-
responding bit in the instruction is one, the control bit will not be affected. All other
bits in the FCW are not affected. There may be one or two operands in the assembly
language statement in either order.

Flags: No flags affected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

EI int
I 01111100 IOOOOO1[ylj] 7 I 01111100 looooo1l YIY] 7

Example: If the NVI contol bit is set (l) in the FCW, and the VI control bit is clear (0), the
instruction
EI VI
will leave both the NVI and VI control bits in the FCW set (1)

93
EX
Exchange
EX dst, src dst: R
EXB src: R, IR, DA, X

Operation: tmp.- src (tmp is a temporary internal register)

src.- dst
dst.- tmp

The contents of the source operand are exchanged with the contents of the destina-
tion operand.

Flags: No flags affected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: EX Rd, Rs
EXB Rbd, Rbs ~ 6 G!110110Iwl~ 6

IR:
~ ~
EX Rd, @Rsl
12 12
EXB Rbd, @Rsl

DA: EX Rd, address

EXB Rbd, address
101110110Iwi 0000 I Rd I 15 SS
011101101w100001 Rd
16
I address I o I segment I offset

01110110lwl00001 Rd
Sl 11 segment 10000 0000 18
offset

X: EX Rd, addr(Rs)
10 1 110 1 1 0 Iw I Rs * 0 1 Rd I 01 11 011 olwl Rs*O I Rd
EXB Rbd, addr(Rs) 16 SS 16
I address I o I segment I offset

I I
o 1 11 0 1 1 0 w RH 0 I Rd
Sl 11 segment 10000 0000 19
offset

Example: If register RO contains 8 and register R5 contains 9, the statement

EX RO,R5
will leave the values 9 in RO and 8 in R5. The flags will be left unchanged.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

94
 EXTS
Extend Sign
EXTSB dst dst: R
EXTS
EXTSL

Operation: Byte
if dst (7) a then dst (8: 15) -- 000... 000
else dst (8: 15) -- Ill.. .111
Word
if dst (15) a then dst (16:31) -- 000... 000
else dst (16:31) -- Ill.. .111
Long
if dst (31) a then dst (32:63) -- 000... 000
else dst (32:63) -- Ill.. .111

The sign bit of the low-order half of the destination operand is copied into all bit
positions of the high-order half of the destination. For EXTSB, the destination is a
word; for EXTS, the destination is a register pair; for EXTSL, the destination is a
register quadruple.
This instruction is useful in multiple precision arithmetic or for conversion of small
signed operands to larger signed operands (as, for example, before a divide).

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: EXISB Rd
~1110001 ~ 11 B110001~ 11

EXIS RRD
~11100011~ 11 ~j110001~ 11

EXISL RQd
~1110001~ 11 B110001~ 11

Example: If register pair RR2 (composed of word registers R2 and R3) contains % 12345678,
the statement
EXTS RR2
will leave the value %00005678 in RR2 (because the sign bit of R3 was 0).

95
HALT Privileged Instruction
Halt
HALT

Operation: The CPU operation is suspended until an interrupt or reset request is received. This
instruction is used to synchronize the 28000 with external events, preserving its state
until an interrupt or reset request is honored. After an interrupt is serviced, the
instruction following HALT is executed. While halted, memory refresh cycles will
still occur, and BUSREQ will be honored.

Flags: No flags affected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles l Instruction Format Cycles l

HALT
101111010 100000000 I 8+3n 101111010 I 00000000 I 8+3n

Note 1: Interrupts are recognized at the end of each 3-cyc1e period; thus n = number of periods without
interruption.

96
 Privileged Instruction IN
(SIN)
(Special) Input
IN dst, src dst: R
INB src: IR, DA
SIN dst, src dst: R
SINB src: DA

Operation dst -- src

The contents of the source operand, an Input or Special Input port, are loaded into
the destination register. IN and INB are used for Standard I/O operation; SIN and
SINB are used for Special I/O operation.

Flags: No flags affected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 1 Cycles Instruction Format 1 Cycles

IR: IN Rd, @Rs

~11 1 1 1 0 [w I Rs,o() I Rd
, 10
~ 10
INB Rbd, @Rs

DA: IN Rd, port

INB Rbd, port
I0 0 11 1 1 0 1 Iw I Rd 10105 I 12
100[11101[wl Rd 101051
12
SIN Rd, port
I port
I I port
I
SINB Rbd, port

Example: If register R6 contains the I/O port address %0123 and the port %0123 contains
%FF, the statement
INB RH2, @R6
will leave the value %FF in register RH2.

Note 1. For SIN, S = 1; otherwise S = o.

97
INC
Increment
INC dst, src dst: R, IR, DA, X
INCB src: 1M

Operation: dst -- dst + src (src = 1 to 16)

The source operand (a value from 1 to 16) is added to the destination operand and
the sum is stored in the destination. Two's complement addition is performed. The
source operand may be omitted from the assembly language statement and defaults
to the value 1.
The value of the source field in the instruction is one less than the actual value of the
source operand. Thus, the coding in the instruction for the source ranges from
a to 15, which corresponds to the source values 1 to 16.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands were of the same sign
and the result is of the opposite sign; cleared otherwise
0: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: INC Rd, #n
INCB Rbd, #n ~ 4
~ 4

IR: I ~] 10 10 0 [!] RRd~ In - 1 I

INC @Rd J , #n 11
INCB @Rd J , #n EI101 00!:!1 Rd*O In - 1 11

DA: INC address, #n

~
INCB address, #n 13 55 01110 100lwl 0000 In - 1 14
o I segment 1 offset

01110100lwl00001 n-1
5L 11 segment 10000 0000 16
offset

X: INC addr(Rd), #n
INCB addr(Rd). #n 1011101 oolwl Rd*O In - 1 I 14 55
01110 100lwl Rd*O n - 1 I I 14
1 adlfress I o I segment I offset I
01110100lwi Rd*O n-1 I
5L 11 segment 10000 0000 17
offset

Example: If register RH2 contains %21, the statement

1NCB RH2,#6
will leave the value %27 in RH2.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

98
 Privileged Instruction IND
(SIND)
(Special) Input and Decrement
IND dst, src, r dst: IR
INDB src: IR
SIND
SINDB

Operation: dst +- src

AUTODECREMENT dst (by 1 byte, by 2 if word)
r+-r-1

This instruction is used for block input of strings of data. IND and INDB are used for
Standard I/O operation; SIND and SINDB are used for Special I/O operation. The
contents of the I/O port addressed by the source word register are loaded into the
memory location addressed by the destination register. I/O port addresses are 16
bits. The destination register is then decremented by one if a byte instruction or by
two if a word instruction, thus moving the pointer to the previous element of the
string in memory. The word register specified by "r" (used as a counter) is then
decremented by one. The address of the I/O port in the source register is
unchanged. The source, destination, and count registers must be separate and non-
overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode 2 Segmented Mode 2

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: IND Rd1, Rs, r

10 0 1 1 1 0 1 Iw IRs *' 0 10 0 0 8 1
([1 ([1

INDB ([1 Rd1, ([1 Rs, r

100111 011wl Rs *' 01 0008 1 21 21
1 0000 1 r IRd*,01 1000 1 1
0000 1 r 1RRd*O 11 00 0 1
SIND ([1 Rdl, ([1 Rs, r
SINDB ([1 Rdl, ([1 Rs, r

Example: In segmented mode, if register RR4 contains %02004000 (segment 2, offset %4000),
register R6 contains the I/O port address %0228, the port %0228 contains %05B9,
and register RO contains %0016, the instruction
IND @RR4, @R6, RO
will leave the value %05B9 in location %02004000, the value 0/002003FFE in RR4,
and the value %0015 in RO. The V flag will be cleared. Register R6 still contains the
value %0228. In nonsegmented mode, a word register would be used instead of
RR4.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: For SIND, S = 1, otherwise S = o.

99
 INDR Privileged Instruction
(SINDR)
(Special) Input, Decrement and Repeat
INDR dst, src, r dst: IR
INDRB src: IR
SINDR
SINDRB

Operation: dst -- src

AUTODECREMENT dst (by 1 if byte, by 2 if word)
r -- r - 1
repeat until r = 0

This instruction is used for block input of strings of data. INDR and INDRB are used
for Standard I/O operation; SINDR and SINDRB are used for special I/O operation.
The contents of the I/O port addressed by the source word register are loaded into
the memory location addressed by the destination register. I/O port addresses are 16
bits. The destination register is then decremented by one if a byte instruction, or by
two if a word instruction, thus moving the pointer to the previous element of the
string in memory. The word register specified by "r" (used as a counter) is then
decremented by one. The address of the I/O port in the source register is
unchanged. The entire operation is repeated until the result of decrementing r is
zero. This instruction can input from 1 to 65536 bytes or 32768 words (the value for r
must not be greater than 32768 for INDR or SINDR).
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted. The source, destination, and count registers must be separate and
non -overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode 3 Segmented Mode 3

Addressing Assembler Language
Mode Syntax Instruction Format Cycles 2 Instruction Format Cycles 2

IR: INDR @Rd 1 , @Rs, r

INDRB @Rd 1 , @Rs, r 1001 1 1 01 Iwi Rs * 0 110 OS I 11 + 10n I0 0 1 1 1 0 1 IwIRs * 0 11 0 0 5 I 11 + 10n
SINDR @Rd 1 , @Rs, r 100001 r IRd * 01 0000 1 100001 r jRRd*ojooool
SINDRB @Rd 1 , @Rs, r

200
Example: If register Rl contains %202A, register R2 contains the Special 1/0 address %OAFC,
and register R3 contains 8, the instruction
SINDRB @Rl, @R2, R3
will input 8 bytes from the Special 1/0 port OAFC and leave them in descending
order from %202A to %2023. Register Rl will contain %2022, and R3 will contain O.
R2 will not be affected. The V flag will be set. This example assumes nonsegmented
mode; in segmented mode, Rl would be replaced by a register pair.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements transferred.
Note 3: For SINDR, S = I, otherwise S = o.

101
 INI Privileged Instruction
(SINI)
(Special) Input and Increment
INI dst, src, r dst: IR
INIB src: IR
SINI
SINIB

Operation: dst +- src

AUTOINCREMENT dst (by 1 if byte, by 2 if word)
r+-r-1

This instruction is used for block input of strings of data. INI, INIB are used for Stand-
ard I/O operation; SINI, SINIB are used for Special I/O operation. The contents of
the I/O port addressed by the source word register are loaded into the memory loca-
tion addressed by the destination register. I/O port addresses are 16 bits. The
destination register is then incremented by one if a byte instruction, or by two if a
word instruction, thus moving the pointer to the next element of the string in
memory. The word register speCified by "r" (used as a counter) is then decremented
by one. The address of the I/O port in the source register is unchanged. The source,
destination, and count registers should be separate and non-overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: INI @Rd 1, @Rs, r

INIB @Rd 1 , @Rs, r 10011101Iw/Rs*ol100sl 21 100111 011wIR8 * ollOosl 21
SINI @Rd 1 , @Rs, r 10000 1 r IRd*ol lO ool 100001 r !Rd*ollOool
SINIB @Rd 1, @Rs, r

Example: In nonsegmented mode, if register R4 contains %4000, register R6 contains the I/O
port address %0229, the port %0229 contains %B9, and register RO contains %0016,
the instruction
INIB @R4, @R6, RO
will leave the value %B9 in location %4000, the value %4001 in R4, and the value
%0015 in RO. Register R6 still contains the value %0229. The V flag is cleared. In
segmented mode, R4 would be replaced by a register pair.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

102
 Privileged Instruction INIR
(SINIR)
(Special) Input, Increment and Repeat
INIH dst, src, r dst: IR
INIRB src: IR
SlNIR
SINIRB

Operation: dst __ src

AUTOINCREMENT dst (by 1 if byte, by 2 if word)
r __ r - l
repeat until r = 0

This instruction is used for block input of strings of data. INIR and INIRB are used
for Standard I/O operation; SINIR and SINIRB are used for Special I/O operation.
The contents of the I/O port addressed by the source word register are loaded into
the memory location addressed by the destination register. I/O port addresses are 16
bits. The destination register is then incremented by one if a byte instruction, or by
two if a word instruction, thus moving the pointer to the next element in the string.
The word register specified by r" (used as a counter) is then decremented by one.
\l

The address of the I/O port in the source register is unchanged. The entire operation
is repeated until the result of decrementing r is zero. This instruction can input from
1 to 65536 bytes or 32768 words (the value for r must not be greater than 32768 for
INIR or SINIR).
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted. The source, destination, and count registers must be separate and
non-overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 3 Cycles 2 Instruction Format 3 Cycles 2

m: INIR @Rd 1 , @Rs, r

10011101 Iw IRs ;10 0 100051 10011101 TwTRs 0 0005 1
1
INIRB @Rd 1, @Rs, r 11 + 10n ;10
11 + 10n
SINIR @Rd 1, @Rs, r 100001 r IRd ;10 01 0000 I 100001 r 1RRd;loO I0000 I
SINIRB @Rd 1, @Rs, r

103
Example: In nonsegmented mode, if register R1 contains %2023, register R2 contains the I/O
port address %0551, and register R3 contains 8, the statement
INIRB @R1, @R2, R3
will input 8 bytes from port %0551 and leave them in ascending order from %2023
to %202A. Register R1 will contain %202B, and R3 will contain O. R2 will not be
affected. The V flag will be set. In segmented mode, a register pair must be used
instead of R1.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements transferred.
Note 3: For SINIR, S = I, otherwise S = O.

i04
 Privileged Instruction
IRET
Interrupt Return
IRET

Operation: Nonsegmented Segmented

SP +- SP + 2 (Pop "identifier") SP +- SP + 2 (Pop "identifier")
PS +- @SP PS +- @SP
SP +- SP + 4 SP +- SP + 6

This instruction is used to return to a previously executed procedure at the end of a

procedure entered by an interrupt or trap (including a System Call instruction).
First, the "identifier" word associated with the interrupt or trap is popped from the
system stack and discarded. Then the contents of the location addressed by the
system stack pointer are popped into the program status (PS), loading the Flags and
Control Word (FCW) and the program counter (PC). The new value of the FCW is
not effective until the next instruction, so that the status pins will not be affected by
the new control bits until after the IRET instruction execution is completed. The next
instruction executed is that addressed by the new contents of the PC. The system
stack pointer (R15 if nonsegmented, or RR14 if segmented) is used to access
memory. When using a 28001 or 28003, the operation of IRET in nonsegmented
mode is undefined. A 2800113 must be in segmented mode when an IRET instruction
is performed.
Flags: c: Loaded from system stack
Z: Loaded from system stack
S: Loaded from system stack
P IV: Loaded from system stack
D: Loaded from system stack
H: Loaded from system stack

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IRET
I 01111011 100000000 I 13 I 01111011 100000000 I 16

Example: In the nonsegmented 28002 version, if the program counter contains %2550, the
system stack pointer (R15) contains %3000, and locations %3000, %3002 and %3004
contain %7F03, a saved FCW value, and % 1004, respectively, the instruction
IRET
will leave the value %3006 in the system stack pointer and the program counter will
contain % 1004, the address of the next instruction to be executed. The program
status will be determined by the saved FCW value.

105
IP
Jump
IP cc, dst dst: IR, DA, X

Operation: If cc is satisfied, then PC -- dst

A conditional jump transfers program control to the destination address if the condi-
tion specified by "cc" is satisfied by the flags in the FCW. See section 6.6 for a list
of condition codes. If the condition is satisfied, the program counter (PC) is loaded
with the designated address; otherwise, the instruction following the IP instruction is
executed.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format CycIes2

IR: IP CC, @Rdl

§1011110~ 1017 ~011110'~ 1517

DA: IP address
CC,
1011011110100001 cc I 7/7 SS
011011110100001 cc 1
8/8
1 address I o1 segment I offset I
011011110100001 cc
SL 11 segment 10000 0000 10110
offset

X: IP addr(Rd)
CC,
10 1 , 0 1 1 1 1 0 ! Rd "" 0 , cc I 818 SS
01 1011110 I Rd""O I cc I 818
1 address 1 01 segment I offset 1

011 011110 I Rd""O 1 cc

SL 11 segment 10000 0000 11/11
offset

Example: If the carry flag is set, the statement

IP C, %1520
replaces the contents of the program counter with % 1520, thus transferring control
to that location.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: The two values correspond to jump taken and jump not taken.

106
 JR
Jump Relative
JR cc, dst dst: RA

Operation: if cc is satisfied then PC -- PC + (2 x displacement)

A conditional jump transfers program control to the destination address if the condi-
tion specified by "cc" is satisfied by the flags in the FCW. See Section 6.6 for a list
of condition codes. If the condition is satisfied, the program counter (PC) is loaded
with the designated address; otherwise, the instruction following the JR instruction is
executed. The destination address is calculated by doubling the displacement in the
instruction, then adding this value to the updated value of the PC. The updated PC
value is taken to be the address of the instruction following the JR instruction, while
the displacement is an 8-bit signed value in the range -128 to + 127. Thus, the
destination address must be in the range - 254 to + 256 bytes from the start of the JR
instruction. In the segmented mode, the PC segment number is not affected.
The assembler automatically calculates the displacement by subtracting the PC value
of the following instruction from the address given by the programmer.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: JR CC, address

~ l displacement I 6 ~I displacement I 6

Example: If the result of the last arithmetic operation executed is negative, the next four
instructions (which occupy a total of twelve bytes) are to be skipped. This can be
accomplished with the instruction
JR MI, $ + 14
If the S flag is not set, execution continues with the instruction following the JR.
A byte-saving form of a jump to the label LAB is
JR LAB
where LAB must be within the allowed range. The condition code is "blank" in this
case, and indicates that the jump is always taken.

107
LD
Load
LD dst, src dst: R
LDB src: R, IR, DA, x, BA, BX
LDL
or
dst: IR, DA, x, BA, BX
src: R
or
dst: R, IR, DA, X
src: 1M

Operation: dst +- src

The contents of the source are loaded into the destination. The contents of the source
are not affected.
There are three versions of the Load instruction: Load into a register, load into
memory and load an immediate value.

Flags: No flags affected

Load Register
Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: LD Rd, Rs
LDB Rbd, Rbs 110110000~ 3
~ Rs I Rd
I 3

LDL RRd, RRs

EJ0101001~ 5 B0101001~ 5

IR: LD Rd, @Rsl

LDB Rbd, @Rsl ~ 7
~ 7

LDL RRd, @Rsl

B0101001~ 11 B0101001~ 11

DA: LD Rd, address

LDB Rbd, address 10 111 00 0 0 Iw I 0 0 0 0 I Rd I 9 SS
o 111 0 0 0 0 Iw I 0 0 0 0 I Rd
10
1 address I oI segment I offset

o 1 11 0 0 0 0 Iw I 0 0 0 0 I Rd

SL 1 I segment I0 0 00 00 0 0 12
offset

LDL RRd, address

10 11 0 1 0 1 00 I0000 I RRd I 12 SS
011010100100001 RRd
13
I address I oI segment I offset

o 11 010100 I0 0 0 0' RRd

SL 1 I segment I0000 0000 15
offset

I
Note 1: \Iv' ora register in nonsegmented mode, register pair in segmented mode.

108
Load Register (Continued)

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

X: LD Rd, addr(Rs) I
r0 111 0 0 0 0 w1 Rs.= 0 I Rd 1 o 1 11 0 0 0 0 w I I Rs.= 01 Rd
LDB Rbd, addr(Rs) 10 55 10
r address I o I segment I offset

o1 110 0 0 0 Iw I Rs.= 01 Rd

5L 1 I segment I 0000 0000 13

offset

LDL RRd, addr(Rs) 10110101001Rs",01 RRd I 13 55

I
o1 010100 I Rs.= 0 I RRd 13
r address 1 O! segment! offset

o 11 0 1 0 1 0 0 1 Rs '" 0 I RRd
5L 1! segment I0000 0000 16
offset

BA: LD Rd, Rsl(#disp)

r0 or 1 1 0 0 01w1 Rs '" 0 ! Rd 1 00111000!wIRRs*01 RRd
LDB Rbd, Rsl(#disp) 14 14
r displacement I displacement

LDL RRd, Rsl(#disp)

10011 1 0 1 01 I Rs '" 0 I RRd I 17
0011 101 01 ! RRs", 0 I RRd
17
displacement -j displacement
r

BX: LD Rd, Rsl (Rx)

LDB Rbd, RSI (Rx)
r0 11 1 1 0 0 0 w I I Rs.= 0 I Rd I 14
o 111 1 0 0 0 ! w ! RRs* 0 I Rd
14
rooool Rx 10 0 0 0 0 0 0 01 00001 Rx i 0000 0000

LDL RRd, Rsl (Rx) 101111010111Rs.=01 RRd I 17

01!1101011[RR5*01 RRd
17
I00 00 I Rx I0000 0 0 0 01 0000 I Rx 10000 0000

Load Memory
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: LD @Rd 1 , Rs
LDB @Rd 1 , Rbs ~ 8 ~ 8

LDL @Rd 1 , RRs E1011101~ 11 B 011101 !RRd",ol RRs I 11

DA: LD address, Rs
LDB address, Rbs
1011101111wl00001 Rs I 11 55
011101111wl00ool Rs
12
I address 1 o I segment ! offset

011 1 0111[w100001 Rs
5L 1[ segment I 0000 0000 14
offset

Note I: Word register In :1onsegmemed mode, register pair In segmented mode.

109
Load Memory (Continued)

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: LDL address, RRs

I0 1\ 0 1 1 1 0 1 I0000 I RRs I o 11 0 1 1 1 0 1 I 0 0 0 0 r RRs
14 55 15
I address I oI segment I offset
I
o 1 011101 I0 0 0 0 I RRs
5L 11 segment I 00000000 17
offset

X: LD addr(Rd), Rs
LDB addr(Rd). Rbs
I
101110111 w 1 Rdo"O I Rs I 12
55 011101111wl Rdo"O I Rs
12
I address I o I segment I offset

011101111wl Rdo"ol Rs

5L 11 segment 100000000 15
offset

LDL addr(Rd). RRs I0 11 0 1 1 10 1 I Rd * 0 I RRs I 15 55

011 011101 I Rdo"O I RRs 15
I address I o I segment I offset
o 11 0 1 1 1 0 1 1 Rd 0 1 RRs *
5L 11 segment I 00000000 18
offset

BA: LD Rd1(#disp). Rs 1001 11 00 llwl Rdo"O I Rs I 00111001!wIRRd*'°1 Rs

LDB Rd1(#disp). Rbs 14 14
I displacement I displacement

LDL Rdl (#disp), RRs

I0 011 1 0 1 1 1 I Rd * 0 I RRs I 17
o 011 1 0 1 1 1 RRd *' 0 I I RRs 17
r displacement I displacement

BX: LD Rdl (Rx). Rs

LDB Rdl (Rx). Rbs
1011110011wl Rd*,ol Rs
I 14
o 1111 0 0 11 w IRRd 0 1 Rs * 14
10 000 1 Rx 100000000 I 0000 I Rx 100000000

LDL Rdl (Rx), RRs

I
10 1 1 1 0 1 1 1 I Rd * 0 I RRs I 17
011110111 IRRdo"ol RRs
17
I0 0 0 0 I Rx I 0 0 0 0 0 0 00 I 0000 I Rx I 00000000

Notei: Word regisier in nonsegmenied mode, regisier pair in segmented mode.

110
Load Immediate Value
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: LD Rd, #data
001100001100001 Rd
7
00110000110000 I Rd
7
data data

LDB Rbd, #data2

001100000 1 0000 I Rbd 001100000 1 0000 I Rbd
7 7
data 1 data data 1 data

~ data
I 5 ~I data
I 5

LDL RRd, #data

0010101001 0000 1 RRd 001010100100001 RRd
31 data (high) 16 11 31 data (high) 16 11
15 data (low) 0 15 data (low) 0

IR: LD @Rd1 , #data 0010011011Rd*010101 I

001 0 0 1 1 0 1 RRd *0 1 0 1 0 1
11 11
data data

LDB @Rd1 , #data 001001100 !Rd*010101 0010011001RRd*010101

11 11
data 1 data data I data

DA: LD address, #data

0110011011000010101 0110011011000010101
address 14 55 oI segment I offset 15
data data

0110011011000010101
1 I segment I0 0 0 0 0000
5L 17
offset
data

LDB address, #data 011001100 I 00001 0101 011001100 1000010101

address 14 55 oI segment I offset 15
data 1 data data i data

011001100[000010101
1 1 segment I 0000 0000
5L 17
offset
data data
1

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: Although two formats exist for "LDB R, 1M", the assembler always uses the short format. In this case, the
"src field" in the instruction format encoding contains the source operand.

III
Load Immediate Value (Continued)

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

X: LD addr(Rd), #data
011 001101 I Rd",O 1 0101 011001101 Rd",O 10 1 0 1
address 15 55 01 segment offset 15
data data

011001101 Rd",O 10101

11 segment 0000 0000

5L 18
offset

data

LDB addr(Rd), #data

o1 1 0 0 1 1 0 0 1 Rd '" 0 I0 1 0 1 011001100 Rd",O 10101
address 15 55 01 segment offset 15
data I data data data

011001100 Rd",O 10101

11 segment 0000 0000

5L 18
offset
data data

Example: Several examples of the use of the Load instruction are treated in detail in Chapter 4
under addressing modes.

112
 LDA
Load Address
LDA dst, src dst: R
src: DA, x, BA, BX

Operation: dst +- address (src)

The address of the source operand is computed and loaded into the destination. The
contents of the source are not affected. The address computation follows the rules for
address arithmetic. The destination is a word register in nonsegmented mode, and a
register pair in segmented mode.
In segmented mode, the address loaded into the destination has an undefined value
in all reserved bits (bits 16-23 and bit 31). However . this address may be used by
subsequent instructions in the indirect, base, or base-index addressing modes
without any modification to the reserved bits.

Flags: No flags affected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: LDA Rd 1, address

I0 1 11 1 0 1 1 0 10 0 0 0 1 I RRd I
Rd I 12 55
o 1 11 1 0 1 1 0 10 0 0 0
13
I address I o 1 segment 1 offset I
o 1 11 1 0 1 1 0 10 0 0 0 1 RRd
5L 1 I segment I 0000 0000 15
offset

X: LDA Rd 1, addr(Rs)
I0 1 11 1 0 1 1 0 I Rs * 0 I Rd I 13 55
o 1 11 1 0 1 1 0 I Rs * 0 I RRd I 13
I address I o 1 segment 1 offset I
011110110 1 Rs*O 1 RRd
5L 1 I segment 10 0 0 0 0 0 0 0 16
offset

BA: LDA Rd l , Rsl (#disp)

I 0 0 1 1 0 1 0 0 I Rs * 0 1 I
Rd I 15
00110100 IRRs*ol RRd
15
I displacement I displacement I
BX: LDA Rd 1, Rsl (Rx)
I 0 1 1 1 0 1 0 0 I Rs * 0 1 Rd I 01110100 IRRs*ol RRd I
15 15
10000 I Rx 0000 0000 I
1 0000 I Rx 10000 0000 I

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

113
Examples: LDA R4/STRUCT lin nonsegmented mode, register R4 is loaded!
!with the nonsegmented address of the location!
!named STRUCTl
LDA RR2, «3» 8(R4) lin segmented mode, if index register R4!
lcontains %20, then register RR2 is loaded!
!with the segmented address (segment 3, offset %28)!
LDA RR2,RR4(#8) lin segmented mode, if base register RR4!
!contains %01000020, then register RR2 is loaded!
!with the segment address« 1 » %28!
!(segment I, offset %28)!

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

114
 LDAR
Load Address Relative
LDAR dst, src dst: R
src: RA

Operation: dst -- address (src)

The address or the source operand is computed and loaded into the destination. The
contents or the source are not affected. The destination is a word register in
nonsegmented mode, and a register pair in segmented mode. In segmented mode,
fl
the address loaded into the destination has all "reserved bits (bits 16-23 and bit 31)
cleared to zero.
The relative addressing mode is calculated by adding the displacement in the
instruction to the updated value of the program counter (PC) to derive the address.
The updated PC value is taken to be the address of the instruction rollowing the
LDAR instruction, while the displacement is a 16-bit signed value in the range
-32768 to + 32767. The addition is performed following the rules of address
arithmetic, with no modifications to the segment number in segmented mode. Thus
in segmented mode, the source operand must be in the same segment as the LDAR
instruction.
The assembler automatically calculates the displacement by subtracting the PC value
of the following instruction from the address given by the programmer.

Flags: No flags affected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: LDAR Rd 1 , address

100110100100001 Rd
I 15
I 00 1 1 0 1 00 I 0000 !_~ 15
I displacement
I I displacement

Example: LDAR R2, TABLE lin nonsegmented mode, register R2 is loaded!

!with the address of TABLE!
LDAR RR4, TABLE lin segmented mode, register pair RR4 is!
!loaded with the segmented address of TABLE,!
!which must be in the same segment as the program!

Note I: Word register In non segmented mode, register pair in segmemed mode.

115
LDeTL Privileged Instruction
Load Control
LDCTL dst, src dst: CTLR
src: R
or
dst: R
src: CTLR

Operation: dst +- src

This instruction loads the contents of a general purpose register into a control
register, or loads the contents of a control register into a general-purpose register.
The control register may be one of the following CPU registers:

FCW Flag and Control Word

REFRESH Refresh Control
PSAPSEG Program Status Area Pointer - segment number
PSAPOFF Program Status Area Pointer - offset
NSPSEG Normal Stack Pointer - segment number
NSPOFF Normal Stack Pointer - offset

The operation of each of the variants of the instruction is detailed below. The ones
which load data into a control register are described first, followed by the variants
which load data from a control register into a general purpose register. Whenever
bits are marked reserved, the corresponding bit in the source register must be either
a or the value returned by a previous load from the same control register. For com-
patibility with future CPUs, programs should not assume that memory copies of con-
trol registers contain as, nor should they store data in reserved fields of memory
copies of control registers.

Load Into Control Register

LDCTL FCW, Rs

Operation: FCW (2:7) +- Rs (2:7)

FCW (11:15) +- Rs (11:15)

LDCTL REFRESH, Rs

Operation: REFRESH (1: 15) +- Rs (1: 15)

Rs:
REFRESH:
15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 0

rrrrrrrrrrrrrr?
I
re I II....
rate I counter reserved

116
 LDCTL NSPSEG, Rs

mrrrrrrrrrrrrr
Operation: NSPSEG (0: 15) -- Rs (0: 15)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rs:

NSPSEG: I I
In segrrrentecrmode, the NSPSEG register is the normal mode R14 and contains the
segment number of the normal mode processor stack pointer which is otherwise
inaccessible for system mode.
In nonsegmented mode, R14 is not used as part of the normal processor stack
pointer. This instruction may not be used in nonsegmented mode.

LDCTL NSPOFF, Rs
NSP, Rs

mrrrrrrrrrrrrr
Operation: NSPOFF (0: 15) ....- Rs (0: 15)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rs:

*NSPOFF: I I
*NSP in nonsegmented mode
In segmented mode, the NSPOFF register is R15 in normal mode and contains the
offset part of the normal processor stack pointer. In nonsegmented mode, R15 is the
entire normal processor stack pointer.
In nonsegmented mode, the mnemonic "NSP" should be used in the assembly
language statement, and indicates the same control register as the mnemonic
"NSPOFF".

LDCTL PSAPSEG, Rs

Operation: PSAPSEG (8: 14) ....- Rs (8: 14)

cn=trrri'
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rs I
PSAPSEG: II seg men! nurn ber ijill~ll!l\il~\ i il ;';;l~;;w::i>:,,~ll~!ii ;1\l;il !ifili~l lil l !ilil !l
+L-----reserved-------l

The PSAPSEG register may not be used in nonsegmented operation. In

segmented Z8000s, care must be exercised when changing the two PSAP register
values so that an interrupt occurring between the changing of PSAPSEG and
PSAPOFF is handled correctly. This is typically accomplished by first disabling
interrupts before changing PSAPSEG and PSAPOFF.

117
 LDCTL PSAPOFF / Rs
PSAP, Rs

Operation: PSAPOFF (8: 15) __ Rs (8: 15)

Rs: ~ 7 6 5 • 3 2 , 6

* PSAPOFF: I ollset (upper byte) jlllliillllmllilillll!lllll~!!::!:I~

*PSAP in nonsegmented mode
In the nonsegmented 28000s, the mnemonic "PSAP" should be used in the assembly
language statement and indiCates the same control register as the mnemonic
ff
"PSAPOFF In the segmented Z8000s, care must be exercised when changing the
•

two PSAP register values so that an interrupt occurring between the changing of
PSAPSEG and PSAPOFF is handled correctly. This is typically accomplished by first
disabling interrupts before changing PSAPSEG and PSAPOFF. The low order byte
of PSAPOFF should be O.

Load From Control Register

LDCTL Rd, FCW

Operation: Rd (2:7) -- FCW (2:7)

Rd (11:15) -- FCW 01:15) (Z8001 only)
Rd 01: 14) -- FCW 01: 14) (Z8002 only)
Rd (0: 1) -- UNDEFINED
Rd (8: 10) -- UNDEFINED
Rd (5) -- 0 (Z8002 only)

15 14 13 12 11 10 9 8
-r--'T""'--.---.---.--...."""",,,",,

Rd:

LDCTL'Rd, REFRESH

Operation: Rd 0 :8) -- REFRESH 0 :8)

Rd (0) -- UNDEFINED
Rd (9: 15) -- UNDEFINED

118
 LDCTL Rd, PSAPSEG

Operation: Rd (8: 14) -- PSAPSEG (8: 14)

Rd (0:7) -- UNDEFINED
Rd (15) -- UNDEFINED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSAPSEG · ~,,:Mdlliblil:_':
·<,·,.:ilIBfiM
. ~ t ~"~,"~""~b~ t ~.~
Rd:D I I
+L-------undefined - - - - '
This instruction may not be used in nonsegmented mode.

LDCTL Rd, PSAPOFF

Rd, PSAP

Operation: •Rd (8: 15) -- PSAPOFF (8: 15)

Rd (0:7) -- UNDEFINED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

.PSAPOFF:~

Rd: I I undefined I
*PSAP in nonsegmented mode

In nonsegmented mode, the mnemonic PSAP should be used in the assembly

language statement, and it indicates the same control register as the mnemonic
PSAPOFF.

LDCTL Rd, NSPSEG

Operation: Rd (0: 15) NSPSEG (0: 15)

m=rrr-rrrn=rrm
+-

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NSPSEG:

Rd: I I

This instruction is not available in nonsegmented mode.

119
 LDCTL Rd, NSPOFF
Rd, NSP

rrmn=rrrrrmr
Operation: Rd (0: 15) +- NSPOFF (0: 15)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

'NSPOFF:

Rd: I I
*NSP in nonsegmented mode

In nonsegmented mode, the mnemonic NSP should be used in the assembly

language statement, and it indicates the same control register as the mnemonic
NSPOFF.

Flags: No flags affected, except when the destination is the Flag and Control Word (LDCTL
FCW, Rs), in which case all the flags are loaded from the source register.

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

LDcn FCW, Rs
I 01111101 I Rs
B 7 01111101 i Rs
B 7

I~ ~
LDCTL REFRESH, Rs
I 01111101 7 01111101 7

LDCn PSAPSEG, Rs 01111101 [ Rs

B 7

LDCn PSAPOFF, Rs
PSAP, Rs
I 01111101 I Rs 1 11 01 I 7 01111101
~ 7

~
LDCn NSPSEG, Rs 01111101 7

LDCn NSPOFF, Rs
NSP, Rs I 01111101 I Rs
a 7 01111101
I~ 7

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

~
LDCTL Rd, FCW
I 01111101 7
I 01111101
~ 7

~
LDCTL Rd, REFRESH
I 01111101 7 I 01111101
03 7

I~
LDCn Rd, PSAPSEG 01111101 7

LDCTL Rd, PSAPOFF

LDCTL Rd, PSAP
I011111011~ 7 01111101
~ 7

I LDCn Rd, NSPSEG 01111101 I Rd [ 0110 1 7

I
I
LDCn Rd, NSPOFF
Rd, NSP
I 01111101 I Rd
!01111 I 7 01111101
~ 7

120
 LDCTLB
Load Control Byte
LDCTLB dst, src dst: FLAGS
src: R
or
dst: R
src: FLAGS

Operation: dst ...- src

This instruction is used to load the FLAGS register or to transfer its contents into a
general-purpose register. Note that this is not a privileged instruction.

Load Into FLAGS Register

LDCTLB FLAGS, Rbs

FLAGS (2:7) ...- src (2:7)

The contents of the source (a byte register) are loaded into the FLAGS register. The
lower two bits of the FLAGS register and the entire source register are unaffected.

76543210

~
Rbs:

FLAGS: ~slplvIDIH.
•
reserved

Load From FLAGS Register

LDCTLB Rbd, FLAGS

dst (2:7) - FLAGS (2:7)

dst (0: 1) - 0

The contents of the upper six bits of the FLAGS register are loaded into the destina-
tion (a byte register). The lower two bits of the destination register are cleared to
zero. The FLAGS register is unaffected.

76543210
FLAGS:

Rbd: I0 ! 0 I

Flags: When the FLAGS register is the destination, all the flags are loaded from the
source. When the FLAGS register is the source, none of the flags are affected.

121
 Nonsegmented Mode Segmented Mode
Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

I~ ~
LDCTLB FLAGS, Rbs
I 10001100 7
I 10001100 7

[~ ~
LDCTLB Rbd, FLAGS
I 10001100 7 I 10001100 7

122
 LDD
Load and Decrement
LDD dst, src, r clst: IR
LDDB sn:;: IR

Operation: dst.- src

AUTODECREMENT clst and src (by I if byte, by 2 if word)
r .- r - I

This instruction is used for block tranl;lf~rs of strings of data. The contents of the loca-
tion addressed by the source register &re loaded into the location addressed by the
destination register. The source and d~stination registers are then decremented by
one if LDDB, or by two if LDD, thus moving the pointers to the previous elements in
the strings. The word register specifi§d by "r" (used as a counter) is then decrement-
ed by one. The source, destination, and counter registers must be sep arate and non-
overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffeded

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: LDD @Rsl, @Rd 1 , r

I
11 0111 01 Iw IRs *011 001 I 11 0111 01 1w1RRs *0 11 001
LDDB @Rsl, @Rd 1, r 20 20
1 0000 I
r IRd * 011 0 00 I 10000 I r IRRd*oj 1000 1

Example: In nonsegmented mode, if register HI contains %202A, register R2 contains %404A,

the word at location %404A contains %FFFF, and register R3 contains 5,
the instruction
LDD @RI, @R2, R3
will leave the value %FFFF at location %202A, the value %2028 in RI, the value
%4048 in R2, and the value 4 in R3. The V flag will be cleared. In segmented mode,
register pairs would be used instead of RI and R2.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

123
LDDR
Load, Decrement and Repeat
LDDR dst, src, r dst: IR
LDDRB src: IR

Operation: dst -- src

AUTODECREMENT dst and src (by 1 if byte, by 2 if word)
r -- r - 1
repeat until r = a

This instruction is used for block transfers of strings of data. The contents of the loca-
tion addressed by the source register are loaded into the location addressed by the
destination register. The source and destination registers are then decremented by
one if LDDRB, or by two if LDDR, thus moving the pointers to the previous elements
in the strings. The word register speCified by "r (used as a counter) is then
lf

decremented by one. The entire operation is repeated until the result of decremen-
ting r is zero. The source, destination, and counter registers must be separate and
non-overlapping registers. This instruction can transfer from 1 to 65536 bytes or from
1 to 32768 words (the value for r must not be greater than 32768 for LDDR).
The effect of decrementing the pointers during the transfer is important if the source
and destination strings overlap with the source string starting at a lower memory
address. Placing the pointers at the highest address of the strings and decrementing
the pointers ensures that the source string will be copied without destroying the
overlapping area.
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven cycles
should be added to this instruction's execution time for each interrupt request that is
accepted.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
0: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: LDDR @Rd 1 , @Rsl, r

IwIRRs",O! 1 0 0 1 I
LDDRB @Rd 1 , @Rsi, r
11 01 1 1 01 IwIRs '" 0 11 001 I 1101 1 101
11 + 9n
11 +9n
I 1 0000 r I RRd",O I0000 I
1 0000 1
r IRd '" 010 0 0 0 1

124
Example: In nonsegmented mode, if register Rl contains 0J0202A, register R2 contains 0J0404A,
the words at locations 0J04040 through 0J0404A all contain OJoFFFF, and register R3
contains 6, the instruction
LDDR @Rl, @R2, R3
will leave the value OJoFFFF in the words at locations 0J02020 through %202A, the
value %20lE in Rl, the value %403E in R2, and 0 in R3. The V flag will be set. In
segmented mode, register pairs would be used instead of Rl and R2.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements transferred.

125
LDI
Load and Increment
LDI dst, src, r dst: IR
LDIB src: IR

Operation: dst.- src

AUTOINCREMENT dst and src (by 1 if byte, by 2 if word)
r .- r - 1

This instruction is used for block transfers of strings of data. The contents of the loca-
tion addressed by the source register are loaded into the location addressed by the
destination register. The source and destination registers are then incremented by
one if LDIB, or by two if LDI, thus moving the pointers to the next elements in the
strings. The word register specified by "r" (used as a counter) is then decremented
by one. The source, destination, and counter registers must be separate and non-
overlapping registers.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero, cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: LDI @Rd 1 , @Rsl, r

LDIB @Rd 1 , @Rsl, r
11 0111 01 Iw IRI'* 01 °°°1 I 20
110111 01!wIRRs,*01 00011
20
100001 r I '* 0/10 0 °I
Rd 100001 r IRRd,*0!10001

Example: This instruction can be used in a "loop" of instructions which transfers a string of
data from one location to another, but an intermediate operation on each data ele-
ment is required. The following sequence transfers a string of 80 bytes, but tests for
a special value (%OD, an ASCII return character) which terminates the loop if
found. This example assumes nonsegmented mode. In segmented mode, register
pairs would be used instead of Rl and R2.
LD R3, #80 !initialize counter!
LDA Rl, DSTBUF !load start addresses!
LDA R2, SRCBUF
LOOP:
CPB @R2, #%OD !check for return character!
JR EO, DONE !exit loop if found!
LDIB @Rl, @R2, R3 !transfer next byte!
JR NOV, LOOP !repeat until counter O!
DONE:

Note I: Word register in nonsegmented mode, register pair in segmented mode.

126
 LDIR
Load. Increment and Repeat
LDIB dst, src, r dst: IR
LDIBB src: IR

Operation: dst ..... src

AUTOINCREMENT dst and src (by 1 if byte; by two if word)
r ..... r - 1
repeat until R = a

This instruction is used for block transfers of strings of data. The contents of the loca-
tion addressed by the source register are loaded into the location addressed by the
destination register. The source and destination registers are then incremented by
one if LDIRB, or by two if LDIR, thus moving the pointers to the next elements in the
strings. The word register specified by "r" (used as a counter) is then decremented
by one. The entire operation is repeated until the result of decrementing r is zero.
The source, destination, and counter registers must be separate and non-overlapping
registers. This instruction can transfer from 1 to 65536 bytes or from I to 32768
words (the value for r must hot be greater than 32768 for LDIR).
The effect of incrementing the pointers during the transfer is important if the source
and destination strings overlap with the source string starting at a higher memory
address. Placing the pointers at the lowest address of the strings and incrementing
the pointers ensures that the source string will be copied without destroying the
overlapping area.
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven cycles
should be added to this instruction's execution time for each interrupt request that is
accepted.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2
... .-,
IR: LDIR @Rd 1, @Rsl, r
11011101Iw!R8,*0100011 110111 01IwIRRS,*0! 00011
LDIRB @Rd 1 , @Rsl, r 11 +90 11 +90
1 0 0 00 1 r IRd'*°looool 1000 0 1 r jRRd*Oj 00001

127
Example: The following sequence of instructions can be used in nonsegmented mode to copy a
buffer of 512 words 0024 bytes) from one area to another. The pointers to the start of
the source and destination are set, the number of words to transfer is set, and then
the transfer takes place.
LDA Rl, DSTBUF
LDA R2, SRCBUF
LD R3, #512
LDIR @R1, @R2, R3
In segmented mode, R1 and R2 must be replaced by register pairs.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = n'~mber of data elements transferred.

128
 LDK
Load Constant
LDK dst, src dst: R
src: 1M

Operation: dst __ src (src = a to 15)

The source operand (a constant value specified in the src field) is loaded into the
destination register. The source operand is a value from a to 15. It is loaded into the
four low-order bits of the destination register, while the high-order 12 bits are
cleared to zero.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: LDK Rd, #data

EJ111101~ 5 B1111011~ 5

Example: To load register R3 with the constant 9:

LDK R3,#9

129
LDM
Load Multiple
LOM dst, src, n dst: R
src: IR, DA, X
or
dst: IR, DA, X
src: R

Operation: dst .- src (n words)

The contents of n source words are loaded into the destination. The contents of the
source are not affected. The value of n lies between 1 and 16, inclusive. This instruc-
tion moves information between memory and registers; registers are accessed in
increasing order starting with the specified register; RO follows R15. The instruction
can be used either to load multiple registers into memory (e.g. to save the contents
of registers upon subroutine entry) or to load multiple registers from memory (e.g. to
restore the contents of registers upon subroutine exit).
The instruction encoding contains values from 0 to 15 in the "num" field correspond-
ing to values of 1 to 16 for n, the number of registers to be loaded or saved.
The starting address is computed once at the start of execution, and incremented by
two for each register loaded. If the original address computation involved a register,
the register's value will not be affected by the address incrementation during
execution. Similarly, modifying that register during a load from memory will not
affect the address used by this instruction.

Flags: No flags affected

Load Multiple - Registers From Memory

Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles 2 Instruction Format Cycles 2

IR: LDM Rd, QI Rsi, #n

001 011 100 1 RuO I 0001 001011100 RRS*010001
11 +3n 11 + 3n
00001 Rd 10000 I n-1 00001 Rd 00001 n-1

OA: LDM Rd, address, #n 0110111001000010001 011 011100 000010001

0000 I Rd 10000 I n-1 14+3n 55 00001 Rd 00001 n-1 15+3n
address oI segment offset

011 011100 000010001

00001 Rd 0000 I n-1 17+3n
5L
11 segment 0000 0000
offset

130
Load Multiple- Registers From Memory (Continued)

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles 2 Instruction Format Cycles 2

X: LDM Rd, addr(Rs), #n

011 011100 I Rs;<O 10001 011 011100 Rs;<O I 0001
00001 Rd 100001 n-1 15+3n 55 0000 I Rd 0000 I n-1 15+3n
address o I segment offset

011 011100 Rs;<O 10001

0000 I Rd 00001n-1
5L 18+3n
11 segment 0000 0000

offset

Load Multiple - Memory From Registers

Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles 2 Instruction Format Cycles 2

IR: LDM@Rd 1, Rs, #n

001011100 I Rd;<011001 001011100 RRd'" 0 11001
11 + 3n 11 + 3n
00001 Rs looilol n-1 00001 Rs OOilol n-1

DA: LDM address, Rs, #n

0110111001000011001 011 011100 000011001
0000 I Rs 1 0000 I n-1 14+3n 55 0000 I Rs 0000 j n-1 15+3n
address o I segment offset

011011100 000011001

0000 I Rs 0000 I n-1

5L 17+3n
11 segment 0000 0000

offset

X: LDM addr(Rd), Rs, #n

01 I 011 100 I Rd;<O 11 001 011 011100 Rd;<O 11001

0000 I Rs 1 0000 I n-1 15+3n 55 0000/ Rs 0000/ n-1 15+3n

address o I segment offset

011 011100 Rd;<O 11001

00001 Rs 0000 I n-1

5L 18+3n
11 segment 0000 0000

offset

Example: In nonsegmented mode, if register R5 contains 5, R6 contains %0100, and R7 con-

tains 7, the statement
LDM @R6, R5, #3
will leave the values 5, %0100, and 7 at word locations %0100, %0102, and %0104,
respectively, and none of the registers will be affected. In segmented mode, a
register pair would be used instead of R6.

No:e I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of registers.

131
LDPS Privileged Instruction
Load Program Status
LDPS src src: IR, DA, X

Operation: PS -- src

The contents of the source operand are loaded into the Program Status (PS), loading
the Flags and Control Word (FCW) and the program counter (PC). The new value
of the FCW does not become effective until the next instruction, so that the status
pins will not be affected by the new control bits until after the LDPS instruction
execution is completed. The next instruction executed is that addressed by the new
contents of the PC. The contents of the source are not affected.
This instruction is used to set the Program Status of a program and is particularly
useful for setting the System/Normal mode of a program to Normal mode, or for run-
ning a nonsegmented program in segmented 28000s. The PC segment number is not
affected by the LDPS instruction in nonsegmented mode.
The format of the source operand (Program Status block) depends on the current
Segmentation mode (not on the version of the 28000) and is illustrated in the
following figure:
NONSEGMENTED SEGMENTED
LOW ADDRESS
FCW

PC FCW

PC SEG. NO.

HIGH ADDRESS PC OFFSET

(shaded area is reserved-must be zero)

Flags: All flags are loaded from the source operand.

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR:
~11110011~
LOPS @Rsl
~11110011~ 12 16

DA: LOPS address

101111100110000100001 0111110011000010000
16 55 20
I address I oI segment I offset

0111110011000010000

5L 1 I segment 10 0 0 0 0 0 0 0 22
offset

X: LOPS addr(Rs)
I 0 1 11 1 1 0 0 1 I Rs * 0 10 0 0 0 I
17 55
o 1 11 1 1 0 0 1 I Rs * 0 10 0 0 0 20
I address I oI segment I offset I
o 1 11 1 1 0 0 1 I Rs * 0 I 0 0 0 0
SL 1! segment ! 0 0 0 0 0 0 0 0 23
I I I I! off~et I
_ _- - . l - L-J... L-
Note 1: Word register is used in non segmented mode, register pair in segmented mode.

132
Example: In nonsegmented Z8000s, if the program counter contains %2550, register
R3 contains %5000, location %5000 contains %1800, and location %5002 contains
%AOOO, the instruction
LDPS @R3
will leave the value %AOOO in the program counter, and the FeW value will be
%1800 (indicating Normal Mode, interrupts enabled, and all flags cleared.) In the
segmented mode, a register pair is used instead of R3.

133
LDR
Load Relative
LOR dst, src dst: R
LORB src: RA
LORL or
dst: RA
src: R

Operation: dst .- src

The contents of the source operand are loaded into the destination. The contents of
the source are not affected. The relative address is calculated by adding the
displacement in the instruction to the updated value of the program counter (PC)
to derive the operand's address. In segmented mode, the segmented number of the
computed address is the same as the segment number of the PC. The updated PC
value is taken to be the address of the instruction following the LDR, LDRB, or
LDRL instruction, while the displacement is a l6-bit signed value in the range
-32768 to + 32767.
Status pin information during the access to memory for the data operand will be Pro-
gram Reference, (1100) instead of Data Memory request (1000).
The assembler automatically calculates the displacement by subtracting the PC value
of the following instruction from the address given by the programmer.
This instruction must be used to modify memory locations containing program infor-
mation, such as the Program Status Area, if program and data space are separated
by the memory system.

Flags: No flags affected

Load Relative Register

Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: LDR Rd, address

LDRB Rbd, address
IOO11000lwlooooI Rd I 14
IOO11000lwlooooi Rd I 14
I displacement I I displacement I
LDRL RRd, address
I 001 10101 I0000 I RRd I 17
I 0 0 1 1 0 1 0 1 I0 0 0 0 I RRd I 17
I displacement I I displacement I

134
Load Relative Memory
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

RA: LDR address, Rs looooi

LDRB address, Rbs
IOO11001j w Rs
I 14
IOO110011wlooool Rs I 14
I displacement I I displacement I

LDRL address, RRs I 0 0 1 1 0 1 1 1 I 0 0 0 0 I RRs I

17
I 00 1 1 0 1 1 1 I 0000 I RRs 1 17
I displacement
I I displacement
I

Example: LDR R2, DATA [register R2 is loaded with the value in thel
!location named DATA!

135
 Privileged Instruction
MBIT
Multi-Micro Bit Test
MBIT

Operation: S .- 1 if MI high (inactive); a otherwise

This instruction is used to synchronize multiple processors' exclusive access to
shared hardware resources. The multi-micro input pin (Ml) is tested, and the S flag
is cleared if the pin is low (active); otherwise, the S flag is set, indicating that the
pin is high (inactive).
After the MBIT instruction is executed, the S flag can be used to determine whether
a requested resource is available or not. If the S flag is clear, then the resource is
not available; if the S flag is set, then the resource is available for use by this CPU.

Flags: c: Unaffected
Z: Undefined
S: Set if MI is high; cleared otherwise
V: Unaffected
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

MBIT
I 0111101100001010
I 7
I 0111101100001010
I 7

Example: The following sequence of instructions can be used to wait for the availability of a
resource.
LOOP:
MBIT !test multi-micro input!
JR PL,LOOP !repeat until resource is available!
AVAILABLE:

136
 Privileged Instruction
MREQ
Multi-Micro Request
MREQ dst dst: R

Operation: z -- a
if MI low (active) then S -- a
MO forced high (inactive)
else MO forced low (active)
repeat dst -- dst - 1 until dst a
if MI low (active) then S -- 1
else S -- a
MO forced high (inactive)
Z -- 1

This instruction is used to synchronize multiple processors' exclusive access to

shared hardware resources. A request for a resource is signalled through the multi-
micro input and output pins (MI and MO), with the Sand Z flags indicating the
availability of the resource after the MREQ instruction has been executed.
First, the Z flag is cleared. Then the MI pin is tested. If the MI pin is low (active),
the S flag is cleared and the MO pin is forced high (inactive),thus indicating that the
resource is not available and removing any previous request by the CPU from the
MO line.
If the MI pin is high (inactive), indicating that the resource may be available, a
sequence of machine operations occurs. First, the MO pin is forced low (active),
signalling a request by the CPU for the resource. Next, a finite delay to allow for
propagation of the signal to other processors is accomplished by repeatedly
decrementing the contents of the destination (a word register) until its value is zero.
The original value of the counter must be greater than 2. Then the MI pin is tested to
determine whether the request for the resource was acknowledged. If the MI pin is
low (active), the S flag is set to one, indicating that the resource is available and
access is granted. If the MI pin is still high (inactive), the S flag is cleared to zero,
and the MO pin is forced high (inactive), indicating that the request was not granted
and removing the request signal for the MO. Finally, in either case, the Z flag is set
to one, indicating that the original test of the MI pin caused a request to be made.
External hardware should inhibit bus request while MO is active to ensure and upper
bound on request timing.
S flag Z flag MO Indicates

a a high Request not signalled

(resource not available)
a high Request not granted
(resource not available)
low Request granted
(resource available)

Flags: c: Unaffected
Z: Set if request was signalled; cleared otherwise
S: Set if request was signalled and granted; cleared otherwise
V: Unaffected
D: Unaffected
H: Unaffected

137
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles l Instruction Format Cycles l

R: MREQ Rd
~1111011~ 12+7" l!!l111011 ~ 12+7"

Example: TRY:
LD RO,#5 !allow for propagation delay!
MREQ RO !multi-micro request with delay!
!in register RO!
JR MI,AVAILABLE
JR Z,NOT_GRANTED
NOT_AVAILABLE: !resource not available!

!request not granted!

JR TRY !try again after awhile!

AVAILABLE: !use resource!

MRES !release resource!

Note 1: If the request is made, n = number of times the destination is decreP-1ented.. If the request is not made,
n = o.

138
 Privileged Instruction MRES
Multi-Micro Reset
MRES

Operation: MO is forced high (inactive)

This instruction is used to synchr-onize multiple processors' exclusive access to

shared hardware resources. The multi-micro output pin MO is forced high (inactive).
Forcing MO high (inactive) indicates that a resource controlled by the CPU is
available for use by other processors.

Flags: No flags affected.

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

MRES 101111011 100001001 I 5 101111011 100001001 I 5

Example: MRES !signal that resource controlled by this CPU!

lis available to other processors!

139
MSET Privileged Instruction
Multi-Micro Set
MSET

Operation: MO is forced low (active)

This instruotion is used to synchronize multiple processors' exclusive access to

shared hardware resources. The multi-micro output pin MO is forced low (active).
Forcing MO low (active) is used either to indicate that a resource controlled by the
CPU is not available to other processors, or to signal a request for a resource con-
trolled by some other processor.

Flags: No flags affected.

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

MSET 101111011 1000 0 1000 I 5 101111011 t 00001000 I 5

Example: MSET !CPU controlled resource not available!

140
 MULT
Multiply
MULT dst, src dst: R
MULTL src: R, 1M, IR, DA, X

Operation: Word
dst (0:31) +- dst (0: 15) X src (0: 15)
Long
dst (0:63) +- dst (0:31) x src (0:31)

The low-order half of the destination operand (multiplicand) is multiplied by the

source operand (multiplier) and the product is stored in the destination. The con-
tents of the source are not affected. Both operands are treated as signed, two's com-
plement integers. For MULT, the destination is a register pair and the source is a
word value; for MULTL, the destination is a register quadruple and the source is a
long word value.
For proper instruction execution, the "dst field" in the instruction format encoding
must be even for MULT and must be a multiple of 4 (0, 4, 8, 12) for MULTL. If the
source operand in MULTL is a register, the "src field" must be even.
The initial contents of the high-order half of the destination register do not affect the
operation of this instruction and are overwritten by the result. The carry flag is set to
indicate that the upper half of the destination register is required to represent the
result; if the carry flag is clear, the product can be correctly represented in the same
precision as the multiplicand and the upper half of the destination merely holds a
sign extension.
The follOWing table gives execution times for word and long word operands in each
possible addressing mode.

src Word Long Word

NS SS SL NS SS SL
R 70 70 70 282 + 7*n 282 + 7*n 282 + 7*n
1M 70 70 70 282 + 7*n 282 + 7*n 282 + 7*n
IR 70 70 70 282 + 7*n 282 + 7*n 282 + 7*n
DA 71 72 74 283 +7*n 284 + 7*n 286 + Tn
X 72 72 75 284 + 7*n 284 +7*n 287 + 7*n
(n = number of bits equal to one in the absolute value of the low-order 16 bits of the destination operand)

When the multiplier is zero, the execution time of Multiply is reduced to the follOWing times:

src Word Long Word

NS SS SL NS SS SL
R 18 18 18 30 30 30
1M 18 18 18 30 30 30
IR 18 18 18 30 30 30
DA 19 20 22 31 32 34
X 20 20 23 32 32 35

Flags: c: MULT-set if product is less than _2 15 or greater than or equal to 2 15 ; cleared

otherwise; MULTL-set if product is less than - 2 31 or greater than or equal to 2 31 ;
cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Cleared
D: Unaffected
H: Unaffected

141
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

R: MULT RRd, Rs
E1011001~ E!:1011001~
MULTL RQd, RRs
E1011000~ E!:1011000~
1M: MULT RRd, #data
001 0 1 1 0 0 1 I0000 I RRd 001 0 1 1 0 0 1 I0 000 I RRd
data data

MULTL RQd, #data 001011000100001 ROd

001011000100001 ROd

31 data (high) 16 31 data (high) 16

15 data (low) 0 15 data (low) 0

IR: MULT RRd, <1?Rsl

~011001~ ~1011001~
MULTL RQd, @Rsl
~ 0 1 1 00 0 I RH 0 I ROd I ~ 011000 IRRso'ol ROd I
DA: MULT RRd, address
011 01100 1J 00001 RRd I
o 1 01100 1 I 0 0 0 0 I RRd
55
address o I segment I offset

I
o 1 01100 1 , 0000 I RRd
5L 11 segment 10000 0000
offset

MULTL RQd, address

I
o1 011000 I 0 0 0 0 I ROd 011011000100001 ROd
address 55 o I segment I offset

011011000 !00001 ROd

5L 1 I segment I0 0 0 0 0000
offset

X: MULT RRd, addr(Rs)

I I RH 0 I RRd J
o 1 0 1 1 00 1
55
o 110 1 1 0 0 1 I Rs * 0 I RRd
address J 01 segment I offset
0110110011 Rso'O I RRd

5L 1 I segment I0 0 0 0 0000
offset

MULTL RQd, addr(Rs)

10 1 1011000 l RHO 1 ROd I I
o1 0 11000 I Rs * 0 I RQd
I address I 55 o I segment I offset

0110110001RSo'O! ROd

5L l' segment I0 0 0 0 0 000

offset

142
Example: If register RQO (composed of register pairs RRO and RR2) contains
%2222222200000031 (RR2 contains decimal 49). the statement
MULTL RQO,#l0
will leave the value %ooOOOOooOOOOOlEA (decimal 490) in RQO.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: Execution times for each instruction are given in the preceding tables.

143
NEG
Negate
NEG dst dst: R, IR, DA, X
NEGB

Operation: dst ...- - dst

The contents of the destination are negated, that is, replaced by its two's comple-
ment value. Note that %8000 for NEG and %80 for NEGB are replaced by
themselves since in two's complement representation the negative number with
greatest magnitude has no positive counterpart; for these two cases, the V flag is set.

Flags: c: Cleared if the result is zero; set otherwise, which indicates a "borrow"
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if the result is %8000 for NEG, or %80 for NEGB: cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
NEG Rd
7 Rd 0010
1 7
NEGB Rbd 1

IR: NEG !!fRdl

NEGB «<RdJ ~0011 0~1 Rd*O 1 0010 I 12 ~0011 oI!IRRd *0 I 001 0 I 12

DA: NEG address

w 0000
NEGB address
10110011 olw10000 10010 I 15 55
011001101 I 1 001 0
16
I address I oI segment I offset

011001101 w1 0000 I 0010

5L 1 I segment I0 0 0 0 0000 18
offset

X: NEG addr(Rd)
I0 1 10 0 1 1 0 Iwi Rd * 0 I0 0 10 I o1 I0 0 1 1 0 IwI Rd * 0 I0 0 10
NEGB addr(Rd) 16 55 16
I address I oI segment I offset
o1 10 0 1 1 0 IwI Rd * 0 I0 0 1 0
5L 1 I segment I0 0 0 0 0000 19
offset

Example: If register R8 contains %05lF, the statement

NEG R8
will leave the value %FAEI in R8.

Note 1: \A../ord register in nonsegmented mode, register pair in ~,egmpnted mode.

144
 NOP
No Operation
NOP

Operation: No operation is performed.

Flags: No flags affected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

NOP
110001101 I 00000111 I 7 110001101 100000111 I 7

145
OR
Or
OR dst, src dst: R
ORB src: R, 1M, IR, DA, X

Operation: dst +- dst OR src

The source operand is logically ORed with the destination operand and the result is
stored in the destination. The contents of the source are not affected. The OR opera-
tion results in a one bit being stored whenever either of the corresponding bits in the
two operands is one; otherwise a zero bit is stored.

Flags: c: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
P: OR-unaffected; ORB-set if parity of the result is even; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
OR Rd, Rs
4 4
ORB Rbd, Rbs

1M: OR Rd, #data

1001000101100001 Rd I 7
001000101100001 Rd
7
I data I data

ORB Rbd, #data

1001000100 1 000 0 I Rd I 001000100100001 Rd
7
7
I data I data I data I data

IR:
~ ~
OR Rd, @Rsi
7 7
ORB Roo, @Rsl

DA: OR Rd, address

ORB Rbd, address
10110001 olwl 0000 1 Rd I 9 55
01100010lwl00001 Rd
10
I address I o I segment I offset

0110001 olwl 0000 I Rd

5L 1 I segment I0 0 0 0 0000 12
offset

X: OR Rd, addr(Rs)
I Rs * 0 I I I Rs * 0 I
ORB Rbd, addr(Rs)
10 1 10 0 0 1 01 w Rd I 10 55
o 1 10 0 0 1 0 w Rd
10
I address I o I segment I offset

o 1 10 0 0 10 wI I Rs * 0 I Rd
5L 1 I segment I0 0 0 0 0000 13

I address

146
Example: If register RL3 contains O/OC3 (1000011) and the source operand is the immediate
value 0/07B (01111011), the statement
ORB RL3,#%7B
will leave the value %FB (1111011) in RL3.

Note 1: Word register in nonsegmented mode. register pair in segmented mode.

147
 OTDR Privileged Instruction
(80TDR)
(Special) Output, Decrement and Repeat
OTDR dst, src, r dst: IR
OTDRB src: IR
SOTDR
SOTDRB

Operation: dst.- src

AUTODECREMENT src (by 1 if byte, by 2 if word)
r.-r-1
repeat until r = 0

This instruction is used for block output of strings of data. OTDR and OTDRB are
used for Standard I/O operation; SOTDR and SOTDRB are used for Special I/O
operation. The contents of the memory location addressed by the source register are
loaded into the I/O port addresses by the destination word register. I/O port ad-
dresses are 16 bits. The source register is then decremented by one if a byte instruc-
tion, or by two if a word instruction, thus moving the pointer to the previous element
of the string in memory. The word register specified by "r" (used as a counter) is
then decremented by one. The address of I/O port in the destination register is
unchanged. The entire operation is repeated until the result of decrementing r is
zero. This instruction can output from 1 to 65536 bytes or 32768 word (the value for r
must not be greater than 32768 for OTDR or SOTDR).
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 3 Cycles2 Instruction Format 3 Cycles2

IR: OTDR @Rd,@Rsl, r

OTDRB @Rd,@Rsl, r I 001 1 1 01 IwIRs * °11 01 S I 11 + 10n
1 0 o 111 01 IwIRRs*011 01 S I 11 + 10n
SOTDR @Rd,@Rsl, r 10000 1
r IRd*olooool 10000 1
r
IRd * °I °°°0 I
SOTDRB atRd,@Rsl, r

148
Example: In nonsegmented mode, if register Rll contains %OFFF, register R12 contains
0/0 B006, and R13 contains 6, the instruction
OTDR @Rll, @R12, R13
will output the string of words from locations O/OB006 to %AFFC (in descending
order of address) to port %OFFF. R12 will contain %AFFA, and R13 will contain O.
Rll will not be affected. The V flag will be set. In segmented mode, R12 would be
replaced by a register pair.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements transferred.
Note 3: For SOTDR, S = 1; otherwise S = o.

149
 OTIR Privileged Instruction
(SOTIR)
(Special) Output. Increment and Repeat
OTIR dst, src, r dst: IR
OTIRB src: IR
SOTIR
SOTIRB

Operation: dst __ src

AUTOINCREMENT src (by 1 if byte, by 2 if word)
r--r-1
repeat until r = a

This instruction is used for block output of strings of data. OTIR and OTIRB are used
for Standard I/O operation; SOTIR and SOTIRB are used for Special 1/0 operation.
The contents of the memory location addressed by the source register are loaded
into the 1/0 port addressed by the destination word register. I/O port addresses are
16 bits. The source register is then incremented by one if a byte instruction, or by
two if a word instruction, thus moving the pointer to the next element of the string in
memory. The word register specified by "r" (used as a counter) is then decremented
by one. The address of I/O port in the destination register is unchanged. The entire
operation is repeated until the result of decrementing r is zero. This instruction can
output from 1 to 65536 bytes or 32768 words (the value for r must not be greater than
32768 for OTIR or SOTIR).
This instruction can be interrupted after each execution of the basic operation. The
program counter value of the start of this instruction is saved before the interrupt
request is accepted, so that the instruction can be properly resumed. Seven more
cycles should be added to this instruction's execution time for each interrupt request
that is accepted.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 3 Cycles Instruction Format 3 Cycles

IR: OTIR ({f Rd, @ Rsl, r

OTIRB ({lRd, ({lRs] , r 100111 01/wl Ra *- 01001 sl 11 + 10n I 0 0 1 1 1 0 1 IwIRRs*- °I00 1 S I 11 + 10n
SOTIR ~l Rd, ({t Rsi , r 1
0000
1
r IRd*olooool 100 00 1
r IRd *- 01 0000 I
SOTIRB ({lRd, (1?Rsl, r

150
Example: In nonsegmented mode, the following sequence of instructions can be used to output
a string of bytes to the speCified 1/0 port. The pointers to the I/O port and the start
of the source string are set, the number of bytes to output is set, and then the output
is accomplished.
LD Rl, #PORT
LDA R2, SRCBUF
LD R3, #LENGTH
OTIRB @Rl, @R2, R3
In segmented mode, a register pair would be used instead of R2.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements transferred.
Note 3: For SOTIR, S = 1; otherwise S = O.

151
 OUT Privileged Instruction
(SOUT)
(Special) Output
OUT dst, src dst: IR, DA
OUTB src: R
SOUT dst, src dst: DA
SOUTB src: R

Operation: dst -- src

The contents of the source register are loaded into the destination, an Output or
Special Output port. OUT and OUTB are used for Standard I/O operation; SOUT
and SOUTB are used for Special I/O operation.

Flags: No flags affected.

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 1 Cycles Instruction Format l Cycles

IR: IOO111111~
OUT @Rd, Rs
OUTB @Rd, Rbs loo11111~ 10 10

DA: OUT port, Rs

IOO111011 W l Rs 1011 S I IOO111011 w l Rs 1011 S I
OUTB port, Rbs 12 12
SOUT port, Rs I port
I I port
I
SOUTB port, Rbs

Example: If register R6 contains %5252, the instruction

OUT % 1120, R6
will output the value %5252 to the port %1120.

Note 1: For SOUL S = 1; otherwise S = o.

152
 Privileged Instruction OUTD
(SOUTO)
(Special) Output and Decrement
OUTD dst, src, r dst: IR
OUTDB src: IR
SOUTO
SOUTDB

Operation: dst+- src

AUTODECREMENT src (by 1 if byte, by 2 if word)
r+-r-1

This instruction is used for block output of strings of data. OUTD and OUTDB are
used for Standard I/O operation; SOUTD and SOUTDB are used for Special I/O
operation. The contents of the memory location addressed by the source register are
loaded into the I/O port addressed by the destination word register. I/O port ad-
dresses are 16 bits. The source register is then decremented by one if a byte instruc-
tion, or by two if a word instruction, thus moving the pointer to the previous element
of the string in memory. The word register specified by "r" (used as a counter) is
then decremented by one. The address of the I/O port in the destination register is
unchanged.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
0: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format 2 Cycles Instruction Format 2 Cycles

IR: OUID @Rd, @Rsl, r

OUIDB @Rd, @Rsl, r
I 0 0 1 1 1 0 1 IW !Rs * 0 11 0 1 5 I 21
1 00 1 1 1 0 1 I w IRRs * 0 11 0 15 1
21
10000 1 r IRd '" 0 11000 1 1 0000 r IRd '" 0 11 0 0 0 1
S~UID e. Rd, e! Rs', r 1
SOUIDB @Rd, @Rsl, r

Example: In segmented mode, if register R2 contains the I/O port address %0030, register RR6
contains % 12005552 (segment % 12, offset %5552), the word at memory location
% 12005552 contains % 1234, and register R8 contains % 1001, the instruction
OUTD @R2, @RR6, R8
will output the value %1234 to port %0030 and leave the value %12005550 in RR6,
and % 1000 in R8. Register R2 will not be affected. The V flag will be cleared. In
nonsegmented mode, a word register would be used instead of RR6.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: For SQUID, S = 1; otherwise S = O.

153
 OUTI Privileged Instruction
(SOUTI)
(Special) Output and Increment
OUTI dst, src, r dst: IR
OUTIB src: IR
SOUTI
SOUTIB

Operation: dst +- src

AUTOINCREMENT src (by 1 if byte, by 2 if word)
r+-r-l

This instruction is used for block output of strings of data. OUTI and OUTIB are
used for Standard I/O operation; SOUTI and SOUTIB are used for Special I/O
operation. The contents of the memory location addressed by the source register are
loaded into the I/O port addressed by the destination word register. I/O port ad-
dresses are 16-bit. The source register is then incremented by one if a byte instruc-
tion, or by two if a word instruction, thus moving the pointer to the next element of
the string in memory. The word register specified by "r" (used as a counter) is then
decremented by one. The address of the I/O port in the destination register is un-
changed.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruc::tion Format 2 Cycles Instruc::tion Format 2 Cyc::les

IR: aUII @Rd, @Rsl, r

aUIIB @Rd, @Rsl, r 1 00111 01 IwIRS * 0 I0015 I 21
10 0 1 1 1 0 1 IwIRRs *0 I0 0 1 S 1
21
SaUTI @Rd, @Rsl, r 10 000 1 r IRd*01 1000 1 10000 1 r I Rd * 011000 I
SaUTIB @Rd, @Rsl, r

154
Example: This instruction can be used in a "loop" of instructions which outputs a string of
data, but an intermediate operation on each element is required. The following
sequence outputs a string of 80 ASCII characters (bytes) with the most significant bit
of each byte set or reset to provide even parity for the entire byte. Bit 7 of each
character is initially zero. This example assumes nonsegmented mode. In segmented
mode, R2 would be replaced with a register pair.
LD RI, #PORT !load I/O address!
LDA R2, SRCSTART !load start of string!
LD R3, #80 !initialize counter!
LOOP:
TESTB @R2 !test byte parity!
JR PE, EVEN
SETB @R2, #7 !force even parity!
EVEN:
OUTIB @RI, @R2, R3 !output next byte!
JR NOV, LOOP !repeat until counter O!
DONE:

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: For SOUT!, S = 1; otherwise S = o.

155
POP
Pop
POP dst, src dst: R, IR, DA, X
POPL src: IR

Operation: dst -- src

AUTOINCREMENT src (by 2 if word, by 4 if long)

The contents of the location addressed by the source register (a stack pointer) are
loaded into the destination. The source register is then incremented by a value
which equals the size in bytes of the destination operand, thus removing the top ele-
ment of the stack by changing the stack pointer. Any register except RO (or RRO in
segmented mode) can be used as a stack pointer.
The same register cannot be used in both the source and destination addressing
fields.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: POP Rd, @Rsl

E1010111~ 8 E10101111~ 8

POPL RRd, a'Rs!

~, 0 1 0 1 0 1 IRS. * 0 I RRd
I 12 ~I 01 01 01 I
RRH 01 RRd I 12

IR: POP @Rd1, @Rsl

~10101111~ 12 ~ 0101111 RRs * 0 8 12

POPL @Rd 1, @Rs!

~I 010101 I Rs*O I
Rd *0 I 19 E1 010101 IRRs,t°IRRd,t°1 19

DA: POP address, @ Rsl

I0 1 I 0 1 0 1 1 1 1 Rs,t 0 I0 0 0 0 I 16
55 01 I 0 1 01 1 1 IRRH 0 i 0000 16
I address I o I segment I offset

011 0101 11 I RRs,tO 1 0000

5L 1 I segment I0000 0000 18

offset

POPL address, Q. Rsl

I0 1 I 0 1 0 1 0 1 I Rs,t 0 I0 0 0 0 I 23 55
011 010101 IRRHO 10000
23
I address I o I segment I offset

0110101011RRHoI0000
5L 1 I segment I0000 0000 25
offset

156
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

X: POP addr(Rd), @Rsl

I0 1 I0 1 0 1 1 1 I Ru 0 I Rd;O 0 I 011010111 [RRHol Rd;OO I
16 55 16
I address I oI segment I offset I
0110101111RRs;OolRd;OO

5L 1 [ segment I 0000 0000 19

offset

POPL addr(Rd), @Rsi

1011 010101 I RuO I Rd;OO I
55
011 01 01 01 I
IRRs;O 0 Rd;O 0 I 23
23
I address I oI segment I offset
I
011 0101011RRs;oO! Rd;OO

5L 1 I segment I0000 0000 26

offset

Example: In nonsegmented mode, if register R12 (a stack pointer) contains %1000, the word at
location % 1000 contains %0055, and register R3 contains %0022, the instruction
POP R3, @R12
will leave the value %0055 in R3 and the value %1002 in R12. In segmented mode,
a register pair must be used as the stack pointer instead of R12.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

157
PUSH
Push
PUSH dst, src dst: IR
PUSHL src: R, 1M, IR, DA, X

Operation: AUTODECREMENT dst (by 2 if word, by 4 if long)

dst.- src

The contents of the destination register (a stack pointer) are decremented by a value
which equals the size in bytes of the source operand. Then the source operand is
loaded into the location addressed by the updated destination register, thus adding a
new element to the top of the stack by changing the stack pointer. Any register
except RO (or RRO in segmented mode) can be used as a stack pointer.
With PUSHL, the Same register cannot be used for both the source and destination
addressing fields.

Flags: No flags affected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: PUSH «L Rd l , Rs
~O10011~ 9 B0100lll~ 9

PUSHL @Rd 1, RRs

~0100011~ 12 B 010001 IRRd*ol RRs I 12

1M: PUSH «L Rdi , #data

10010Ol101I Rd *0/10011 0010011011RRd*0110011
12 12
I data I data I
PUSH If! Rd 1, «L Rsl
EJ0100lll~ 13 B010011~ 13

EJ 01 000 1 I Rd * 0 IRS * 0 I 20 EI 01000 lI RRd *oIRRS*ol 20

DA: PUSH VI Rd , address

1011010011/ Rd*olooool 011010011!RRd*0Iooool
14 55 14
I address I o I segment! offset I
0110100111RRd*010000
5L 11 segment I 00000000 16
offset

PUSHL@Rd 1 , address 0110100011RRd*0100001

21 55 o 1 segment I offset I 21

0110100011RRd*010000
5L 11 segment I 00000000 23
offset

I I I I

158
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

X: PUSH @Rdl, addr(Rs)

101 1 010011 I Rd;eO 1 RHO I 011 0100111RRd;e01 Rs;eO
14 55 14
I address I oj segment 1 offset

011 010011IRRd;e0! Rs;eO

5L 1 I segment '0 0 0 0 0 0 0 0 17
offset

PUSHL @Rdl, addr(Rs)

10 1 1010001 I Rd;eO 1 Rs;eO I 21 55
011 0100011RRd;e01 Rs;eO
21
I address I o I segment 1 offset

o 11 I
0 1 00 0 1 IRRd;e 0 RS;e 0

5L 1 1 segment I0000 0000 24

offset

Example: In nonsegmented mode, if register R12 (a stack pointer) contains %1002, the word at
location % 1000 contains %0055, and register R3 contains %0022, the instruction
PUSH @R12, R3
will leave the value %0022 in location %1000 and the value %1000 in R12. In
segmented mode, a register pair must be used as the stack pointer instead of R12.

Note 1: Word register is used in nonsegmented mode, register pair in segmented mode.

159
RES
Reset Bit
RES dst, src dst: R, IR, DA, X
RESB src: 1M
or
dst: R
src: R

Operation: dst(src) .,.- 0

This instruction clears the specified bit within the destination operand without
affecting any other bits in the destination. The source (the bit number) can be
specified as either an immediate value (Static), or as a word register which contains
the value (Dynamic). In the second case, the destination operand must be a register,
and the source operand must be RO through R7 for RESB, or RO through R15 for
RES. The bit number is a value from 0 to 7 for RESB, or 0 to 15 for RES, with 0
indicating the least significant bit.
Only the lower four bits of the source operand are used to specify the bit number for
RES, while only the lower three bits of the source operand are used with RESB.
When the source operand is an immediate value, the "src field" in the instruction
format encoding contains the bit number in the lowest four bits for RES, or the
lowest three bits for RESB.

Flags: No flags affected

Reset Bit Static

Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
RES Rd, #b
4 4
RESB Rbd, #b

IR:
~ ~
RES (/I Rd', #b
11 11
RESB ~I Rd J , #b

DA: RES address, #b

RESB address, /fb
I011100011wlooooi b I 13 55
o11100011wlooooI b
14
I address
I o I segment 1 offset

o11100011wlooool b
5L 1I segment 10000 0000 16
offset

X: RES addr(Rd), #b
I0111 00011wI Rd '" 0 1 o1110 0011 wI Rd '" 0 I
RESB addr(Rd), #b
b I 14 55
b
14
I address I oI segment 1 offset

I 0111000 'Iwl Rd" I b

10000 0000 !
5L 11! segment

L.....--_o_ffse_t -----111_ 17

160
Reset Bit Dynamic
Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: RES Rd, Rs
I0 0 11 0 0 0 1Iw 1 0000 1 Rs I 1001100011wl 0000 I Rs J
RESB Rbd, Rs 2 10 10
I 0000 I Rd 10 0 0 0 1 0 0 0 0 I 100001 Rd 10000100001

Example: If register RL3 contains %B2 (0110010), the instruction

RESB RL3, #1
will leave the value %BO (0110000) in RL3.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: Word register 0-7 only.

161
RESFLG
Reset Flag
RESFLG flag flag: C, z, s, P, V

Operation: FLAGS (4:7) FLAGS (4:7) AND NOT instruction (4:7)

Any combination of the C, z, s, P or V flags are cleared to zero if the corresponding

bits in the instruction are one. If the bit in the instruction corresponding to a flag is
zero, the flag will not be affected. All other bits in the FLAGS register are
unaffected. Note that the P and V flags are represented by the same bit.
There may be one, two, three, or four operands in the assembly language statement,
in any order.

Flags: c: Cleared if speCified, unaffected otherwise

Z: Cleared if speCified, unaffected otherwise
S: Cleared if speCified, unaffected otherwise
P/V: Cleared if speCified, unaffected otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

RESFLG flags
~ 0011 01 Ie Z S PIYI 0011 I 7 ~ 0 0 1 1 0 1 Ie Z S PlY! 00 1 1 I 7

Example: If the C, S, and V flags are set 0) and the Z flag is clear (0), the statement
RESFLG C. V
will leave the S flag set 0), and the C, Z, and V flags cleared (0).

162
 RET
Return
RETcc

Operation: Nonsegmented Segmented

if cc is true then if cc is true then
PC-- @SP PC -- @SP
SP -- SP + 2 SP -- SP + 4

This instruction is used to return to a previously executed procedure at the end of a

procedure entered by a CALL or CALR instruction. If the condition specified by
"ce" is satisfied by the flags in the FCW, then the contents of the location addressed
by the processor stack pointer are popped into the program counter (PC). The next
instruction executed is that addressed by the new contents of the PC. See section
6.6 for a list of condition codes. The stack pointer used is Rl5 in nonsegmented
mode, or RRl4 in segmented mode. If the condition is not satisfied, then the instruc-
tion following the RET instruction is executed. If no condition is specified, the return
is taken regardless of the flag settings.

Flags: No flags affected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles l Instruction Format Cycles l

RET cC
B011110~ 10/7 B011110E:0 13/7

Example: In nonsegmented mode, if the program counter contains %2550, the stack pointer
(RI5) contains %3000, location %3000 contains %1004, and the Z flag is clear, then
the instruction
RET NZ
will leave the value %3002 in the stack pointer and the program counter will contain
%1004 (the address of the next instruction to be executed).

Note 1: The two values correspond to return taken and return not taken.

163
RL
Rotate Left
RL dst, src dst: R
RLB src: 1M

Operation: Do src times: (src = 1 or 2)

tmp -- dst
c -- tmp (msb)
dst(O) .- tmp (msb)
dst (n + 1) -- tmp (n) (for n o to msb - 1)

Word: 0~15 . . . - - - -_ _-----,0 fJ

Byte: 0~7 °IJ
The contents of the destination operand are rotated left one bit position if the source
operand is 1, or two bit positions if the source operand is 2. The most significant bit
(msb) of the destination operand is moved to the bit 0 position and also replaces the
C flag.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: c:Set if the last bit rotated from the most significant bit position was 1; cleared
otherwise
Z~ Set if the result is zero; cleared otherwise
S~ Set if the most significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax 1 Instruction Format2 Cycles3 Instruction Format2 Cycles3

R: RL Rd, #n
RLB Rbd, #n ~ 617
~ 617

Example: If register RH5 contains %88 (l 000 1000), the statement

RLB RH5
will leave the value %11 (00010001) in RH5 and the Carry flag will be set to one.

Note 1: n = source operand.

Note 2: s = 0 for rotation by 1 bit; s = 1 for rotation by 2 bits.
Note 3: The given execuliu!l lirIles dfe fUI !'ui.dliu!l Ly 1 dIlJ 2 lJll~ n::!~fJe(;tiV'ely.

164
 RLC
Rotate Left through Carry
RLC dst, src dst: R
RLCB src: 1M

Operation: Do src times: (src = 1 or 2)

tmp __ c
c ....- dst (msb)
dst (n + 1) ....- dst (n) (for n msb -1 to 0)
dst (0) -- tmp

Word:
L0C-1 15

Byte: L[iH7 o~
The contents of the destination operand with the C flag are rotated left one bit posi-
tion if the source operand is I, or two bit positions if the source operand is 2. The
most significant bit (msb) of the destination operand replaces the C flag and the
previous value of the C flag is moved to the bit 0 position of the destination during
each rotation.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: C: Set if the last bit rotated from the most significant bit position was 1; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntaxl Instruction Format2 Cycles3 Instruction Format2 Cycles3

R: RLC Rd, #n
B110011w~
RLCB Rbd, #n ~ 6/7 6/7

Example: If the Carry flag is clear (= 0) and register RO contains %800F (000000000001111),
the statement
RLC RO,#2
will leave the value %003D (0000000000111101) in RO and clear the Carry flag.

Note 1: n = source operand.

Note 2: s = 0 for rotation by 1 bit; s = 1 for rotation by 2 bits.
Note 3: The given execution times are for rotation by 1 and 2 bits respectively.

165
BLDB
Rotate Left Digit
RLDB link, src src: R
link: R

Operation: tmp (0:3) .,.- link (0:3)

link (0:3) .,.- src (4:7)
src (4:7) .,.- src (0:3)
src (0:3) .,.- tmp (0:3)

o
link I src

The low digit of the link byte register is logically concatenated to the source byte
register. The resulting three-digit quantity is rotated to the left by one BCD digit
(four bits). The lower digit of the source is moved to the upper digit of the source;
the upper digit of the source is moved to the lower digit of the link, and the lower
digit of the link is moved to the lower digit of the source. The upper digit of the link
is unaffected. In multiple-digit BCD arithmetic, this instruction can be used to shift
to the left a string of BCD digits, thus multiplying it by a power of ten. The link
serves to transfer digits between successive bytes of the string. This is analogous to
the use of the Carry flag in multiple precision shifting using the RLC instruction.
The same byte register must not be used as both the source and the link.

Flags: c: Unaffected
Z: Set if the link is zero after the operation; cleared otherwise
S: Undefined
V: Unaffected
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: RLDB RbI, Rbs

B111110~ 9 B111110~ 9

166
Example: If location 100 contains the BCD digits 0,1 (00000001)/ location 101 contains 2,3
(00100011), and location 102 contains 4,5 (01000101)

100 GJ 101 rn 102 rn

the sequence of statements
LD R3,#3 !set loop counter for 3 bytes!
1(6 digits)!
LD R2,#102 !set pointer to low-order digits!
CLRB RHI !zero-filliow-order digit!
LOOP:
LDB RLl,@R2 !get next two digits!
RLDB RHl,RLl !shift digits left one position!
LDB @R2,RLl Jreplace shifted digits!
DEC R2 !advance pointer!
DJNZ R3, LOOP !repeat until counter is zero!
will leave the digits 1,2 (00010010) in location 100, the digits 3,4 (00110100) in loca-
tion 101/ and the digits 5,0 (01010000) in location 102.

100 C2El 101 rn 102 rn

In segmented mode, R2 would be replaced by a register pair.

167
RR
Rotate Right
RR dst, src dst: R
RRB src: 1M

Operation: Do src times: (src = 1 or 2)

tmp -- dst
c -- tmp (0)
dst (msb) -- tmp (0)
dst (n - 1) -- tmp (n) (for n 1 to msb)

Word: [1- 15
~GJ
----,0

Byte:
[,_7 _---,0 ~GJ

The contents of the destination operand are rotated right one bit position if the
source operand is I, or two bit positions if the source operand is 2. The least signifi-
cant bit of the destination operand is moved to the most significant bit (msb) and
also replaces the C flag.
The source operand may be ~mitted from the assembly language statement and thus
defaults to the value 1.

Flags: c: Set if the last bit rotated from the least significant position was l; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Formatl Cycles2 Instruction Format 1 Cycles2

R:
~
RR Rd, #n
RRB Rbd, #n
6/7
~ 6/7

Example: If register RL6 contains %31 (00110001), the statement

RRB RL6
will leave the value %98 (0011000) in RL6 and the Carry flag will be set to one.

Note I: s = 0 for rotation by I bit; s = 1 for rotation by 2 bits.

Note 2: The given execution times are for rotation by 1 and 2 bits respectively.

168
 RRC
Rotate Right through Carry
RRC dst, src dst: R
RRCB src: 1M

Operation: Do src times: (src = 1 or 2)

tmp -- c
c ....- dst (0)
dst (n) -- dst (n + 1) (for n o to msb - 1)
dst (msb) __ tmp

Word: [""'---1
15

-----°r--GJ
Byte: ~_7_ - - - - , 0~

The contents of the destination operand with the C flag are rotated one bit position if
the source operand is 1, or two bit positions if the source operand is 2. The least
significant bit of the destination operand replaces the C flag and the previous value
of the C flag is moved to the most significant bit (msb) position of the destination
during each rotation.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: C: Set if the last bit rotated from the least significant bit position was 1; cleared
otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during rotation; cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format l Cycles2 Instruction Format 1 Cycles2

RRC Rd, #n
RRCB Rbd, #n ~ 6/7
~ 6/7

Example: If the Carry flag is clear ( = 0) and the register RO contains %OODD
(00000000110 III 01), the statement
RRC RO,#2
will leave the value %8037 (10000000110111) in RO and clear the Carry flag.

Note 1: s = 0 for rotation by I bit; s = I for rotation by" 2 bits

Note 2: The given execution times are for roiation by I and 2 bits respectively.

169
RRDB
Rotate Right Digit
RRDB link, src src: R
link: R

Operation: tmp (0:3) ..,.- link (0:3)

link (0:3) ..,.- src (0:3)
src (0:3) ..,.- src (4:7)
src (4:7) +- tmp (0:3)

link
,....--_43
I
I 0I I
7+ 43:
l.....-_......----JI src
L....-__ t
L
- -----1_

The low digit of the link byte register is logically concatenated to the source byte
register. The resulting three-digit quantity is rotated to the right by one BCD digit
(four bits).
The lower digit of the source is moved to the lower digit of the link; the upper digit
of the source is moved to the lower digit of the source and the lower digit of the link
is moved to the upper digit of the source.
The upper digit of the link is unaffected. In multiple-digit BCD arithmetic, this
instruction can be used to shift to the right a string of BCD digits, thus dividing it by
a power of ten. The link serves to transfer digits between successive bytes of the
string. This is analogous to the use of the carry flag in multiple precision shifting
using the RRC instruction.
The same byte register must not be used as both the source and the link.

Flags: c: Unaffected
Z: Set if the link is zero after the operation; cleared otherwise
S: Undefined
V: Unaffected
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: RRDB RbI, Rbs

[£011111001 Rbs I Rbi I 9 I
11 0 1 1 1 1 00 I Rbs I Rbi I 9

170
Example: If location 100 contains the BCD digits 1,2 (00010010), location 101 contains 3,4
(00110100), and location 102 contains 5,6 (01010110)

100 r:T:l 101 r:;T';1 102 r:T':1

L...L:.J ~ L..:.L:.J
the sequence of statements
LD R3,#3 !set loop counter for 3 bytes (6
digits)!
LD R2,#100 !set pointer to high-order digits!
CLRB RHI !zero-fill high-order digit!
LOOP:
LDB RLl,@R2 !get next two digits!
RRDB RHl,RLl !shift digits right one position!
LDB @R2,RLl !replace shifted digits!
INC R2 !advance pointer!
DJNZ R3,LOOP !repeat until counter is zero!
will leave the digits 0,1 (00000001) in location 100, the digits 2,3 (00100011) in loca-
tion 101, and the digits 4,5 (01000101) in location 102. RHI will contain 6, the
remainder from dividing the string by 10.

100 101r:T:1 102

rn L.:...L:J rn
In segmented mode, R2 would be replaced by a register pair.

171
SBC
Subtract with Carry
SBC dst, src dst: R
SBCB src: R

Operation: dst .- dst - src - C

The source operand, along with the setting of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the
source are not affected. Subtraction is performed by adding the two's complement of
the source operand to the destination operand. In multiple precision arithmetic, this
instruction permits the carry ("borrow") from the subtraction of low-order operands
to be subtracted from the subtraction of high-order operands.

Flags: C: Cleared if there is a carry from the most significant bit of the result; set
otherwise, indicating a "borrow"
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs
and the sign of the result is the same as the sign of the source; cleared otherwise
0: SBC-unaffected; SBCB-set
H: SBC-unaffected; SBCB-cleared if there is a carry from the most significant bit
of the low-order four bits of the result; set otherwise, indicating a "borrow"

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
SBC Rd, Rs
5 5
SBCB Rbd, Rbs

Example: Long subtraction may be done with the following instruction sequence, assuming RO,
RI contain one operand and R2, R3 contain the other operand:
SUB Rl,R3 !subtract low-order words!
SBC RO,R2 !subtract carry and high-order words!
If RO contains ~/o0038, RI contains %4000, R2 contains %OOOA and R3 contains
%FOOO, then the above two instructions leave the value %002D in RO and %5000
in RI.

172
 SC
System Call
SC src src: 1M

Operation: Nonsegmented Segmented

SP -- SP - 4 SP -- SP - 6
@SP -- PS @SP ...- PS
SP -- SP - 2 SP -- SP - 2
@SP __ instruction @SP -- instruction
PS -- System Call PS PS -- System Call PS

This instruction is used for controlled access to operating system software in a man-
ner similar to a trap or interrupt. The current program status (PS) is pushed on the
system processor stack, and then the instruction itself, which includes the source
operand (an 8-bit value) is pushed. The PS includes the Flag and Control Word
(FCW), and the updated program counter (PC). (The updated program counter
value used is the address of the first instruction following the SC instruction.)
The system stack pointer is always used (R15 in nonsegmented CPUs, or RR14 in
segmented CPUs), regardless of whether system or normal mode is in effect. The
new PS is then loaded from the Program Status block associated with the System
Call trap (see section 6.2.4), and control is passed to the procedure whose address is
the program counter value contained in the new PS. This procedure may inspect the
source operand on the top of the stack to determine the particular software service
desired.
The following figure illustrates the format of the saved program status in the system
stack:
NONSEGMENTED SEGMENTED

LOW LOW
ADDRESS ADDRESS
SPAFTER_ IDENTIFIER
STACK POINTER
AFTER TRAP IDENTIFIER FCW
OR INTERRUPT
FCW PC SEGMENT

PC PC OFFSET
STACK POINTER f-------
BEFORE TRAP SP BEFORE_
OR INTERRUPT

---1 WORD--
HIGH HIGH
ADDRESS ADDRESS

The segmented 28000s always execute the segmented mode of the System Call in-
struction, regardless of the current mode, and set the Segmentation Mode bit (SEG) to
segmented mode ( = 1) at the start of the SC instruction execution. All 28000s set
the SystemlNormal Mode bit (SIN) to system mode ( = 1) at the start of the SC in-
struction execution. The status pins reflect the setting of these control bits during the
execution of the SC instruction. However, the setting of SEG and SIN does not affect
the value of these bits in the old FCW pushed onto the stack. The new value of the
FCW is not effective until the next instruction, so that the status pins will not be
affected by the new control bits until after the SC instruction execution is completed.
The "src field" in the instruction format encoding contains the source operand. The
"src field" values range from 0 to 255 corresponding to the source values 0 to 255.

Flags: Flags loaded from Program Status Area

173
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

1M: SC #src
I 01111111 I src I 33 I 01111111 I src
I 39

Example: In the nonsegmented Z80Q2, if the contents of the program counter are % 1000, the
contents of the system stack pointer (HIS) are %3006, and the Program Counter and
FCW values associated with the System Call trap in the Program Status Area are
%2000 and %5800, respectively, the instruction
SC #3 !system call, request code = 3!
causes the system stack pointer to be decremented to %3000. Location %3000 con-
tains %7F03 (the SC instruction). Location %3002 contains the old FCW, and loca-
tion %3004 contains %1002 (the address of the instruction following the SC instruc-
tion). System mode is in effect, and the Program Counter contains the value %2000,
which is the start of a System Call trap handler, and the FCW contains %5800.

174
 SDA
Shift Dynamic Arithmetic
SOA dst, src dst: R
SOAB src: R
SOAL

Operation: Right (src negative)

Do - src times:
c +- dst (0)
dst (n) +- dst (n + 1) (for n 0 to msb - 1)
dst (msb) +- dst (msb)
Left (src positive)
Do src times:
c +- dst (msb)
dst (n + 1) +- dst (n) (for n = msb - 1 to 0)
dst (0) +- 0
Right Left
7 0 7 0

l--0 &-1 1_
Byte:
c9 0

r-
15 0 15 0

Word:
CS=I ~ &-1 o

15 0 15 0

~ ~~
Rn Rn
Long:

Rn + 1

n=O,2,4, ... ,14

15

Rn+ 1

n=O,2,4, ... ,14

20
The destination operand is shifted arithmetically left or right by the number of bit
positions specified by the contents of the source operand, a word register.
The shift count ranges from -8 to +8 for SDAB, from -16 to + 16 for SDA and from
-32 to + 32 for SDAL. If the value is outside the specified range, the operation is
undefined. The source operand is represented as a 16-bit two's complement value.
Positive values specify a left shift, while negative values specify a right shift. A shift
of zero positions does not affect the destination; however, the flags are set according
to the destination value. The sign bit is replicated in shifts to the right, and the C
flag is loaded from bit 0 of the destination. The least significant bit is filled with 0 in
shifts to the left, and the C flag is loaded from the most significant bit (msb) of the
destination. The setting of the carry bit is undefined for zero shift.

Flags: c: Set if the last bit shifted from the destination was 1, undefined for zero shift;
cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during shifting; cleared otherwise
0: Unaffected
H: Unaffected

175
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language 1 - - - - - - - - - - - - , . - - - - + - - - - - - - - - - - . , . . - - -
Mode Syntax Instruction Format Cycles 1 Instruction Format Cycles 1

R: SDA Rd, Rs
15 +3n 15+3n

SDAB Rbd, Rs
15 +3n 15+3n

SDAL RRd, Rs
15+3n 15+3n

Example: If register R5 contains %C705 (11000 III 00000 101) and register R1 contains - 2
(%FFFE or 1111111111111110), the statement
SDA R5,Rl
performs an arithmetic right shift of two bit positions, leaves the value %FICI
(1111000 III 00000 1) in R5, and clears the Carry flag.

Note I: n = number of bit positIOns; the execution time for n = 0 is the same as for n = 1.

176
 SDL
Shift Dynamic Logical
SOL dst, src dst: R
SOLB src: R
SOLL

Operation: Right (src negative)

Do - src times
c +- dst (0)
dst (n) +- dst (n + 1) (for n 0 to msb - 1)
dst (msb) +- 0
Left (src positive)
Do src times
c +- dst (msb)
dst (n + 1) +- dst (n) (for n msb - 1 to 0)
dst (0) +-

Right Left

Byte: o-r ----'l-{~ 0-{'---- I-- o

Word: o-I_ 5

l-G
..... 0~_5 1-o
15
.-1 '"
0

1~ '"
1~5------------.,;o

o~o
L-r-----Rn-+-1-----~ W..;..5-----R-n-+-1------i~
Long:

n=0,2A, ... ,14 n=0,2,4, ... ,14

The destination operand is shifted logically left or right by the number of bit posi-
tions specified by the contents of the source operand, a word register. The shift
count ranges from - 8 to + 8 for SDLB, from - 16 to + 16 for SDL and from - 32 to
+ 32 for SDLL. If the value is outside the specified range, the operation is
undefined. The source operand is represented as a 16-bit two's complement value.
Positive values specify a left shift, while negative values specify a right shift. A shift
of zero positions does not affect the destination; however, the flags are set according
to the destination value. The most significant bit (msb) is filled with 0 in shifts to the
right, and the C flag is loaded from bit 0 of the destination. The least significant bit
is filled with 0 in shifts to the left, and the C flag is loaded from the most significant
bit of the destination. The setting of the carry bit is undefined for zero shift.

Flags: c: Set if the last bit shifted from the destination was I, undefined for zero shift;
cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
V: Undefined '
0: Unaffected
H: Unaffected

177
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language 1 - - - - - - - - - - - - . . . . . . - - - - + - - - - - - - - - - - - . - - - -
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: SDL Rd, Rs
15+3n

SDLB Rbd, Rs
15+3n

SDLL RRd, Rs
15+3n

Example: If register RL5 contains %B3 (0110011) and register R1 contains 4

(0000000000000100), the statement
SDLB RL5,R1
performs a logical left shift of four bit positions, leaves the value %30 (00110000) in
RL5, and sets the Carry flag.

Note I: n = number of bit positions; the execution time for n = 0 is the same as lor n

178
 SET
Set Bit
SET dst, src dst: R, IR, DA, X
SETB src: 1M
or
dst: R
src: R

Operation: dst(src) ...- 1

Sets the specified bit within the destination operand without affecting any other bits
in the destination. The source (the bit number) can be specified as either an immedf-
ate value (Static), or as a word register which contains the value (Dynamic). In the
second case, the destination operand must be a register, and the source operand
must be RO through R7 for SETB, or RO through R15 for SET. The bit number is a
value from 0 to 7 for SETB or 0 to 15 for SET, with 0 indicating the least significant
bit.
Only the lower four bits of the source operand are used to specify the bit number for
SET, while only the lower three bits of the source operand are used with SETB.
When thE) source operand is an immediate value, the "src field" in the instruction
format encoding contains the bit number in the lowest four bits for SET, or the
lowest three bits for SETB.

Flags: No flags affected

Set Bit Static

Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
~ ~
SET Rd, #b
4 4
SETB Rbd, #b

IR:
~ ~
SET Q' Rd 1 , #b
11 11
SETB Q, Rd i , #b

DA: SET address, #b

SETB address, #b
101110010lwl00001 b I 13 55
01110010[w100001 b
14
I address I oI segment I offset

01110010lwl00001 b

5L 1 I segment I 0000 0000 16

offset

X: SET addr(Rd), #b
I0 1 110 0 10 Iw I Rd,< 0 I
SETB addr(Rd), #b
b I 14
55011100101w1Rd,<01 b
14
I address I oI segment I offset

01110010IwIRd,<°1 b
5L 1 I segment I0000 0000 17
offset

179
Set Bit Dynamic
Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: SET Rd, Rs
I0 0 110 0 1 0 Iw I 0 0 0 0 1 Rs I I0 0 110 0 10 Iw I0 0 0 0 I Rs I
SETB Rbd, Rs 2 10 10
I 0 0 0 0 I Rd I 0 0 0 0 0 0 0 0 I I 0 0 0 0 1 Rd I 0 0 0 0 0 0 0 01

Example: If register RL3 contains %B2 (10110010) and register R2 contains the value 6, the
instruction
SETB RL3, R2
will leave the value %F2 (1110010) in RL3.

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: Word registers 0-7 only.

180
 SETFLG
Set Flag
SETFLG flag Flag: C, Z, S, P, V

Operation: FLAGS (4:7) .- FLAGS (4:7) OR instruction (4:7)

Any combination of the C, Z, S, P or V flags are set to one if the corresponding bits
in the instruction are one. If the bit in the instruction corresponding to a flag is zero,
the flag will not be affected. All other bits in the FLAGS register are unaffected.
Note that the P and V flags are represented by the same bit.
There may be one, two, three, or four operands in the assembly language statement,
in any order.

Flags: c: Set if specified; unaffected otherwise

Z: Set if specified; unaffected otherwise
S: Set if specified; unaffected otherwise
P/V: Set if specified; unaffected otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Assembler Language
Syntax Instruction Format Cycles Instruction Format Cycles

SETFLG flags
110001101 ICZSPIVI 0001 I 7 110001101 \CZSPIVI 0001 I 7

Example: If the C, Z, and S flags are all clear (0), and the P flag is set (1), the statement
SETFLG C
will leave the C and P flags set (1), and the Z and S flags cleared (0).

181
SLA
Shift Left Arithmetic
SLA dst, src dst: R
SLAB src: 1M
SLAL

Operation: Do src times:

c .... dst (msb)
dst (n + 1) .... dst (n) (for n msb - 1 to 0)
dst (0) .... 0

7 0

Byte: 0-i~ I-o

15 0

Word: 0-i~ I-o

15 0

~~,=====R="====='o~l:J
Long:

Y,. . R_"_+1 I--o

n = 0, 2, 4, ... , 14

The destination operand is shifted arithmetically left the number of bit positions
specified by the source operand. For SLAB, the source is in the range 0 to 8; for
SLA, the source is in the range 0 to 16; for SLAL, the source is in the range 0 to 32.
The least significant bit of the destination is filled with 0, and the C flag is loaded
from the sign bit of the destination. The operation is the equivalent of a multiplica-
tion of the destination by a power of two with overflow indication. A shift of zero
positions does not affect the destination; however, the flags are set according to the
destination value with the C flag undefined.
The src held is encoded in the instruction format as the 8- or 16-bit two's comple-
ment positive value of the source operand. For each operand size, the operation is
undefined if the source operand is not in the specified range.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: c: Set if the last bit shifted from the destination was 1, undefined for zero shift;
cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the sign of the destination changed
during shifting; cleared otherwise
D: Unaffected
H: Unaffected

182
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language 1 - - - - - - - - - - - - , - - - - - + - - - - - - - - - - - - - - . - - -
Mode Syntax Instruction Format Cycles l Instruction Format Cycles l

R: SLA Rd, #b
13+3b 13+3b

SLAB Rbd, #b
13+3b 13+3b

SLAL RRd, #b
13 +3b 13+3b

Example: If register pair RR2 contains % 1234ABCD , the statement

SLAL RR2/#8
will leave the value %34ABCDOO in RR2 and clear the Carry flag.

Note I: b = number of bit positions; the execution time for b = 0 is the same as for b = I.

183
SLL
Shift Left Logical
SLL dst, src dst: R
SLLB src: 1M
SLLL

Operation: Do src times:

c +- dst (msb)
dst (n + 1) +- dst (n) (for n msb - 1 to 0)
dst (0) +- 0

7 0
Byte:
&--1 1_ 0

15 0

Word: &--1 /---0

15 0

0~

2.
Long: Rn

Lr Rn+ 1

n = 0, 2, 4, ... , 14
The destination operand is shifted logically left by the number of bit positions
specified by the source operand. For SLLB, the source is in the range 0 to 8; for
SLL, the source is in the range 0 to 16; for SLLL, the source is in the range 0 to 32.
The least significant bit of the destination is filled with 0, and the C flag is loaded
from the most significant bit (msb) of the destination. This instruction performs an
unsigned multiplication of the destination by a power of two. A shift of zero positions
does not affect the destination; however, the flags are set according to the destina-
tion value. The setting of the carry bit is undefined for zero shift.
The src field is encoded in the instruction format as the 8- or 16-bit positive value of
the source operand. For each operand size, the operation is undefined if the source
operand is not in the specified range.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: c: Set if the last bit shifted from the destination was I, undefined for zero shift;
cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
V: Undefined
D: Unaffected
H: Unaffected

184
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language t - - - - - - - - - - - - . - - - - + - - - - - - - - - - - . . . . . , . . . - - -
Mode Syntax Instruction Format Cycles I Instruction Format Cyclesl

R: SLL Rd, #b
13+3b 13+3b

SLLB Rbd, #b
13+3b 13+3b

SLLL RRd, #b
13+3b 13+3b

Example: 1£ register R3 contains %4321 (01000011 001 0000 1), the statement
SLL R3,#1
will leave the value %8642 (10000 11 00 10000 10) in R3 and clear the carry flag.

Note I: b = number of bit positIons; the execution lIme for b = 0 is the same as for b = I.

185
SRA
Shift Right Arithmetic
SRA dst, src dst: R
SRAB src: 1M
SRAL

Operation: Do src times:

c -- dst (0)
dst (n) -- dst (n + 1)(for n o to msb - 1)
dst (msb) -- dst (msb)

Byte:

15

Word: CS....l....-[ ~0

15

_~
Long:

QI_"
u.. . r-~
I _R_n

R_n+_1

n = 0, 2, 4, ... , 14

The destination operand is shifted arithmetically right by the number of bit positions
specified by the source operand. For SRAB, the source is in the range 1 to 8; for
SRA, the source is in the range 1 to 16; for SRAL, the source is in the range 1 to 32.
A right shift of zero for SRA is not possible. The most significant bit (msb) of the
destination is replicated, and the C flag is loaded from bit 0 of the destination, this
instruction performs a signed division of the destination by a power of two.
The src field is encoded in the instruction format as the 8- or 16-bit two's comple-
ment negative of the source operand. For each operand size, the operation is
undefined if the source operand is not in the specified range.
The source operand may be omitted from the assembly language statement and thus
defaults to the value 1.

Flags: c: Set if the last bit shifted from the destination was 1; cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Cleared
D: Unaffected
H: Unaffected

186
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language 1 - - - - - - - - - - - - , - - - - + - - - - - - - - - - - - , - - - -
Mode Syntax Instruction Format Cyclesl Instruction Format Cycles l

R: SRA Rd, #b
13+3b 13+3b

SRAB Rbd, #b
13+3b 13+3b

SRAL RRd, #b
13+3b 13+3b

Example: If register RH6 contains 0/03B (00111011), the statement

SRAB RH6,#2
will leave the value O/OOE (00001110) in RH6 and set the carry flag.

Note 1: b = number of bit positions; the execution time for b = 0 is the same as for b = 1.

187
SRL
Shift Right Logical
SRL dst, src dst: R
SRLB src: 1M
SRLL

Operation: Do src times:

c .... dst (0)
dst (n) .... dst (n + 1)(for n o to msb - 1)
dst (msb) .... 0

Byte:

15
Word: 0-1'---------~~
15
Long:
.-: '----_Rn --1
Lj15
_ _ _ _ _ _ _ _L--r;l Rn+1 r~L::.J

n = 0/ 2, 4, ... , 14

The destination operand is shifted logically right by the number of bit positions
specified by the source operand. For SRLB, the source operand is in the range 1 to
8; for SRL, the source is in the range 1 to 16; for SRLL, the source is in the range 1
to 32. A right shift of zero for SRL is not possible. The most significant bit (msb) of
the destination is filled with 0, and the C flag is loaded from bit 0 of the destination.
This instruction performs an unsigned division of the destination by a power of two.
The src field is encoded in the instruction format as the 8- or l6-bit negative value of
the source operand in two's complement notation. For each operand size, the opera-
tion is undefined if the source operand is not in the range specified above.
The source operand may be omitted from the assembly language statement and thus
defaults to the value of 1.

Flags: c: Set if the last bit shifted from the destination was l; cleared otherwise
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is one; cleared otherwise
V: Undefined
D: Unaffected
H: Unaffected

188
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language I------------~--+-----------__r---
Mode Syntax Instruction Format Cyclesl Instruction Format Cycles l

R: SRL Rd, #b
13+3b 13+3b

SRLB Rbd, #b
13+3b 13+3b

SRLL RRd, #b
13+3b 13+3b

Example: If register RO contains % 1111 (0001000100010001), the statement

SRL RO,#6
will leave the value %0044 (0000000001000100) in RO and clear the carry flag.

Note I: b = number of bit positions; the execution time for b = 0 is the same as for b = I.

189
SUB
Subtract
SUB dst, src dst: R
SUBB src: R, 1M, IR/ DA, X
SUBL

Operation: dst ....- dst - src

The source operand is subtracted from the destination operand and the result is
stored in the destination. The contents of the source are not affected. Subtraction is
performed by adding the two/ s complement of the source operand to the destination
operand.

Flags: c: Cleared if there is a carry from the most significant bit; set otherwise, indicating
a "borrow"
Z: Set if the result is zero; cleared otherwise
S: Set if the result is negative; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if the operands were of opposite signs
and the sign of the result is the same as the sign of the source; cleared otherwise
D: SUB, SUBL-unaffected; SUBB-set
H: SUB, SUBL-unaffected; SUBB-cleared if there is a carry from the most
significant bit of the low-order four bits of the result; set otherwise, indicating a
"borrow"

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
BOOO01Iw~ ~
SUB Rd, Rs 4
4
SUBB Rbd, Rbs

SUEL RRd, RRs R010010~ I 8 B0100101~ 8

1M: SUB Rd, #data 00[000010100001 Rd 001000010100001 Rd

7 7
data data

SUBB Rbd, #data I

o0 000011 I 0 0 0 0 I Rbd I
o0 000011 I 0 0 0 0 I Rbd
7 7
data I data data I data
SUBL RRd, #data 001 01 0010 I 0000 I RRd I
o 0 0 100 10 I 0 0 0 0 I RRd
31 data (high) 16 14 31 data (high) 16 14
15 data (low) 0 15 data (low) 0

IR: SUB Rd, @Rsl

SUBB Rbd, @Rsl
[00 10000 1j wi Rs;< 0 I Rd
I 7 BOOO01EI RRhO I Rd
I 7

SUBL RRd, lftRsl I0 0 I 0 1 0 0 1 0 I Rs;< 0 I RRd I 14 B 010010 IRRS;<ol RRd I 14

190
 Source Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

DA: SUB Rd, address

SUBB Rbd, address
101[00001I w! 0000 1 Rd I 9
o 1 i 0 0 0 0 11 w 10 0 0 0 i Rd I
10
I 55 o I I
address
I segment I offset

o 1 I0 0 0 0 1 I W I 0 0 0 0 1 Rd

5L 1I segment i 00000000 12
offset

SUBL RRd, address 1011 01 001 0 I0000 I RRd I o1 I 0 1 00 1 0 I 0000 1 RRd I

I address
I
15 55 o I segment I offset I 16

o 11 0 1 001 0 I 0000 [ RRd

5L 1I segment I 0000 0000 18

offset

X: SUB Rd, addr(Rs) o 1 10 0 0 0 11 W 1 Rs * 0 I Rd I

SUBB Rbd, addr(Rs)
101 1000 01 1W 1 Rs *0 I Rd I 10 55 10
I address I o I segment I offset I
o 1 10 0 0 0 1 ! W [ Rs '" 0 I Rd
5L 1I segment I 0000 0000 13
offset

SUBL RRD, addr(Rs)

I 0 1 I 0 1 0 0 1 0 I Rs '" 0 1 RRd I 16 55
o1 I 0 1 0 0 1 0 I Rs * 0 1 RRd I 16
I address I 01 segment i offset I
o11 0 1 0 0 1 0 I Rs '" 0 I RRd

5L 1I segment I 0000 0000 19

offset

Example: If register RO contains %0344, the statement

SUB RO,#%AA
will leave the value %029A in RO.

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

191
TCC
Test Condition Code
Tee cc, dst dst: R
TeCB

Operation: if cc is satisfied then

dst (0) -- 1

This instruction is used to create a Boolean data value based on the flags set by a
previous operation. The flags in the FCW are tested to see if the condition specified
by "ce" is satisfied. If the condition is satisfied, then the least significant bit of the
destination is set. If the condition is not satisfied, bit zero of the destination is not
cleared but retains its previous value. All other bits in the destination are unaffected
by this instruction.

Flags: No flags affected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: Tee CC, Rd
TeeB CC, Rbd ~ 5
~ 5

Example: If register Rl contains 0/ and the Z flag is set, the statement

TCC EQ/Rl
will leave the value 1 in Rl.

192
 TEST
Test
TEST dst dst: R, IR, DA, X
TESTB
TESTL

Operation: dst OR 0

The destination operand is tested (logically ORed with zero), and the Z, Sand P
flags are set to reflect the attributes of the result. The flags may then be used for
logical conditional jumps. The contents of the destination are not affected.

Flags: c: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
P: TEST-unaffected; TESTL-undefined; TESTB-set if parity of the result is even;
cleared otherwise
D: Unaffected
H: Unaffected

Destination Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: TEST Rd
TESTB Rbd
[10100110~ 7 ~ 7

TESTL RRd
~10111001~ 13 ~1011100~ 13

IR: TEST illRdl

TESTB iZlRdl ~ 8 Eloo 11 0BRRd*ol 01 00 I 8

TESTL illRdi
~011100~ 13 El I
0 1 1 1 0 0 RRd *0 11 0 0 0 I 13

DA: TEST address

101100110lWl00ool01001 01100110Iwi 00001 0100
TESTB address
I address I
11 55
oI segment 1 offset
12

0110011 01 W I 0000 I 01 00
5L 1 I segment I 0000 0000 14
address

TESTL address
101101110010000110001 0110111001000011000

I address
I
16 55
oI segment 1 offset
17

0110111001000011000

5L 1 I segment I 0000 0000 19

offset

193
Destination Nonsegmented Mode Segmented Mode
Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

X: TEST addr(Rd)
10110011 olwl Rd,*O 101001 o1 10 0 1 1 0 IwI Rd '* 0 I0 1 0 0
TESTE addr(Rd) 12 55 12
I address I oI segment I offset
o1 I0 0 1 10 1wI Rd '" 0 I 0 1 0 0
5L 1 I segment I 0000 0000 15
offset

I0 1 1 0 1 1 1 0 0 I Rd '" 0 11 0 0 0 I 17 55
o1 I 0 1 1 1 0 0 I RM 0 11 0 0 0 17
I address I oI segment 1 offset
011 011100 I Rd,*O 11 000
5L 1 I segment I0000 0000 20
offset

Example: If register R5 contains %FFFF (1111111111111111), the statement

TEST R5
will set the S flag, clear the Z flag, and leave the other flags unaffected.

NC:t": I: '/v'ord register in ~on.segmented mooe, reglS!er paIr segmE-:::eG mode.

194
 TRDB
Translate and Decrement
TRDB dst, src, r dst: IR
src: IR
Operation: dst +- src[ dst]
AUTODECREMENT dst by 1
r+-r-l

This instruction is used to translate a string of bytes from one code to another code.
The contents of the location addressed by the destination register (the "target byte")
are used as an index into a table of translation values whose lowest address is con-
tained in the source register. The index is computed by adding the target byte to the
address contained in the source register. The addition is performed following the
rule for address arithmetic, with the target byte treated as an unsigned 8-bit value
extended with high-order zeros. The sum is used as the address of an 8-bit transla-
tion value within the table which replaces the original contents of the location
addressed by the destination register.
The destination register is then decremented by one, thus moving the pointer to the
previous element in the string. The word register specified by "r" (used as a
counter) is then decremented by one. The original contents of register RHI are lost
and are replaced by an undefined value. RO and Rl in nonsegmented mode, or RRO in
segmented mode, must not be used as a source or destination pointer, and Rl should
not be used as a counter. The source, destination, and counter registers must be
separate and non-overlapping registers.
Because the 8-bit target byte is added to the source register to obtain the address of
a translation value, the table may contain 256 bytes. A smaller table size may be
used where it is known that not all possible 8-bit target byte values will occur. The
source register is unchanged.

Flags: c: Unaffected
z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: TRDB a? Rd 1 , a, Rs:, r

110 1 1 1 1 0 0 0 I Rd '" 0 110 0 0 I 1101111000 IRRd",0!1000 I
25 25
10000 1 r I Rs '" 0 I 0 0 0 0 I 1 0000 1 r I
!RRS '" 0 0000 I

Example: In nonsegmented mode, if register R6 contains %4001, the byte at location %4001
contains 3, register R9 contains % 1000, the byte at location % 1003 contains %AA,
and register R12 contains 2, the instruction
TRDB @R6, @R9, R12
will leave the value %AA in location %4001, the value %4000 in R6, and the value
1 in R12. R9 will not be affected. The V flag will be cleared. RHI will be set to an
undefined value. In segmented mode, R6 and R9 would be replaced with
register pairs.

Note I: Word regisrer In nonsegmenred mode, reglsrer pair in segmented mode.

195
TRDRB
Translate, Decrement and Repeat
TRDRB dst, src, r dst: IR
src: IR

Operation: dst -- src [dst]

AUTODECREMENT dst by 1
r -- r - 1
repeat until r = a

This instruction is used to translate a string of bytes from one code to another code.
The contents of the location addressed by the destination register (the "target byte")
are used as an index into a table of translation values whose lowest address is con-
tained in the source register. The index is computed by adding the target byte to the
address contained in the source register. The addition is performed following the
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value
extended with high-order zeros. The sum is used as the address of an 8-bit transla-
tion value within the table that replaces the original contents of the location
addressed by the destination register.
The destination register is then decremented by one, thus moving the pointer to the
previous element in the string. The word register specified by "r" (used as a
counter) is then decremented by one. The entire operation is repeated until the
result of decrementing r is zero. This instruction can translate from 1 to 65536 bytes.
The original contents of register RH 1 are lost and are replaced by an undefined
value. The source register is unchanged. The source, destination, and counter
registers must be separate and non-overlapping registers.
Because the 8-bit target byte is added to the source register to obtain the address of
a translation value, the table may contain 256 bytes. A smaller table size may be
used where it is known that not all possible 8-bit target byte values will occur.
This instruction can be interrupted after each execution of the basic operation. The
program counter of the start of this instruction is saved before the mterrupt request
is accepted, so the instruction can be properly resumed. Seven cycles should be
added to this instruction's execution time for each interrupt request that is accepted.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: TRDRB @Rd 1, @RS1, r 11011110001Rd*0111001 1101 1110001RRd*0111001

11+14n 11 +14n
looooi r
IRs * °I°°°°I 100001 r IRRs*O! 0000 I

196
Example: In nonsegmented mode, if register R6 contains %4002, the bytes at locations %4000
through %4002 contain the values %00, %40, %80, respectively, register R9 con-
tains %1000, the translation table from location %1000 through %lOFF contains 0,
1, 2, ... , %7F, 0, 1, 2, ... , % 7F (the second zero is located at % 1080), and register
R12 contains 3, the instruction
TRDRB @R6, @R9, R12
will leave the values %00, %40, %00 in byte locations %4000 through %4002,
respectively. Register R6 will contain %3FFF, and R12 will contain O. R9 will not be
affected. The V flag will be set, and the contents of RHI will be replaced by an
undefined value. In segmented mode, R6 and R9 would be replaced by register
pairs.

BEFORE
%1000 00000000
%4000 %1001 00000001
%4001 %1002 00000010

···
%4002

AFTER %107F o 11 1 1 1 1 1
%1080 00000000
%4000 %1081 00000001
%4001 %1082 00000010

···
%4002

%10FF o1 1 1 1 1 1 1

Note 1: Word register in nonsegmenied mode, register pair in segmented mode.

Note 2: n = number of data elements translated.

197
TRIB
Translate and Increment
TRIB dst, src r I dst: IR
src: IR

Operation: dst .... src[ dst]

AUTOINCREMENT dst by 1
r .... r - 1

This instruction is used to translate a string of bytes from one code to another code.
The contents of the location addressed by the destination register (the "target byte")
are used as an index into a table of translation values whose lowest address is con-
tained in the source register. The index is computed by adding the target byte to the
address contained in the source register. The addition is performed following the
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value
extended with high-order zeros. The sum is used as the address of an 8-bit transla-
tion value within the table which replaces the original contents of the location
addressed by the destination register. The destination register is then incremented
by one, thus moving the pointer to the next element in the string. The word register
specified by "r" (used as a counter) is then decremented by one. The original con-
tents of register RHI are lost and are replaced by an undefined value. The source
register is unchanged. The source, destination, and counter registers must be
separate and non-overlapping registers.
Because the 8-bit target byte is added to the source register to obtain the address of
a translation value, the table may contain 256 bytes. A smaller table size may be
used where it is known that not all possible 8-bit target byte values will occur.

Flags: c: Unaffected
Z: Undefined
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

TRIB @Rd 1 • @Rsl, r

11011110001Rd*0100001 110111 1 0001RRd*0100001
25 25
10000 1 r /Rs*%oool 10000 1
r IRRS *°I0 °0 0 I

198
Example: This instruction can be used in a "loop" of instructions which translate a string of
data from one code to any other desired code, but an intermediate operation on
each data element is required. The following sequence translates a string of 1000
bytes to the same string of bytes, with all ASCII "control characters" (values less
than 32, see Appendix C) translated to the "blank" character (value = 32). A test,
however, is made for the special character "return" (value = 13) which terminates
the loop. The translation table contains 256 bytes. The first 33 (0-32) entries all con-
tain the value 32, and all other entries contain their own index in the table, counting
from zero. This example assumes nonsegmented mode. In segmented mode, R4 and
R5 would be replaced by register pairs.
LD R3, #1000 !initialize counter!
LDA R4, STRING !load start addresses!
LDA R5, TABLE
LOOP:
CPB @R4, #13 !check for return character!
JR EO, DONE !exit loop if found!
TRIB @R4, @R5, R3 !translate next byte!
JR NOV, LOOP !repeat until counter O!
DONE:

TABLE +0 00100000
TABLE + 1 00100000
TABLE + 2 00100000

·
TABLE + 32
·
00100000
TABLE + 33 00100001
TABLE + 34 00100010

···
TABLE + 255 11111111

Note I: Word register in nonsegmented mode, register pair in segmented mode.

199
TRIRB
Translate, Increment and Repeat
TRIRB dst src, r
I dst: IR
src: IR

Operation: dst +- src[ dst]

AUTOINCREMENT dst by 1
r +- r - 1
repeat until r = a

This instruction is used to translate a string of bytes from one code to another code.
The contents of the location addressed by the destination register (the "target byte")
are used as an index into a table of translation values whose lowest address is con-
tained in the source register. The index is computed by adding the target byte to the
address contained in the source register. The addition is performed following the
rules for address arithmetic, with the target byte treated as an unsigned 8-bit value
~ •• +~~....l~....l uTah h;,....h_'"'..M"".. 7""..("'\'" Th~ !'mm i!=l 1l!=lP.c1 as the address of an 8-bit transla-
Example: The following sequence of instructions can be used to translate a string of 80 bytes
from one code to another. The pointers to the string and the translation table are set,
the number of bytes to translate is set, and then the translation is accomplished.
After executing the last instruction, the V flag is set and the contents of RHI are lost.
The example assumes nonsegmented mode. In segmented mode, R4 and R5 would
be replaced by register pairs.
LDA R4, STRING
LDA R5, TABLE
LD R3, #80
TRIRB @R4, @R5, R3

Note 1: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number of data elements translated.

201
THTDB
Translate, Test and Decrement
TRTDB srcl, src2, r src 1: IR
src 2: IR

Operation: RH 1 __ src2[srcl ]
AUTODECREMENT srcl by 1
r--r-l

This instruction is used to scan a string of bytes testing for bytes with special
meaning. The contents of the location addressed by the first source register (the
"target byte") are used as an index into a table of translation values whose lowest
address is contained in the second source register. The index is computed by adding
the target byte to the address contained in the second source register. The addition
is performed following the rules for address arithmetic, with the target byte treated
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the
address of an 8-bit value within the table which is loaded into register RHl. The Z
flag is set if the value loaded into RHl is zero; otherwise the Z flag is cleared. The
contents of the locations addressed by the source registers are not affected. The first
source register is then decremented by one, thus moving the pointer to the previous
element in the string. The word register specified by "r" (used as a counter) is then
decremented by one. The second source register is unaffected. The source and
counter registers must be separate and non-overlapping registers.
Because the 8-bit target byte is added to the second source register to obtain the
address of a translation value, the table may contain 256 bytes. A smaller table size
may be used where it is known that not all possible 8-bit target byte values will
occur.

Flags: c: Unaffected
Z: Set if the translation value loaded into RH 1 is zero; cleared otherwise
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: TRTDB @Rsll, @Rs2 1, r

I
11 0 11 1 1 000 IRS1 *- ~ 1010
25
110 1 1 1 0 0 0 IRRS1*- ~ 1 0 1 0 1
1
25
10000 1 r /RS2 *- 01 00001 10000 r IRRSU~ 0000 I
1

Example: In nonsegmented mode, if register R6 contains %4001, the byte at location %4001
contains 3, register R9 contains %1000, the byte at location %1003 contains %AA,
and register R12 contains 2, the instruction
TRTDB @R6, @R9, R12
Will leave the value %AA in RH1, the value %4000 in R6, and the value 1 in R12.
Location %4001 and register R9 will not be affected. The Z and V flags will be
cleared. In segmented mode, register pairs must be used instead of R6 and R9.

Note Word register in tlonsegmented mode, register pair in segmented mode.

202
 TRTDRB
Translate, Test, Decrement and Repeat
TRTDRB srcl, src2, r srcl: IR
src2: IR

Operation: RHI +- src 2[srcl]

AUTODECREMENT srcl by 1
r +- r - 1
repeat until RH 1 =1= 0 or r = 0

This instruction is used to scan a string of bytes testing for bytes with special
meaning. The contents of the location addressed by the first source register (the
"target byte") are used as an index into a table of translation values whose lowest
address is contained in the second source register. The index is computed by adding
the target byte to the address contained in the second source register. The addition
is performed following the rules for address arithmetic, with the target byte treated
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the
address of an 8-bit value within the table which is loaded into register RHl. The Z
flag is set if the value loaded into RHI is zero; otherwise the Z flag is cleared. The
contents of the locations addressed by the source registers are not affected. The first
source register is then decremented by one, thus moving the pointer to the previous
element in the string. The word register specified by "r" (used as a counter) is then
decremented by one. The entire operation is repeated until either the Z flag is clear,
indicating that a non-zero translation value was loaded into RHl, or until the result
of decrementing r is zero. This instruction can translate and test from I to
65536 bytes. The source and counter registers must be separate and non-overlapping
registers.
Target byte values which have corresponding zero translation-table entry values are
to be scanned over, while target byte values which have corresponding non-zero
translation-table entry values are to be detected. Because the 8-bit target byte is
added to the second source register to obtain the address of a translation value, the
table may contain 256 bytes. A smaller table size may be used where it is known that
not all possible 8-bit target byte values will occur.
This instruction can be interrupted after each execution of the basic operation. The
program counter of the start of this instruction is saved before the interrupt request
is accepted so that the instruction can be properly resumed. Seven cycles should be
added to this instruction's execution time for each interrupt request that is accepted.

Flags: c: Unaffected
Z: Set if the translation value loaded into RHI is zero; cleared otherwise
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: TRTDRB@Rsl] ,@Rs2] ,r

110 11 1 1 0 0 0 IRS1 * 0)1 1 1 0 1 1101111000IRRs1*0!11101
11+14n 11 +14n
100 0 0 I r !RS2 * 011 1 10 I 1 0000 1 r IRRsuol1 1 1 0 I

203
Example: In nonsegmented mode, if register R6 contains %4002, the bytes at locations %4000
through %4002 contain the values %00, %40, %80, repectively, register R9 contains
% 1000, the translation table from location % 1000 through % lOFF contains 0, 1,
2, """, %7F, 0, 1, 2, """, %7F (the second zero is located at %1080), and register
Rl2 contains 3, the instruction
TRTDRB @R6, @R9, R12
will leave the value %40 in RHI (which was loaded from location %1040). Register
R6 will contain %4000, and R12 will contain 1. R9 will not be affected. The Z and V
flags will be cleared. In segmented mode, register pairs are used instead of R6
and R9.

%1000 00000000
%4000 %1001 00000001
%4001 %1002 00000010

···
%4002

%107F o1 1 1 1 1 1 1
%1080 00000000
%1081 00000001
%1082 00000010

···
%10FF o1 1 1 1 1 1 1

Note I: Word register in nonsegmented mode, register pair in segmented mode.

Note 2: n = number oj data elements translated.

204
 TRTIB
Translate, Test and Increment
TRTIB src I, src2, r srcl: IR
src2: IR

Operation: RH 1 -- src2[srcl ]
AUTOINCREMENT srcl by 1
r -- r - 1

This instruction is used to scan a string of bytes testing for bytes with special
meaning. The contents of the location addressed by the first source register (the
"target byte") are used as an index into a table of translation values whose lowest
address is contained in the second source register. The index is computed by adding
the target byte to the address contained in the second source register. The addition
is performed following the rules for address arithmetic, with the target byte treated
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the
address of an 8-bit value within the table which is loaded into register RHl. The Z
flag is set if the value loaded into RHI is zero; otherwise the Z flag is cleared. The
contents of the locations addressed by the source registers are not affected. The first
source register is then incremented by one, thus moving the pointer to the next ele-
ment in the string. The word register speCified by "r" (used as a counter) is then
decremented by one. The second source register is unaffected. The source and
counter registers must be separate and non-overlapping registers.
Because the 8-bit target byte is added to the second source register to obtain the
address of a translation value, the table may contain 256 bytes. A smaller table size
may be used where it is known that not all possible 8-bit target byte values
will occur.

Flags: c: Unaffected
Z: Set if the translation value loaded into RHI is zero; cleared otherwise
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

IR: TRTIB@Rsll, @Rs2 1, r

11 0 11 1 1 0 0 0 IRS1 oF ~ 0 0 10 I 25
11 0 11 1 1 0 0 0 !RRS1oF 01 0 0 1 0 I 25
1 0000 I r IRS2 oF 01 0 0 0 0 1 10 000 1 r IRRS2oFOI 0000 I

205
Example: This instruction can be used in a "loop" of instructions which translate and test a
string of data, but an intermediate operation on each data element is required. The
following sequence outputs a string of 72 bytes, with each byte of the original string
translated from its 7-bit ASCII code to an 8-bit value with odd parity. Lower case
characters are translated to upper case, and any embedded control characters are
skipped over. The translation table contains 128 bytes, which assumes that the most
significant bit of each byte in the string to be translated is always zero. The first 32
entries and the 128th entry are zero, so that ASCII control characters and the
"delete" character (%7F) are suppressed. The given instruction sequence is for
nonsegmented mode. In segmented mode, register pairs would be used instead of R3
and R4.
LD R5, #72 !initialize counter!
LDA R3, STRING !load start address!
LDA R4, TABLE
LOOP:
TRTIB @R3, @R4, R5 !translate and test next byte!
JR Z, LOOP !skip control character!
OUTB PORTn, RHl !output characters!
JR NOV, LOOP !repeat until counter = O!
DONE:

Note I: Word regIster In non segmented mode, register pair in segmented mode.

206
 TRTIRB
Translate, Test, Increment and Repeat

TRTIRB srcI, src2, r srcI: IR

src2: IR

Operation: RHI -4- src2[srcI]

AUTOINCREMENT srcl by 1
r-4-r-I
repeat until RH 1 '" 0 or r = 0

This instruction is used to scan a string of bytes, testing for bytes with special
meaning. The contents of the location addressed by the first source register (the
"target byte") are used as an index into a table of translation values whose lowest
address is contained in the second source register. The index is computed by adding
the target byte to the address contained in the second source register. The addition
is performed following the rules for address arithmetic, with the target byte treated
as an unsigned 8-bit value extended with high-order zeros. The sum is used as the
address of an 8-bit value within the table which is loaded into register RHl. The Z
flag is set if the value loaded into RH 1 is zero; otherwise the Z flag is cleared. The
contents of the locations addressed by the source registers are not affected.
The first source register is then incremented by one, thus moving the pointer to the
next element in the string. The word register specified by "r" (used as a counter) is
then decremented by one. The entire operation is repeated until either the Z flag is
clear, indicating that a non-zero translation value was loaded into RHI, or until the
result of decrementing r is zero. This instruction can translate and test from 1 to
65536 bytes. The source and counter registers must be separate and non-overlapping
registers.
Target byte values which have corresponding zero translation table entry values are
scanned over, while target byte values which have corresponding non-zero transla-
tion table entry values are detected and terminate the scan. Because the 8-bit target
byte is added to the second source register to obtain the address of a translation
value, the table may contain 256 bytes. A smaller table size may be used where it is
known that not all possible 8-bit target byte values will occur.
This instruction can be interrupted after each execution of the basic operation. The
program counter of the start of this instruction is saved before the interrupt request
is accepted, so that the instruction can be properly resumed. Seven cycles should be
added to this instruction's execution time for each interrupt request that is accepted.

Flags: c: Unaffected
Z: Set if the translation value loaded into,RHl is zero; cleared otherwise
S: Unaffected
V: Set if the result of decrementing r is zero; cleared otherwise
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles2 Instruction Format Cycles2

IR: TRTIRB lifRsll, lifRs2 1, r

1101111000 IRRS1oFOI 0110 I
11 0 t 1 1 1 0 0 0 IRS1 oF 01 0 1 1 0 1
11 + 14n 11+14n
1 0000 1 r \RS2 oF 011 1 1 0 1 1 0000 1
r !RRS2oFOI1 11 0 I

207
Example: The following sequence of instructions can be used in nonsegmented mode to scan a
string of 80 bytes, testing for special characters as defined by corresponding non-
zero translation table entry values. The pointers to the string and translation table
are set, the number of bytes to scan is set, and then the translation and testing is
done. The Z and V flags can be tested after the operation to determine if a special
character was found and whether the end of the string has been reached. The
translation value loaded into RHl might then be used to index another table, or to
select one of a set of sequences of instructions to execute next. In segmented mode,
R4 and R5 must be replaced with register pairs.
LDA R4, STRING
LDA R5, TABLE
LD R6, #80
TRTIRB @R4, @R5, R6
JR NZ, SPECIAL
END_OF_STRING:

SPECIAL:
JR

LAST_CHAR_SPECIAL:

Note 1; Word register in nonsegmented mode, reg:ster pair in segmented mode.

Note 2: n = number of data elements translated.

208
 T8ET
Test and Set
TSET dst dst: R, IR, DA, X
TSETB

Operation: S +- dst( msb)

dst(O:msb) +- 111...111

Tests the most significant bit of the destination operand, copying its value into the S
flag, then sets the entire destination to all 1 bits. This instruction provides a locking
mechanism which can be used to synchronize software processes which require
exclusive access to certain data or instructions at one time.
During the execution of this instruction, BUSRQ is not honored in the time between
loading the destination from memory and storing the destination to memory. For
systems with one processor, this ensures that the testing and setting of the destination
will be completed without any intervening accesses. To synchronize software
processes residing on separate processors where the destination is a shared memory
location, this instruction should be used with a 28003.

Flags: c: Unaffected
Z: Unaffected
S: Set if the most significant bit of the destination was 1; cleared otherwise
V: Unaffected
D: Unaffected
H: Unaffected

Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R: TSET Rd
TSETB Rbd ~ 7
~ 7

IR:
~
TSET @Rd 1
11 B0011 oEIRRd*ol 011 01 11
TSETB @Rd 1

DA: TSET address

101100110lwl0000101101 01100110Iwi 00001 0110 1
TSETB address 14 55 15
I address I o I segment I offset I
011001101 w I 0000 I 0110
5L 1 I segment I0000 0000 17
offset

X: TSET addr(Rd)
I0 1 10 0 1 1 0 Iw I Rd * 0 I 0 1 1 0 I I I Rd * 0 I 0 1 10 I
o 1 10 0 1 1 0 w
TSETB addr(Rd) 15 55 15
I address I o I segment I offset I
I I Rd * 0 I0 1 1 0
o 1 10 0 1 1 0 w
5L 1 I segment [0 0 0 0 0 0 0 0 18
offset

209
Example: A simple mutually-exclusive critical region may be implemented by the follOWing
sequence of statements:
ENTER:
TSET SEMAPHORE
JR MI,ENTER !loop until resource con-!
!trolled by SEMAPHORE!
!is available!

!Critical Region-only one software process!

!executes this code at a time!

CLR SEMAPHORE ! release resource controlled!

!by SEMAPHORE!

210
 XOR
Exclusive Or
XOR dst, src dst: R
XORB src: R, 1M, IR, DA, X

Operation: dst .,.- dst XOR src

The source operand is logically EXCLUSIVE ORed with the destination operand and
the result is stored in the destination. The contents of the source are not affected.
The EXCLUSIVE OR operation results in a one bit being stored whenever the cor-
responding bits in the two operands are different; otherwise, a zero bit is stored.

Flags: c: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the most significant bit of the result is set; cleared otherwise
P: XOR-unaffected; XORB-set if parity of the result is even; cleared otherwise
D: Unaffected
H: Unaffected

Source Nonsegmented Mode Segmented Mode

Addressing Assembler Language
Mode Syntax Instruction Format Cycles Instruction Format Cycles

R:
I ~
XOR Rd, Rs
XORB Rbd, Rbs
E!]00100B Rs Rd
I 4 4

1M: XOR.Rd, #data

1001001001100001 Rd 00100100110000 I Rd
1 7 7
I data I data

XORB Rbd, #data

I
10 0 00 1 0 0 0 I0 000 I Rbd I 7
001001000 10000 I Rbd
7
I data I data I data 1
If>
data

IR:
~
XOR Rd. !JlRsl
XORB Rbd, !Jl Rsl
7
~ 7

DA: XOR Rd, address

XORB Rbd, address
101100100lwl00001 Rd
I 9 55
01/001001wl 0000 I Rd
10
I address I o I segment I offset

01100100lwl00001 Rd

5L 1 I segment I 0000 0000 12

offset

X: XOR Rd, addr(Rs)

XORB Rbd, addr(Rs)
101100100lwi Rs;<°l Rd I 10 55
o 1 10 0 1 0 0 Iw I RH 0 I Rd
10
I address
I o I segment I offset

o 1 10 0 1 0 0 Iw I Rs;< 0 I Rd

5L 1 I segment I 0000 0000 13

offset

211
Example: If register RL3 contains %C3 (1000011) and the source operand is the immediate
value %7B (01111011)/ the statement
XORB RL3/#%7B
will leave the value %B8 (0111000) in RL3.

Note 1; Word register in nonsegmented mode, register pair in segmented mode.

212
6.8 EPA There are seven "templates" for EPA instruc- but the full specification of the instruction
Instruction tions. These templates correspond to EPA depends upon the implementation of the EPU
Templates instructions, which combine EPU operations and is beyond the scope of this manual.
with possible transfers between memory and an Fields ignored by the CPU are shaded in the
EPU, between CPU registers and EPU regis- diagrams of the templates. The 2-bit field in bit
ters, and between the Flag byte of the CPU's positions 0 and 1 of the first word of each
FCW and the EPU. Each of these templates is template would normally be used as an identi-
described on the following pages. The descrip- fication field for selecting one of up to four
tion assumes that the EPA control bit in the EPUs in a multiple EPU system configuration.
CPU's FCW has been set to 1. In addition, the Other shaded fields would typically contain
description is from the point of view of opcodes for instructing an EPU as to the oper-
the CPU-that is, only CPU activities are ation it is to perform in addition to the data
described; the operation of the EPU is implied, transfer specified by the template.

Extended Instruction
Load Memory from EPU

Operation: Memory ...- EPU

The CPU performs the indicated address calculation and generates n EPU memory
write transactions. The n words are supplied by an EPU and are stored in n con-
secutive memory locations starting with the effective address and increasing in
address.

Flags/Registers: No flags or CPU registers are affected by this instruction.

Clock Cycles
mode dst N5 55 5L
0 0 IR (dst *- 0) 11 +3n
0 1 X (dst *- 0) 15 + 3n l5+3n 18 +3n
0 1 DA (dst = 0) 14+3n 15+3n 17 +3n

213
Extended Instruction
Load EPU from Memory

Operation: EPU __ Memory

The CPU performs the indicated address calculation and generates n EPU memory
read transactions. The n consecutive words are fetched from the memory locations
starting with the effective address. The data is read by an EPU and operated upon
according to the EPA instruction encoded into the shaded fields.

Flags/Registers: No flags or CPU registers are affected by this instruction.

Clock Cycles
mode src NS SS SL
0 0 IR (src 1= 0) 11 +3n
0 1 X (src 1= 0) 15+3n 15 +3n 18+3n
0 1 DA (src = 0) 14+3n 15+3n 17+3n

Extended Instruction
Load CPU from EPU

Operation: CPU -- EPU registers

The contents of n words are transferred from an EPU to consecutive CPU registers
starting with register dst. CPU registers are transferred consecutively with register 0
I

following register 15.

Flags/Registers: No flags are affected by this instruction.

Execution Time: 11 + 4n cycles.

214
 Extended Instruction
Load EPU from CPU

Operation: EPU -- CPU registers

The contents of n words are transferred to an EPU from consecutive CPU registers
starting with register src. CPU registers are transferred consecutively, with register 0
following register 15.

Flags/Registers: No flags are affected by this instruction.

Execution Time: 11 + 4n cycles.

Extended Instruction
Load FCW from EPU

Operation: Flags ..,.- EPU

The Flags in the CPU's Flag and Control Word are loaded with information from an
EPU on AD lines ADo-AD7.

Flags/Registers: The contents of CPU register 0 are undefined after the execution of this instruction.

Execution Time: 15 cycles.

215
Extended Instruction
Load EPU from FeW

Operation: EPU ...- Flags

The Flags in the CPU's Flag and Control Word are transferred to an EPU on AD
lines ADo- AD7.

Flags/Registers: The flags in the FCW are unaffected by this instruction.

Execution Time: 15 cycles.

Extended Instruction
Internal EPU Operation

Operation: Internal EPU Operation

The CPU treats this template as a No Op. It is typically used to initiate an internal
EPU operation.

Flags/Registers: The flags in the FCW are unaffected by this instruction.

Execution Time: 11 + 4n cycles.

216
 7
.-
 Chapter 7
Exceptions
7.1 Intro- The 28000 CPU supports three types of attempted execution of an instruction. Thus,
duction exceptions (conditions that can alter the nor- the major distinction between traps and inter-
mal flow of program execution): rupts is their origin: a trap condition is always
reproducible by re-executing the program that
• interrupts
created the traps, whereas an interrupt is
• traps generally independent of the currently exe-
• reset cuting task. A reset overrides all other condi-
Interrupts are asynchronous events typically tions, including all interrupts and traps. It
triggered by peripheral devices needing atten- occurs when the RESET line is activated, and it
tion. They cause the processor to temporarily causes certain control registers to be initial-
suspend its present program execution in ized. The action that the 28000 CPU takes in
order to service the requesting device. Traps response to an interrupt, trap, or reset is
are synchronous events that are responses by similar; hence, they are treated together in this
the CPU to certain events detected during the chapter.

7.2 Interrupts Three kinds of interrupts are activated by CPU hardware as a pointer to select a particu-
three different pins on the 28000 CPU. (Inter- lar interrupt service routine. The processing of
rupt handling for all interrupts is discussed in vectored interrupts is thus considerably faster
Section 7.6.) than would be the case if a general trap hand-
7.2.1 Non-Maskable Interrupt (NMI). ler had to first examine the identifier, then
This type of interrupt cannot be disabled branch off to the appropriate service routine.
(masked) by software. It is typically reserved These interrupts can be disabled by software.
for highest-priority external events that require 7.2.3 Nonvectored Interrupts (NVI). These
immediate attention. interrupts also result in an identifier word
7.2.2 Vectored Interrupt (VI). One result of being pushed onto the system stack. However,
any interrupt or trap is that a l6-bit identifier the CPU does not use the identifier as a vector
word is pushed onto the system stack (see Sec- to select a service routine: all non-vectored
tion 7.6.2). This word may be used to identify interrupts are serviced by the same routine.
the source of the interrupt or trap. In vectored They can be disabled by software.
interrupts, this identifier is also used by the

7.3 Traps The 28001 and 28002 CPUs support three This trap allows the CPU to detect and prevent
traps generated internally. The 28001 supports operation (such as I/O) that could disable the
a fourth trap, which is generated externally system.
(but synchronously) by the Memory Manage- 7.3.3 System Call Trap. This trap occurs
ment Unit. Since a trap always occurs when all whenever a System Call (SC) instruction is
its defining conditions are present, traps can- executed. It allows an orderly transition to be
not be disabled. (Trap handling operations are made between normal mode and system mode.
discussed in Section 7.6.)
7.3.4 Segment Trap. This trap occurs when
7.3.1 Extended Instruction Trap. This trap ever the SEGT line is asserted on a 28001,
occurs when the CPU encounters an extended regardless of the state of the SEG bit in the
instruction (see Section 6.2.10) while the EPA FCW. This trap is generated by external
bit in the FCW is cleared. This trap allows the memory management hardware, such as the
program to simulate the operations of the EPU 28010 Memory Management Unit (MMU), and
when none is present in the system or to abort is the result of detecting a memory access
the program. violation (such as an offset larger than the
7.3.2 Privileged Instruction Trap. This trap assigned segment length) or a write warning
occurs whenever an attempt is made to execute (a write into the lowest 256 bytes of a stack).
a privileged instruction while the CPU is in See the MMU Technical Manual for more
normal mode (SiN bit in the FCW is cleared). information on memory management hardware.

219
7.4 Reset A reset initializes selected control registers clock cycles to properly reset the CPU.
of the CPU to system specifiable values. A Three clock cycles after RESET has returned
reset can occur at the end of any clock cycle, to High, consecutive memory read cycles are
provided the RESET line is Low. executed in system mode to initialize the Pro-
A system reset overrides all other consider- gram Status registers. In the 28001, the first
ations, including interrupts, traps, bus cycle reads the FCW from location 0002 of
requests, and stop requests. A reset should be segment 0, the next reads the PC from location
used to initialize a system as part of the power- 0004, and the following initial instruction fetch
up sequence. cycle starts the program. Each of these fetches
Within five clock cycles of the RESET is made from system program address space.
becoming Low, ADo-ADI5 are 3-stated; In the 28002, the first cycle reads the FCW
AS,DS, MREQ, BUSACK, and MO are forced from location 0004 and the following initial in-
High; STo-ST3 are forced High and SNo - SN6 struction fetch cycle starts the program. Each
are forced Low. The R/W, B/W, and NiSlines of these fetches is made from the program
are undefined. RESET must be held Low five address space.

7.5 Interrupt Vectored and nonvectored interrupts can be or cleared together or separately. In addition,
Disabling enabled or disabled independently via software these control bits are set when the FCW is
by setting or clearing appropriate control bits loaded via a LDPC and DCTL FCW.
in the Flag and Control Word (FCW). Two When a type of interrupt has been disabled,
control bits in the FCW control the maskable the CPU ignores any interrupt request on the
interrupts: VIE and NVIE. Any control bit may corresponding input pin. Because maskable
be changed by automatically loading a new interrupt requests are not retained by the
FCW during an interrupt or trap acknowledge CPU, the request signal must be asserted until
sequence and may be restored to its previous the CPU acknowledges the request.
setting by an Interrupt Return (IRET) instruc-
tion. When VIE is I, vectored interrupts are
enabled; when NVIE is I, non-vectored inter-
rupts are enabled. These two flags may be set

7.6 Interrupt The CPU response to a trap or interrupt (FCW); and finally, the interrupt/trap
and Trap request consists of five steps: acknowledging identifier word. The identifier word contains
Handling the external request (for interrupts and seg- the reason or source of the trap or interrupt.
ment traps), saving the old program status For internal traps, the identifier is the first
information, loading a new program status, word of the trapped instruction. For segment
executmg the service routine, and returning to trap or interrupts, the identifier is the value
the mterrupted task. Interrupt timing is shown on the data bus read by the CPU during the
on page 236. interrupt-acknowledge or trap-acknowledge
7.6.1 Acknowledge Cycle. An external cycle. The format of the saved program status
acknowledge cycle is required only for exter- in the system stack is illustrated in Figure
nally generated requests. As described in 7.1.
Chapter 9, the main effect of such a cycle is to
receive from the external device a 16-bit iden-
tifier word, which will be saved with the old lOW lOW
ADDRESS ADDRESS
program status. Before the acknowledge cycle, SYSTEM STACK
~~l~T~= AFTER ..... SYSTEM SP IDENTIFIER
the CPU enters segmented (28001 only) system INTERRUPT
AFTER TRAP
OR INTERRUPT Few
mode. (The Nis line indicates that a transition
PC SEGMENT
has been made to system mode.) The old FCW SYSTEM STACK
PC OFFSET
is not affected by this change in mode. The ~~~~T6: BEFORE--..
INTERRUPT
SYSTEM SP .-
BEFORE TRAP
CPU remains in this mode until it begins to OR INTERRUPT

execute the exception service routine', at which . - 1 WORD~ 4-1 WORD .....
time its mode is dictated by the FCW. HIGH HIGH
ADDRESS ADDRESS
7.6.2 Status Saving. The old program status
information is saved by being pushed on the
system stack in the follOWing order: the Pro- Figure 7-1. Format of Saved Program Status in the
System Stack
gram Counter; the Flag and Control Word

220
7.6 Interrupt The following table shows the PC value that the value 2 selects the second PC, and so on
and Trap is pushed on the stack for each type of inter- up to the identifier value 254, which selects
Handling rupt and trap. the 128th PC value. All vectors on Z8001
(Continued) Exception: PC Value Is Address of: systems must be even.
Second Word of Instruction
The Program Status Area is addressed by a
Extended Instruction Trap
Privileged Instruction Trap Word Following First Word special control register, the Program Status
of Instruction Area Pointer, or PSAP. This pointer is one
System Call Trap Next Instruction word for the nonsegmented Z8002 and two
Segment Trap Next Instruction' t words for the segmented Z8001. As shown in
All Interrupts Next Instructiont Figure 7.2, the pointer contains a segment
• Assumes successful completion of instruction fetch number (if applicable) and the high-order byte
t If executing an interruptable instruction (e.g. LDIR) of a 16-bit offset address. The low-order byte is
and the instruction has not completed, then the next assumed to contain zeros; thus the Program
instruction is the current instruction. Status Area must start on a 256-byte address
7.6.3 Loading New Program Status. After boundary. The programmer accesses the PSAP
saving the current program status, the new using the Load Control Register instruction
(LDCTL).

r
program status (PC and FCW) is automatically
loaded from the Program Status Area in system PROGRAM STATUS AREA
program memory. The particular status words POINTER (PSAP)
~
fetched from the Program Status Area are a
~ =~~~
PPER
function of the type of trap or interrupt and OFFSET IMPLIED

(for vectored interrupt) of the interrupt vector.

Figure 7.2 shows the format of the Program BYTE OFFSET Z8002 BYTE OFFSET
HEX DECIMAL ~
Status Area. o 0 o 0

For each kind of interrupt or trap other than

a vectored interrupt, there is a single program
status block that is automatically loaded into
RESERVED
the Program Status registers (which includes Few I~~~~~~~I~N 1------1
the Flag and Control Word and the Program -3 SEG L-. TRAP
PC OFFSET
Counter). RESERVED
SYSTEM
FCW
Note that the size of each program status =.JSEGL-
CALL
TRAP

block depends on the version of the 28000 (two PC OFFSET

RESERVED
words for the nonsegmented Z8002 and four :rSE~C SE';R~~NT
words for the segmented Z800 1). PC OFFSET -1-----1
For all vectored interrupts, the same Flag RESERVED
, Few NON.MASKABlEI--_ _- - l
and Control Word (FCW) is loaded from the U seG L - INTERRUPT
PC OFFSET
corresponding program status block. However, RESERVED

the appropriate Program Counter (PC) value is Few NON-VECTOREDI--_ _--I

U SEG L - INTERRUPT
selected from up to 256 (28002) or 128 (Z8001) PC OFFSET
RESERVED
different values in the Program Status Area. FCW
The low-order eight bits of the identifier PSEGL-
PC,OFFSET
PC,

placed on the data bus by the interrupting

Wp~~~~ PC,
device is multiplied by two and used as an off- o SE~
VECTORED
INTERRUPTS

set into the Program Status Area following the PC3 OFFSET

FCW for vectored interrupts. On the Z8002,

the identifier value 0 selects the first PC value, USEG~ PC n
pen OFFSET
the value 1 selects the second PC, and so on
up to the identifier value 255. On the Z8001,
the identifier value 0 selects the first PC value,
Figure 7-2. Program Status Area

221
7.6 Interrupt 7.6.4 Executing the Service Routine. Loading 7.6.5 Returning from an Interrupt or Trap.
and Trap the new program status automatically initializes Upon completion, the service routine can exe-
Handling the Program Counter to the starting address of cute an Interrupt Return instruction, IRET, to
(Continued) the service routine to process the interrupt or cause execution to continue at the point where
trap. This program is now executed. Because a the interrupt or trap occurred. IRET causes
new FCW was loaded, the maskable interrupts information to be popped from the system stack
can be disabled for the initial processing of the in the follOWing order: the identifier is dis-
service routine by a suitable choice of FCW. carded, the saved FCW and PC are restored.
This allows critical information to be stored The newly loaded FCW takes effect with the
before subsequent interrupts are handled. Ser- next fetched instruction, which is determined
vice routines that enable interrupts before exit- by the restored Program Counter.
ing permit interrupts to be handled in a nested On 28001 CPUs, IRET can be executed only
fashion. in segmented mode; in nonsegmented mode
the operation is undefined.

7.7 Priority Because it is possible for several exceptions • This process is repeated until no enabled
to occur simultaneously, the CPU enforces a exceptions remain. At that point, the cur-
priority scheme for deciding which event will rent PC and FCW will contain the status
be honored first. The follOWing gives the values for the lowest priority exception that
descending priority order: was acknowledged.
• Reset • The execution of the service routines now
• Internal Trap (i.e., privileged instruction, proceeds in reverse priority order. That
system call, extended instruction) is, the lowest priority exception is
serviced first.
• Non-Maskable Interrupt
• After all the exceptions have been serviced,
• Segment Trap (28001 only) the original status is restored and execution
• Vectored Interrupt resumes.
• Nonvectored Interrupt Within each of the classes above, there can
This is how the priority system works: be multiple-interrupt sources. The internal
traps are mutually exclusive and therefore
• Whenever a reset is requested, it is immedi- need no priority resolution within that class.
ately performed. The other types arise from external sources;
• If several non-reset exceptions occur simul- thus when multiple devices share the same
taneously, the one that has the highest request line, the possibility arises that more
priority and is also enabled (traps and non- than one device mav reauest service from the
maskable interrupts are always enabled) is CPU simultaneously. Either all the interrupt
acknowledged, old status is saved, and new sources must be serviced simultaneously (as
status is loaded. The new status consists of with the MMU) or competing requests must be
the starting address of the service routine resolved externally to the CPU, for example,
(PC) and a new FCW that may disable vec- by means of a daisy-chain or priority interrupt
tored and nonvectored interrupts. controller. This resolution is done during the
interrupt acknowledge cycle.
• If any enabled exceptions remain, the
highest-priority one is acknowledged, the
old status is saved, and the new status is
loaded. Note that in this case, the old status
is the PC and FCW of the previous excep-
tion's service routine.

222
 8
.-
 Chapter 8
Refresh
8.1 Intro- The 28000 CPU has an internal mechanism • When the STOP line is activated, the CPU
duction for refreshing dynamic memory. This generates memory refreshes continuously.
mechanism can be activated in two ways: (See Section 8.4.)
• When the Refresh Enable (RE) bit in the I I
RATE
I I
CPU Refresh Counter is set to one (Figure
8.1), memory refresh is performed period- +++++++++
ADa AD 7 AD6 ADs AD 4 AD 3 AD 2 AD 1 ADo
ically at a rate specified by the RATE field
in the counter. (See Section 8.3.) Figure 8-1. Refresh Control Register

8.2 Refresh The refresh mechanism is a way of gener- set to the value of the row address counter.
Cycles ating a special kind of bus transaction called a Address lines ADg-ADj5 are undefined, and
refresh cycle, which is described in Chapter 9. ADo is always O. The ROW value determines
A refresh cycle is three clock cycles long and the memory row that is being refreshed on this
may be inserted immediately after the last cycle. Since memory is word-organized, ADo
clock cycle of any transaction. is always zero. After the refresh cycle is com-
During a refresh cycle, the status lines are plete, the ROW field is incremented by two,
set to 0001 and the address lines ADj-ADa are thus stepping through 256 rows.

8.3 Periodic The Refresh Enable (RE) bit controls only trap or an interrupt simultaneously with a
Refresh Periodic Refresh; refresh cycles may be Periodic Refresh request, the refresh operation
generated using the STOP line, regardless of is performed first.
the state of RE. When RE is set to one, the When the CPU does not have control of the
value of the 6-bit RATE field determines the bus (that is, when BUSACK is asserted and the
time between successive refreshes (the refresh CPU enters Bus-Disconnect state or when the
period). When RATE = 0, the refresh period WAIT line is deactivated), the CPU cannot
is 256 clock cycles; when RATE = n, the issue refresh cycles. To deal with the situa-
refresh period is 4n clock cycles. (Thus, if tion, both 28000 CPUs have internal circuitry
there is a 4 MHz clock, the refresh period can that records when the refresh period has
be from 1 JLS to 64 /l-s.) elapsed and refresh cycles cannot be gener-
The LDCTL instruction is used to set the ated. When the CPU regains control of the
refresh rate, to set or clear RE, or to initialize bus, or when the WAIT line is deactivated, it
or read the ROW field. (See Section 6.7 for a immediately issues the skipped refresh cycles.
detailed discussion of this instruction.) The internal circuitry can record up to two
The refresh cycle is generated as soon as such skipped refresh operations.
possible after the refresh period has elapsed. After a reset operation, Periodic Refresh is
This usually means after the last clock cycle of disabled (RE is cleared) and the internal cir-
the current transaction. If the CPU receives a cuitry that counts skipped refreshes is cleared.

8.4 Stop-State The CPU has three internal operating states: instruction if the STOP line is activated before
Refresh Running, Stop, and Bus-Disconnect states (see the start of the machine cycle. When STOP is
Section 2.8). Stop state is entered during the found High again, one more refresh cycle is
first word fetch of an instruction if STOP is performed, then the remaining clock cycles of
activated before the machine cycle begins, or the instruction fetch are executed. (See
during the second word fetch of an EPA Appendix A for more timing information.)

225
 9
.-
 Chapter 9
External Interface
9.1 Intro- This chapter covers the external manifesta- on the bus and bus operations. The Z8000 CPU
duction tions (e.g., the activity on the CPU pins) that is designed to be compatible with the Zilog
result from the operations described in Z-Bus protocols, which are described in the
Chapters 2 through 8. Since the pins are con- Z-Bus Summary. In the sections that follow, the
nected to the system bus (see Figure 2.3 in interface between the Z8000 CPU and its
Chapter 2), much of the discussion will center environment is described in detail.

9.2 Bus Two kinds of operations can occur on the not transfer data. They indicate that the
Operations system bus: transactions and requests. At any CPU is performing an operation that does
given time, one device (either the CPU or a not require data to be transferred on the bus
bus requester, such as the Z8016 DMA Con- (Section 9.4.6).
troller) has control of the bus and is known as Only the bus master may initiate trans-
the bus master. A transaction is initiated by actions. A request, however, may be initiated
the bus master and is responded to by some by a component that does not have control of
other device on the bus. Only one transaction the bus. Four types of requests can occur:
can proceed at a time; six kinds of transactions
can occur: • Interrupt request. This type is used to
request the attention of the CPU (Section
• Memory transaction. This type is used to 9.6.1).
transfer eight or 16 bits of data to or from a
memory location (Section 9.4.2). • Bus request. This type is used to request
control of the bus to initiate transactions
• 1/0 transaction. This type is used to transfer (Section 9.6.2).
eight or 16 bits of data to or from a periph-
eral or CPU support component, such as an • Resource request. This type is used to
MMU (Section 9.4.3). request control of a particular system
resource (Section 9.6.3).
• EPU transfer. This type is used to transfer
16 bits of data between the CPU and an EPU • Stop request. This type is used to delay
(Section 9.4.4). CPU instruction execution (Section 9.6.4).

• Interrupt/Trap Acknowledge. This type is When an interrupt or bus request is made, it

used to acknowledge an interrupt or trap is answered by the CPU according to its type:
and to transfer an identification/status word for interrupt request, an interrupt acknowledge
from the interrupting or trapping device transaction is initiated; for bus requests, the
(Section 9.4.5). CPU enters Bus Disconnect state, relinquishes
the bus, and activates an acknowledge signal;
• Refresh. These transactions do not transfer for stop requests, the CPU stops execution and
data. They refresh dynamic memory (Sec- enters Stop/Refresh state. A resource request
tion 9.4.6). is generated by the CPU when it executes a
• Internal operation. These transactions do multi-micro request instruction.

229
9.3 CPU Pins The CPU pins can be grouped into five BUSACK. Bus Acknowledge (Output, active
categories according to their functions Low). A Low on this line indicates that the
(Figure 9.1). CPU has relinquished control of the bus in
9.3.1 Transaction Pins. These signals provide response to a bus request.
timing, control, and data transfer for Z-Bus 9.3.3 Interrupt/Trap Pins. These pins convey
transactions. interrupt and external trap requests to
ADo-AD 1S • Address/Data (Output, active High, the CPU.
3-state). These multiplexed data and address NMI. Non-Maskable Interrupt (Input, Edge
lines carry I/O addresses, memory addresses, activated). A High-to-Low transition on NMI
and data during Z-Bus transactions. For the requests a non-maskable interrupt.
Z8001, only the offset portion of memory NVI. Non- Vectored Interrupt (Input, active
addresses is carried on these lines. Low). A Low on this line requests a non-
SNo-SN7 • Segment Number (28001 only, Out- vectored interrupt.
put, active High, 3-state). These lines contain VI. Vectored Interrupt (Input, active Low). A
the segment number portion of a memory Low on this line requests a vectored interrupt.
address.
SEGT. Segment Trap (28001 only, Input,
STo-ST3 • (Output, active, High, 3-state). active Low). A Low on this line requests a seg-
These lines indicate the kind of transaction ment trap.
occurring on the bus and give additional
information about the transaction (such as the
AD ,S
address space for memory transactions).
AD,.
AS. Address Strobe (Output, active Low, AD 13 ..........

3-state). The rising edge of AS indicates the AO , 2

READ~ AD" ..........
beginning of a transaction and shows that the NORMAUS'i'S'i'EM AD1o~

Address, STo-ST 3 , N/S, R/W, and B/W signals BYTElWORD Ao.,_

TRANS-
are valid. ACTIONS AD, - ADDRESS I
ST, AD, _ DATA BUS
DS. Data Strobe (Output, active Low, 3- ST,
ADo -
state). DS provides timing for data movement ST, ADs ........
ST, AD,
to or from the CPU.
28001
R/W. Read/Write (Output, Low = Write, 3- 28002
state). This signal determines the direction of CPU

data transfer for memory, I/O, or EPU transfer

transactions. --1- Z8001l
ONLY,

B/W. Byte/Word (Output, Low = Word, ( ----NM1

I
3-state). This signal indicates whether a byte INTERRUPTS{ ~ SEQMENT i
I
or word of data is 10 be transmitted during a l NVI
NUMBER
I
transaction. I

N/S. Normal/System Mode (Output, Low-

MULTI.MICRO{
CONTROL
iii
iii)
J
SEGMENT
I
I
System Mode, 3-state). N!S indicates the CPU _~R~ __ --.J
is in the normal or system mode.
WAIT. (Input, active Low). A Low on this line t
+5 V GND elK
indicates that the responding device needs
more time to complete a transaction.
MREQ. Memory Request (Output, active Low, Figure 9-1. Pin Functions
3-state). A falling edge on this line indicates
that the address/data bus is holding a memory
address.
9.3.2 Bus Control Pins. These pins carry
signals for requesting and obtaining control of
the bus from the CPU.

BUSREQ. Bus Request (Input, active Low). A

Low indicates that a bus requester has
obtained or is trying to obtain control of
J.1- _ L .. _
l1!~ uu~,

230
9-3. CPU Pins 9.3.4 Multi-Micro Pins. These pins are the 9.3.5 CPU Control. These pins carry signals
(Continued) Z8000's interface to the Z-Bus resource request which control the overall operation of
lines. the CPU. -
MI. Multi-Micro In (Input, active Low). This STOP. (Input, active Low). This line is used to
input is used to sample the state of the suspend CPU operation during the fetch of the
resource request lines. first word of an instruction, or during an EPU
MO. Multi-Micro Out (Output, active instruction if an EPU is busy.
Low). This line is used by the CPU to make RESET. (Input, active Low). A Low on this line
resource requests. resets the CPU.

9.4 Trans- Data transfers to and from the CPU are All transactions start with Address Strobe
actions accomplished through the use of transactions. (AS-) being driven Low and then raised High
Figure 9.2 shows the general timing for a by the CPU. On the rising edge of AS, the
transaction. status lines STo-ST3 are valid; these lines indi-

WAIT sampled WAIT sampled for

for memory and 1/0 and interrupt/trap Data on AD lines
EPU transfer acknowledge is sampled for
transactions. transactions. transfers to CPU.

CLOCK

Cycle present only for I/O

interrupt/trap
acknowledge transactions.

.......- WAIT clock cycles added

here in response to WAIT line.

AS
(ADDRESS STROBE)
AS falling indicates first AS rising indicates that status
clock cycle of a transaction. and address lines are valid.

SNo-SN6
(SEGMENT NO.) SEGMENT NUMBER

Segment No_ becomes

available one clock cycle
before rest of address.

ADo-AD15
(ADDRESS OFFSED
, For continuation see Read and
Write below.

STO-ST3.
RtW, BtW, SIN
(STATUS
INFORMATION) _-+ +' 1"-----1------1------1------1-------1-
Status information becomes
available at the same time
as the address and remains
active throughout the trans·
action.

OS
(DATA
Memory, EPU transfers and"#
READ STROBE) interrupt/trap acknowledge.
I I
For transfers to the CPU
(Memory reads, 1/0 reads,
{ AOo-AD 15
(DATA) :~~~~~~~t~::'a~~~~:~~ge)-.G----+-----+~
the AD lines are first
3·stated by the CPU.

OS
(DATA
STROBE)

For transfers from the CPU

WRITE ADo-AD" (Memory writes, 1/0 writes,
{ and transfers to the EPU) ""-
the CPU places the data on
(DATA)
'her Iines_

Figure 9-2. Transaction Timing

231
9-4. Trans- cate the type of transaction being initiated (see 9.4.1 WAIT. As shown in Figure 9.2, WAIT is
actions Table 9.1; the six types of transactions are dis- sampled on a falling clock edge one cycle
(Continued) cussed in the sections that follow). Associated before data is sampled by the CPU (Read) or
with the status lines are three other lines that DS rises (Read or Write). If WAIT is Low,
become valid at this time. These are Normal! another cycle is added to the transaction
System (N/S), ReadlWrite (RlW), and before data is sampled or DS rises. In this
Byte/Word (B/W). Except where indicated added cycle and all subsequent cycles added
below, NIS designates the operating mode of due to WAIT being Low, WAIT is again sam-
the CPU, RlW designates the direction of data pled on the falling edge and, if it is Low,
transfer (read to the CPU, write from the another cycle is added to the transaction. In
CPU), and B/W designates the length of the this way, the transaction can be extended to an
data item being transferred. arbitrary length to accommodate (for example)
If the transaction requires an address, it too slow memories or I/O devices that are not yet
is valid on the rising edge of AS. No address is ready for data transfer.
required for interrupt acknowledge, EPU It must be emphasized that the WAIT input
transfer, or internal operation transactions. (In is synchronous. Thus, it must meet the setup
the 28001, the segment number lines SNo-SN6 and hold times given in Appendix A in order
are valid one clock cycle earlier to allow for for the CPU to function correctly. This
external memory management hardware. See requires asynchronously generated WAIT
Chapter 2 for more information.) signals to be synchronized before they are
The CPU uses Data Strobe (DS) to time the input into the CPU.
actual data transfer. (Note that refresh and 9.4.2 Memory Transactions. Memory Trans-
internal operation transactions do not transfer actions move data to or from memory when the
any data and thus do not activate DS.) For CPU makes a memory access. Thus, they are
write operations (RIW = Low), a Low on DS generated during program execution to fetch
indicates that valid data from the bus master is instructions from memory and to fetch and
on the ADo-ADI5 lines. For read operations store memory data. They are also generated to
(RIW = High), the bus master makes store old program status and fetch new pro-
ADo-ADI5 3-state before driving DS Low so gram status during interrupt and trap handling
that the addressed device can put its data on and after reset.
the bus. The bus master samples this data on As shown in Figure 9.3, a memory trans-
the falling clock edge just before raising action is three clock cycles long unless
DS High.

Kind of Transaction Additional Information

1":'2rn<31 Operation 0000

Refresh 0001
DOlO Standard I/O
I 0 Transaction { 0011 Speciall/O
0100 Segment Trap
Interrupt Non-Maskable Interrupt
0101
Acknowledge
Transaction
10110
0111
1000
Non- Vectored Interrupt
Vectored Interrupt
Data Address Space
1001 Stack Address Space,
Memory 1010 Data Address Space, EPU Transfer
Transaction 1011 Stack Address Space, EPU Transfer
1100 Program Address Space,
1101 Program Address Space, First Word of Instruction
1111 Test and Set (28003 only)
EPU Transfer 1110

Table 9-1. Status Codes

232
9-4. Trans- extended as explained above in WArT. The Status codes 1000 and 1001 may also indi-
actions status pins, besides indicating a memory trans- cate that the EPU is to capture or supply the
(Continued) action, give the following information: data.
• Whether the memory access is to the data For the 28002, the full memory address will
(1000, 1010), stack (100 I, 1011), or program be on AD o-AD I5 when AS rises. For the
(1100, 1101) address space (Chapter 3). 28001, the offset portion of the segmented
• Whether the first word of an instruction is address will be on AD o-AD I5 and the segment
being fetched (1101). number portion will be on SNo-SN6 when AS
rises. The segment portion will also be on
• Whether the data for the access is to be SNo-SN6 approximately one cycle before
supplied (write) or captured (read) by an ADO-AD I5 is valid.
Extended Processing Unit (1010, 1011).

Tn T, T, T,

p.....--

I Lr-L-
~
CLOCK ~ DATA SAMPLED

- "'WAIT C : : : : :
FOR READ

WAIT

STATUSES
(BM', NIS, [
STo-ST,) i
I

SNo-SNs SEGMENT NUMBER

!

is !

I
I I I
- -
MREQ i

I
I

AD
READ
MEMORY ADDRESS
>--- II <=:)
-OS
READ

/ ~
R1W
READ I

AD
MEMORY ADDRESS! DATA OUT
WRITE

i
-OS
WRITE

i !

-
R1W
WRITE
i \ I i \ /

Figure 9-3. Memory Read and Write Transaction

233
9-4. Trans- Bytes transferred to or from odd memory As shown in Figure 9.5, I/O transactions are
actions (address bit a is 1) locations are always trans- four clock cycles long at minimum, and they
(Continued) mitted on lines ADo-AD? (bit a on ADo). Bytes may be lengthened by the addition of WAIT
transferred to or from even memory locations cycles. The extra clock cycles allow for slower
(address bit a is 0) are always transmitted on peripheral operation.
lines ADs-AD15 (bit a on ADs). Thus, the The status lines indicate whether the access
memory attached to a 28000 will look like that is to the Standard I/O (0010) or Special I/O
shown in Figure 9.4. For byte reads (B/W (00 11) Address Spaces. The N/S line is always
High, R/W High) the CPU uses only the byte Low, indicating system mode. The I/O address
whose address it outputs. For byte writes (BIW is found on ADo-AD15 when AS rises. Since
High, R/W Low), the memory should store only the I/O address is always 16 bits long, the seg-
the byte whose address was output. During ment number lines are undefined on 28001
byte memory writes, the CPU places the same CPUs. For byte transfers (B/W = High) in
byte on both halves of the bus, and the proper Standard I/O space, addresses must be odd;
byte must be selected by testing Ao. For word for byte transfers in Special I/O space,
transfers, (B/W = Low), all 16 bits are cap- addresses must be even.
tured by the CPU (Read: RlW = High) or Word data (B/W = Low) to or from the CPU
stored by the memory (Write: R/W = Low). is transmitted on ADo-AD15. Byte data
As explained more fully in Section 9.5, a (B/W = High) is transmitted on ADO-AD? for
28001 CPU and an Extended Processing Unit Standard I/O and on ADs-AD15 for Special
act like a single CPU with the CPU providing I/O. This allows peripheral devices or CPU
addresses, status and timing information and support devices to attach to only eight of the
the EPU providing or capturing data. 16 ADo-AD16 lines. The Read/Write line (RlW)
indicates the direction of the data transfer:
9.4.3 I/O Transactions. I/O transactions move peripheral-to-CPU (Read: RlW = High) or
data to or from peripherals or CPU support CPU-to-peripheral (Write: RlW = Low).
devices (e.g., MMUs). They are generated
during the execution of I/O instructions.

i6.BIT Z·BUS DATA PATH

D ADo

ADO-AD,.
LOWER
BYTE
BANK
1000 ADDRESS)

Bffl -ot>------,.....-t'"'
ADo ~-...- ...e~<r-H_L../
LOWER
BANK
RIW ---i:::====~::::;L)-----------' ENABLE

Figure 9-4. Memory Organization

234
9-4. Trans- 9.4.4 EPU Transfer Transactions. These trans- participate in a transaction is selected implic-
actions actions move data between the CPU and an itly, as described in Secion 9.5, rather than
(Continued) Extended Processing Unit (EPU), thus allowing by an address. EPU -CPU transactions have the
the CPU to transfer data to or from an EPU or same timing relationship as I/O transactions
to read or write an EPU's Status Registers or (Figure 9-5).
between EPU and memory. They are generated The data transferred is l6-bit words (BIW
during the execution of the EPA instruction. Low), except for transfers between the Flags
EPU memory transfer transactions have the byte of the FCW and an EPU. In this case a
same form as memory transactions (Figure 9.3) byte of data is transferred on AD o-AD7
and thus are three clock cycles long, unless (BiW = High). The Read/Write line (R/W)
extended by WAIT. No address is generated, indicates the direction of the data transfer. The
and there is only one status code that can be N/S line indicates either system mode (Low) or
used on the STo-ST 3 lines (111 0). In a normal mode (High).
multiple EPU system, the EPU which is to

T, T, TWA

CLOCK m...- - + DATA SAMPLED

FOR READ

WAIT

STATUSES
(8m, 5T0-5T3)

HIS

AS

MREQ

AD
INPUT

os
INPUT

~'E
'''~ j
I
I

~~=p< PORT ADDRESS I

X DATA OUT

os
OUTPUT
\
~Wn
OUTPUT:

Figure 9-5. Input/Output Transaction

235
9-4. Trans- 9.4.5 Interrupt/Trap Acknowledge Trans- system mode (Low), the RlW line indicates
actions actions. These transactions acknowledge an READ (High), and the B/W line indicates
(Continued) interrupt or trap and read a 16-bit identifier Word (Low).
word from the device that generated the inter- The only item of data transferred is the
rupt or trap. The transactions are generated indentifier word, which is always 16 bits long
automatically by the hardware when an inter- and is captured from the ADo-ADlilines on
rupt or segment trap is detected. the falling clock edge just before DS is
These transactions are eight clock cycles raised High.
long at a minimum (as shown in Figure 9.6), As shown in Figure 9.6, there are two places
having five automatic WAIT cycles. The WAIT where WAIT is sampled and thus a WAIT
cycles are used to give the interrupt priority cycle may be inserted. The first serves to delay
daisy chain (or other priority resolution the falling edge of DS to allow the daisy chain
device) time to settle before the identifier word a longer time to settle, and the second serves
is read. (Consult the Z-Bus Summary for more to delay the point at which data is read.
information on the operation of the priority 9.4.6 Internal Operations and Refresh Trans-
daisy-chain. ) actions. There are two kinds of bus trans-
The status lines identify the type of excep- actions made by the CPU that do not transfer
tion that is !>eing acknowledged. The possibil- data: internal operations and memory refresh.
ities are Segment Trap (0100), Non-Maskable Both transactions look like a memory trans-
Interrupt (OlGl), Non-Vectored Interrupt action, except that Data Strobe remains High
(0110), and Vectored Interrupt (0111). No and no data is transferred.
address is generated. The N/S line indicates

'~i---~~~~iU~JT!~~---i-I-I~~f!:J~N_-t--
__-----A-UTO-MA-TtC ::~}:T~~~~E

fr~
T T,

CLOCK

~
\ *-SAMPlE
INTER,!!! _ _ SAMPLE

NIIII "---+--
.,w-:r-
.,wll-
STO.ST.=r=:= =D<~----------.-
DS-_._-------------..
\'--_ _-J!
.~~---------( 10'_NT"""_>_ - t o -

Figure 9-6. Interrupt and Segment Trap Request and Acknowledge Transition.

236
9-4. Trans- For internal operation transaction (shown in refresh mechanism as described in Chapter 8
actions Figure 9.7), the Address and Segment Number and can corne immediately after the final clock
(Continued) lines contain arbitrary data when the Address cycle of any other transaction. The memory
Strobe goes High. The R/W line indicates refresh counter's 9-bit ROW field is output on
Read (High); the B/W line is undefined, and ADO-ADs during the normal time for
N/S is the same as for the immediately addresses. This transaction can be used to
preceding transaction. This transaction is initi- generate refreshes for dynamic RAMs. The
ated to maintain a minimum transaction rate value of N/S, R/W, and B/W is the same as for
while the CPU is doing a long internal the immediately preceeding transaction.
operation. WAIT is not sampled during internal opera-
A memory refresh transaction (shown in tion or refresh cycles.
Figure 9.8) is generated by the Z8000 CPU's

~.,="
CLOCK

~~~~ .__.1. ·

MREQ. iii,
:~-
RlW . HIGH

NIS

Figure 9-7. Internal Operation Timing

STO-STa

REFRESHADOAESS )------- -------- -C

RIW.BIW.IIIi}_--+- -+__...
_.. _S"""OUS_....,...CY_Cl_E _

Figure 9-8. Memory Refresh llmmg

237
9.5 CPU and A 28000 CPU and one or more Extended AD lines while data is being transferred
Extended Pro- Processing Units (EPUs) work together like a (DS Low). EPU memory transfers are always
cessing Unit single CPU component, with the CPU pro- word-oriented (B/W Low).
Interaction viding address, status and timing signals and • If the instruction involves a transfer between
the EPU supplying and capturing data. The the CPU and EPU, the next one to 16 non-
EPU monitors the status and timing signals out- refresh transactions by the CPU will transfer
put by the CPU so that it will know when to data between the EPU and CPU
participate in a memory or EPU transfer trans- (ST3-STO = 1110).
action. When the EPU is to participate in a Note that in order to follow this sequence, an
memory transaction, the CPU puts its AD lines EPU will have to monitor the BUSACK line to
in 3-state while DS is Low, so that the EPU may verify that the transaction it is monitoring on
use them. the bus was generated by the CPU. It should
In order to know which transaction it is to also be noted that in a multiple EPU system,
participate in, the EPU must track the follow- there is no indication on the bus as to which
ing sequence of events: EPU is cooperating with the CPU at any given
• When the CPU fetches the first word of an time. This must be determined by the EPUs
instruction (ST3-STO = 1101), the EPU must from the extended instructions they capture.
also capture the instruction returned by A final aspect of CPU-EPU interaction is the
memory. If the instruction is an extended use of the CPU's STOP pin. When an EPU
instruction, it will have an ID field which begins to execute an extended instruction, the
indicates whether or not the EPU is to CPU can continue fetching and executing
execute the instruction. instructions. If the CPU fetches another
extended instruction before the first one has
• If the instruction is to be executed by the
completed execution, the EPU must activate
EPU, the next non-refresh transaction by the
the CPU's STOP pin to stop the CPU (as
c;PlT will fAkh thA f':Acond word of the
9-6. Requests 9.6.1 Interrupt/Trap Request. The 28000 CPU • The next machine cycle is the interrupt
(Continued) supports three interrupts and one external trap acknowledge transaction (see Section 9.4.4)
(segment trap) as shown in Figure 9.6. The that results in an identifier word from the
Interrupt Request line (INT) of a device that is highest-priority interrupting device being
capable of generating an interrupt may be tied read off the AD lines.
to any of the three 28000 interrupt pins (NMI, • This word, along with the program status
NVI, VI). Several devices can be connected to information, is stored on the system stack,
one pin, the devices arranged in a priority and new status information is loaded (see
daisy chain (see the Z-Bus Summary). The seg- Chapter 7).
ment trap pin (SEGT) is activated by the
memory management hardware. The CPU uses For more information about the system-level
the same protocol for handling requests on any aspects of the interrupt structure, consult the
of these pins. Here is the sequence of events Z-Bus Summary.
that is followed: 9.6.2 Bus Request. To generate transactions
• Any High-to-Low transition on the NMI on the bus, a potential bus master (such as the
input is asynchronously edge-detected, and DMA Controller) must gain control of the bus
the internal NMI latch is set. At the begin- by making a bus request (shown in Figure
ning of the last clock cycle in the last 9.9). A bus request is initiated by pulling
machine cycle of any instruction, the VI, BUSREQ Low. Several bus requesters may be
NVI, and SEGT inputs are sampled along wired to the BUSREQ pin; priorities are
with the state of the internal NMI latch. resolved externally to the CPU, usually by a
priority daisy chain (see the Z-Bus Summary) .
• If an interrupt or trap is detected, the sub-
The asynchronous BUSREQ signal generates
sequent initial instruction fetch cycle is
an internal BUSREQ, which is synchronous. If
exercised, but nullified.
the external BUSREQ is Low at the beginning

_ - - - - B U S AVAILABLE----. .

Tx Ix Tx Tx Tx

CLOCK

BUSREQ

INTERNAL
BUSREQ

BUSACK

~-- ---- --- ----

SN

----------+--1
>---
----t---- ---
AD
_ _ _ _ _ _ _ _ _ _-+-J)-.-- ---- ---

. . . -. .
MREQ, OS,
STo-ST 3 •
------------4-_
1-- ----f---- ---
)-

Figure 9-9. Bus Request/Acknowledge Timing

239
9-6. Requests of any machine cycle, the internal for arbitration of priority, MI is tested again. If
(Continued) l3DSREQ will cause the bus acknowledge line it is Low, the CPU has control of the resource;
(BUSACK) to be asserted after the current if it is still High, the request was not granted.
machine cycle is completed. The CPU then In the case of failure, MO must be deactivated.
enters Bus-Disconnect state and gives up con- But if successful, MO must be kept active until
trol of the bus. All CPU Output pins, except the CPU is ready to release the resource
BUSACK and MO, are 3-stated. whereupon MO is deactivated by an MRES
The CPU regains control of the bus two instruction.
clock cycles after BUSREQ rises. Any device The Z-Bus Summary describes an arbitration
desiring control of the bus must wait at least scheme that is implemented with a resource
two cycles after BUSREQ has risen before request daisy chain.
pulling it down again. 9.6.4 Stop Request. As shown in Figure 9-10,
9.6.3 Resource Request. The CPU generates the STOP pin is normally sampled on the fall-
resource requests by executing the Multi-Micro ing clock edge immediately preceding an ini-
Request (MREQ) instruction. The CPU tests the tial instruction fetch cycle. If STOP is found
availability of the shared resource by examin- Low, the CPU enters Stop/Refresh state and a
ing 'MI. If MI is High, the resource is stream of memory refresh cycles is inserted
available, otherwise the CPU must try again after the third clock cycle in the instruction
later. The MO pin is used to make the resource fetch. The ROW field in the Refresh Counter is
request. MO is pulled Low, then, after a delay incremented by two after every refresh cycle.

---REFRESH---I
I T,,. T'll Tlil

STOP""\ ! \ ! )()C J \~ _
-c::=:>-- ~~TRUCT~::~~~~ >-- -< :~6~~~~ :>--
u\J V ~

os "---I

STO-ST, ===>< --.JXI...... _ ________x:=

! _ x:=
Alii

Figure 9-10. Stop Timing

240
9-6. Requests When STOP is found High again, the next instruction fetch-if the first word indicates an
(Continued) refresh cycle is completed, then the original extended instruction. Thus, the STOP line may
instruction continues. be used by an EPU to deactivate the CPU
If the EPA bit in the FCW is set (indicating whenever the CPU fetches an extended
an EPU is in the system), the STOP line is also instruction before the EPU has finished pro-
sampled on the on the falling clock edge cessing an earlier one. The STOP line may
immediately preceding the second word of an also be used to externally single-step the CPU.

9.7 Reset A hardware reset puts the Z8000 in a known line becominSLlo~igure9.11), ADo-AD15
state and initializes selected control registers are 3-stated; AS, DS, MREQ, BUSACK,
of the CPU to system speCifiable values (as MO, and ST 0 - ST 3 are forced High; SN 0 - SN 6
described in Section 7.4). A reset will begin at are forced Low. The R/W, B/W and N/S lines
the end of any clock cycle, if the RESET line are undefined. Reset must be held Low at least
is Low. five clock cycles.
A system reset overrides all other operations After RESET has returned High for three
of the chip, including interrupts, traps, bus clock cycles, consecutive memory-read trans-
requests and stop requests. A reset should be actions are executed in the system mode to ini-
used to initialize a system as part of the power- tialize the Program Status Registers. These cor-
up sequence. respond to the memory accesses described in
Within five clock cycles of the RESET Section 7.4

\'---------
----------')-----
... ..,.,1

STO-ST3 ..,.,1

.iii
---------------- \
BUSAK ,.,I
_ _ _ _ _ _ _ _...J 1

Figure 9-11. Reset Timing

241
 A
.-
 Appendix A

AD, AD,
AD, SN,
READIWRITE AD10 SNs
NORMAUSYSTEM AD 11 AD,
TRANS- BYTElWORO
ACTIONS AD12 AD,
A013 AD,
STOP SN,
iii ADs
AD 1 s AD,
AD t • AD,
+5V AD,
Z8001
CPU
Vi SN,
NVi GND
SEGT CLOCK
NMi AS
RESET RESERVED
iTo BtW
MREci NIS
os piw
ST, BUSACK
ST, WAIT
iii

r
MULTIOMICRO{ ST, BUSREQ
CONTROL iTo ST, 23 26 SN,

_..,....-..,.._:--_ _S-_EG_T ~~;~mlT SN3924 2SPSN 1

t t t
+5 V GND eLK

Z8001 Pin Assignments

Z8001 CPU Pin Functions

J; 1 40 AD,

~
READIWRITE 2 39 AD,
NORMAUS\'SfEM 3 38 AD,
TRANS- BYTElWORD 4 37 AD,
ACTIONS
5 36 AD,
ADDRESSl
DATA BUS 6 35 ADs
7 34 AD,
AC 1s 8 33 AD,
AD,. 9 32 AD,
+5V 10 31 GND
Z8002
Z8002 VI 11 30 CLOCK
CPU
NYI 12 29 AS
NilI 13 28 RESERVED
RESET 14 27 8tW
iTo 15 26 NIS
MREQ 16 25 R1W
os 17 24 BUSACK
ST, 18 23 WAIT

~
ST, 19 22P BUSREQ
ST, 20 21 lJ
ST,
iii
MULTI.MICRO{
CONTROL iTo

Z8002 Pin Assignments

t t t
+5 V GND ClK

Z8002 CPU Pin Functions

245
 B
.- .-
IIIIW • III _
.,.:,~
17':'~~
7;1",.
Zilog
 Z8010 MMU
Memory
Management Unit

~
Zilog
Product
Brief
Features • Dynamic segment relocation makes software • Sixty-four variable-sized segments from 256
addresses independent of physical memory to 64K bytes can be managed within a total
addresses. physical address space of 16M bytes; all 64
• Sophisticated access validation protects segments are randomly accessible.
memory areas from unauthorized or unin- • Multiple MMUs can support several transla-
tentional access. tion tables for each of the six 28001 address
spaces.
• MMU architecture supports multiprogram-
ming systems.

Description Declining memory costs coupled with the efficient support for this large address space
increasing power of microprocessors has by offering dynamic segment relocation as well
accelerated the use of high-level languages, as numerous memory-protection features.
sophisticated operating systems, complex pro- The primary memory of a computer is one
grams and large data bases in micromputer of its major resources. As such, the manage-
systems. The 28001 microprocessor CPU sup- ment of this resource becomes a major con-
ports these trends with an eight megabyte cern as demands on it increase. These
direct address space as well as a rich and demands arise from multiple users (or multiple
powerful instruction set. The 28010 Memory tasks within a dedicated application), the need
Management Unit (MMU) provides flexible and to increase system integrity by limiting access

A"
A22
A21
cs NIS
DMASYNC ANi
A20
SEGT AS
A,.

A"
SUP os
AESET STo
An
A 2, ST,
A" PHYSICAL
A 22 ST2
A15 ADDRESS
A 2, ST,
A14
A 20 AD,
A13
A,. AD.
Z8010 A12
MMU +5V AD 10
Al1
A" AD '1
A,O
An ClK
A.
AlB GND
As
A 15 AD '2
SEGMENT A 14 AD '3
TRAP
SEGT SUP SUPPRESS
A 13 AD,4

DMAISEGMENT _ _ DMASYNC A'2 AD,s

AM } A l1 SNo
NfS - 4 - -
_ _ AS A lO SN,
ST3 .......-
BUS TIMING _
_ _ OS STATUS Ag SN,
{ ST2 ......-
As SN,
ST,
CHIP SELECT _ _ cs RESERVED SN,
STo .......-
SN. SN s

ttt
+ 5 V GND ClK RESET DECOUPLE

Figure 1. Pin Functions Figure 2. Pin Assignments

249
Description to various portions of the memory, and from a powerful set of memory protection features.
(Continued) the need to structure large, complex programs Relocation. Dynamic segment relocation
and systems. makes user software addresses independent of
Multiple tasks (or users) of a system that the physical memory addresses, thereby free-
can reside anywhere in memory are called ing the user from specifying where information
reJocatabJe. Generally, systems in which all is actually located in the physical memory and
tasks are relocatable offer far greater flexibility providing a flexible, efficient method for sup-
in responding to changing system environ- porting multi-programming systems.
ments. Another aspect of multiple-task envi- The Z-MMU uses a translation table to
ronments is sharing: separate tasks can transform the 23-bit logical addresses from the
execute the same program on different data, or 28001 CPU into 24-bit addresses for the
several tasks may execute different programs physical memory. Memory segments are
using the same da ta. variable in size from 256 bytes to 64K, in
Unfortunately, a problem that arises in increments of 256 bytes. Pairs of Z-MMUs sup-
multiple-task systems is that of system integrity. port the 128 segment numbers available for the
Tasks must be protected from unwanted inter- various Z8001 CPU address spaces. Within an
actions with other tasks; user tasks must be address space, any number of Z-MMUs can be
prohibited from performing operating system used to accommodate multiple translation
functions; and user tasks must also be pro- tables for system and normal operating modes,
tected from themselves so they cannot overflow or to support more sophisticated memory-
the areas allotted to them. management systems.
In addition to these considerations, support
for the design and implementation of large, System Integrity. Z-MMU memory-protection
complex programs and systems is itself an features safeguard memory areas from
important consideration. Modern trends are unauthorized or unintended access by
toward the partitioning of a complex task into associating special access restrictions with
small, simple, self-contained subtasks that have each segment. A segment is assigned a "per-
well-defined interfaces. Because these subtasks sonality" consisting of several attributes when
interact with each other, communication it is initially entered into the Z-MMU. When a
between them must be carefully controlled. memory reference is made, these attributes are
Memory-management systems can offer effec- checked against the status information sup-
tive solutions for implementing large systems plied by the 28001 CPU. If a mismatch occurs,
modularly designed. a trap is generated and the CPU is inter-
The Z8010 Memory Management Unit sup- rupted. The CPU can then check the status
ports multiple-process and large modular soft- registers of the MMU to determine the cause
~are systems with dynamic segment relocation. and take appropriate action to correct the pro-
Futhermore, it enhances system integrity with blem.

1\
00- 0 ,
>
r
r>)
°8- 0 15

IJ1--;Do- AD, Ao-A,

1 ADe-AD15 ~ Ao- A 23
~
) MEMORY

.~
~
V
Z8001 K 5 N o- 5N 6
SUP

CPU \j

5 To-5T3
A Z8010
MMU
5To-5T3 ~
5EGT
AS
IT
f---+ ~
JlSV
OS

rF
f---+
R/W
f---+
N/5
f---+
BIW

, 1 I
IL-.l 1 II
Figure 3. The MMU in a Z8001 System

250
 Z-Bus
System Structure

~
Zilog
Descriptive
Brief
Features • Multiplexed address/data bus, shared by • Daisy-chained bus request.
I/O and memory.
• Daisy-chained resource request.
• Peripherals may be asynchronous. • Vectored or nonvectored interrupts.
• Up to 24-bit memory address, 16-bit I/O. • Separate memory and I/O address space.
• 8 or 16 data bits.

Description The Z-bus is a shared bus that links the com- ------PRIMARy SIQNALS------
ponents of the Z8000 family. A bus user can be
any device that can generate bus transactions.
Five different types of transactions can be
< ADo-AD" >
passed on the Z-bus to serve the basic needs of
EXTENDED ADDRESS\
I/O and memory structures in a distributed- V
processing environment. The five types are:
• Memory access STATUS>

• I/O transfer BUS - - AS - PERIPHERAL

MASTER _ _ Os _ AND MEMORY
• Interrupt --R/W_
• Bus request ---B/W_
_WAIT--
• Resource request _RESET_

Memory Access. Status signals issued by the

CPU distinguish memory transactions from
others and select the address space to be
accessed. Slow memory devices may assert the
WAIT signal to prolong the transaction. -CLOCK_
Extended addresses may be used with the - - - - - B U S REQUEST S I G N A L S - - - - -
_ _ BUSREQ_
segmented Z8001 CPU and the Z80 10 MMU.
Other status signals define direction (R/W) , CPU
--BUSACK- REQUESTER

Normal/System (Nls), Byte/Word (B/W), and ,--.ilAi-

L-- _
BAO
the various address spaces. ------INTERRUPT S I G N A L S - - - - - -
_iNT---

PERIPHERAL

C::i:~==
----RESOURCE REQUEST SIGNALS----
--MMRQ_

Z-BUS -MMST-- MULTI-MICRO

COMPONENT REQUEST
_MMAI--, NETWORK
_ MMAO-----.J

Figure 1. Z-Bus Signals

251
Description HIGHEST LOWEST
PRIORITY PRIORITY
(Continued)
Z·BUS Z·BUS Z·BUS
PERIPHERAL PERIPHERAL PERIPHERAL

+5Y lEI ADo-AD7 is os i'NT INTACK 'EO lEI ADo-AD7 AS os fNf INTACK lEO lEI ADo-AD7 AS os iNf INTACK lEO

I Itt I II i t I t t

AI>{)-AD7

AS
AL.'::f
~ I I I I I I ,
,
, Iii +1
Z-BUS
os I I
CPU
INT
WAIT I---

STATUS

H STATUS
DECODER rt ,

AD8-AD15 ~ FROM 16-BIT PERIPHERALS

Figure 2. Interrupt Connections

I/O Transfer. The status line I/O reference outputs. (Multiple INTs might occur
distinguishes I/O transactions from others. The simultaneously.) The highest-priority IEO has
l6-bit multiplexed bus is used for address and the effect of removing IEI inputs from all
data (without extension), and AS, DS, R/W, devices beyond it on the same daisy chain,
B/W, and WAIT are used in a similar way. thereby preventing them from requesting inter-
Direct addressing of the internal registers of rupts further until their IEI inputs are restored.
peripherals is facilitated by the use of Three Wait cycles after the leading edge of
multiplexed address and data lines. (See INTACK (or more, if WAIT has been asserted
Figure 1.) The Z-bus is asynchronous, so by the highest-priority device requesting ser-
peripherals' clocks need not be synchronized vice). to allow the chain to settle, a DS from
with the CPU clock, which is therefore not the CPU stimulates the one highest-priority re-
transmitted on the bus directly. The signals questing peripheral to place its vector on the
(strobes, acknowledges, etc.) generated in the bus. Two (or more) additional Wait cycles
course of any transaction provide all necessary later, the service routine is invoked, and
timing information. INTACK is returned high. At this time, all re-
Interrupt. The Z-bus interrupt scheme is an questers of higher priority than the one being
interrupt-under service priority daisy chain serviced (those whose IEI lines are still high)
that requires no separate priority controller. are enabled, and may generate new interrupt
Interrupt requests are all tied directly to the requests. Once a peripheral has been serviced
INT pin of the CPU. (See Figure 2.) Physical it unmasks the daisy chain so lower-priority in-
position along the IEI/IEO daisy chain deter- terrupts can be generated.
mines the priority assigned to any given Bus Request. The bus request is used to
peripheral. Upon receipt of an INT signal, the transfer control of the Z-bus for memory or I/O
CPU issues an INTACK. (See Figure 3.) This transactions. The BUSRQ input line to the
temporarily inhibits further interrupt requests, Z-bus CPU, the wired-OR of BRQ outputs from
while all devices that have initiated interrupt all requesters, initiates a bus request. The
requests prior to that INTACK drop their IEO BUSAK output line from the CPU is daisy-
WAIT SAMPLED
chained through BAI inputs and BAO outputs
TO EXTEND
VECTOR ACCESS
of all requesters in order of priority, to grant
TIME
use of the bus to the first requester whose
;' READ
VECTOR BAO is held high at that time.
( /
T, TW, Tw Tw Tw. \ Tw. \ T,
CLOCK
Resource Request. The resource request
, I
chain is used to share a resource among
::::x::::t:::.......--
ADo-AD7 i w~~ ;:T~~LOEOI I-":L:~""-
: DAISY CHAIN i I VECTO~ ./m,- several Z-bus CPUs, none of which is default
iNn: 1'-. I SETTU[G TIMEI I I (fff master of that resource. The resource-request
AS --l-'--.J IUS SET FOR HIGHEST PRIORITY PERIPHERAL protocol is similar to that of the bus request,
OS • i I i<' > r- except for an added status line that inhibits il11
WAIT :~::~::::::~:::~T\F::iT"1::::: requesters from issuing requests any time the
I I I resource is busy. The acknowledge daisy-chain
resolves contention in the event of simul-
taneous requests.
Figure 3. Interrupt Acknowledge Timing

252
 18090 Z-UPC
UDiversal
Pedpheral CODlroDer

~
Zilog
Product
Brief
Features • Complete slave microcomputer, for • Two programmable 8-bit counter/timers with
distributed-processing Z-Bus use. 6-bit prescalers.
• Unmatched power of Z8 architecture, • 256 byte register £jle, accessible by both
instruction set. master CPU and Z-UPC, as allocated by
• Three programmable I/O ports, two with Z- UPC program.
2-wire handshake, or any combination of • 2K bytes of on-chip program ROM for effi-
data and control lines. ciency, versatility.
• Six levels of priority interrupts to Z- UPC.

Description The Z- UPC Universal Peripheral Controller program controL its three 8-line I/O ports can
is a distributed microcomputer that performs be tailored to the needs of its user. Perma-
the three basic interfacing functions needed to nently configured as a single-chip controller
interface a CPU with peripherals: device con- with 2K bytes of internal ROM, the Z- UPC
trol by ROM-resident internal software, data executes instructions in 2.2 jJ.S average using a
manipulation, such as reformatting or 4-MHz clock source. Its register £jle contains
arithmetic, and data buffering in internal 256 bytes, of which 234 are general-purpose
registers. registers, 19 are status and control registers,
The Z- UPC is similar to the Z8 microcom- and three are port registers.
puter and uses the Z8 instruction set. Under

.....-. AD? +5 V P3,

Pl _
.......... AD6 P16 ...........

Pl'-l
PCLK PJ,;
............. ADs P1s .....-.... lEO OR P3, P2,
AODRESSI AD, lEI OR P30 P20
, PORT 1
DATA BUS AD, P13 ......... iNf OR P3, P2,
....-..... AD2 P12 ............ INTACK OR P32 P2,
.....-.. AD, PI, Ril P2,
......... ADo P10 .............. ViR P22

T1M~~~ I - - AID UPC P3'_}

AID P2,

AND RESET I -- Ril P3,

PORT 3
Cs P20

I - - WR P32 ....-- GND P3,

CONTROL I -- ~'T PJ,;

AD,
PJ,
Pl,
iNfOR P3, P20- AD. Pl.
P2'_j
INTERRUPT - - INTACK OR P32 P2s ............ AD, Pl,
MASTER CPU _ _ lEI OR P30 P24 ........... AD, Pl,
lEO OR P3, P2, PORT 2 AD, Pl,
\
P22 AD2 P12
PCLK ----+- P2, AD, Pl,
P20 ADo Plo

Figure 1. Pin Functions Figure 2. Pin Assignments

253
Description The Z-UPC Universal Peripheral Controller accumulators, address pointers, index regis-
(Continued) is an intelligent device that generates all the ters, or stack. Registers not used as buffer are
control signals peripheral devices need. protected against CPU access.
Because it does off-line arithmetic, translates The register file is divided into 16 groups of
data before transmitting, and buffers data, the 16 working registers each. A register pointer
Z- UPC unburdens the master CPU, thereby allows fast, short-format instructions to access
increasing the overall speed and efficiency of anyone of these groups quickly, resulting in
the system in which it resides. fast and easy task switching. Two-way com-
Based upon the Z8 microcomputer architec- munication between the master CPU and the
ture, the Z-UPC offers fast execution time, effi- register file is facilitated by another pointer
cient use of memory, and sophisticated inter- that positions 16 interface registers anywhere
rupt, I/O, and bit manipulation. Its powerful within the register file. These registers are
and extensive instruction types, combined with accessed directly by both the master CPU and
its efficient internal register addressing the slave Z-UPC. Four more registers, similarly
scheme, not only speeds program execution, accessed, convey control and status informa-
but also efficiently packs program into the on- tion.
chip ROM. All of Z-Bus's daisy-chained priority inter-
A unique characteristic of the Z- UPC is its rupt system can be implemented in the Z- UPC
register file, which contains I/O port and con- under software control, or the Z-UPC can be
trol registers that can be accessed both by the programmed to function in a polled
Z-UPC program and by its associated master environment. In all, the Z-UPC has 24 pins
CPU. This results in byte efficiency, program- that can be dedicated to I/O functions.
ming efficiency, and address space efficiency Grouped logically into three 8-line ports, they
because Z- UPC instructions can operate direct- can be programmed in many combinations of
lyon I/O data without moving it to and from inputs, outputs, and bidirectional lines, with or
an accumulator. It also allows the Z- UPC user without handshake and with push-pull or open-
to allocate as data buffer between the CPU and drain outputs.
the peripheral all register space not in use as

HOST CPU INTERFACE

PROGRAM
MEMORY 110
INTERFACE
REGISTERS 2K)(8
(PART OF REGISTER
FILE)
HANDSHAKE

r
110
Z·BUS TO
MASTER
CPU

T'N
TOUT

(110 OPTIONAL
CONTROL FUNCTION)

Voo Vss CLOCK

Figure 3. Z-UPC Functional Block Diagram

254
 Z8036 Z-CIG
CoDDler/Timer aad
ParaDeI I/O Unit

~
Zilog
Product
Brief
Features • Two independent 8-bit double-buffered • Three independent l6-bit counters.
bidirectional I/O ports plus a special- • All registers read/write and directly
purpose 4- bi t I/O port. addressable.
• Four handshake modes including 3-wire. • Flexible pattern recognition logic, program-
• Request/Wait line for high speed data mable as l6-input interrupt controller.
transfer.

Description The Z8036 CIO Counter/timer and Parallel byte port or a bit port. In the bit mode, data
I/O element is a general-purpose peripheral direction is programmable bit by bit. In the
circuit that satisfies most counter/timer and handshake mode, the ports can be input, out-
parallel I/O needs encountered in system put, or bidirectional, and they may be linked
deSIgns. ThIs versatIle deVIce contams three to form a 16-bit port. The four handshake
I/O ports and three counter/timers. Many pro- modes include 3-wire (like IEEE-488),
grammable options tailor its configuration to interlocked (for interfacing to a Z-UPC, Z-FIO
specific applications. The use of the device is or another Z-CIO), strobed, and pulsed. The
Simplified by making all internal registers pulsed mode connects one counter/timer with
(command, status, and data) readable and the handshake logic for interfacing a
(except for status bits) writable. Also, each mechanical device such as a printer. The 4-bit
register is given its own unique address so it port provides handshake controls, special
can be accessed directly-no special sequen- controls (Wait/Request) or general-purpose I/O.
tial operations are required. The Z-CIO is The counter/timer section contains three
directly Z-Bus compatible. l6-bit counters, two of which can be software-
Either 8-bit I/O port can be a handshake configured as a 32-bit counter/timer. Up to

~)~.,.
AD, PA,

AD~~l~
AD, AD,
AD. PA.
ADs AD,
AD, PAs AD,
AD.
AD, PA,
AD, ADo
DATA

--- Gsa
AD, PA 3
BUS --- OS

---
AD, PA,
RIW CS,

---
AD, PA,
GND AS

.
ADo PAc
PB o PAc
BUS { ___ As PB,

~l
Z8036 PB, PA,
TIMING
OS CIO PB.
AND RESET --- PB, PA,

{=:
CONTROL
RfW
cs;;
CS,
PB,
PB,
PB,
PB,
PB,
PB 5
PA,
PA,
PAs
iNr

'""M"~{ =
PB, m PB. PA.
INTACK PB, PB, PA,
lEI PBo PClK INTACK

~}
lEO PC,
lEI iNT
PC,
lEO +5V
PC, ..m PCo PC,
PCo
PC, PC,

t t
PClK +5 V GND

Figure 1. Pin Functions Figure 2. Pin Assignments

255
Description four I/O lines for each counter are available need be accessed often. One register contains
(Continued) for direct external control and status informa- the interrupt vector associated with each port.
tion. All counters have a programmable output To facilitate initialization, the port logic is
duty cycle, continuous or single-cycle oper- designed so that if a capability of the port is
ation, and the counting process can be pro- not required the registers associated with that
grammed to be either retriggered or nonretrig- capability are ignored and need not be pro-
gered. grammed.
Figure 3 shows how the Z-CIO is used. The The function of port C depends upon the
two general purpose 8-bit ports are similar. roles of ports A and B. Port C provides hand-
They can be programmed as handshake shake lines for the other two when required.
driven, double-buffered ports (input, output, Any bits of port C not so used can be used as
or bidirectional) or as control ports in which I/O lines or as external access to the third
the direction of each bit is individually pro- counter/timer.
grammable. Port B can also be specified to Besides the data input and output registers,
provide external access for two of the counter/ three registers are needed. These specify the
timers. Each port includes pattern recognition details of each bit path: data path polarity,
logic allowing interrupt generation when a data direction, and special I/O control.
specified pattern is detected. The pattern The three counter/timers are all identical.
recognition logic can be programmed so that Each is composed of a 16-bit down-counter, a
the port functions like a priority interrupt con- 16-bit time constant register (which holds the
troller. value loaded into the down-counter), a 16-bit
To control these capabilities, each port con- current count register (used to read the con-
tains 13 registers. Three of these, the input, tents of the down-counter), and two 8-bit
output, and buffer registers, are data path registers for control and status (the mode
registers. Two others, the mode specification select and control registers). All three share a
and handshake specification registers, define common vector register.
the mode of the port and specify what hand- Each counter/timer can be programmed as
shake to use, if any. The reference pattern for either counter or timer. Up to four port I/O
the pattern recognition logic is defined in lines can be designated as external access
three registers, the pattern polarity, pattern lines for it. The lines are: Counter Input, Gate
transition, and pattern mask registers. The Input, Trigger Input, and Counter/Timer Out-
detailed characteristics of each bit path (for put. Three different counter/timer output duty
example, the direction of data flow, or whether cycles are available: pulse, one-shot, or
a path is inverting or non inverting) are pro- square wave. The operation of the counter/
grammed using the data path polarity, data timer can be speCified to be either single cycle
direction, and special I/O control registers. or continuous. The counting sequence may be
The primary control and status bits are retriggered or nonretriggered lJ!:.der ;;:-cqrer!1
l

grouped in (j cinglf' register so that after the control.

ports are codigured initially, only this register

A 1\ A~7 P~l ~ 0,
PRINTER
(
'I V ADo PAo V Du
pCo
J HANDSHAKE
AS PC,
OS PC,
PC,
ZB036
CSo cia PB, ) 00"'""
AND
STATUS
CS, PB,
PB,

::: r - - - - , l l l ''i
'
L
Z·BUS

'--
PBl

p_BO.. l i

L-
tNT
CONTROL

NON Z·BUS
PERIPHERAL

Figure 3. Functional Block Diagram

256
 Z8030 Z-SCC Serial
Communications
Controller

~
Zilog
Product
Brief
Features • Two independent, 0 to 1M bit per second, ing error detection.
full-duplex channels, each with its own • Bisynchronous mode with internal or exter-
quartz oscillator, baud-rate generator, and nal character synchronization on one or two
digital phase-locked loop for clock sync characters and CRC generation and
recovery. checking with CRC-16 or CRC-CCITT
• Multi-protocol operation under program preset to either Is or Os.
control. • SDLC/HDLC mode with comprehensive
• Programmable for NRZ, NRZI, or FM frame-level control, automatic zero insertion
coding. and deletion, I-field residue handling, abort
• Asynchronous mode with 5 to 8 bits and 1, generation and detection, CRC generation
11/2 , or 2 stop bits per character, program- and checking, and SDLC loop mode
mable clock factor, brea.k detection a.nd operation.
generation, and parity, overrun, and fram- • Local loopback and auto-echo modes.

Description The Z-SCC Serial Communication Controller external random logic on the circuit card.
is a dual-channel, multi-protocol data com- The Z-SCC handles asynchronous formats,
munication peripheral for Z-Bus use. It is synchronous byte-oriented protocols such as
software-configured to satisfy a wide variety of IBM Bisync, and synchronous bit-oriented pro-
serial communication applications. Its basic tocols such as HDLC and IBM SDLC. This ver-
function is serial-to-parallel and parallel-to- satile device also supports virtually any other
serial conversion. However, the Z-SCC also serial data transfer application (cassette or
contains a repertoire of new, sophisticated diskette interface, for example).
internal functions that minimize the need for The device can generate and check CRC

ADDRESSI
DATA BUS
---- AD,
AD,
ADs
AD,
AD,
AD,
ADs
AD,
ADo
AD 2
AD,
AD,
AD,
CH·A iNT Os

---
AD2 CHANNEL lEO AS
AD, CONTROLS
lEI RIW

----
FOR MODEM,
ADo

BUS
TIMING
l- AS
Os
CTSA
DCDA
DMA,OR
OTHER
INTACK
+5V
WIREQ A
CSo
CS,
GND

I=:
AND RESET -
RIW TxDB SYNCA W/REQ B
} SERIAL
CONTROL CS, RxDB _ _ DATA
RTxCA SYNCB
CSo TRxes -}CHANNEL RxDA RTxCB
iNT RTxCB _ CLOCKS

,~.."""I:::::
RxDB

-\I
TRxCA
INTACK SYNCB TxDA TRxes
lEI WIREQ B CHANNEL CH·B
DTRIREQ A TxDB
lEO DTRJREQ B CONTROLS
RTSA DTR/REQ B
RTSB FOR MODEM,
DMA, OR CTSA RTSB
z:g~o

-
CTSB _ OTHER
DCDA CTSB
DCDB PCLK DCDB

t t t
+ 5 V GND PCLK

Figure 1. Pin Functions Figure 2. Pin Assignments

257
Description codes in any synchronous mode and can be The read and write register group for each
(Continued) programmed to check data integrity in various channel includes ten control registers, two
modes. It also has facilities for modem controls sync-character registers, and four status
in both channels. In applications where these registers. Each baud rate generator has two
controls are not needed, the modem controls read/write registers for holding the time con-
can be used for general-purpose I/O. stant that determines baud rate. Associated
As is standard among Zilog peripheral com- with the interrupt logic is a write register for
ponents, the Z-Bus daisy-chain interrupt interrupt vector and three read registers: vec-
heirarchy is supported. tor with status, vector without status, and inter-
The Z-SCC contains the necessary multi- rupt pending status.
plexed address/data bus interface with strobe The logic for both channels provides format-
and chip select lines to function as a Z-Bus ting, synchronization and validation for data
peripheral. It includes internal control and transferred to and from the channel interface.
interrupt logic, two full-duplex channels and The modem control inputs are monitored by
two baud-rate generators. Associated with the control logic under program control. All of
each channel are several read and write the modem control signals are general purpose
registers for mode control as well as the logic in nature and optionally can be used for func-
necessary to interface to modems or other tions other than modem control.
external devices.

INTERNAL
CONTROL
lOGIC

_ } MOOEM, DMA, OR
OTHER CONTROLS
ADDRESS/
DATA
CPU
BUS 110

CONTROL

-} MODEM, DUA, OR
OTHER CONTROLS

INTERRUPT INTERRUPT
CONTROL CONTROL
LINES LOGIC
I SERIAL DATA

_ I CHANNEL CLOCKS

SYNC
WAIT/REQUEST

Figure 3. Functional Block Diagram

Typical Figure 4 shows how a Z-SCC can be con-

Applications nected with channel A programmed for the
Synchronous Data Link Control (SDLC) Loop
mode, functioning as a secondary station. If
NRZI or FM coding is used, no clock lines are
required because the clock can be recovered
CHANNEL
A
{
TxOA
~
RxOA _
t>J} SDLC
LOOP

from the received data, using the Z-SCC's on-

chip digital phase locked loop (DPLL). ZB030
SCC
Another Z-SCC (not shown), programmed for
hOB
the SDLC mode, would be the controlling sta- TRxCB
tion, polling the loop for traffic. The figure
shows a typicaL asynchronous serial port "':'" I RTxCB
RxOB
MODEM _ } DATA
LINK

being serviced by channel B of the Z-SCC. It }

could just as well support another synchronous l CONTROL

data link, or even a high-speed link, transfer-

ring data via a DMA controller. Figure 4. Loop Secondary Station and Serial Port

258
 Z8038 z-no
FIFO Inpal/Gatput
Interface 1JDit

~
Zilog
Product
Brief
Features • Asynchronous bidirectional FIFO buffer, • Preset byte count in FlO buffer can inter-
used with most major microprocessors as rupt CPU.
CPu/CPU or CPU/peripheral interface.
• All registers directly addressable.
• Interlocked 2-wire or 3-wire handshake port • Vectored/non-vectored interrupts on
mode; Empty, Full, and Request/Wait lines pattern/status match, over/underflow error,
for high-speed data transfer. buffer status.
• 128 x 8 organization, expandable to any
width; cascadable to any depth.

Description The Z-FIO is a general-purpose micro- words as well as bytes. This bidirectional
processor interface that provides elastic buffer- device accepts data and holds it until it can be
ing bet-vvecn a.synchronous CPUs in a parallel- used by another device in the system. In most
processor network or between CPU and I/O transactions, introducing a l28-deep buffer
peripheral circuits. The Z-FIO can interface a cuts interrupt servicing overhead by two
Z-Bus microprocessor or any other major pro- orders of magnitude.
cessor to another microprocessor or to a The Z-FIO greatly facilitates system
peripheral circuit or port. throughput by moving variable-size blocks
In Z8000 systems, the FlO furthers dis- under either direct memory access or interrupt
tributed-processor operation because it can control-an especially important consideration
interconnect components or subsystems when fast peripheral circuits need interfacing.
operating at different speeds. Also, it can Complete status information is also provided
increase system throughput by transferring for operation in polled environments.

+5V

0, Do
0,
0,
0,
0,
0,
D.
M, 07
Mo

+5V GND

Figure 1. Pin Functions Figure 2. Pin Assignments

259
Pin Z-Bus Z-Bus 2-Wire 3-Wire
Assignments Low Byte High Byte Non-Z-Bus HS Port'" HS Port'"

[K] REO/WT REO/WT REO/WT RFD/DA'l RFDDAV

[I] DMASTB DMASTB DACK ACKIN DAVDAC
@] J5S i5S R5 FULL DACRFD
@] R/W R/W WR EMPTY EMPTY
~ CS CS CS CLEAR CLEAR
[!] :AS" :AS" C/i) DATA DIR DATADIR
@J INTACK Ac INTACK IN IN,
~ lEO A, lEO OUT, OUT,
ITJ lEI A" lEI ill ill
CD ];>-JT Aj INT OUT, OUT

'Port 2 side only. See table below.

Description The internal functions of the Z-FIO are address the buffer RAM, and also are fed into
(Continued) shown in the block diagram (Figure 3). It is a subtractor to determine the current number
made up of two ports that are identical except of bytes in the memory. This number can be
for programming. The port programmed by read by either CPU from a status register
pins Mo and M I is called Port 1; the port pro- dedicated to each port. Another programmable
grammed by bits Bo and Bl is called Port 2. register is compared against the status register
Each port of the FlO has sixteen program- to generate interrupts and/or start and stop
mable registers that define operating protocols DMA transfers. A pair of port registers allows
and pin signals. Common to both ports, and for communication between CPUs, bypassing
situated between them, is the 128 x 8 RAM the main buffer memory.
used for data storage. The RAM is capable of Operating Modes. The Z-FIO has twelve
simultaneous, independent read and write different programmable modes (Table below).
operations. This means, for example, that the The states of two package pins determine the
Port 1 CPU can write a byte of data into the mode of operation of Port 1, and Port 2 is pro-
FlO without disturbing a simultaneous read grammed by two bits (Bo and Bl) in one of the
operation by the Port 2 CPU. The outputs of Port 1 control registers.
the read and write counters are used to

TO
Z·BUS
OR GENERAL
MICROPROCESSOR
OR
PORT WITH
HANDSHAKE

Figure 3. Functional Block Diagram

Operating Mode MI MO BO
Modes
Z·Bus Low Byte Z·Bus Low By!e
Z· Bus Low Byte Non·Z·Bus
Z·Bus Low Byte 3Wlre HS
Z· Bus Low Byte 2·Wire HS

Z·Bus High Byte Z-Bus High Byte

Z· Bus High Byl.e Non·Z·Bus
Z·Bus High Byte 3·Wire HS
Z·Bus High Byte 2·Wlre HS

Non·Z·Bus Z Bus Low Bylp

Non·Z·Bus Non-Z-Bus Low Byte

10 Non·Z·Bus 3·Wire HS
Nun-Z-Bus 2-Wire HS

260
 Z8060
Z-FIFO Baffer Vllil
aad z.no Expaader

~
Zilog
Product
Brief
Features • Asynchronous, bidirectional first-in, first-out • 3-state data outputs.
buffer. • Empty and Full status pins are wire-ORed
• Extends depth of Z-FIO without limit. among multiple stages.
• 128 x 8 organization.

Description The Z-FIFO first-in, first-out buffer unit is a

128 x 8-bit memory with bidirectional data
transfer capability and handshake logic. Its
structure is similar to that of other FIFOs that
0, : 0'_)
DO, PORT I PORT
5 1 2
~'5 -
...........

are commonly available, such as the AM2812 DATA - 0, : 0, DATA

1
BUS 0 I 03 BUS
and the 3351. The handshake logic used is _ 0,3 Z8060 0,_
compatible with that of the Z8, the Z-CIO, and -0, FI~O 0,_
Z-FIO. Z-FIFO buffers can be cascaded, end to \ - 00 I 0o-J
ACKIN I ACKIN _ _ }
end, without limit, their RFD/DAV and ACKIN
CONTROL . . /D
_ _ RFO/DAv : RF.O ..AV _ CONTROL
signals daisy-chained, to make a FIFO array { OUTPI,IT I OUTPUT
any desired number of words deep. Two such ---- E~~r:...l ~~·~E - -
AlBIN
channels in parallel, suitably controlled, make
COMMON - - FULL
up a 16-bit-wide buffer array. CONTROL EMPTY
{
RESET

+SV GNO

Figure 1. Pin Functions

ANY NUMBER OF FIFOS

.-----..., ,....------,

TO Z·BUS TO Z·BUS
OR GENERAL OR QENERAL
MICROPROCESSOR MICROPROCESSOR

Figure 2. Using nFOs to Extend nos

261
 c
.-
 Appendix C
Clock Cycles·

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS SS SL NS SS SL
ADC R,src R Add with Carry
ADCB R - R + src + carry
ADD R,src R 4 4 4 8 8 8 Add
ADDB 1M 7 7 7 14 14 14 R - R + src
ADDL 1R 7 7 7 14 14 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
AND R,src R 4 4 4 AND
ANDB 1M 7 7 7 R - RAND src
IR 7 7 7
DA 9 10 12
X 10 10 13
BIT dst,b R 4 4 4 Test Bit Static
BITB 1R 8 8 8 Z flag - NOT dst bit specified by b
DA 10 II 13
X II II 14
BIT dst,R R 10 10 10 Test Bit Dynamic
BITB Z flag - NOT dst bit specified by
contents of R
CALL dst IR 10 15 l:i Call Subroutine
DA 12 18 20 Autodecrement SP
X 13 18 21 @ SP - PC
PC - dst
CALR dst RA 10 15 15 Call Relative
Autodecrement SP
@ SP - PC
PC - dst (range PC - 4094 to PC
+4096)
CLR dst R 7 7 7 Clear
CLRB 1R 8 8 8 dst - 0
DA II 12 14
X 12 12 15
COM dst R 7 7 7 Complement
COMB IR 12 12 12 dst - NOT dst
DA 15 16 18
X 16 16 19
COMFLG flags 7 7 7 Complement Flag
(Any combination of C, Z, S, PIV)
CP R,src R 4 4 4 8 8 8 Compare with Register
CPB 1M 7 7 7 14 14 14 R - src
CPL IR 7 7 7 14 14 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
CP dst,1M IR II II II Compare with Immediate
CPB DA 14 15 17 dst - 1M
X 15 15 18
* NS = Non-Segmented, SS = Shorl Segmented Offset. SL =Segmented Long Offset. Blank = Not Implemented.

265
 Clock Cycles
Mnemonics Operands Addr. Word. Byte Long Word Operation
Modes NS SS SL NS SS SL

CPD RX,src,Ry,cc IR 20 20 20 Compare and Decrement

CPDB RX - src
Autodecrement src address
Ry - Ry - 1
CPDR Rx,src,Ry,cc IR 01 + 9n) Compare. Decrement and Repeat
CPDRB Ry - src
Autodecrement src address
Rx - Ry - I
Repeat until cc is true or Ry = 0
CPI RX,src,Ry,cc IR 20 20 20 Compare and Increment
CPIB RX - src
Autoincrement src address
Ry - Ry - 1
CPIR RX,src,Ry,cc IR 01 + 9n) Compare. Increment and Repeat
CPIRB RX - src
Autoincrement src address
Ry - Ry - 1
Repeat until cc is true or Ry = 0
CPSD dst,src,R,cc IR 25 25 25 Compare String and Decrement
CPSDB dst - src
Autodecrement dst and src addresses
R - R- 1
CPSDR dst,src,R,cc IR 01 + 14n) Compare String. Deer. and Repeat
CPSDRB dst - src
Autodecrement dst and src addresses
R-R-l
Repeat until cc is true or R = 0
CPSI dst,src,R,cc IR 25 25 25 Compare String and Increment
cpsm dst - src
Autoincrement dst and src addresses
R-R-l
CPSIR dst,src,R,cc IR 01 + 14n) Compare String. Incr. and Repeat
CPSIRB dst - src
Autoincrement dst and src addresses
R-R-l
Hepeat untJi cc 1S true or R = 0

DAB dst R Decimal AdjUllt

DEC dst,n R 4 4 4 Decrement by n
DECB IR 11 II II dst - dst - n
DA 13 14 16 (n = 1...16)
X 14 14 17
DI* int Disable Interrupt
(Any combination of NV!, VI)
DIV R,src R 10'1 107 107 '/44 744 744 Divide (signed)
DIVL 1M 107 107 107 744 744 744 Word: Rn + 1- Hn,n -'- I -i- src
IR 101 1U'J 10'1 744 '/44 '/44 Rn - remainder
DA 108 109 ill 745 746 '148 Long Word: Rn + 2,n .;- 3- Rn... n + 3 7 src
X 109 1m lU 746 746 749 Rn,n + 1- remainder
*Privileged instruction. Executed in system mode only.

266
 Clock Cycles
Mnemonics Operands Addr. Word. Byte Long Word Operation
Modes NS 55 SL NS 55 SL

DJNZ R,dst RA 11 11 11 Decrement and Jump if Non-Zero

DBINZ R-R-l
If R *- 0: PC - dst(range PC - 252 to PC + 2)
EI* int Enable Interrupt
(Any combination of NVI, VI)
EX R,src R 6 6 6 Exchange
EXB IR 12 12 12 R - src
DA 15 16 18
X 16 16 19
EXTS dst R 11 11 11 11 11 11 Extend Sign
EXTSB Extend sign of low order half of dst
EXTSL through high order half of dst
HALT* ( 8 + 3 n) HALT
IN* R,src IR 10 10 10 Input
INB* DA 12 12 12 R - src
INC dst,n R 4 4 4 Increment by n
INCB IR 11 11 11 dst - dst + n
DA 13 14 16 (n = 1...16)
X 14 14 17
IND* dst,src,R IR 21 21 21 Input and Decrement
INDB* dst - src
Autodecrement dst address
R-R-l
INDR* dst,src,R IR (11 + IOn) Input. Decrement and Repeat
INDRB* dst - src
Autodecrement dst address
R-R-l
D .... __ ~ ....... _.j.~1 D _ f'I
.
~~C"t-I'C;::;;U~ U.l..LlJ. .L ~l - v

Im* dst,src,R IR 21 21 21 Input and Increment

INIB* dst - src
Autoincrement dst address
R-R-l
INIR* dst,src,R IR (11 + 1On) Input. Increment and Repeat
INIRB* dst - src
Autoincrement dst address
R-R-l
Repeat until R = 0
IRET* 13 16 16 Interrupt Return
PS - @ SP
Autoincrement SP
JP cC,dst IR 10 15 15 (taken) Jump Conditional
IR 7 7 OJ (not taken) If cc is true: PC - dst
DA 7 8 10
X 8 8 11
JR cC,dst RA 6 6 6 Jump Conditional Relative
If cc is true: PC - dst
(range PC - 256 to PC + 254)
*Privileged instruction. Executed in system mode only.

267
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes N5 55 5L N5 55 5L

LO R,sre R 3 3 5 5 5 Load into Register

LOB 1M 7 7 11 11 11 R - sre
LOL 1M 5 (byte only)
IR 7 7 7 11 11 11
DA 9 10 12 12 13 15
X 10 10 13 13 13 16
BA 14 14 14 17 17 17
BX 14 14 14 17 17 17
LO dst,R IR 8 8 8 11 11 11 Load into Memory (Store)
LDB DA 11 12 14 14 15 17 dst - R
LOL X 12 12 15 15 15 18
BA 14 14 14 17 17 17
BX 14 14 14 17 17 17
LO dst,IM IR 11 11 11 Load Immediate into Memory
LOB DA 14 15 17 dst - 1M
X 15 15 18
LOA R,sre DA 12 13 15 Load Address
X 13 13 16 R - address (sre)
BA 15 15 15
BX 15 15 15
LOAR R,sre RA 15 15 15 Load Address Relative
R -address (sre)
LOCn* CTLR,sre R Load into Control Register
CTLR - sre
LDCn* dst,CLTR R Load from Control Register
dst - CTLR
LOCnB FLAGS,sre R Load into Flag Byte Register
FLAGS - sre
LOCTLB dst,FLAGS R Load from Flag Byte Register
dst - FLAGS
LOO dst,sre,R IR 20 20 20 Load and Decrement
LOOB dst - sre
Autodeerement dst and sre addresses
R-R+l
LOOR dSI,sre,R IR (11 -to 9 n) Load. Decrement and Repeat
LOORB dst ~ sre
Autodeerement dst and sre addresses
R-R-l
Repeat until R = 0
LOI dst,sre,R IR 20 20 20 Load and Increment
LDIB dst - sre
Autoinerement dst and sre addresses
R-R-l
LOIR dst,sre,R IR (11 ... 9 n) Load. Increment and Repeat
LOIRB dst - sre
Autoinerement dst and sre addresses
R-R-I
Repeat until R = 0

268
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS 55 SL NS 55 SL

LDK R,src 1M Load Constant

R - n (n = 0 .. 15)
LDM R,src,n IR II II I] Load Multiple
DA 14 15 17 + 3n dst - src (n consecutive words)
X 15 15 18 (n = 1...16)
LDM dst,R,n IR II II II Load Multiple (Store Multiple)
DA 14 15 17 + 3n dst - R (n consecutive words)
X 15 15 18 (n = 1...16)
LDPS* src IR 12 12 12 Load Program Status
DA 16 20 22 PS - src
X 17 20 23
LDR R,src RA 14 14 14 17 17 17 Load Relative
LORB R - src
(range -32768 . . + 32767)
LOR dst,R RA 14 14 14 17 17 17 Load Relative (Store Relative)
LORB dst - R
LDRL (range -32768... + 32767)
MBIT* Test Multi-Micro Bit
Set if MI is Low; reset S if MI is High.
MREQ* dst R (12 + 7n) Multi-Micro Request
MRES* 5 Multi-Micro Reset
MSET* 5 Multi-Micro Set
MULT R,src R 70 70 70 282 + 282 + 282 + Multiply (signed)
MULTL 1M 70 70 70 282 + 282 + 282 + Word: Rn,n+ 1- Rn + I X src
IR 70 70 70 282 + 282 + 282 + Long Word: Rn ... n+3-Rn+2, n+3x src
D1'>, 71 72 74 283 + 283.j. 286.j. -l- Plus seven cycles for each 1 in the

X 72 72 75 284 + 284 + 287 + absolute value of the low order 16 bits of the
multiplicand.
NEG dst R 7 7 7 Negate
NEGB IR 12 12 12 dst - 0 - dst
DA 15 16 18
X 16 16 19
NOP No Operation
OR R,src R 4 4 4 OR
ORB 1M 7 7 7 R - R OR src
IR 7 7 7
DA 9 10 12
X 10 10 13
OTDR* dst,src,r IR (II + 10 n) Output. Decrement and Repeat
OTDRB* dst - src
Autodecrement src address
R-R-I
Repeat until R = 0
*Privileged instructions. Executed in system mode only.

269
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS SS SL NS SS SL

orm* dst,src,R IR (II + 10 n) Output. Increment and Repeat

OTIRB* dst - src
Autoincrement scr address
R-R-I
Repeat until R = 0
OUT* dst,R IR 10 10 10 Output
OUTB* DA 12 12 12 dst - R
OUTD* dst,src,R IR 21 21 21 Output and Decrement
OUTDB'" dst - src
Autodecrement src address
R-R-I
OUTI* dst,src,R IR 21 21 21 Output and Increment
OUTIB* dst - src
Autoincrement src address
R-R-I
POP dst,IR R 8 8 8 12 12 12 Pop
POPL IR 12 12 12 19 19 19 dst - IR
DA 16 16 18 23 23 25 Autoincrement contents of R
X 16 16 19 23 23 26
PUSH IR,src R 9 9 9 12 12 12 Push
PUSHL 1M 12 12 12 Autodecrement contents of R
IR 13 13 13 20 20 20 IR - src
DA 14 14 16 21 21 23
X 14 14 17 21 21 24
RES dst,b R 4 4 4 Reset Bit Static
RESB IR II II II Reset dst bit specified by b
DA 13 14 16
X 14 14 17
RES dst,R R 10 10 10 Reset Bit Dynamic
RESB Reset dst bit specified by contents of R
RESflG flag Reset Flag
(Any combination of C, Z, S, PIV)
RET cc 10 10 13 (taken) Return Conditional
7 7 7 (not taken) If cc is true: PC - @ SP
Autoincrement SP
RL dst,n R 6 for n =I Rotate Left
RLB R 7 for n =2 by n bits (n = L 2)
RLC dst,n R 6 for n =I Rotate Left through Carry
RLCB R 7 for n =2 by n bits (n = I, 2)
RLDB R,src R 9 9 Rotate Digit Left
RR dst,n R 6 for n '" I Rotate Right
RRB R 7 for n '" 2 by n bits (n = I, 2)
RRC dst,n R 6 for n = I Rotate Right through Carry
RRCB R 7 for n = 2 by n bits (n = L 2)
·Prlvlleged instruction. Executed in system mode only.

270
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS SS SL NS SS SL

RRDB R,src R Rotate Digit Right

SBC R,src R Subtract with Carry
SBCB R - R - src - carry
SC src 1M 33 39 39 System Call
Autodecrement SP
@ SP - old PS
Push instruction
PS - System Call PS
SDA dst,R R (15 + 3n) (15 + 3n) Shift Dynamic Arithmetic
SDAB Shift dst left or right
SDAL by contents of R
SDL dst,R R (15 + 3n) (15 + 3n) Shift Dynamic Logical
SDLB Shift dst left or right
SDLL by contents of R
SET dst,b R 4 4 4 Set Bit Static
SETB IR II II II Set dst bit specified by b
DA 13 14 16
X 14 14 17
SET dst,R R 10 10 10 Set Bit Dynamic
SETB Set dst bit specified by contents of R
SETFLG flag Set Flag
(Any combination of C, Z, S, PIV)
SIN* R,src DA 12 12 12 Special Input
SINB* R - src
SIND* dst,src,R IR 21 21 21 Special Input and Decrement
SINDB* dst - src
Autodecrement dst address
R - R - I
SINDR* dst,src,R IR (11 + IOn) Special Input. Decrement and Repeat
SINDRB* dst - src
Autodecrement dst address
R-R-I
Repeat until R = 0
SINI* dst,src,R IR 21 21 21 Special Input and Increment
SINIB* dst - src
Autoincrement dst address
R - R - I
SINIR* dst,src,R IR (11 + IOn) Special Input. Increment and Repeat
SINIRB* dst - src
Autoincrement dst address
R-R-I
Repeat until R = 0
SLA dst,n R (13 + 3n) (13 + 3n) Shift Left Arithmetic
SLAB by n bits
SLAL
SLL dst,n R (13 + 3n) (13 + 3n) Shift Left Logical
SLLB by n bits
SLLL
*Privileged instruction. Executed in system mode only.

271
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS SS SL NS SS SL

SOTDR* dst,src,R IR (II + 10 n) Special Output. Deer. and Repeat

SOTDRB* dst - src
Autodecrement src address
R-R-I
Repeat until R = 0
SOTIR* dst,src,R R (II + 10 n) Special Output. Incr. and Repeat
SOTIRB* dst - src
Autoincrement src address
R - R - I
Repeat until R = 0
SOUT* dst,src DA 12 12 12 Special Output
SOUTB* dst - src
SOUTD* dst,src,R IR 21 21 21 Special Output and Decrement
SOUTDB* dst - src
Autodecrement src address
R-R-I
SOUTI* dst,src,R IR 21 21 21 Special Output and Increment
SOUTIB* dst - src
Autoincrement src address
R-R-I
SRA dst,n R (13 + 3 n) (13 + 3 n) Shift Right Arithmetic
SRAB by n bits
SRAL
SRL dst,n R (l3 + 3 n) (13 + 3 n) Shift Right Logical
SRLB by n bits
SRLL
SUB R,src R 4 4 4 8 8 8 Subtract
SUBB 1M 7 7 7 14 14 14 R - R - src
SUBL lR 7 7 7 14 14 14
DA 9 10 12 15 16 18
X 10 10 13 16 16 19
TCC cC,dst R 5 5 Test Condition Code
TCCB Set LSB if cc is true
TEST dst R 13 13 Test
TESTB IR 8 13 dst OR C
''"'
DA II 12 11 17 19
X 12 12 15 17 20
*Privileged instructions, Executed in system mode only.

272
 Clock Cycles

Mnemonics Operands Addr. Word. Byte Long Word Operation

Modes NS SS SL NS SS SL

TRDB dst,src,R IR 25 25 25 Translate and Decrement

dst - src(ds!)
Autodecrement dst address
R-R-I
TRDRB dst,src,R IR (11 + 14n) Translate. Decrement and Repeat
dst - src (ds!)
Autodecrement dst address
R-R-I
Repeat until R = 0
TRIB dst,src,R IR 25 25 25 Translate and Increment
dst - src(dst)
Autoincrement dst address
R-R-I
TRffiB dst,src,R IR (11 + 14n) Translate. Increment and Repeat
dst - src(dst)
Autoincrement dst address
R-R-l
Repeat until R = 0
TRTDB srcl ,src2,R IR 25 25 25 Translate and Test. Decrement
RHI +- src2 (srcl)
Autodecrement src I address
R-R-I
TRTDRB srcl ,src2, R IR (11 + 14n) Translate and Test. Decr. and Repeat
RHI - src2 (srcl)
Autodecrement src I address
R-R-I
Repeat until R = 0 or RH I
TRTIB src 1,src2,R IR 25 25 25
'*
Translate and Testr Increment
RHI - src2 (src 1)
Autoincrement src address
R-R-I
TRTIRB srcl,src2,R IR (11 + 14n) Translate and Test. Incr. and Repeat
RHI - src2 (srcl)
Autoincrement src I address
R - RI
Repeat until R = 0 or RH I U
TSET dst R 7 7 7 Test and Set
'*
TSETB IR II II II S flag - MSB of dst
DA 14 15 17 dst - allIs
X 15 15 18
XOR R,src R 4 4 4 Exclusive OR
XORB 1M 7 7 7 R - R XOR src
IR 7 7 7
DA 9 10 12
X 10 10 13

273
 LOWER NIBBLE (HEX). UPPER INSTRUCTION BYTE
0 I 2 3 4 5 6 7 8 9 A B C 0 E F
ADDB ADD SUBB SUB ORB OR ANDB AND XORB XOR CPB CP See See EXTEND EXTEND
R-IR R - IR R -IR R -IR R -IR R -IR R -IR R - IR R -IR R -IR R -IR R - iR Table Table INST INST
R -1M R -1M R -1M R -1M R -1M R -1M R -1M R -!M R -1M R -1M R - 1M R -1M I I

CPL PUSHL SUBL PUSH LOL POPL ADDL POP MULn MULT DIVL DIV See LDL JP CALL
R-IR IR-IR R-IR IR-IR R-IR IR -IR R - IR IR -IR R - IR R - IR R - IR R - IR Table IR-R PC-IR PC-IR
R -1M R -1M R - 1M R - 1M R -1M R -1M R -1M R -1M 2

LOB LO RESB RES SETB SET BITB BIT INCB INC DECB DEC EXB EX LOB LD
R -IR R -IR IR -1M IR -1M IR - 1M IR -1M IR - 1M iR -1M IR -1M IR - 1M IR -1M IR - 1M R-iR R-IR IR-P IR-R
R -1M R -1M R - R R - R R-R R - R R-R R - R

LOB LO LOB LD LOA LOL RSVD LOL RSVD LOPS See See INB IN OUTB OUT
R - SA R - SA SA - R SA - R R - SA R - SA SA - R IR Table Table R-IR R-IR lR-R IR-R
LORB LOR LDRB LOR LDAR LORL LDRL 3 3
R - RA R - RA RA - R RA - R R - RA R - RA RA - R
ADDB ADD SUBB SUB ORB OR ANDB AND XORB XOR CPB CP See See EXTEND EXTEND
R-X R - X H-X H-X R-X R-X R - X R - X A - X R-X R - X R - X Table Table INST INST
R - DA R - DA R - DA R - DA R - DA R - DA R - DA R - DA R - DA R - DA R - DA R - DA I I

CPL PUSHL SUBL PUSH LDL POPL ADDL POP MULn MULT DIVL DIV See LOL JP CALL

5
Z
5
R-X
R - DA
IR - X
IR - DA
R-X
R - DA
IE - X
IA - DA
R-X
R - DA
IR -
IR -
X
DA
R - X
R - DA
IR - X
IR -DA
R - X
R - DA
R-X
R - DA
R - X
R - DA
h - X Table X-A
DA-R
PC-X
PC-DA
PC-X
PC-DA
0 LO
;:: LOB RESB RES SETB SET BITB BIT INCB INC DECB DEC EXB EX LOB LO
U 6 R-X R - X X - 1M X -1M X -1M X -1M X -1M X -1M X -1M X -!M X -!M X - 1M A-X A-X X-R X-R
::J R - DA R - DA DA -1M DA -1M DA -1M DA -1M DA -1M DA -1M DA -1M DA -1M DA -1M DA -1M R-DA R-DA DA-R DA-R
~ 10
!i LOB LOB LD LOA LDL LOA LOL RSVD LOPS HALT See EI See RSVD SC
A - SX R....... BX SX - R SX - R R - BX R - BX R - X SX - R PS - X Table 01 Table
~ 7 R - DA PS - DA 7 7
~
ADDB ADD SUBB SUB ORB OR ANDB AND XORB XOR CPB CP See See EXTEND EXTEND

~ 8
R-R R-R R - R R - R R - R R -R R - R R - R R - A R-R 8 - R R - R Table
I
Table
I
INST. INST.

~
::i: 9
CPL
1'. - R
PUSHL
11'. - R
SUBL
R - R
PUSH
IR - R
LDL
R-R
POPL
R - IR
ADDL
1'. - R
POP
1'. - 18
MULn
R - R
MULT
1'. -R
DIVL
R - R
DIV
R - R
See
Table
RSVD RET
PC-ISP'
RSVD

2
!5
g: INC DECB EXB EX TCCB TCC
::J LOB LO RESB RES S,ETB SET BITB BIT INCB DEC
A 1'. - R R - R R -1M R -1M R - 1M R- 1M R -1M R -1M R - 1M H - 1M R -1M R - 1M H-R 1'.-R A

DAB EXTS See See ADCB ADC SBCB SBC See RSVD See See RHOB LOI RLOB RSVD
EXTSB Table Table R - R H - R R -H R - H Table Table Table A P-IM P
~SL 4 4 5 6 6

LOB
C R - 1M

CALR
D PC - RA

IR
PC - RA

DIJIZ
DBIJIZ
PC - RA

Op Code Map

Notes:
I) Reserved Instructions (RSVD) should not be
used. The result of their execution is not defined.
2) The execution of an extended instruction will
result in an Extended Instruction Trap if the EPA
bit in the FCW is a zero. If the flag is a one the
Extended Instruction will be executed by the EPU
function.
3) The zaooo CPU will interpret any bit pattern
(including reserved and undocumented opcodes.
and illegal register endings) as some other cor-
rectly encoded instruction, and either execute
that instruction or generate a trap (e.g. if the new
instruction is a privileged instruction and the
CPU is in normal mode). Non-documented in-
struction encodings will be used in future 28000
Family CPUs to extend the instruction set.

274
 oc 00 4C 40 8C 80 3A 3B
COMB COM COMB COM COMB COM INIB 1NI
IR IR X X R R IR-IR IR-lR
DA DA lNIRB INIR
lR-lR IR-lR
CPB CP CPB CP LDCTLB SETFLG
lR.IM lR,IM KIM X.IM R-FLGS 51mB SlNI
DA,IM DA,IM IR-IR lR-lR

'"...>- NEGB NEG NEGB NEG NEGB NEG

SlNIRB
IR-lR
SINIR
IR-lR
III 2 lR lR X x R R
Z DA DA oum OUT!
~
U RSVD RSVD RSVD RSVD RSVD RESFLG
lR-IR IR-lR
OTIRB OUTIR
~ 3 IR-IR IR-IR

~ soum SOUT!
TESTB TEST TESTB TEST TESTB TEST IR-IR IR-lR
ffi IR IR x X R R SOTIRB SOTIR
~ DA DA IR-lR IR-lR

LOB LO LOB LO RSVD COMFLG INB IN

><
~ IR-IM lR-IM X-1M X-1M R-DA R-DA

.'"
5
DA-IM DA-IM

III TSETB TSET TSETB TSET TSETB TSET

III
z: 6 IR lR X X R R SINB SIN
DA DA R-DA R-DA
ffi
:t RSVD RSVD RSVD RSVD RSVD NOP
o
.. 7
OUTB OUT
DA-R DA-R
CLRB CLR CLRB CLR CLRB CLR
lR lR X X R R
DA DA
SOUTB SOUT
PUSH LDCnB DA-R DA-R
1M FLGS-R

L-- - INDB IND

lR-lR IR-IR
Table I. INORB INOR
lR-IR IR-lR

SINDB SIND
...'" r--r-nMI
I R"=---IR I
r--r-nMI ... ... ......

~
--'>-
i><1Il
SINORB SINOR
R-DA lR-IR IR-lR
"'z
eo
I ~TL I
"';:: TESTL TESn OUTOB OUTO
;~
8 IR X IR-lR IR-lR
JA OTORB OTOR
Z ...
lR-IR IR-IR
ffi~ 9
LOM
lR-R
LOM
X-R
:til: SOUTOB SOUTO
0'" JA-P
.. :t IR-IR IR-IR
SOTORB SOTOR
9 IR-rR IR-IR

Table 2.

Table 3.

275
 B2 B3 B8 BA BB 7B 70

RLB RL TRIB CPIB CPI IRET RSVD

PC -,SSP
(l bit) (l bit)
R R
LOIB LOI
RSVD lR-II-<. lR-iF. RSVD RSVD
SLLB SLL
LOIRB LOIR
R R
lR-IF lR-iF
SRLB SRL
R R
TRTIB CPSIB CPSI RSVD LDCTL
IF Ii'. F.-FC"V
RLB RL
(2 bits) (2 bits)
R R
RSVD RSVD RSVD RSVD LDCTL
SOLB SOL
R R

TRIRB CPRIB CPIR RSVD LDCTL

IR IR R-
RRB RR P:::AF'5EG
I: b.i) Ii bit)
R R
RS'v"u FS'v'u ?,S"iD R5\iD LDCTL
p-
SLLL P'iAPUff
RSVD R
SRLL
...'" ~ TRTIRB CPSIRB CPSIR RSVD LDCTL
~ RRB RR ~ I"
Z Z
0
;::
6 (2 bits)
R
(2 bits)
R g
U U PSVD RSVD RSVD RSVD LDCTL
::> ::>
l!: RSVD SOLL ...
lit: f- -~';5FC'FF

~ 7 R ~
15 l5 TROB CPOB CPO MSET RSVD
~ ~
9 BLCB BLC 9
'1 bll'
>< B
'"
;; ;; PSVC LDDB LDD MRES RSVD

~Z :l'"
;P-IF. ?-IP
SLAB SLA LDDRB LDDR
9 R R Z
SRAB SM
15 R R 15 TRTDB CPSOB CPSD MBIT LDCTL
~ ~ Ff:'.",'_p
9 BLCB RLC 9
(2 bi!s) (2 bIts)
R R
RSVD RSVD RSVD RSVD LDCTL
RFRSH-R

U
SOAB SOA
R R
I I
CPORB CPDR
I LDCTL

RRCB
'j bll;
R
RRC
I TRDRB

! PSAP'iE(;
-p

RSVD RSVD RSVD MREQ LDCTL

R PSAPc;FF
-p
SLAL
RSVD R
SRAL
TRTDRB CPSDRB CPSDR RSVD LDCTL
IR N;:;PSEG-I'
RRCB RRC
b:ts)
LDCTL
R:::VD HS'v'[l RSVD .'bf\;F'
SDAL
RSVD R

Table 4. Table 5. Table 6. Table 7.

276
Topical
Index Data Addressing Flags
Instruction Description Mnemonic Types Modes Affected
Arithmetic
Add with Carry ADC B, W R C, Z, S, V, D', H
Add ADD B, W, L R, 1M, IR, DA, X C, Z, S, V, Di , Hi
Compare (Immediate) CP B, W IR, DA, X C, Z, S, V
Compare (Register) CP B, W, L R, 1M, IR, DA, X C, Z, S, V
Decimal Adjust DAB B IR C, Z, S
Decrement DEC B, W R, IR, DA, X Z, S, V
Divide DIV W, L R, 1M, IR, DA, X C, Z, S, V
Extend Sign EXTS B, W, L R
Increment INC B, W R, IR, DA, X Z, S, V
Multiply MULT W, L R, 1M, IR, DA, X C, Z, S, V
Negate NEG B, W R, IR, DA, X C, Z, S, V
Subtract with Carry , SBC B, W R C, Z, S, V, D', H'
Subtract SUB B, W, L R, 1M, IR, DA, X C, Z, S, V, D', Hi
Bit Manipulation
Bit Test BIT B, W R Z
Bit Reset (Static) RES B, W R, IR, DA, X
Bit Reset (Dynamic) RES B, W R
Bit Set (Static) SET B, W R, IR, DA, X
Bit Set (Dynamic) SET B, W R
Test and Set TSET B, W R, IR, DA, X S
Block Transfer and String Manipulation
Compare and Decrement CPD B, W IR C, Z, S, V
Compare, Decrement, qnd Repeat CPDR B, W IR C, Z, S, V
Compare and Increment CPI B, W IR C, Z, S, V
Compare, Increment, and Repeat CPIR B, W IR C, Z, S, V
Compare String and Decrement CPSD B, W IR C, Z, S, V
Compare String, Decrement, and Repeat CPSDR B, W IR C, Z, S, V
Compare String and Increment CPSI B, W IR C, Z, S, V
Compare String, Increment, and Repeat CPSIR B, W IR C, Z, S, V
Load and Decrement 10D B, Vi IR Z, V
Load, Decrement, and Repeat 10DR B, W IR Z, V
Load and Increment 101 B, W IR Z, V
Load, Increment, and Repeat 10IR B, W IR Z, V
Translate and Decrement TRDB B IR Z, V
Translate, Decrement, and Repeat TRDRB B IR Z, V
Translate and Increment TRIB B IR Z, V
Translate, Increment, and Repeat TRIRB B IR Z, V
Translate, Test, and Decrement TRTDB B IR Z, V
Translate, Test, Decrement, Repeat TRTDRB B IR Z, V
Translate, Test, and Increment TRTIB B IR Z, V
Translate, Test, Increment, and Repeat TRTIRB B IR Z, V
CPU Control Instructions
Complement Flag COMFLG C', Z', S', p', V'
Disable Interrupt DI
Enable Interrupt EI
Halt HALT
Load Control Register (from register) 10Cn R C', Z', S', p', D', H'
Load Control Register (to register) LDCn
Load Program Status 10PS IR, DA, X C, Z, S, P, D, H
Multi-Bit Test MBIT Z, S
Multi-Micro Request MREQ Z, S
Multi-Micro Reset MRES
Multi-Micro Set MSET
No Operation NOP
Reset Flag RESFLG C', Z', S', p', V'
Set Flag SETFLG C', Z', S', p', V'

1. Flag aflected only for byte operation.

2. Flag modIfIed only if specified by the InstructIOn.

277
Topical
Index
(Continued) Data Addressing Flags
Instruction Description Mnemonic Types Modes Affected
Input/Output Instructions' Regular Special
Input (S)lN' B, W JR, DA (DA)
Input and Decrement (S)lND' B, W IR (lR) Z, V
Input, Decrement and Repeat (S)lNDR' B, W IR (lR) Z, V
Input and Increment (S)lNI' B, W IR (JR) Z, V
Input, Increment, and Repeat (S)lNIR' B, W JR (lR) Z, V
Output (S)OUT' B, W JR, DA (DA)
Output and Decrement (S)OUTD' B, W JR OR) Z, V
Output, Decrement, and Repeat (S)OUTDR' B, W JR (IR) Z, V
Output and Increment (S)OUTI' B, W JR (JRJ Z, V
Output, Increment, and Repeat (S)OUTJR' B, W JR (lR) Z, V

Load and Exchange Instructions

Clear CLR B, W R, JR, DA, X
Exchange EX B, W R, IR, DA, X
Load LD B, W R, JR, DA, X, BA, BX, 1M
Load Address LDA B, W DA,X,BA,BX
Load Address Relative LDAR B, W RA
Load Constant LDK B, W R
Load Immediate Into Memory LD B, W IR, DA, X
Load Into Memory LD B, W, L JR, DA, X, BA, BX
Load Into Register LD B, W, L R, 1M, JR, DA, X, BA, BX
Load Multiple LDM B, W IR, DA, X
Load Relative LDR B, W RA
Pop POP W, L R, JR, DA, X
Push PUSH W, L R, 1M, IR, DA, X

Logical Instructions
And AND B, W R, 1M, JR, DA, X Z, S, p'
Complement COM B, W R, JR, DA, X Z, S, p'
Or OR B, W R, 1M, IR, DA, X Z, S, p'
Test TEST B, W, L R, IR, DA, X Z, S, p'
Test Condition Code TCC B, W R
Exclusive Or XOR B, W R, 1M, IR, DA, X Z, S, p'

Program Control Instructions

Call Procedure CALL JR, DA, X
Call Procedure Relative CALR RA
Decrement, Jump if Not Zero DJNZ B, W RA
Interrupt Return JRET C, Z, S, P, 0, H
Jump JP JR, DA, X
Jump Relative JR RA
Return From Procedure RET
System Call SC
Rotate and Shift Instructions
Rotate Left RL B, W R C, Z, S, V
Rotate Left Through Carry RLC B, W R C, Z, S, V
Rotate Left Digit RLDB B R Z, S
Rotate Right RR B, W R C, Z, S, V
Rotate Right Through Carry RRC B, W R C, Z, S, V
Rotate Right Digit RRDB B R Z, S
Shift Dynamic Arithmetic SDA B, W, L R C, Z, S, V
Shift Dynamic Logical SDL B, W, L R C, Z, S, V
Shift Left Arithmetic SLA B, W, L R C, Z, S, V
Shift Left Logical SLL B, W, L R C, Z, S, V
Shift Right Arithmetic SRA B, W, L R C, Z, S, V
Shift Right Logical SRL B, W, L R C, Z, S, V

3. Each I/O instructIOn has a Speclal counierpart used to alert other devices that a Special L·O transactJon IS occur·
ring. The Specwll'O mnemOnIC is S + Regular mnemonic. Reier to section 6.2.8 ior further details.

278
 .01, O? 01 .01, 01
••0\ ••oi Rll,s
R1115 01 01

··'l ·JI
·,1 I
::::J
..,[ ·JI·,1 I·"
... [ ··1.51 I
I ··'1 ··1
.51
.61 I .61 ~
···1 ·,1 I ···1 ·,1
01 Rsl,s 01

I~
RailS
RR·l RR'[
R91 R91
RRtO 1Rnl
R101 RR10 IR101
Rll!
I·"
IR121R131 IR131R121
I~"'
RR12

I
RR1Z

RR14
R14R14
R15
SYSTEM STACK POINTER (SEG. NO.)
NORMAL STACK POINTER lSEG. NO,1 (N$PSEG)

SYSTEM STACK POINTER (OFFSET)

RR14
I R141
R15
R1S' SYSTEM STACK POINTER
NORMAL STACK POINTER (NSPj

R15 NORMAL STACK POINTER (OFFSET) (N$POFF)

Segment ZaDOO General Purpose Registers Non-Segmented ZSOOO General Purpose Registers

Register Binary Hex

RQO RRO RO RHO 0000 a
RI RHI 0001 I
RR2 R2 RH2 0010 2
R3 RH3 0011 3
RQ4 RR4 R4 RH4 0100 4
Wi HH:i 0101 5
nnu nu lUlU VJ.1U

R7 RH7 alII 7
RQ8 RR8 R8 RLO 1000 8
R9 RLl 1001 9
RRIO RIO RL2 1010 A
Ril RL3 lOll B
RQI2 RRI2 RI2 RL4 1100 C
RI3 RL5 1101 D
RRI4 RI4 RL6 IlIa E
RI5 RL7 IIII F

Binary Encoding for Register Fields

28002

LOW LOW
ADDRESS ADDRESS
SYSTEM STACK
~~~~T~~ AFTER ..... IDENTIFIER SYSTEM SP IDENTIFIER
AFTER TRAP
INTERRUPT OR INTERRUPT

PC SEGMENT
SYSTEM STACK
POINTER BEFORE .... PC OFFSET
TRAP OR SYSTEM SP
INTERRUPT BEFORE TRAP
OR INTERRUPT

.....-1 WORD ........ .....-1 WORD ......

HIGH HIGH
ADDRESS ADDRESS

Format of Saved Program Status in the System Stack

279
 CONTROL BITS FLAGS
15 0

F9'+AI VI INVlli i i!!P!!W '" II I I IpNI I

E s C z S D H tii yy Ilil
PROGRAM COUNTER I
NONSEGMENTED

CONTROL BITS FLAGS

PROGRAM COUNTER OFFSET

SEGMENTED

Program Status Blocks

PROGRAM STATUS AREA

POINTER (PSAP)
~

~r=~O::~ OFFSET IMPLIED

BYTE OFFSET Z8001 Z8002 BYTE OFFSET

HEX DECIMAL DECIMAL HEX
0 0 RESERVED 0 0

RESERVED
EXTENDED FCW
FCW
INSTRUCTION

Wp~E~~ TRAP

RESERVED
PRIVILEGED FCW
FCW
INSTRUCTION
WSEGL- TRAP PC
PC OFFSET
RESERVED
24 SYSTEM FCW
FCW
CALL
WSEGL- TRAP PC
PC OFFSET
RESERVED
FCW SEGMENT
NOT USED
TRAP
--.Jp~E~F~
RESERVED
40 FCW
FCW NON-MASKABLE
INTERRUPT
--.Jp~E~F~ PC

RESERVED
--
30
FCW NON-VECTORED
INTERRUPT
Wp~~~~ PC

RESERVED
38 56 FCW 28
FCW

3C 60 ~~E~km- PC, 30

~D~~~km- VECTORED
iNTERRUPTS
PC,

H~~~~ PC,

H~:~~ PC,

23A 540

Program Status Area

280
Condition
Codes Code Meaning Flag Setting Binary
F Always false' 0000
Always true 1000
Z Zero 2 = 1 0110
NZ Not zero 2 = a lIla
C Carry C = 1 aliI
NC No carry C = a 1111
PL Plus 3 = a 1101
MI Mmus 3 = 1 0101
NE Noi equal Z = a 1110
EQ Equal 2 = I 0110
OV Overflow V = I 0100
NOV No overflow V = a 1100
PE Panty even P = I 0100
PO Parity odd P = a 1100
GE Greater than (3 XOR V) 1001
or equal
LT Less than (3 XOR V) I 0001
GT Greater than (Z OR (3 XOR V)) = a 1010
LE Less than or (Z OR (3 XOR V)) = 1 0010
equal
UGE UnsIgned C = a 1111
greater than
or equal
ULT Ur;signed C = 1 0111
less than
UGT Unsigned ((C = 0) AND (2 = 0)) 1011
greater than
ULE Unsigned less (C OR 2) = I 0011
than or equal

This iable provides ihe condition codes and the flag settings they represent.
Note thai some of the condition codes correspond to identical flag settings: i.e., 2-EQ, N2-NE,
.... T" TTf1I:' DC (\11 Dt\ ~Tni.T
.I.'l'-'-U\,,;AL/ .I. L·'-"V, .L '-"-J.,'-"V.

'Presenily nor lmplemented In PLZ,ASM Z8000 compiler.

7 6 5 4 3 2 1 °
I I I 1 1 1 I BITS IN A BYTE

,1511411311211111°19 8171615141312111°, BITS IN A WORD

BYTE

WORD

Address n Address n + 1

Addressable Data Elements

281
Z8000
Addressing Addressing Mode Operand Addressing Operand Value
Modes
In the Instruction In a Register In Memory

Register I REGISTER ADDRESS ~ The content 01 the

register

1M

Immediate In the instruction

*IB
The content 01 the location
Indirect
Register
I REGISTER ADDRESS ~1------.... 1 OPERAND I whose address is in the
register

DA
The content 01 the location
Direct ~~-----------_.~ whose address is in the
Address instruction

*X The content 01 the loca-

tion whose address is the
Index address in the instruction
plus the content 01 the
working register.

BA The content 01 the location

whose address is the
PC VALUE ~ content 01 the program
Relative
Address ~~====~I OPERANO I counter. olfset by the
displacement in the
instruction

*BA The content 01 the location

Base whose address is the
address in the register.
Address olfset by the displacement
in the instruction

*BX The content 01 the loca-

Base tion whose address is
Index the address in a register
plus the index value in
another register.

+ Do not use RO or RHO as indirect, index, or base registers.

Powers
2n 16"
of 2 I 0
256 8 2° 16°
and 16 2' 16' 16 1
512 9
28 162 256 2
I 024 10 4096 3
2 12 16'
2048 11 2" 16' 65536 4
4096 12 2" 16' I 048576 5
8 192 13 224 16" 16777216 6
2'" 16' 268 435 456 7
16384 14 4294967296 8
2 32 168
32768 15 68719476736 9
236 169
65536 16 2'" 16'° 1 099511 627776 10
131 072 17 2'" 16" 17592 186044416 11
2'" 16" 281 474976710656 12
262 144 18
2" 16" 4 503 599 627 370 496 13
524 288 19 72 057 594 037 927 936 14
256 16 14
I 048 576 20 - 1 152921 504606846976 15
2'" 16 15
2097 152 21
4 194304 22 Powers of IS
8388608 23
16 777 216 ~~

Powers of 2

282
Hex Decimal Hex Decimal Hex Decimal Hex Decimal Hex Decimal Hex Decimal Hex Decimal Hex Decimal

268,435,456 16,777,216 1,048,576 65,536 4,096 256 16

536,870,912 33,554,432 2,097,152 131,072 8,192 512 32

805,306,368 50,331,648 3,145,728 196,608 12,288 768 48

1.073,741.824 4 67,108,864 4,194,304 262,144 16,384 1,024 64

5 1,342,177,280 83,886,080 5,242,880 327,680 20,480 J.280 80

1.610,612,736 6 100,663,296 6,291,456 393,216 24,576 1,536 96

1,879,048,192 7 117,440,512 7,340,032 458,752 28,672 1,792 112

8 2,147,483,648 134,217,728 8,388,608 524,288 32,768 2,048 128

2,415,919,104 9 150,994,944 9,437,184 589,824 36,864 2,304 144

A 2,684,354,560 A 167,772,160 A 10,485,760 A 655,360 A 40,960 A 2,560 A 160 A 10

B 2,952,790,016 B 184,549,376 B 11,534,336 B 720,896 B 45,056 B 2,816 B 176 B 11

C 3,221,225,472 C 201,326,592 C 12,582,912 C 786,432 C 49,152 C 3,072 C 192 C 12

D 3,489,660,928 D 218,103,808 D 13,631,488 D 851,968 D 53,248 D 3,328 D 208 D 13

E 3,758,096,384 234,881.024 14,680,064 917,504 57,344 3,584 224 14

F 4,026,531,840 251,658,240 15,728,640 983,040 61,440 3,840 240 15

Hexadecimal and Decimallnterger Conversion Table

To Convert Hexadecimal to Decimal To Convert Decimal to Hexadecimal

l. Locate the column of decimal numbers corresponding to l. (a) Select from the tabel the highest decimal number
the left-most digit or letter of the hexadecimal: select that is equal to or less than the number to be
from this column and record the number that cor- converted.
responds to the position of the hexadecimal digit or (b) Record the hexadecimal of the column containing
letter. the selected number.
(c) Subtract the selected decimal from the number to be
2. Repeat step I for each remaining position.
converted.
3. Add the numbers selected from the table to form the
2. Using the remainder from step I(c) repeat all of step 1
decimal number.
to develop successive positions of the hexadecimal (and
To convert integer numbers greater than the capacity of a remainder).
the table, use the techniques below:
3. Combine terms to form the hexadecimal number.
Hexadecimal to Decimal
Decimal to Hexadecimal
Succesive cumulative mulitplication from left to right,
adding units position. Divide and collect the remainder in reverse order.

Example: D3416 = 338010 Example: Example: 338010 = D3416 Example:

D = 13 Conversion of 16 ~remainder Conversion of

16~41
x 16 Hexadecimal Value Decimal Value
208 D34 3380
3 = +13 16~3
2TI l.D 3328 D l.D -3328
x 16 52
3376 2. 48
4 = +4 2. 3 -48
3380 3. 6

4. Decimal 3380
3.4 -4

4. Hexadecimal D34

283
ASCII Hexadecimal Character Meaning Hexadecimal Character
Characters
00 NUL NULL Character 40 @
01 SOH Start of Heading 41 A
02 STX Start of Text 42 B
03 ETX End of Text 43 C
--04 EOT - - End of Transmission 44 D
05 ENQ Enquiry 45 E
06 ACK Acknowledge 46 F
07 BEL Bell 47 G
--08 BS - - Backspace 48 H
09 HT Horizontal Tabulation 49 I
OA LF Line Feed 4A J
OB VT Vertical Tabulation 4B K
--OC FF - - Form Feed 4C L
OD CR Carriage Return 4D M
OE SO Shift Out 4E N
OF SI Shift In 4F 0
--10 DLE - - Data Link Escape 50 P
II DCI Device Control I 51 Q
12 DC2 Device Control 2 52 R
13 DC3 Device Control 3 53 S
--14 DC4 - - Device Control 4 54 T
15 NAK Negative Acknowledge 55 U
16 SYN Synchronous Idle 56 V
17 ETB End of Transmission Block 57 W
--18 CAN - - Cancel 58 X
19 EM End of Medium 59 Y
IA SUB Substitute 5A Z
IB ESC Escape 5B [
--IC FS - - File Separator 5C \
lD GS Group Separator 5D )
IE RS Record Separator 5E
IF US Unit Separator 5F
--20 SP - - Space 60
21 ! 61
22 62 b
23 63
--24 64 d
25 % 65 e
26 & 66 f
27 67 g
--28 68 h---
29 69
2A 6A
2B + 6B
--2C 6C
2D 6D m
2E 6E
2F / 6F 0
--30 0 70 p
31 I 71 q
32 2 72
33 3 73
--34 4 74
35 5 75
36 6 76
37 7 77
--38 8 78
39 9 79
3A 7A
3B 7B
- - 3C < 7C
3D 7D
3E > 7E
3F ? 7F DEL Delete

284
 D
.-
 Appendix D

Glossary of address: An entity that specifies one par- BCD digit: A Binary Coded Decimal digit is
Terms ticular element in a set of similar elements. an encoding of the ten decimal digits into a
May be either a memory address or an I/O 4-bit code that is simply the first ten binary
address (q.q.v). (See also segmented address, numbers in the binary number system (starting
logical address, physical address.) with 0). This code is used to represent and
address space: A set of addresses. The Z8000 process numbers in the base-lO (decimal)
can access eight separate address spaces: format.
normal-mode program memory space, system- bus: A group of signal lines, which connects
mode program memory space, normal-mode the devices in a system.
data memory space, system-mode data memory Bus-Disconnect state: The CPU state during
space, normal-mode stack memory space, which the CPU is not the bus master and may
system-mode stack memory space, standard not initiate transactions (q.v.) on the bus.
I/O space, and special I/O space. (See normal
mode, system mode, program memory address bus master: The device in control of the bus.
space, data memory address space, stack Must be a device that is able to initiate
memory address space, standard I/O address transactions.
space, and special I/O address space.) bus request: A request for control of the bus.
addressing mode: The way in which the byte: A byte is eight contiguous bits; a byte in
address of an operand (q.v.) is specified. memory starts on an addressable byte
There are eight addressing modes: Register, boundary.
Immediate, Indirect Register, Direct Address, byte register: An 8-bit register. The Z8000
Index, Base Address, Relative Address, Base CPU contains 16 general-purpose byte
Index (q.q.v). registers, designated RLn and RHn (n = 0-7).
autodecrement: The contents of a register are clock cycle: One cycle of the CPU clock,
decremented and then used as speCified by the beginning with a rising edge.
instruction.
condition: An event detected by the hardware
autoincrement: The contents of a register are
and indicated by setting the appropriate flag.
used as speCified by the instruction and then
A condition is caused by the execution of an
incremented.
instruction and is always reproducible. The
Base address (BA) addressing mode: A Z8000 has six flags to record these events,
based address consists of a register that con- called status flags (q.v.).
tains the base and a 16-bit displacement (q.v.). context switching: Interrupting the activity in
The displacement is added to the base and the progress and switching to another activity. A
resulting address indicates the effective context switch involves saving for later restora-
address (q.v.). In nonsegmented mode, the tion the contents of the general-purpose
base address is held in a word register (q.v.) registers, the Program Counter and the Flag
and the displacement is in the instruction. In and Status Word (q.v.).
segmented mode, the segmented base address
is held in a register pair and the displacement CPU state: Either Running state, Stop/Refresh
is in the instruction. state, or Bus-Disconnect state (q.q.v.).
Base Index (BX) addressing mode: Based data memory address space: A memory
Indexed addressing is similar to Based address space (q.v.) that is identified by the
addressing except that the displacement status codes 1000 or 1010.
("index"), as well as the base, is held in a data structure: A logical organization of
register. In nonsegmented mode, the base primitive elements (e.g. byte or word) whose
address is held in a word register and the format and access conventions are well-
index is held in a word register. In segmented defined. Examples of data structures are
mode, the segmented base address is held in a tables, lists and arrays.
register pair (q. v.) and the index is held in a
word register.

287
Glossary of data type: The way in which bits are grouped I/O address: The address of an I/O port,
Terms and interpreted. For an instruction, the data always 16 bits long. Word ports may have even
type of an operand determines its size and the or odd addresses, Special I/O byte ports are
significance of its bits. Operand data types even, Standard I/O byte ports are odd.
include byte, word, long word, byte string, I/O transaction: A transaction that transfers
word string, and BCD digit. data to or from a peripheral device or memory
Direct Address (DA) addressing mode: In this management hardware.
mode, the operand address is contained within logical address: The address manipulated by
the instruction. the programmer, used by instructions and out-
displacement: A number contained in the put by the 28000.
instruction for use in calculating the effective long word: A long word is 32 contiguous bits;
address (q.v.) of an operand. The displace- a long word in memory starts on an even
ment is added to the contents of a register dur- addressable byte boundary.
ing the calculation.
machine cycle: One basic CPU operation,
DMA: Direct Memory Access is a method for starting with a bus transaction (q.v.).
transferring data to or from main memory at
high speed by avoiding the CPU registers. memory address: An address specifying a
location in memory. Word and long-word
effective address: The address obtained after addresses must be even, byte addresses may
indirect or indexing modification. In non- be even or odd.
segmented mode, the effective address is a
16-bit number. In segmented mode, the effec- memory management: The process of trans-
tive address consists 01 a 7-bit segment number lating logical addresses into physical
and 16-bit offset. In systems with memory addresses (q.q.v.), plus certain protection
management, the effective address is the functions.
logical address which must be translated to memory transactions: A transaction that
obtain the physical memory address. transfers data to or from main memory.
flags: Bits in the Flag and Control Word normal mode: A Running-state (q.v.) mode in
(q.v.) that indicate conditions (q.v.). which the SIN flag in the FCW is 0 and the
Flag and Control Word: One of the two Pro- N/S line is High. In this mode, the CPU may
gram Status registers; it contains flags (q.v.) not execute privileged instructions (q.v.).
and bits that control the operation of the CPU. non-maskable interrupts: Interrupts (q. v .)
Immediate (I) addressing mode: In this which cannot be disabled.
mode, the operand is contained within the nonsegmented mode: A Running-state mode
instuction. of the 28000 CPUs. For segmented CPUs in this
Index (X) addressing mode: In this mode, the mode, all addresses are generated with the same
operand address is obtained by adding the segment number (q.v.).
contents of an index register (q.v.) to a base non-vectored interrupts: Interrupts (q.v.)
address contained in the instruction. which do not use the identifier word as a vec-
index register: A word register used to con- tor to an interrupt service routine (q.v.).
tain a displacement for use in effective address offset: In a 28001 CPU, the 16-bit value that
calculation. appears on the AD lines when an address is
Indirect Register (lR) addressing mode: In generated.
this mode, the operand address is contained operand: An item of data operated on by an
within a register. instruction.
instruction fetch: An access to program physical address: The address required for
memory address space (q.v.). accessing the memory, obtained from the
interrupt request: An event other than a trap logical address generated by the 28000 by
or jump or call instruction that changes the memory management hardware, for example,
normal flow of instruction execution. (See non- the 28010 Memory Management Unit.
maskable, non-vectored, and vectored privileged instruction: An instruction intend-
interrupts. ) ed for use primarily by an operating system,
interrupt service routine: The rou tine exe- which can be executed only in System mode.
cuted in response to an interrupt. In general, instructions that change the pro-
cessor state or perform I/O are privileged.
interrupt/trap acknowledge transaction: The
transaction initiated by the CPU in response to Program Counter (PC): One of the two Pro-
an interrupt or trap. Obtains an identifier word gram Status registers (q.v.). Contains the
from the interrupting device or memory man- address of the current instruction.
agement hardware.

288
Glossary of program memory address space: The segmented address: In segmented Z8000
Terms memory address space (q.v.) indicated by the CPU's, a 23-bit value consisting of a 7-bit seg-
status codes (1100 or 1101). ment number (q.v.) and a 16-bit offset (q.v.)
Program Status Area: The area in memory segmented mode: One of the Running-state
reserved for the starting program status of the modes of the segmented Z8000 CPU. In this
interrupt and trap service routines. mode, CPU generates addresses that can have
Program Status Area Pointer: The register different segment members.
that contains the starting address of the Pro- Special I/O address space: An I/O address
gram Status Area. space (q. v.). that is identified by the status
Program Status registers: The two registers code 0011. Used to access memory manage-
(PC and FCW) that contain the program ment hardware.
status. stack: A data structure used for temporary
refresh counter: A register that controls the storage or for procedure and interrupt service
Z8000 dynamic memory, periodic-refresh routine linkages. A stack uses the last-in, first-
mechanism. Used to set the refresh rate and to out concept. As items are added to, or pushed
enable the mechanism. onto, the stack, the stack pointer decrements;
as items are removed from, or popped off, the
refresh cycle: A type of transaction used to stack, the stack pointer increments.
refresh dynamic memory. It is three clock
stack memory address space: A memory
cycles long.
address space (q.v.) that is identified by the
Refresh/Stop state: A CPU state entered status codes 1001 and lOll.
whenever the STOP line is asserted. A con-
stack pointer: A general-purpose register
tinuous stream of refresh cycles (q.v.) is
indicating the top (lowest address) of a stack.
generated.
Standard I/O address space: An I/O address
register: A storage location in hardware logic
space (q.v.) that is identified by the status
other than the memory. Bits within a register
code 0010. Used for accessing peripherals.
are numbered from 0, with the least significant
being the rightmost. See also byte register, status code: A 4-bit encoding of the CPU's
word register, register pair, and register quad. current transaction, for example, internal
operation, segment trap acknowledge, or stack
Register (R) addressing mode: In this mode,
memory request.
the operand is in a general-purpose register.
status flags: Status flags are set according to
register pair: One of eight pairs of general-
the outcome of certain instructions to direct
purpose word registers, designated RRn
the subsequent flow of the program as neces-
(n = 0,2,4, ... , 12, 14).
sary. There are six status flags: Carry, Zero,
register quad: One of four groups of four Sign, Parity/Overflow, Decimal Adjust and
word registers, designated RQn (n = 0, 4, Half Carry. The first four are grouped together
8, 12). to determine the condition code, the last two
Relative Address (RA) addressing mode: In are used in programs manipulating BCD
this mode, the operand address is calculated digits.
by adding a displacement found in the instruc- status lines: The lines ST o-ST3 , which contain
tion to the current PC value. the status code during transactions.
request: Either an interrrupt request, bus stop request: A request that is made by acti-
request, resource request, or STOP request vating the STOP line.
(qq.v.). An external device requests that the
Stop/Refresh state: See Refresh/Stop state.
CPU perform some action.
system mode: A Running-state mode (q.v.) in
reset: An internal CPU operation that initial-
which the SIN flag in the FCW is 1 and the
izes the Program Status registers. It is acti-
N/S line is Low. In this mode, the CPU may
vated by the RESET line.
exercise privileged instructions (q.v.).
Running state: One of the three CPU states.
transaction: One of the basic bus operations.
Tn this state, the CPU is fetching and exe-
A transaction lasts three or more clock cycles
cuting instructions or handling interrupts.
and covers a single data movement on the bus.
segment: In a Z8001, a set of adjacent
memory addresses (up to 64K) with the same
segment number (q.v.) on lines SNo-SN 6 .
segment number: A number specifying a
memory segment (q.v.). Placed on the
SNO-SN6 lines during memory transactions in
Z8001 system. Part of a segmented
address (q. v.).

289
Glossary of trap: A condition that occurs at the end of an WAIT cycle: A clock cycle during which the
Terms instruction that caused an illegal operation. WAIT line is active. Used to prolong trans-
The 28000 traps are internal traps arising from actions, since no signal line is sampled while
system call, EPA instruction and privileged in- WAIT is active.
structions executed in normal mode, and an word: Two contiguous bytes (16 bits) starting
external trap, the segmentation/address trap, on an even addressable byte boundary. Bits
arising from memory access violations in systems are numbered from the right, 0 through 15. A
with memory management. A trap is similar to word is identified by the address of the byte
an interrupt in that it causes the executing pro- containing the most significant bit, bit 15.
gram to be interrupted and the Program Status
word register: A 16-bit register.
registers to be saved on the system stack. Traps
cannot be disabled.
vectored ·interrupts: Interrupts (q. v.) which
use the identifier word as a vector to the inter-
rupt service routine (q.v.). May be
disabled.

290