© 201 6 Pearson Education, Inc.: Problem Solutions - Chapter 6

Problem Solutions – Chapter 6
CHAPTER 6
© 2016 Pearson Education, Inc.
6-1.
(a) R1 + 2’s complement of R2 = 2n + R1 - R2. If R1  R2, the result is  2n. The 2n gives C = 1.
R1 + 2’s complement of R2 = 2n + R1 - R2, if R1 < R2, the result is < 2n giving C = 0.
(b) If C = 1 then R1  R2 and there is no borrow.
If C = 0 then R1 < R2 and there is a borrow. Thus, the borrow is the complement of the C status bit.
(c) For signed numbers, the carry bit C does not indicate whether a borrow occurs. Instead, to tell if R1 is less than R2, one
must examine the sign (leftmost bit) of the result of R1-R2 and the overflow bit V. If the sign bit and the overflow bit V are
not equal to each other, then R1 is less than R2. To show that this condition is true, consider four cases based upon the signs
of R1 and R2:
1) Both R1 and R2 are positive. If R1 < R2, then the result R1-R2 is negative and no overflow occurs. If R1 ≥ R2,
then the result R1-R2 is non-negative and no overflow occurs.
2) Both R1 and R2 are negative. If R1 < R2, then the result R1-R2 is negative and no overflow occurs. If R1 ≥ R2,
then the result R1-R2 is non-negative and no overflow occurs.
3) R1 is positive, and R2 is negative. R1 > R2, but the result R1-R2 could be either positive (with no overflow) or
negative (with overflow).
4) R1 is negative, and R2 is positive. R1 < R2, but the result R1-R2 could be either negative (with no overflow) or
positive (with overflow).
In cases 1, 2, and 4, when R1 < R2, the sign of the result does not equal the overflow bit V. In all other cases, when R1 ≥ R2,
the sign of the result is equal to the overflow bit V.
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6-2.*
m ld a
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1001 1001
th k ( de f i es
1100 0011
of or stu e o tat
ity s w g us d S
1000 0001 AND

is
te f t ss th nite
e rt ss fo U
1101 1011 OR
gr hi in e
th a a ly by
0101 1010 XOR

in o e r
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st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
6-3.
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(a) AND, 1010 1010 1010 1010 (b) OR, 0000 0000 0000 1111
T
(c) XOR, 1111 1111 0000 0000
6-4.*
sl 1001 0100 sr 0110 0101
6-5.*
Qi remains connected to MUX data input 0. Connect Di to MUX data input 1 instead of Mux data input 3. Connect Qi−1 to MUX data
input 2 instead of MUX data input 1. Finally, 0 is connected to MUX data input 3.
6-6.*
a) 1000, 0100, 0010, 0001, 1000. ...
b) # States = n
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
6-7.
a) 000, 100, 110, 111, 011, 001, 000, ...
b) # States = 2n
6-8.
a) 8 b) 4 c) 1
6-9.+
Examine an n-bit ripple counter and an n-bit synchronous counter. If
either of these counters cycles through all of its states, there are 2(2n) =
2n+1 transitions for the clock, and there are 2n+1– 2 total transitions for all
flip-flop outputs. For the ripple counter, the clock transitions occur on
the input of only one stage, the 0th stage. For the synchronous counter,
the clock transitions occur on the inputs to all of the n stages. Combining
the transition counts above, the ratio of the input + output transitions for
the synchronous counter compared to the ripple counter is:
[n 2n 1  2n 1  2]/[2n 1  2n 1  2]  (n  1)2n 1 /2(2n 1)  (n  1)/2
Thus, the power dissipated by the synchronous counter is at least as large
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as that dissipated by the ripple counter in all cases and grows more rapidly
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with the number of stages.
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D
th k ( de f i es
6-10.
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
a) Assuming there is an input “Up” for which the Gray code counter counts up when Up = 1 and down
e rt ss fo U
gr hi in e
th a a ly by
when Up = 0, and that the counter outputs are G3, G2, G1, and G0, then the input equations for the
k
in o e r
y y p d le d
counter’s four flip-flops are the following:

ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
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D0  Up(G 3 G 2 G1  G 3G 2G1  G 3 G 2G1  G 3G 2 G1 )   Up(G 3 G 2G1  G 3G 2 G1  G 3G 2G1  G 3 G 2 G1)

th nd wo
a his
D1 =G1 G 0 +Up(G 3 G 2G 0 +G 3G 2G 0 )+Up(G 3G 2G 0 +G 3 G 2G 0 )

T
D 2 =G 2 G1 +G 2G 0 +UpG 3G1 G 0 +UpG 3G1 G 0

D3 =G 3G 0 +G 3G1 +UpG 2 G1 G 0 +UpG 2 G1 G 0
b) For an n-bit Gray code counter, there are 2n total transitions for the flip-flop outputs instead of
2n+1 -2 output transitions for the ripple and synchronous binary counters.
6-11.
CLK
CT R 4 CT R 4 CT R 4 CT R 4
Count EN Q0 EN Q0 EN Q0 EN Q0
Q1 Q1 Q1 Q1
3 x (CO delay) + (C1-C3 delay) Q0-Q 3 Q4-Q 7 Q8 -Q 11 Q12-Q 15
Q2 Q2 Q2 Q2
= 3 + 1 = 4 AND gates Q3 Q3 Q3 Q3
CO CO CO CO
6-12.
CTR 4 CTR 4
CLK CLK
Load Load
1 Count 1 Count
D0 Q0 D0 Q0
D1 Q1 D1 Q1
D2 Q2 D2 Q2
D3 Q3 D3 Q3
CO CO
6-13.
Clk
Init CTR 4 CTR 4

Load Load
1 Count Count
D0 Q0 D4 Q4
D1 Q1 D5 Q5
D2 Q2 D6 Q6
D3 Q3 D7 Q7
CO CO
6-14. *
The equations giv en on page
64-53 can be manipulated into SOP f orm as f ollows:
= D
The equations given on page 352 can be manipulated into SOP form as follows: D1  Q1, D2  Q2 1 Q1Q8  Q1Q2Q8  Q1Q2  Q2Q8 ,
Q1, D2 = Q2  Q1Q8 = Q1Q2Q8 + Q1Q2 + Q2Q8, D4 = Q4  Q1Q2 = Q1Q2Q4 + Q1Q4
)
eb
D4  Q4  Q1Q2  Q1Q2Q4  Q Q  Q28Q4 , (Q
D18Q8 Q
+ 8Q (Q Q  Q Q Q )  Q (Q Q  Q1Q Q Q12  Q8 )(Q1  Q2  Q4 )  Q1Q2
er or in ing
2QQ48))(Q 8 (Q
ed id n
+Q 2Q4,1 D48 = Q 1Q2Q14) 8= Q81(Q21Q48+Q1Q82Q41) +8 Q8(Q1+ 1+
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+ Q4) = The
Q4Q8  Q1Q8 . These equations areQ1mapped
Qequations
2Q4Q8 + Qgiv
onto Qen
8. K-maps
1 the These
on page equations
64-5
3 can
for are mapped
be manipulated
Table andonto
6-9 below into SOP
meetthe ormK-maps
f the f or D
as f ollows:
1=
specifications Table
given by the maps and the
7-9 belowQ1and Q2  the

, D2 =meet Q1Q8specif
= Q1Q2ications
Q8 + Q1Qgiv
2 + en
Q2Qby
8, Dthe 4  Q1Q
maps
4 = Q and
2 = the
Q1Q2table.
Q4 + Q1Q4
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table. + Q2Q4, D8 = Q8  (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2

w cl le tr p
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D
th k ( de f i es
D1 + Q4) = Q1Q Q Q + Q1 Q8D

22 4 8
. These equations are mapped onto the K-maps f or Table
Q2
of or stu e o tat
2
7-9 below and meet the specif ications giv en by the maps and the table.
ity s w g us d S
1 0 0 1 0 1 0 1
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1 D
01 0 1 Q2
0 D21 0 1Q2
e rt ss fo U
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Q
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Q
k
1 0 04 1 1 0 14
Q8 X X X1 X 0
in o e r
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Q8 X X X X
ro n an o te
0 0 1
st f a s d s ec
1 1
1 0 X X Q4 0 00 X X0
de o rse de ot
Q4
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Q8Q1X X X X
Q8 X Q1 X X X ToTo add add theenable,
the enable, change D1
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1 0 X X 0 0 X X change to: D1 to:

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D4 Q2 D8 Q2
Q1 Q1 To add the enable,
 EN.
a his
0 0 1 0 Q 0 D 0 0 0Q D1 D= Q1 Q  EN.
T
change
1 1 D1 to:
D4 2 8 2
00 01 1 0 ForForthe
D1 =theother
 EN.three
Q1 other threef functions,
unc
1 1 0 00 10 00 0
Q4 Q4 tions,
AND AND
EN EN with
with the the
expression
X X X1 X For the other three f unc
Q8 1 0 1 X X0 X0 X1 0 expression XORed with
Q4 Q8 Q4 XORed
tions, ANDwithENthewith
state
the
0 0 X
Q8 X X X X 1Q 0X XX X X X thevariable.
state v The
expression ariable. The
circuit
XORed below
with
8
Q10 0 X X 1Q1 0 X X circuit
the below
state vresults.
results. ariable. The
Q1 Q1 circuit below results.
Q1 Y
D Q1
D Y
C
C
Q2
D Q2
EN D
EN
C C
Q 4 Q4
D D
C C
Q8
D Q8
D
C
C
Clock
Clock
3
6-15. *
a) DB  C b) DA  BC  AC
Present Next
state state DC  B C DB  ABC  BC
DC  C
A B C A B C
0 0 0 1
0 1 1 0
1 0 0 0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0
6-16.
DA  AB  AC  ABC
Present state Next state
DB  B
A B C A B C
DC  BC  BC
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0 0 1 0 1 1
0 1 0 0 0 1
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0 1 1 1 0 0
th k ( de f i es
1 0 0 1 1 0
of or stu e o tat
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1 0 1 1 1 1
is
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1 1 0 1 0 1
e rt ss fo U
gr hi in e
1 1 1 0 0 0
th a a ly by
k
in o e r
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ill le u vi pr
w r sa co pro is
6-17.
o eir is rk
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The basic cell cell

of the register
registerisisas f ollows:
a his
The basic of the as follows:

T
S1
S0
S1
S0 D Out
S1 C
S0
In
Clock
6-18.
X : R1  R 2
XY : R1  R3  R 4
6-19.*
R1 R2
Load Load
C3
Clock
6-20.
6-21. R2 R2 R1 1111
R1 R1
0 1 2 3
0 1 4-bit wide S1 Y
R1 4 to 1 mux
4-bit wide X S0 Z
2 to 1 mux
A B
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4-bit adder Carry-in W
Carry-out
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th k ( de f i es
of or stu e o tat
ity s w g us d S
F
is
te f t ss th nite
e rt ss fo U
6-22.*
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
R1
st f a s d s ec
LOAD
de o rse de ot
C2 C1C0
ill le u vi pr
C
w r sa co pro is
o eir is rk
D0 Q0
th nd wo
D1 Q1
D2 Q2
a his
D3 Q3
T
R2
LOAD
C
D0 Q0
D1 Q1
D2 Q2
D3 Q3
Clock
6-23.
Assuming that C1 and C0 will not both be 1 simultaneously and using don’t cares for those cases:
Di  AC0  AB  BC1
6-24.
S1
S0 D R0
D R1
Clock
6-25.
D A
Ci = S0 for lowest order bit.
C
Ci
CI
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Clock
th k ( de f i es
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is
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6-26.
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
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ro n an o te
st f a s d s ec
de o rse de ot
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w r sa co pro is
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T
6-27.*
a) CLK CT R 4
R2 ADD 4
C1
Load
REG 4 0 CI C1
C2 Count R1
D(0-3) Q(0-3) A(0-3) C(0-3) D(0-3) Q(0-3)
B(0-3) CO CO
b)
R1
C1 REG 4
C2 D(0-3) L Q(0-3)
ADD 4
CI R2
A(0-3) C(0-3) REG 4
B(0-3) CO D(0-3) Q(0-3)
L
Clock
6-28.
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The register transfer logic is as follows:
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Operation Select Load
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D
th k ( de f i es
S1 S0 L0 L1 L2
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
CA: R1 ← R0 0 0 0 1 0
e rt ss fo U
gr hi in e
th a a ly by
CB: R0 ←R1, R2 ← R0 0 1 1 0 1
in o e r
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ro n an o te
st f a s d s ec
de o rse de ot
CC: R1 ← R2, R0 ← R2
ill le u vi pr
1 0 1 1 0
w r sa co pro is
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a his
T
R0
0 S1 S0
1 LO
2
3-to-1 Mux
R1
L1
R2
L2
Clock
6-29.
a)
H = XY + XZ
b)
F = XY + XY
6-30.
Replace multiplexer with:
Replace multiplexer with:
K1
R1
4 4
R0
4
R2
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6-31.* w
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a) Destination ← Source Registers b) Source Registers → Destination
.
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a)R0 ← R1, R2<- Source Registers

Destination R0 → Registers
b) Source R4 -> Destination
th k ( de f i es
R1R0←<-R4
R1, R2 R0
R1->
→R4R0, R3
of or stu e o tat
R1 <- R4 R1 -> R0, R3

ity s w g us d S
R2R2←<-R3,
R3,R4
R4 R2 →R0,
R2-> R0,R4
R4
is
te f t ss th nite
R3R3←<-R1
R1 R3 →R2
R3-> R2
e rt ss fo U
gr hi in e
R4R4←<-R0,
R0, R2 R4 -> R1, R2
th a a ly by
R2 R4 → R1, R2
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
c) T he minimum number of buses needed for operation of the transfers

ill le u vi pr
isc)three
The minimum number
since transfer of busesthree
Cb requires needed
dif for operation
ferent sources. of the transfers is
w r sa co pro is
o eir is rk
three since transfer Cb requires three different sources.

th nd wo
a his
d)
T
R0 R1 R2 R3 R4
MUX MUX
MUX
6-32.
a) Using two clock cycles, the minimum # of buses is 2 .
a) Using two clock cycles, the minimum # of buses is 2 .
b)
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
MUX MUX
6-33.
Two clock cy cles minimum
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
MUX
MUX
6-34.*
0101, 1010, 0101, 1010, 1101, 0110, 0011, 0001, 1000
6-35.*
Shifts: 0 1 2 3 4
A 0111 0011 0001 1000 1100
B 0101 0010 0001 0000 0000
C 0 1 1 1 0
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6-36.*
e
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Default: Z1 = 0, Z2 = 0
w cl le tr p
e in nt ns co
D
th k ( de f i es
Def ault: Z1 = 0, Z2 = 0
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
· X2
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
S0 S1 S2
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
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a his
T
Reset
6-37.*
State: STA, STA, STB, STC, STA, STB, STC, STA, STB
Z: 0, 0, 1, 1, 0, 0, 1, 0, -
6-38.
State Input Next State Output
STA W STA * *Default: Z = 0
STA W STB *
STB XY STA *
STB X STC *
STB XY STC Z
STC STA Z
6-39.
DefDefault:
ault: Z Z==00
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.
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w cl le tr p
A B
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
6-40.*
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
Default: Z = 0
w r sa co pro is
o eir is rk
th nd wo
Def ault: Z = 0 STA

a his
T
STB STD
STC STE
10
6-41.+
a) Default: HOT = 0,
DEC = 0, TURN = 0,
DRAIN = 0, COLD = 0, Start IDLE Full RINSE1
Load = 0.
Start Full
Full WASH1 Zero RINSE2

Full
Zero WASH2 Empty SPIN3
Empty SPIN1 Zero SPIN4
Zero SPIN2 b) Add a flip-flop called ACTION controlled by Pause and Start.
The flip-flop is set by START and reset by Pause.
OR ACTION with each input condition on the “loop”
)
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W
for each state. AND ACTION with1) each input condition on the
no the iss tea s
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m ld a
the transition to the following state from each state and 2) all
Stop
the output signals.
.
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w cl le tr p
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END Stop causes a transition from each state to a new state END
Empty
th k ( de f i es
of or stu e o tat
ity s w g us d S
of the states. The partial diagram for state END appears

is
te f t ss th nite
at the left.
e rt ss fo U
gr hi in e
th a a ly by
To IDLE
in o e r
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ro n an o te
st f a s d s ec
de o rse de ot
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6-42.
T
Def ault: GN = 0, RE = 0,
Y N = 0, RN = 0, GE = 0,
YE = 0
S0 S1 S2 S3
11
6-43.*
DA  AW  BXY  C
Present state Input Next state Output
DB  AW
A B C A B C
DC  B(X  Y)
Z  BXY  C
1 0 0 W 1 0 0
STA
1 0 0 W 0 1 0
The implementation consists of the logic represented by the
above equations and three D flip-flops with Reset connected
0 1 0 XY 1 0 0 to S on the first flip-flop and to R on the other two flip-flops.
STB 0 1 0 X 0 0 1
0 1 0 XY 0 0 1 Z
STC 0 0 1 1 0 0 Z
6-44.
This state
This state diagram has a diagram
closed loophasof athree
closed loop of
transitions (STAthree transitions
to STB to STC to(STA
STA).to In
STB to STC
a Gray code,to STA).
only one bit In
maya Gray
changecode, only
in going one
from onebitstate
may change Any
to another. in going f rom one
state machine state. with
diagram to
Any another
astate
loop of
an odd numbermachine diagram
of transitions with a loop
is impossible of an odd
to encode withnumber of transitions
a Gray code. is to
For example, impossible
go from STA to encode
to
STB supposewith a Gray
bit B1 of thecode. For example,
code changes. Then to to go go
fromf rom
STBSTA to STB
to STC, somesuppose
other bit, bit
sayB1 B2 of
mustthe code
)
changes. Thenchanged,
to go f rom STB to STC, some to other bit, say
Thus,B2
themust change.
to this Since
eb
change. Since two bits have It is impossible to return state STA. answer
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W
no the iss tea s
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twothisbitsstate
havdiagram
e changed,
cannotItbeisimplemented
impossible with to return
a Graytocode.
w state STA. Thus, the answer to this problem is that
t p W em ch
problem is that
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this state diagram cannot be implemented with a Gray code.
.
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or ud a uc y
But suppose that we use two equivaent states to represent each of the original states, STA1, STB1,
w cl le tr p
e in nt ns co
STC1, STA2, But suppose

STB2, that we
and STC2. Is ituse two to
possible equiv aent states
implement the newtodiagram
represent each such
generated of the theoriginal
it has states, STA1, STB1,
th k ( de f i es
exactly the same properties as the old diagram. Suppose that the codes are 000, 001, 011, 111, 110,such
STC1, STA2, STB2, and STC2. Is it possible to implement the new diagram generated 100, the
of or stu e o tat
ity s w g us d S
respectively,itfor
has theexactly the
six states. Thesame
codedproperties
diagram is:as the old diagram. Suppose that the codes are 000,
is
te f t ss th nite
001, 01 1, 111, 110, 100, respectiv,ely f or the six states. The coded diagram is:
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
Def ault:Z Z
Default: = 0= 0 STA1 STB1 STC1
o eir is rk
th nd wo
000 001 011

a his
T
STC2 STB2 STA2

100 110 111
The behav ior of this diagram is the same as that of the original and it has been successf ully Gray coded
The behavior ofbythis
assigning
diagramtwo codes
is the sametoaseach
that state.
of theThe implementation
original is asuccessfully
and it has been straightforward
Graydesign problem
coded by withtwo
assigning two unused states.
codes to each state. The implementation is a straightforward design problem with two unused states.
12
6-45.
a) 0 0 1 b) Count Count Count Count
Load D4 D2 D1
Count Cnt Parallel Load
Reset R Binary Counter Count Count Count Count
Clock Q4 Q2 Q1 000 001 010 011
100 101 110

Count Count Count
D2 D1 D0
Note: Reset to zero is not a problem since the f irst
v alue will nev er be used in the design. Af ter one
count, the v alues will hav e entered the desired range Count Count Count
of 1 through 6.
Applying K-maps to the table entries:
State Cnt = 0 Cnt = 1 DQ4 = Q4 C + Q4 Q2 + Q1 Q2 C
000 000
State
001
Cnt = 0 Cnt = 1 DQ4  Q4 C  Q4 Q2  Q1 Q2 C
DQ2 = Q2 C + Q1 Q2 C + Q4 Q2 Q1
001 001 000 010 000 001 DQ2  Q2 C  Q1 Q2 C  Q4 Q2 Q1
DQ1 = Q1 C + Q1 C
010 010 001 011 001 010 DQ1  Q1C  Q1 C
Cost comparison:
)
eb
011 011 010 100
er or in ing
010 011
ed id n
W
Cost comparison:
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
a) 3(14 + 2 + 8 + 6) + 1 + 2 = 93
m ld a
100 100 011 101
011 100 a) 3 (14 + 2 + 8 + 6) + 1 + 2 = 93
.
r
or ud a uc y
b) 3(14) + 4 + 6 + 11 + 10 = 73
w cl le tr p
101 101 110

e in nt ns co
100 100 101 b) 3 (14) + 4 + 6 + 11 + 10 = 73

th k ( de f i es
110 110 111 The gate input cost of b) is 78.5 % that of a).
of or stu e o tat
ity s w g us d S
101 101 110 The gate input cost of b) is 78.5 % that of a).
is
te f t ss th nite
111 ddd ddd

e rt ss fo U
110 110 111

gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
111 ddd ddd

st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
6-46.
T
a)a) DE1
DE1= D4
D4D2
a)D2
D1D1 = D4 D2 D1
DE1 b) D2 b) D2
D3 D3 GTE100
D2 D2 D4 GTE100
D5D4 D5
D1 D6 D6
DE1 This circuit This
can be easily
D1 DE1 circuit canderiv ed by describing
be easily deriv ed by the range ofthe
describing v alues
range of v alu
greater
Thisthan or
circuit equal
can
greater thanbe to
easily100 in
derivedterms by of powers
describing the of 2.
D0 6 5or equal
2 to 100 in terms of powers of 2.
D0 The range
smallest
of The v alue
values is+22 than
greater + 2 orand 6 the
equal 5tolar
gest
2 in
100 value
theislar
terms of
3 smallest 1 v alue is+226 + 25 and gest value is
26 + powers
25 + 24 +of
2 2
62.
+ + 5
The
2 2 2
+ + 42 .
smallest
2 + This
23
+ range
2
value
2 + 1 of
is2 2. This D
+2 + can 2 be described by say ing
2 andofthe
range D can be described by say
26 and 2
that largest 5
must
value
that 26 be
is 6 presentand
2and + 2255 must
+ 24 +be 3
2any presentand
2 3
+ 22of+ 22,1.2This
, any24ofmust
or range 2 of3 be present
2
, 2 , or 24 must in
beD.present i
6 5
The D can beThe
resulting described
equation
resulting byis saying
D6 D5 that(D4 2 and
+ D32 +must
D2). beAn alternativ e way of f indin
2 equation
3 4 is D6 D5 (D4 + D3 + D2). An alternativ e wa
this present
is to contract
and
this any
is tothe 2carry
, 2 , orcircuit
of contract 2the must f or
carry beDpresent
+ 2’s in
circuit comp
100100.
D.
f or D+ of2’s
1 comp of 1
100100.
The resulting equation is D6 D5 (D4 + D3 + D2). An
alternative way of finding this is to contract the carry
circuit for D + 2’s comp of 1100100.
13
6-47.
For C0  0,
Binary BCD (C0 = 0) BCD (C0 = C4  B3 B2  B3 B1
1)
D3  B3 B2 B1
B3B2B1B0 C4D3D2D1D0 C4D3D2D1D0 D2  B3 B2  B2 B1
D1  B3 B1  B3 B2 B1
0000 00000 00001
0001 00001 00010 D0  B0
0010 00010 00011
0011 00011 00100 For C0  1,
010 0 00100 00101 C4  B3 B2  B3 B1  B3 B0
0101 00101 00110
0110 00110 00111 D3  B3 B2 B1 B0  B3 B2 B1 B0
0111 00111 01000
D2  B3 B2 B1  B3 B2 B0  B2 B1 B0  B3 B2 B1 B0
1000 01000 01001
1001 01001 10000 D1  B3 B1 B0  B3 B1 B0  B3 B1 B0  B3 B2 B1 B0
1010 10000 10001
D0  B0
1011 10001 10010
1100 10010 1 0 0 11
Combining,
1101 10011 10100 C4  C0 (B3 B2  B3 B1)  C0 (B3 B2  B3 B1  B3 B0)
1110 10100 10101
D3  C0 (B3 B2 B1)  C0 (B3 B2 B1 B0  B3 B2 B1 B0)
1111 10101 10110
D2  C0 (B3 B2  B2 B1)  C0 (B3 B2 B1  B3 B2 B0  B2 B1 B0  B3 B2 B1 B0)
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
D1  C0 (B3 B1  B3 B2 B1)  C0 (B3 B1 B0  B3 B1 B0  B3 B1 B0  B3 B2 B1 B0)
d on g. in t la
m ld a
.
r
D0  C0 B0  C0 B0
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
Optimizing,
ity s w g us d S
C4  B3 (B2  B1  C0 B0)
is
te f t ss th nite
e rt ss fo U
gr hi in e
D3  (C0  B0)B3 B2 B1  C0 B3 B2 B1 B0
th a a ly by
k
in o e r
y y p d le d
ro n an o te
D2  B2 (C0 B1  B3 B1  B1 B0  C0 B3 B0)  C0 B3 B2 B1 B0
st f a s d s ec
de o rse de ot
ill le u vi pr
D1  (C0  B0) B3 B2 B1  C0 B3 B1  C0 B0 (B3 B1  B3 B1)  B3 B1 B0

w r sa co pro is
o eir is rk
th nd wo
D0  C0 B0  C0 B0
a his
T
6-48.
a) Transition constraint checking for Figure 6-30.
Constraint 1: Constraint 2:
INIT: No possible conflicts since a single transition. Condition implicitly = 1 OK
BEGIN: ROLL  ROLL  0 OK BEGIN: ROLL  ROLL  1 OK
ROL: ROLL  ROLL  0 OK ROL: ROLL  ROLL  1 OK

ONE: DIE1  DIE1  0 OK DIE1  DIE1  1 OK
ROH: ROLL  ROLL  HOLD  0 OK ROH: ROLL  ROLL  HOLD  ROLL  HOLD  1 OK
ROLL  ROLL  HOLD  0 OK
ROLL  HOLD  ROLL  HOLD  0 OK
TEST: WN  WN  0 OK TEST: WN  WN  1 OK
WIN: NEW _ GAME  NEW _ GAME  0 OK WIN: NEW _ GAME  NEW _ GAME  1 OK
b) Implementation of state machine diagram Figure 6-30 using 1-hot code.
The order from LSB to MSB for the state variables is the same as the order of the states in the diagram from top to bottom. The state
variables have the same respective names as the states, e.g., INIT, BEGIN, ...
14
The flip-flop input equations:

DINIT  INIT(t  1)  WIN  NEW _ GAME
D BEGIN  BEGIN(t  1)  INIT  ONE  DIE1  TEST  WN  BEGIN  ROLL
D ROL  BEGIN  ROLL  ROH  ROLL  ROL  ROLL
DONE  ROL  ROLL
D ROH  ONE  DIE1  ROH  ROLL  HOLD
DTEST  ROH  ROLL  HOLD
D WIN  TEST  WN  WIN  NEW _ GAME
The output equations:
RST1  INIT, RST2  INIT, CPFI  INIT, LDCP  INIT  TEST  WN  ONE  DIE1, RSSU  BEGIN, ENDI  ROL, LDSU
 ONE, LDT1  ROH  CP  ROLL  HOLD, LDT2  ROH  CP  ROLL  HOLD, BP1  WIN  CP, BP2  WIN  CP
The circuit consists of gates implementing the above equations with logic shared where possible, and seven D flip-flops. The flip-
flop for INIT has Reset attached to S and the remaining flip-flops have Reset attached to R.
6-49.+
Default: = CP
Default:P1P1 CP, P2= CP
, P2 CP
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
INIT
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
ROLL BEGIN SUR 0

is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
ROLL
in o e r
0, ROLL
y y p d le d
(DIE1 = 1)·(DIE2 = 1)·CP/TR1

ro n an o te
st f a s d s ec
de o rse de ot
(DIE1 = 1)·(DIE2 = 1)·CP/TR2 0, ROL if (DIE1 = 1 0) DIE1 001,

ill le u vi pr
w r sa co pro is
CP CP if (DIE2 = 1 0) DIE2 001,

o eir is rk
th nd wo
ROLL else DIE2 DIE2 +1,

a his
else DIE1 DIE1 + 1

T
(DIE1 = 1) + (DIE2 = 1)
T1&2
SUR SUR + DIE1 + DIE2
(DIE1 = 1)·(DIE2 = 1)
ROLL
ROLL· HOLD ROH CP/TR1 TR1 + SUR,
CP/TR2 TR2 + SUR
(CP· (TR1  1100100) ROLL· HOLD
+ CP· (TR2  1100100))/CP CP
TEST
CP· (TR1  1100100) + CP· (TR2  1100100)
WIN
CP/ P1 = BLINK, CP/P2 = BLINK
NEW_GAME
15
6-50.*
IN
A(14:0)||0 B(14:0)||0
CLK CLK
S 1 MUX 0
LA L AR LB L BR
CLK
Bit 15 B(15:0) LC L
A(15:0) CR
R
Zero
R is a synchronous reset that overrides any
simultaneous synchronous transfer
.
Def ault: LA = 0, A
LB = 0, LC = 0
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
16
6-51.
// 4-bit Binary Counter
C[0] = EN,
// Positive Edge-Triggered D Flip-Flop with Reset: C[1] = C[0] & Q[0],
C[2] = C[1] & Q[1],
module dff_v(CLK, RESET, D, Q); C[3] = C[2] & Q[2],
input CLK, RESET, D; CO = C[3] & Q[3];
output Q;
reg state; assign
D_in[0] = C[0] ^ Q[0],
assign Q = state; D_in[1] = C[1] ^ Q[1],
D_in[2] = C[2] ^ Q[2],
always @(posedge CLK or posedge RESET) D_in[3] = C[3] ^ Q[3];
begin
if (RESET)
state <= 0; dff_v
else g1(Clock, Reset, D_in[0], Q[0]),
state <= D; g2(Clock, Reset, D_in[1], Q[1]),
end g3(Clock, Reset, D_in[2], Q[2]),
endmodule g4(Clock, Reset, D_in[3], Q[3]);
module Counter_4bit (Clock, Reset, EN, Q, CO) ; endmodule
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
input Clock, Reset, EN ;
output [3:0] Q ;
.
r
or ud a uc y
w cl le tr p
e in nt ns co
output CO ;
th k ( de f i es
wire[3:0] Q ;
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
wire [3:0] C, D_in;

e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
// (continued in next column)

st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
17
6-52. *
library IEEE;
use IEEE.std_logic_1164.all;
entity reg_4_bit is
port (
CLEAR, CLK: in STD_LOGIC;
D: in STD_LOGIC_VECTOR (3 downto 0);
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end reg_4_bit;
architecture reg_4_bit_arch of reg_4_bit is

begin
process (CLK, CLEAR)

begin
if CLEAR = ‘0’ then --asynchronous RESET active Low
Q <= “0000”;
elsif (CLK’event and CLK= ‘1’) then --CLK rising edge
Q <= D;
end if;
)
eb
er or in ing
end process;
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
end reg_4_bit_arch;
.
r
or ud a uc y
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
ity s w g us d S
is
te f t ss th nite
e rt ss fo U
gr hi in e
th a a ly by
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
de o rse de ot
ill le u vi pr
w r sa co pro is
o eir is rk
th nd wo
a his
T
6-53.
library IEEE; architecture reg_4_bit_load_arch of reg_4_bit is
use IEEE.std_logic_1164.all; begin
entity reg_4_bit is process (CLK)

port ( begin
LOAD, CLK: in STD_LOGIC; if (CLK’event and CLK= ‘1’) then --CLK rising edge
D: in STD_LOGIC_VECTOR (3 downto 0); if LOAD = ‘1’ then
Q: out STD_LOGIC_VECTOR (3 downto 0) Q <= D;
); end if;
end reg_4_bit; end if;
end process;
-- (continued in next column)
endreg_4_bit_load_arch;
18
6-54.
library ieee; architecture counter_4_bit_arch of counter_4_bit is
use ieee.std_logic_1164.all; component dff
entity dff is port(CLK, RESET, D: in std_logic;
port(CLK, RESET, D: in std_logic; Q: out std_logic
Q : out std_logic); );
end dff; end component ;
signal D_in, C, Q_out: std_logic_vector(3 downto 0);
architecture pet_pr of dff is
-- Implements positive edge-triggered bit state storage begin
-- with asynchronous reset. C(0) <= EN;
signal state: std_logic; C(1) <= C(0) and Q_out(0);
begin C(2) <= C(1) and Q_out(1);
Q <= state; C(3) <= C(2) and Q_out(2);
process (CLK, RESET) CO <= C(3) and Q_out(3);
begin
if (RESET = ‘1’) then D_in(0) <= C(0) xor Q_out(0);
state <= ‘0’; D_in(1) <= C(1) xor Q_out(1);
else D_in(2) <= C(2) xor Q_out(2);
if (CLK’event and ClK = ‘1’) then D_in(3) <= C(3) xor Q_out(3);
state <= D;
end if; bit0: dff
)
eb
er or in ing
end if; port map (Clock, Reset, D_in(0), Q_out(0));
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
end process; bit1: dff
end; port map (Clock, Reset, D_in(1), Q_out(1));
.
r
or ud a uc y
w cl le tr p
e in nt ns co
bit2: dff
th k ( de f i es
library IEEE; port map (Clock, Reset, D_in(2), Q_out(2));

of or stu e o tat
ity s w g us d S
use IEEE.std_logic_1164.all; bit3: dff

is
te f t ss th nite
entity counter_4_bit is port map (Clock, Reset, D_in(3), Q_out(3));

e rt ss fo U
gr hi in e
th a a ly by
port (
in o e r
y y p d le d
ro n an o te
Clock, Reset, EN: in STD_LOGIC; Q <= Q_out;

st f a s d s ec
de o rse de ot
Q: out STD_LOGIC_VECTOR (3 downto 0);

ill le u vi pr
w r sa co pro is
CO: out STD_LOGIC end counter_4_bit_arch;

o eir is rk
th nd wo
);
a his
end counter_4_bit;
T
19
6-55. *
module register_4_bit (D, CLK, CLR, Q) ;
input [3:0] D ;
input CLK, CLR ;
output [3:0] Q ;
reg [3:0] Q ;
always @(posedge CLK or negedge CLR)

begin
if (~CLR) //asynchronous RESET active low
Q = 4’b0000;
else //use CLK rising edge
Q = D;
end
endmodule
)
eb
er or in ing
ed id n
W
no the iss tea s
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
.
r
or ud a uc y
6-56.
w cl le tr p
e in nt ns co
D
th k ( de f i es
of or stu e o tat
module register_4_bit_load (D, CLK, LOAD, Q) ;

ity s w g us d S
input [3:0] D ;
is
te f t ss th nite
e rt ss fo U
input CLK, LOAD ;

gr hi in e
th a a ly by
k
in o e r
y y p d le d
output [3:0] Q ;
ro n an o te
st f a s d s ec
reg [3:0] Q ;
de o rse de ot
ill le u vi pr
w r sa co pro is
always @(posedge CLK)

o eir is rk
th nd wo
begin
a his
T
if (LOAD)
Q = D;
end
endmodule
20
6-57. *
library IEEE; if W = ‘1’ then
use IEEE.std_logic_1164.all; next_state <= STB;
entity prob_6_57 is else
port (clk, RESET, W, X, Y : in STD_LOGIC; next_state <= STA;
Z : out STD_LOGIC); end if;
end prob_6_57; when STB =>
if X = ‘0’ and Y = ‘1’ then
architecture process_3 of prob_6_57 is next_state <= STA;
type state_type is (STA, STB, STC); else
signal state, next_state: state_type; next_state <= STC;
begin end if;
when STC =>
-- Process 1 - state register next_state <= STA;
state_register: process (clk, RESET) end case;
begin end process;
if (RESET = ‘1’) then
state <= STA; -- Process 3 - output function
else if (CLK’event and CLK=’1’) then output_func: process (X, Y, state)
state <= next_state; begin
end if; case state is
end if; when STA =>
end process; Z <= ‘0’;
when STB =>
-- Process 2 - next state function if X = ‘0’ and Y = ‘0’ then
next_state_func: process (W, X, Y, state) Z <= ‘1’;
)
eb
er or in ing
ed id n
W
no the iss tea s
begin else
itt W tio
w
t p W em ch
e
d on g. in t la
m ld a
case state is Z <= ‘0’;
.
r
when STA => end if;

or ud a uc y
w cl le tr p
e in nt ns co
-- Continued in next column when STC =>

th k ( de f i es
Z <= ‘1’;
of or stu e o tat
ity s w g us d S
end case;
is
te f t ss th nite
end process;
e rt ss fo U
gr hi in e
th a a ly by
end process_3;
k
in o e r
y y p d le d
ro n an o te
st f a s d s ec
6-58. *
de o rse de ot
ill le u vi pr
w r sa co pro is
// State Diagram in Figure 6-38 using Verilog next_state <= STA;

o eir is rk
module prob_6_58 (clk, RESET, W, X, Y, Z); STB: if (X == 0 & Y == 1)

th nd wo
a his
input clk, RESET, W, X, Y; next_state <= STA;

T
output Z; else
next_state <= STC;
reg[1:0] state, next_state; STC:
parameter STA = 2’b00, STB = 2’b01, STC = 2’b10; next_state <= STA;
reg Z; endcase
end
// State Register
always@(posedge clk or posedge RESET) // Output Function
begin always@(X or Y or state)
if (RESET == 1) begin
state <= STA; Z <= 0;
else case (state)
state <= next_state; STB: if (X == 0 & Y == 0)
end Z <= 1;
// Next StateFunction else
always@(W or X or Y or state) Z <= 0;
begin STC:
case (state) Z <= 1;
STA: if (W == 1) endcase
next_state <= STB; end
else endmodule
// (continued in the next column)
21

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Problem Solutions – Chapter 6

1000 0001 AND

0101 1010 XOR

(c) XOR, 1111 1111 0000 0000

[n 2n 1  2n 1  2]/[2n 1  2n 1  2]  (n  1)2n 1 /2(2n 1)  (n  1)/2

Thus, the power dissipated by the synchronous counter is at least as large

counter’s four flip-flops are the following:

D0  Up(G 3 G 2 G1  G 3G 2G1  G 3 G 2G1  G 3G 2 G1 )   Up(G 3 G 2G1  G 3G 2 G1  G 3G 2G1  G 3 G 2 G1)

D1 =G1 G 0 +Up(G 3 G 2G 0 +G 3G 2G 0 )+Up(G 3G 2G 0 +G 3 G 2G 0 )

D 2 =G 2 G1 +G 2G 0 +UpG 3G1 G 0 +UpG 3G1 G 0

Init CTR 4 CTR 4

7-9 belowQ1and Q2  the

table. + Q2Q4, D8 = Q8  (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2

D1 + Q4) = Q1Q Q Q + Q1 Q8D

1 0 X X 0 0 X X change to: D1 to:

The basic cell cell

The basic of the as follows:

Operation Select Load

a) Destination ← Source Registers b) Source Registers → Destination

a)R0 ← R1, R2<- Source Registers

R1 <- R4 R1 -> R0, R3

c) T he minimum number of buses needed for operation of the transfers

three since transfer Cb requires three different sources.

State Input Next State Output

STA W STA * *Default: Z = 0

Def ault: Z = 0 STA

Full WASH1 Zero RINSE2

Zero WASH2 Empty SPIN3

Empty SPIN1 Zero SPIN4

the output signals.

of the states. The partial diagram for state END appears

STC1, STA2, But suppose

000 001 011

STC2 STB2 STA2

100 101 110

State Cnt = 0 Cnt = 1 DQ4 = Q4 C + Q4 Q2 + Q1 Q2 C

011 100 a) 3 (14 + 2 + 8 + 6) + 1 + 2 = 93

101 101 110

100 100 101 b) 3 (14) + 4 + 6 + 11 + 10 = 73

111 ddd ddd

110 110 111

111 ddd ddd

D1  (C0  B0) B3 B2 B1  C0 B3 B1  C0 B0 (B3 B1  B3 B1)  B3 B1 B0

BEGIN: ROLL  ROLL  0 OK BEGIN: ROLL  ROLL  1 OK

ROL: ROLL  ROLL  0 OK ROL: ROLL  ROLL  1 OK

The flip-flop input equations:

ROLL BEGIN SUR 0

(DIE1 = 1)·(DIE2 = 1)·CP/TR1

(DIE1 = 1)·(DIE2 = 1)·CP/TR2 0, ROL if (DIE1 = 1 0) DIE1 001,

CP CP if (DIE2 = 1 0) DIE2 001,

ROLL else DIE2 DIE2 +1,

else DIE1 DIE1 + 1

module Counter_4bit (Clock, Reset, EN, Q, CO) ; endmodule

wire [3:0] C, D_in;

// (continued in next column)

architecture reg_4_bit_arch of reg_4_bit is

process (CLK, CLEAR)

entity reg_4_bit is process (CLK)

end; port map (Clock, Reset, D_in(1), Q_out(1));