Computer Architecture

Wednesday, August 27, 2008

8:58 AM
Canas
 
Digital Computers
Perform computational task
Digital
Discrete values
Binary system
Binary digit
Bit
Bit groups
Character
Number
Hardware
Electronic components
Mechanical devices
Physical devices
Cpu
Memory
i/o devices
Software
Programs
Instructions
Data
System
OS
User
User programs
Functional design
Digital level
Machine level
Overall architecture
General purpose machine
Turning machine
Enough memory and time
Definitions
Bits
Bytes - 8 bits, 1 character
Word
Hertz
Reciprocal of seconds
Clock period of 100 ns--> clock rate of 10 mhz
User
Do useful work
Application
 high level programming
OS provided environment
Speed storage memory peripherals
 
Machine language programmer
Bit level
Assembly language/machine language
Mnemonic for language instructions
Assembler: translator
Depends upon the processor used
Every instruction has an Op-Code, a source and a target
Processor just executes instructions until there's a stop code
Data types
Arbitrary
Contents/use
Integers
BCD/EBCDIC/ASCII
No data type checking
Tools
Assembler
Linker
Why assembly language?
Compiler writer
Familiar with machine language
Optimize code
Number of registers
Size
Registers exist to interpret the op code in instructions
Instruction set
Possible operations
Machine language instructions
ISA instruction set architecture
Instruction set
Memory
Programmer accessible registers
Instruction classes
Data movement
Arithmetic and logic
Control flow
Machine state
Registers
Memory
Interrupts
Timer ticks down to 0
And IO operation terminates and is back at cpu
If there is another process that needs to be executed, cpu will
execute the first one for a set amount of time, saves the memory
 address where it left off, then sets that process aside and starts the
new one
Memory
Bit/byte/word addressable word is how many bits are in one word
Example;
MC68000 processor
Byte addressable
Instructions 16 bits (2 bytes)
PC increments by two
Most machines are word addressable
Memory Hierarchy
CPU
Cache->main->disk->tape
Peripherals
I/O devices
Tools
Benchmark
Simulators/emulators
RTN
Register transfer language
Computer architect
Design and performance
Speed/size/networking
Building blocks
I/O
ISA
Interface between programmer/functional unit
Computer logic design
Gates
NAND, OR, AND
MACs and Linux exact same except MAC has GUI
Boolean Algebra
 * Is AND
 + is OR
 ' is NOT
 All 0s, if x=0,y=1,z=1, then M=xy'z'
 (x+y)' = x'y'
 Demorgans law:
o When finding compliment, convert 0 t 1, 1 to 0, AND to OR, OR to AND
 Minterm /Maxterm
o Any boolean expression may be expressed in terms of either
minterms or maxterms. To do this we must first define the concept of a
literal. A literal is a single variable within a term which may or may not
be complemented. For an expression with N variables, minterms and
maxterms are defined as follows :
o A minterm is the product of N distinct literals where each literal
occurs exactly once.
 o A maxterm is the sum of N distinct literals where each literal occurs
exactly once.
o
  For a two-variable expression, the minterms and maxterms are
as follows
 
  X Y Minterm Maxterm
0 0 X'.Y' X+Y
0 1 X'.Y X+Y'
1 0 X.Y' X'+Y
1 1 X.Y X'+Y'

 
  For a three-variable expression, the minterms and maxterms are
as follows
 
  X Y Z Minterm Maxterm
0 0 0 X'.Y'.Z' X+Y+Z
0 0 1 X'.Y'.Z X+Y+Z'
0 1 0 X'.Y.Z' X+Y'+Z
0 1 1 X'.Y.Z X+Y'+Z'
1 0 0 X.Y'.Z' X'+Y+Z
1 0 1 X.Y'.Z X'+Y+Z'
1 1 0 X.Y.Z' X'+Y'+Z
1 1 1 X.Y.Z X'+Y'+Z'
 
 
Pasted from <http://www.asic-world.com/digital/boolean2.html>
 
 If a function is expressed as a product or sum of … is said to be in canonocal form
o Express any function as a sum of minterms
 F=A+B'C
 Consider term A, its missing B and C to be a minterm
 A = A(B'+B)
 …
 (AB'+AB)(C+C')
  …
o Express as a function of minterms
 Use distributive law x+yz=(x+y)(x+z)
 Add +x'x if needed, because anything + 0 = 0 anything
o If asked to find ' of a function, pick the remaining min/maxterms
 K maps
o The function for this is F= x’y + xy’ + x’y’
o
x\y 0 1

0 1 1

1 1 0
o Adjacent squares differ by one variable
 You can simplify this kmap
Combine m0 and m1
x’y’ + x’y => x’( y + y’) = x’
Combine m0 and m2
x’y’ + xy’ => y’( x + x’) = y’
 
F = x’ + y’
 
o 3 variable kmap
o
Y0z0 Y0z1 Y1z1 y1z0

x0 m0 m1 m3 m2

x1 m4 m5 m7 m6
You can find out how to simply the equation by looking at adjacent blocks that don't
change
 
 
o F(x,y,z) = Σ(2,3,4,5)
 y'yz'+x'yz+xy'z'+xy'z
 Put a 1 in the k map for the m(n) corresponding to Σ(n)
o
x\yx Y0z0 Y0z1 Y1z1 y1z0

x0 m0 m1 1 m3 1 m2

x1 1 m4 1 m5 m7 m6
o m2 and m3
 X is always 0 Y is always 1, drop the z
 =x'y
o m4 and m5
 X is always 1 and y is always 0, drop the z
  Xy'
o Final function is only F=x'y+xy'
 
 
F(x,y,z) = Σ(3,4,6,7)
o
x\yx Y0z0 Y0z1 Y1z1 y1z0

x0 m0 m1 1 m3 m2

x1 1 m4 m5 1 m7 1 m6
o You have a choice for simplification here
 You can combine m4 and m6 because kmaps are cylinders
 Drop the y
 xz'
 Combine m3 and m7
 Drop the x
 yz
 You can reuse an m(n) box when simplifying
o Final F=xz'+yz
 
 
Four variable
o
wx\yx Y0z0 Y0z1 Y1z1 y1z0

w0x0 m0 m1 m3 m2

w0x1 m4 m5 m7 m6

w1x1 m12 m13 m15 m14

w1x0 m8 m9 m11 m10

 
Canonical form
Means an equation with, say, 4 variables, must have all four variables in each part of
the equation
Ex:
F(x,y,z) = Σ(2,3,4,5)
 y'yz'+x'yz+xy'z'+xy'z
 Simplified (not canonical): F=x'y+xy'
 
Adders carry look-ahead logic
Takes two values and produces a sum and a carry
The carry in is initially zero, the carry out is the result, which can at most be 1
Uses exclusive-or
Only 1,0 or 0,1 produces a 1, a 1,1 or 0,0 produces a 0
z x-or(x x-or y)
 Carry=xy'z+xýz+xy
The delay in waiting for the previous digit to be finished is called carry propagation
 
Number systems
Dec Hex Oct Bin

0 0 0 0

1 1 1 1

2 2 2 10

3 3 3 11

4 4 4 100

5 5 5 101

6 6 6 110

7 7 7 111

8 8 10 1000

9 9 11 1001

10 A 12 1010

11 B 13 1011

12 C 14 1100

13 D 15 1101

14 E 16 1110

15 F 17 1111
 
Storing and remembering things: synchronous sequential logic
Has a storage element
Affected by a signal
Clock pulse
Storage element affected by clock pulse
Memory elements
Time delayed devices
Master clock generator
Generates periodic clock pulses
Memory elements affected at clock pulses
Clocked sequential circuits
Memory elements (flip flops)
Store 1 bit of information
Flip flop
D flip flop eliminates indeterminate states ensures R& S are never 1
Set, Reset, Clock pulse (if =0, nothing happens, only changes when it goes 0 to
1)
 Out: Q' Q
As long as C.P is at 1, the values of Q and Q' will keep changing.
Clock pulse needs to be shorter than propagation delay to prevent that
 
T flip flop
Instead of set and reset, just one input, T
 
Master-Slave flip flop
2 next to each other
Outputs of 1 go to set and rest of the other
Pulse for the second is NOT of CP for first
 
Carry look-ahead logic
Simultaneous addition so there isn't as big of a propagation delay
C2=G1+P1C1
C3=G2+P2C2 = G2+P2(G1+P1C1)
C3=G2+P2G1+P2P1C1
Do a new set of gates for each bit digit
 

 
Screen clipping taken: 9/26/2008, 9:28 AM
 
 
  
Screen clipping taken: 9/26/2008, 9:31 AM
2s compliment (to get the negative of a binary # or subtraction
Flip all except leading 0s and the first 1
Example: compliment of 0010 would be 1110
Addition and subtraction straight forward
1s compliment
Flip all
Ex 0010 would be 1101
Addition and subtraction
If the carry carries over how many bits you are using, add 1 to the carry in
Arithmetic
22-7=15
 2s compliment
11111 1111 1111 000-- carry
0000 0000 0001 0110 22
1111 1111 1111 1001 – 7 (+ -7)
0000 0000 0000 1111 =15
 1s compliment
11111 1111 1110 0001 carry (+1)
0000 0000 0001 0110 22
1111 1111 1111 1000 -7
0000 0000 0000 1111 =15
Signed integers
The first bit is the sign, 1=- 0=+
Then just the regular # in binary
 
Number representation
Integers vs floating point numbers
 
 
Test
Boolean algebra
Kmaps

wx\yx Y0z0 Y0z1 Y1z1 y1z0

w0x0 m0 m1 m3 m2

w0x1 m4 m5 m7 m6

w1x1 m12 m13 m15 m14

w1x0 m8 m9 m11 m10

 3 variable kmap

Y0z0 Y0z1 Y1z1 y1z0

x0 m0 m1 m3 m2

x1 m4 m5 m7 m6
 2 var

x\y 0 1

0 1 1

1 1 0
Simplification of functions
Adder
 

 
Screen clipping taken: 10/6/2008, 8:14 Pm
Flip flops
 

 
  
 

 
 
 
 
Octal x, number system
0-7
01234567 10 11 12 13 14 15 16 17 20
Compliments, 1 2
2s compliment (to get the negative of a binary # or subtraction
Flip all except leading 0s and the first 1
Example: compliment of 0010 would be 1110
Addition and subtraction straight forward
1s compliment
Flip all
Ex 0010 would be 1101
Addition and subtraction
If the carry carries over how many bits you are using, add 1 to the
carry i
Floating point
Normalize mentissa
First value in binary guarnteed to be 1, can leave it out
Bias e' = if range of exp, is 255, aka, -127 to 127, then 127 is the bias
e = é - 127
 
  
Screen clipping taken: 10/6/2008, 7:56 PM
 
 
 
 
 
Tuesday, October 07, 2008
1:22 PM
Test
Boolean algebra
Kmaps

wx\yx Y0z0 Y0z1 Y1z1 y1z0

w0x0 m0 m1 m3 m2

w0x1 m4 m5 m7 m6

w1x1 m12 m13 m15 m14

w1x0 m8 m9 m11 m10

 3 variable kmap

Y0z0 Y0z1 Y1z1 y1z0

x0 m0 m1 m3 m2

x1 m4 m5 m7 m6
 2 var

x\y 0 1

0 1 1

1 1 0
Simplification of functions
Adder
 
  
Screen clipping taken: 10/6/2008, 8:14 Pm
Flip flops
 

 
 

 
 
 
 
Octal x, number system
0-7
01234567 10 11 12 13 14 15 16 17 20
Compliments, 1 2
2s compliment (to get the negative of a binary # or subtraction
Flip all except leading 0s and the first 1
Example: compliment of 0010 would be 1110
 Addition and subtraction straight forward
1s compliment
Flip all
Ex 0010 would be 1101
Addition and subtraction
If the carry carries over how many bits you are using, add 1 to the carry i
Floating point
Normalize mentissa
First value in binary guarnteed to be 1, can leave it out
Bias e' = if range of exp, is 255, aka, -127 to 127, then 127 is the bias
e = é - 127
 

 
Screen clipping taken: 10/6/2008, 7:56 PM
 
Lab 1
Wednesday, August 27, 2008
8:59 AM
 
For each
a. Truth table
a. Kmap
a. Simplified function
a. Logic diagram
F1 (ABCD)= 0,1,2,4,5,7,11,15
1.
A B C D F1

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1
 1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

2.
AB\CD C0D0 C0D1 C1D1 C1D0

A0B0 1 1 0 1

A0B1 1 1 1 0

A1B1 0 0 1 0

A1B0 0 0 1 0
3. A'C'+BCD+ACD+A'B'D'
4.

 
Screen clipping taken: 9/12/2008, 4:22 PM
 
 
F2(ABCD)= 0,2,4,5,6,7,8,10,13,15
1.
A B C D F2

0 0 0 0 1

0 0 0 1 0

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1
 1 0 0 0 1

1 0 0 1 0

1 0 1 0 1

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1
 
2.
AB\CD C0D0 C0D1 C1D1 C1D0

A0B0 1 0 0 1

A0B1 1 1 1 1

A1B1 0 1 1 0

A1B0 1 0 0 1
3. A'B+DB+D'B'
 4.

 
Screen clipping taken: 9/11/2008, 9:10 PM
 
 
 
Lab 2 adder
Wednesday, September 17, 2008
9:04 AM
Build an adder
Input for each is A1 B1 (current digit bit) and Cin
Output is S1 and Cout
Cout goes to the next Cin
Do 8 little adders like this
1's compliment
2's compliment
1's compliment +1
(put a 1 in the carry in)
If there's a carry out, ignore it, if there's no carry out, it's negative
To have both subtraction and addition on same circuit, have ex-ors before the Bs and cin
 
Timeline
 The start is when you change cin
The end solution bit changes to 1 (*pick a number such that the last bit will change
and that will be the end
 
HW
Tuesday, September 23, 2008
7:31 PM
 
1.  
a.
AB\CD C0D0 C0D1 C1D1 C1D0

A0B0 m0 m1 m3 m2

A0B1 1 m5 1 1

A1B1 m12 m13 1 m14

A1B0 m8 m9 m11 m10

F= A'BC+BCD
 
a.
AB\CD C0D0 C0D1 C1D1 C1D0

A0B0 m0 m1 1 m2

A0B1 m4 m5 1 m6

A1B1 m12 1 1 1

A1B0 m8 m9 1 m10
F=CD+ABD+ABC

b.
AB\CD C0D0 C0D1 C1D1 C1D0

A0B0 1 m1 m3 1

A0B1 1 1 1 1

A1B1 m12 1 1 m14

A1B0 1 m9 m11 1
F=B'D'+A'B+BD
 
 
2. F=XY'Z+X'Y'Z+XYZ
a.
 X Y Z F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1
b. F=XY'Z+X'Y'Z+XYZ
F=XZ+Y'Z
3.
a. F=AB+A(CD+CD')
F=AB+ACD+ACD'
F=AB+AC
b. F=(BC'+A'D)(AB+CD')
F=A(BB)C+B(CC')D+(AA')BD+A'C(DD')
F=A(B)C+B(0)D+(0)BD+A'C(0)
F=A(BB)C+B(CC')D+(AA')BD+A'C(DD')
F=ABC
4. -
a. X'Z'+Y'Z'+YZ'+XY
i. Sum of products
X'Y'Z'+X'YZ'+XY'Z'+XYZ'+XYZ
S(0,2,4,6,7)
b. Product of sums
P(1,3,5)
(X+Y+Z')(X+Y'+Z')(X'+Y+Z')
b. AC'+B'D+A'CD+ABCD
i. Sum of products
A'B'C'D+A'B'CD+A'BCD+AB'C'D'+AB'C'D+AB'CD+ABC'D'+ABC'D+ABCD
S(1,3,7,8,9,11,12,13,15)
b. Product of sums
P(0,2,4,5,6,10,14)
(A+B+C+D)(A+B+C'+D)(A+B'+C+D)(A+B'+C+D')(A+B'+C'+D)(A'+B+C'+D)
(A'+B'+C+D)
 
2nd part
Friday, October 10, 2008
9:18 AM
 
Register Transfer and Micro operations
Code on a machine level
Execute stuff
Microprogram; stored to rom, read only, every clock pulse takes code and does stuff
If there's a bug you don't have to rewire it, just change ROM
Register
Group of flip flops
N bit registers
N flip flops
Register with parallel load
Continuous train of clock pulses
Master clock
Speed depends on processor
Memory
Collection of storage cells
Bit
Byte (8 bits)
Word
16, 32, 64
May represent anything
Binary number, instruction code, character
Structure
Byte addressable
Word addressable
RAM
Random access memory
ROM
Read only memory
m*n Rom
M words, N bits
Register transfer language
Digital circuit
Interconnection of digital hardware
Vary in size and complexity
Design in modules
Modules constructed from digital components
Registers
Multiplexors
Decoders
Arithmetic unit
Register with parallel load
Continuous train of clock pulses
Master clock
Seprate control signal required
Activate register a specific clock pulse
ROM
Non volatile; maintains even when power is off
Mask programmed
 Customized
PROM
Programmable
EROM
Erasable
more modern types such as EPROM and flash EEPROM can be erased and re-programmed
multiple times; they are still described as "read-only memory" because the reprogramming
process is generally infrequent
Decoder
N bits-> 2n distinct elements
Triangle thing, tristate 2
A input, C control input
Out put Y=A if c=1, high impedance if c=0
 
Types of Registers
Symbol # of bits Register name Function

DR 16 Data register Holds memory operand

AR 12 Address register Holds address for memory

AC 16 Accumulator Processor register after adder/logic

IR 16 Instruction register Holds instruction code

PC 12 Program counter Holds address for instruction

TR 16 Temporary register Holds temporary data

INPR 8 Input register Holds input character

OUTR 8 Output register Holds output character

SC   Sequence Counter  
Types of executions
 
Register transfer notation
individual bits
R3(0..3) or PC(L)
L means least significant half of bits
R2 <-- R3
• transfer contents of R3 to R2
• R3 is unchanged
• requires circuits form output of R3 to input of R2
• control condition:
• P is control signal
if ( P==1 ) then ( R2 <- R3 )
P: R2 <- R3
every statement in RTN implies a control signal
Sync'd with clock
memory transfer
 • read : MDR <-- M[MAR]
• write: M[MAR] <-- R2
R3 R1 + R2 R1 plus R2 transfered to R3

R3 R1 - R2 R1 minus R2 transfered to R3

R2 R2’ Complement R2 (1’s complement)

R2 R2’ + 1 Complement R2 (2’s complement)

R3 R1 + R2’ + 1 Subtract

R1 R1 + 1 Increment R1 by 1

R3 R3 - 1 Decrement R3 by 1
Instruction code
Oppcode and operands (addresses of source and targets)
direct and indirect addressing
• effective address
address to be used
• direct address (address in the current statement)
specified in instruction
• indirect addressing I=1
Instruction specifies address of address
Memory address of the operator
I = direct/indirect indicator
 
  

common bus system

 

• basic computer
• eight registers
• memory unit
• control unit
 • one common bus
• load input signal
• master clock
Instruction format
 

Symbol I=0 I=1 Description

AND 0xxx 8xxx AND memory to AC

ADD 1xxx 9xxx ADD memory to AC

LDA 2xxx Axxx LOAD memory to AC

STA 3xxx Bxxx STORE AC to memory

BUN 4xxx Cxxx Branch unconditional

BSA 5xxx Dxxx Branch and save

ISZ 6xxx Exxx increment and skip if zero

+ more      
memory access
• memory read/write cycle
• if smaller than one clock cycle
• completed in one cycle
• if longer than one clock cycle
• processor must wait
• wait cycle
Instruction cycle
Fetch from mem
Decode
Read effective address from mem if necessary
Execute instruction
T0-T2 fetch and decode
T0 : AR ←PC
PC initially has address of first instruction
T1 : IR ←M[AR}, PC ←PC + 1
Clear SC to 0, first instruction
Increment SC on pulse
 Move code from memory at the address specified by the Address Register,
move it to the Instruction Register
T2 : D0,...D7 ← Decode IR(12-14)
Opp code is decoded
AR ←IR(0-11)
Sends address part from instruction code to address register
I ←IR(15)
Determines In/direct type of addressing
at T3 control unit determines type of instruction
D7, least sig bit of opp code (after decode?)
0 =Means memory (from memory) reference, or 1=1 register (from multi purpose
register) reference
Then see what I=
If 0, direct addressing, don't need to do anything for execution
I/O means dealing with memory
 

D7I’T3 = r (common to all register-reference instructions)

IR(i) = Bi[bit in IR(0-11) that specifies the operation]
 
• effective address is in AC
• placed at T2 when I=0 or T3 when I=1
• execution start with timing T4
• data must be read from memory to a register
Types of instructions with executions
AND to AC
• AND of AC with memory word
• D0 is active when opcode = 000
D0T4: DR M[AR]
D0T5: AC AC ^ DR, SC 0
ADD to AC
• ADDS contents of memory word
• D1 is active when opcode = 001
D1T4: DR M[AR]
D1T5: AC AC + DR, E Cout, SC 0
LDA: load to AC
• transfers memory word to AC
 • D2 is active when opcode = 010
• there is no direct path from bus to AC
• would take more than one clock cycle
• by not connecting bus to AC mircoinstructions
take one clock cycle
D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA: store AC
• stores AC to memory
• both AC and AR are connected to the bus
• can execute in one micro instruction
D3T4: M[AR] AC, SC 0
BUN: branch unconditionally
• transfer control to instruction specified by address
• must change contents of PC
• can execute in one micro instruction
D4T4: PC AC, SC 0
BSA: branch and save return address
• use to branch to a function
• return address (PC) is saved in memory
• effective address +1 (next one) is stored in PC
T4
• initiates memory write operation
• places contents of PC on bus
• enables INR input in AR
39
D5T4: M[AR] PC, AR AR
ISZ: increment and skip if zero
• increments word specified by effective
address
• if incremented value = 0
PC = PC + 1
D6T4: DR M[AR]
D6T5: DR DR + 1
D6T6: M[AR] DR, if (DR=0) then (PC PC+1), SC 0
 
  
Overflow
Only occurs when there is a sign change in the number that it shifted
 
 
 
 

 
3rd part
Wednesday, November 12, 2008
9:30 AM
 
Input/output and interrupts
User interface
Simple I/O
Cpu has to wait for input from keyboard/user
INPR receives byte from keyboard
FGI
Flip flop that turns to 1 when a character has come
Interrupts
Input is thousands of times slower than CPU, checking for new input as often as possible is
too slow
Informs device when input has come in so that cpu isnt constantly checking for it
Any keystroke fires off an interrupt and series of code
Assembly Language
Hardware and software
Binary codes
Difficult to understand
Programming
Assembler
High level language
Computers can only take binary