ECE 538

VLSI System Testing

Krish Chakrabarty

Test Generation: Part 1

ECE 538 Krish Chakrabarty 1

Introduction
•  Classification of test generation methods
•  Fault table analysis
•  Boolean difference method
•  Propagation, implication and justification
procedures
•  D-algorithm
•  9-V algorithm (multiple path sensitization)

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 General Approaches
•  Systematic (algorithmic)
–  Fault table analysis
–  Boolean difference method
–  Fault-oriented methods (D-algorithm, PODEM)
–  Fault-independent methods (critical path tracing)
•  Exhaustive/pseudoexhaustive
•  Random/pseudorandom

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Fault Table Analysis

Fault
a/0 a/1 b/0 b/1 z/0 z/1
2-input OR gate
ab
a 00 x x x
z
b Test 01 x x
10 x x
11 x

•  Determine fault table via simulation and solve covering

problem
•  Covering problems are NP-complete
•  Computationally infeasible

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 Fault-Oriented ATPG
Procedure Generate_Tests()
begin
repeat
begin
Select uncovered fault f
Generate test for f
Evaluate current fault coverage
end
until fault coverage > limit, or time runs out
end

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Boolean Difference
The Boolean difference of F(x1, x2 , x3,…, xn) with respect to xi is given
by
∂F
= F(x1, x2 ,…,1, x3,…, xn) ⊕ F(x1, x2 ,…,0, x3,…, xn)
∂xi

Cofactor w.r.t. xi Cofactor w.r.t. xi

Boolean difference provides input combination for sensitized path
A test pattern for xi/0 is an input combination that makes xi ∂F = 1
∂xi
∂F
A test pattern for xi/1 is an input combination that makes xi = 1
∂xi

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 Boolean Difference
a f j
b
g
c
h i z
d
k
e

To find a test for a/0 or a/1, determine the Boolean difference of output z with
respect to a:
∂z
=?
∂a
How to handle internal faults, e.g. j/0?

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Key Terminology
•  Backtrace: move a goal value backwards in a circuit to a
primary input
•  Backtrack: return to a previous decision point in an algorithm
and make an alternative decision
•  D-frontier: Set of gates closest to primary output with D or D
on some input
•  Implication: Determine unique signal values that are forced
by signal values already assigned
•  Justification: Determine values to unspecified inputs of gates
whose outputs are specified (backward)
•  Propagation (D-drive): Determine path values needed to
propagate an error signal to a primary output (forward)

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 Testing Fanout-Free Circuits
•  No (reconvergent) fanout
–  Propagation path from any line is unique
–  Each line justification problem is independent of all others

Test generation for line l/v in a fanout-free circuit

begin
set all values to X (unknown)
Justify(l,v)
if v = 0 then Propagate(l,D)
else Propagate(l,D)
end

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Testing Fanout-Free Circuits

Error propagation:

Propagate(l,err)
/* err is D or D */
begin 1 err
set l to err l err
if l is PO then return 1
k = the fanout gate of l
c = controlling value of k
i = inversion of k
for every input j of k other than l
Justify(j,c)
Propagate(k,err⊕ i)
end

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 Testing Fanout-Free Circuits
Justify(l,val) Line Justification
begin
set l to val
if l is PI then return
/* l is a gate (output) */ 1 0
c = controlling value of l 1
l
1
i = inversion of l
inval = val ⊕ i
if(inval = c) X 1
then for every input j of l 0
Justify(j,inval) X l
else
begin
Select one input (j) of l
Justify(j,inval)
end
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Functional vs Structural Testing

•  Functional ATPG – generate complete set of tests for circuit
input-output combinations
–  129 inputs, 65 outputs:
–  2129 patterns
–  Using 1 GHz ATE, would take 2.15 x 1022 years
•  Structural test:
–  No redundant adder hardware, 64 bit slices
–  Each with 27 faults (using fault equivalence)
–  At most 64 x 27 = 1728 faults (tests)
–  Takes 0.000001728 s on 1 GHz ATE
•  Designer gives small set of functional tests – augment with
structural tests to boost coverage to 98+ %

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 Algorithm Completeness
•  Definition: Algorithm is complete if it ultimately
can search entire binary decision tree, as needed,
to generate a test
•  Untestable fault – no test for it even after entire
tree searched
•  Combinational circuits only – untestable faults
are redundant, showing the presence of
unnecessary hardware

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D-Algorithm
b
a C
B
c G z
A B/1 E
d
e F
b
H

Decision Implication Comment

B=D E = D, A = 0, a = 0 Activate fault

b=1 C=D Propagate via C
F=0 z=D End of D-drive
H=0 e=0 Justify F
c = 0 (1) Justify A
Test: abce = 0100
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 D-Algorithm
b
a C
B
c G z
A B/1 E
d
e F
b
H

Decision Implication Comment

B=D E = D, A = 0, a = 0 Activate fault

H=1 F=D Propagate via F
C=0 z=D End of D-drive
b=0 e=0 Justify C
c = 0 or e = 0 Justify A
Test: abce = 0000
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D-Algorithm
Fault e/0
h
f
c i Single path sensitization
a e does not always work!
b z
j
d
g k

Decision Implication Action

e = D, c = 0 i = D, f =1, h = 0 Activate fault, propagate via i

j=k=0 z=D Contradiction End of D-drive
d = 1, b = 1 g = 0, e = 0 Justify j = 0, k = 0 (Backtrack)
c = 0, d = 0 i=j=D propagate through i and j

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 Comments on the D-Algorithm
•  Based on propagation (primary procedure),
justification and implication
•  In complete form, guarantees test generation but
may require multiple path sensitization
(computationally expensive)
•  Practical restrictions:
–  Single path sensitization only
–  Limits placed on backtracking time (aborted faults)

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9-V Algorithm
•  Nine logic values, specified as good/bad pairs:
1/1, 0/0, 1/0, 0/1, u/u, 1/u, 0/u, u/0, u/1
•  Example of logic operations: D.X = 1/0.u/u = u/0,
i.e. provides more information than the X outcome
for 5-valued algebra
•  Reduces backtracking
–  When there are k possible paths for error propagation,
D-algorithm may try all 2k-1 combinations of paths
–  9-V enumerates only k ways of propagation

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 Path Sensitization
1  Fault Sensitization
2  Fault Propagation
3  Line Justification

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Path Sensitization
  Try path f – h – k – L blocked at j, since there
is no way to justify the 1 on i

1 D

D D
1 D
D 0
1

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 Path Sensitization
  Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because D-frontier (chain of D
or D) disappears
1 D
D 1
1
D D
D
1

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Path Sensitization
  Final try: path g – i – j – k – L – test found!

0
0 D
1 D
D D D
1
1

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 Random Test Generation
•  Flow chart for
method
•  Use to get tests
for 60-80% of
faults, then
switch to D-
algorithm or
other ATPG for
rest

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