FINITE STATE MACHINES (FSM)

DESCRIPTION IN VHDL

Cristian Sisterna
UNSJ
 FSM Review
2

 A sequential circuit that is implemented in a fixed

number of possible states is called a Finite State
Machine (FSM).

 Finite state machines are critical for realizing the

control and decision-making logic in a digital system.
 Finite state machines have become an integral part of
the system design.

 VHDL has no formal format for modeling finite state

machines.
 To model a finite state machine in VHDL certain
guidelines must be followed.

FSM - DSDA Cristian Sisterna

 FSM Example
3

Realizar la descripción en VHDL de un transmisor de dato serie

bajo el protocolo RS-232. El dato a transmitir debe tener el
siguiente formato:
1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.
La Tx se inicia por medio de la señal start_tx

FSM - DSDA Cristian Sisterna

 FSM Example
4

RS-232 Tx format

FSM - DSDA Cristian Sisterna

 State Machine State Diagram
5

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 State Machine State Diagram
6

start_tx

Idle

stop

start
parity

shift

8_bits

FSM - DSDA Cristian Sisterna

FSM General Schemes

FSM - DSDA Cristian Sisterna

 State Machine General Scheme 1
8

Inputs
Current Outputs
Next State
Next Current
State
Output
Output
Logic
State Next State Logic
Logic Current Logic
Logic
Logic State
State

Clk
Rst

FSM - DSDA Cristian Sisterna

 State Machine General Scheme 1
9

Inputs Outputs
Next State Logic
&
Output Logic

Current
Current
State
State Logic
Logic

Clk
Rst

FSM - DSDA Cristian Sisterna

 State Machine General Scheme 2
10

Inputs Current
Next
Next Current
Current Synchr. Outputs
State Output
Output Sync
State
State State
State Logic Output
Output
Logic Next Logic Logic
Logic State Logic Logic
FFs

Clk
Rst

FSM - DSDA Cristian Sisterna

 State Machine General Scheme 3
11

Output A
Synchronous
Output Logic

Inputs
Next
Next
Next Current
Current Current
State
State
State State
State State ...
Logic
Logic Logic
Logic ...

Synchronous Output Z
Output Logic

Clk
Rst

FSM - DSDA Cristian Sisterna

 State Machine - Special Case 1
12

Synchronous
Sync Outputs
Output
Output
Logic
FFs

Inputs
Next
Next Current
Current
State
State State
State
Logic Next
Logic State Logic
Logic
Current
State

Clk
Rst

FSM - DSDA Cristian Sisterna

FSM – VHDL Considerations

FSM - DSDA Cristian Sisterna

 FSM VHDL General Design Flow
14

Specifications

Understand the
Problem Traditional Steps

Draw the ASM or State

Diagram

Define an FSM +
Enumerated Type

Define FSM
Signals
VHDL Steps
Select an Encoding
Technique (optional)

Write the VHDL

Code
FSM - DSDA Cristian Sisterna
FSM Enumerated Type Declaration

FSM - DSDA Cristian Sisterna

 FSM Enumerated Type Declaration
16

Declare an enumerated data type with values (names) the states of

the state machine
Symbolic State
-- declare the states of the state-machine Names
-- as enumerated type
type FSM_States is(IDLE,START,STOP_1BIT,PARITY,SHIFT);

Declare the signals for the next state and current state of the state
machine as signal of the enumerated data type already defined
for the state machine

-- declare signals of FSM_States type

signal current_state, next_state: FSM_States;

The only values that current_state and next_state can hold are:
IDLE,START,STOP_1BIT,PARITY,SHIFT
FSM - DSDA Cristian Sisterna
FSM – Encoding Techniques
 FSM Encoding Techniques
18

type FSM_States is(IDLE, START, STOP_1BIT, PARITY, SHIFT);

signal current_state, next_state: FSM_States;

State Assignment
 During synthesis each symbolic state name has to be

mapped to a unique binary representation

 A good state assignment can reduce the circuit size
and increase the clock rate (by reducing
propagation delays)
 The hardware needed for the implementation of
the next state logic and the output logic is directly
related to the state assignment selected
FSM - DSDA Cristian Sisterna
 FSM Encoding Schemes
19

An FSM with n symbolic states requires at least [log2 n ]

bits to encode all the possible symbolic values

Commonly used state assignment schemes:

 Binary: assign states according to a binary sequence

 Gray: use the Gray code sequence for assigning

states
 One-hot: assigns one ‘hot’ bit for each state

 Almost one-hot: similar to one-hot but add the all

zeros code (initial state)

FSM - DSDA Cristian Sisterna

 FSM Encoding Schemes
20

Binary Gray One-Hot Almost One-hot

idle 000 000 00001 0000
start 001 001 00010 0001
stop_1bit 010 011 00100 0010
parity 011 010 01000 0100
shift 100 110 10000 1000

FSM - DSDA Cristian Sisterna

 Encoding Schemes in VHDL
21

During synthesis each symbolic state name has to be

mapped to a unique binary representation

How is the map process done ?

user attribute enum_encoding

(synthesis attribute) (VHDL standard

explicit user-defined default encoding

assignment
FSM - DSDA Cristian Sisterna
 syn_encoding – Quartus & Synplify
22

• syn_encoding is the synthesis user-attribute of Quartus

(Synplify) that specifies encoding for the states modeled by an
enumeration type

• To use the syn_encoding attribute, it must first be

declared as string type. Then, assign a value to it, referencing
the current state signal.
-- declare the (state-machine) enumerated type
type my_fms_states is (IDLE,START,STOP_1BIT,PARITY,SHIFT);
-- declare signals as my_fsm_states type
signal nxt_state, current_state: my_fsm_states;
-- set the style encoding
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states : type is “one-hot”;

FSM - DSDA Cristian Sisterna

 syn_encoding - Quartus & Synplify
23

Possible values:
 default: assign an encoding style based on the number of states:
 Sequential encoding for 0 - 4 enumerated types
 One-hot encoding for 5 – 50 enumerated types
 Gray encoding for > 50 enumerated types
 sequential: 000 001 010 011 100 101 110 111
 one-hot: 0000001 00000010 00000100 . . .
 gray: 000 001 011 010 110 111 101 100
 johnson : 0000 0001 0011 0111 1111 1110 1100 1000
 safe: default encoding + reset logic to a known state
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “one-hot, safe”;

 user-defined: assign an encoding style defined by the user

attribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “10 11 01 00”;
FSM - DSDA Cristian Sisterna
 Examples of Synthesis Reports (Quartus)
24

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 Results for Different Encoding Schemes
25

Simple, 5 states, state machine

One-hot One-hot Gray Gray-Safe Binary Johnson
safe
Total
combinatio
76 66 66 68 66 68
nal
functions
Dedicated
logic 45 45 43 43 43 43
registers
Max. frq. 352.24 340.95 331.02 335.01 338.34 311.72

FSM - DSDA Cristian Sisterna

 Results for Different Encoding Schemes
26

19 states, state machine

One-hot One-hot Gray Gray-Safe Binary Johnson

safe
Total
combinati
556 523 569 566 561 573
onal
functions
Dedicated
logic 215 215 201 201 201 206
registers
Max. frq. 187.3 175.22 186.39 180.6 197.63 186.22

FSM - DSDA Cristian Sisterna

 Xilinx XST State Encoding Techniques
27

XST (the synthesis tool for ISE) supports the following

state encoding techniques:
Auto-State Encoding
One-Hot Encoding
Gray State Encoding
Compact State Encoding
Johnson State Encoding
Sequential State Encoding
Speed1 State Encoding
User State Encoding

FSM - DSDA Cristian Sisterna

 XST State Encoding Techniques
28

Declare the attribute as follows:

attribute fsm_encoding: string;

Specify as follows:
attribute fsm_encoding of {entity_name|signal_name }:
{entity |signal} is "{auto | one-hot | compact|
sequential| gray| Johnson | speed1|user}";

The default is auto

FSM - DSDA Cristian Sisterna

 State Machine Coding: Residual States
29

 If one-hot state coding is not used, the maximum

number of states is equal to 2**N, where N is the vector
length of the state vector

 In state machines where not all the states are used,

there are three options:
 Let chance decide what is to happen if the machine goes to
an undefined state
 Define what is to happen if the state machine goes to an
undefined state by ending the case statement with when
others
 Define all the possible states in the VHDL code

FSM - DSDA Cristian Sisterna

 State Machine Coding: Synplify Report
30

FSM - DSDA Cristian Sisterna

 State Machine Coding: XST Report
31

==============================================
* Advanced HDL Synthesis *
==============================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <rs232_tx/tx_current_state/FSM> on signal
<tx_current_state[1:3]> with sequential encoding.
-----------------------------
State | Encoding
-----------------------------
idle | 000
start | 001
shift | 010
parity | 011
stop_1bit | 100
-----------------------------

FSM - DSDA Cristian Sisterna

 State Machine Coding: Quartus Report
32

FSM - DSDA Cristian Sisterna

 State Machine Coding: Simulation
33

FSM - DSDA Cristian Sisterna

FSM Style Description Example
 State Machine VHDL Coding Styles
35

Inputs
Next
Next Current
Current Output Outputs
State
State
Next
State
State Output
Logic
Logic
Logic
Logic State Logic
Logic Current
State

CLK
RST

Coding Style Current State Next State Logic Output Logic

Style E Seq. Logic Comb. Logic Seq. Logic

Style A Seq. Logic Comb. Logic Comb. Logic

Style C Seq. Logic Comb. Logic

Style D Seq. Logic Comb. Logic

Style B Seq. Logic

FSM - DSDA Cristian Sisterna

 FSM: Clocked Process for Current State
36

 The current_state clocked process decides when the state machine

should change state
 This process is activated by the state machine’s clock signal
 Depending on the current state and the value of the input signals,
the state machine can change state at every active clock edge
 Current state gets the value of the next state on the active edge of
the clock
 The next state value is generated in the next state process
(combinational process), depending on the values of current state
and the inputs

Cristian Sisterna FSM - DSDA

 FSM: Combinational Process
37

Next State and Output Logic

 Assigns the output signals their value depending on the current state
 Assigns the next state value depending on the current state and the
input’s value(s)
 Next state logic and output logic is best modeled using case
statements are better for this process
 All the rules of combinatorial process have to be followed to avoid
generating unwanted latches
 For Mealy Machines if-then-else statement is used to create
the dependency between the current state, the input signals and
output signals

FSM - DSDA Cristian Sisterna

 State Machine: Reset behavior
38

 Asynchronous reset: ensure that the state machine

is always initialized to a known valid state, before
the first active clock transition and normal operation
commences

 No reset : there is no way to predict the initial value

of the state register flip-flops. It could power up
and become permanently stuck in an uncoded state.

FSM - DSDA Cristian Sisterna

 FSM Style Descriptions - Example
39

Moore FSM X=0

S0 S1
X=0 Z=0 Z=1 X=1

X=1

Mealy FSM
X=0
Z=1

X=0 S0 S1 X=1
Z=0 Z=1

X=1
Z=0
FSM - DSDA Cristian Sisterna
 Style A - Moore State Machine
40
Next State Logic

process (state, X)
begin
case state is Present State Logic Output Logic
when S0 =>
if(X=‘0’) then
next_state <= S0; process (clk, rst)
else(X=‘1’) then begin process (state)
next_state <= S1; if(rst = ‘1’) then begin
X end if; state <= S0; case state is
when S1 => elsif (rising_edge(clk)) then when S0 => Z <=‘0’;
Z
if …. state <= next_state; when S1 => Z <=‘1’;
next_state <=..; end if; when others => Z <=‘0’;
else .. end process; end case;
….
end process;
when others =>
….
end case;
end process;

Clock

Reset

FSM - DSDA Cristian Sisterna

 Style E - Moore State Machine
41

Comb. Next State Logic

Seq. Output Logic
process (state, X)
process (clk, rst)
begin Seq. Present State Logic
begin
case state is
if(rst = ‘1’) then
when S0 => process (clk, rst) Z <= ‘0’;
if(X=‘0’) then
begin elsif (rising_edge(clk))
next_state <= S0;
if(rst = ‘1’) then then Z
else(X=‘1’) then state
X next_state <= S1;
state <= S0; case state is
elsif (rising_edge(clk)) when S0 =>
end if;
then Z <= ‘0’;
when S1 =>
state <= next_state; when S1 =>
if ….
end if; Z <= ‘1’;
next_state <= .. ;
end process; when others =>
….
Z <= ‘1’;
when others =>
end case;
….
end process;
end case;
end process;

Clk

Rst

FSM - DSDA Cristian Sisterna

 Style E - Moore State Machine
42
-- next state logic
-- VHDL code example for an FSM nxt_pr:process (state, X)
library ieee; begin
use ieee.std_logic_1164.all; case state is
when S0 =>
entity my_fsm is if(X=‘0’) then
port( next_state <= S0;
x: in std_logic; else(X=‘1’) then
clk: in std_logic; next_state <= S1;
rst: in std_logic; end if;
z: out std_logic ); when S1 =>
end entity my fsm; if ….
next_state <= .. ;
architecture beh of my_fsm is ….
-- fsm enumerated type declaration when others =>
type fsm_states is (S0, S1); ….
end case;
-- fsm signal declarations end process nxt_pr;
signal next_state, state: fsm_states; - - output logic
begin out_pr:process (clk, rst)
begin
-- current state logic if(rst = ‘1’) then
cst_pr: process (clk, rst) Z <= ‘0’;
begin elsif (rising_edge(clk)) then
if(rst = ‘1’) then case state is
state <= S0; when S0 => Z <= ‘0’;
elsif (rising_edge(clk)) then when S1 => Z <= ‘1’;
state <= next_state; when others => Z<= ‘1’;
end if; end case;
end process cst_pr; end process out_pr;
end architecture beh;

FSM - DSDA Cristian Sisterna

 Style E - Mealy State Machine
43
Comb.Next State Logic
process (state, X) Seq. Output Logic
begin
case state is
when S0 => process (clk, rst)
if(X=‘0’) then begin
Seq.Present State Logic if(rst = ‘1’) then
next_state <= S0;
else(X=‘1’) then Z <= ‘0’;
X next_state <= S1; process (clk, rst) elsif (rising_edge(clk)) then
end if; begin case state is
when S1 => if(rst = ‘1’) then when S0 =>
if …. state <= S0; state if (X = ‘0’) then
next_state <= .. ; elsif (rising_edge(clk)) Z <=…;
…. then else
when others => state <= next_state; Z <=... ; Z
…. end if; end if;
end case; end process; when S1 =>
end process; if (X = ‘1’) then
.... ;
else
.... ;
end if;
when others =>
Z<=‘0’;
Clk end case;
Rst end if;
end process;
Warning on Mealy Outputs !

FSM - DSDA Cristian Sisterna

 Style A - Moore State Machine
44

Comb. Next State Logic

process (state, X)
begin
case state is
Seq. Present State Logic Comb.Output Logic
when S0 =>
if(X=‘0’) then
next_state <= S0; process (clk, rst) process (state)
else(X=‘1’) then begin begin
X next_state <= S1; if(rst = ‘1’) then Z <= ‘0’; -- default value Z
end if; state case state is
state <= S0;
when S1 => elsif (rising_edge(clk)) when S0 => Z <= ‘0’;
if …. then when S1 => Z <= ‘1’;
next_state <= .. ; state <= next_state; when others => Z <= ‘0’;
…. end if; end case;
when others => end process; end process;
….
end case;
end process;

Clock

Reset

FSM - DSDA Cristian Sisterna

 Style A – Moore Synthesis
45

FSM - DSDA Cristian Sisterna

 Style A - Mealy State Machine
46

Comb. Next State Logic

process (state, X)
begin Comb. Output Logic
case state is
when S0 => process (state, X)
if(X=‘0’) then begin
Seq. Present State Logic
next_state <= S0; case state is
else(X=‘1’) then when S0 =>
X next_state <= S1; process (clk, rst) if (X = ‘0’) then
end if; begin Z <=…;
when S1 => if(rst = ‘1’) then else
if …. state <= S0; Z <=... ; Z
next_state <= .. ; elsif (rising_edge(clk)) then end if;
…. state <= next_state; when S1 =>
when others => end if; if (X = ‘1’) then
…. end process; .... ;
end case; else
end process; .... ;
end if;
when others =>
Z<=‘0’;
end case;
end process;
Clock
Reset

FSM - DSDA Cristian Sisterna

 Style A – Mealy Synthesis
47

Mealy

FSM - DSDA Cristian Sisterna

 Style A – Moore & Mealy State Machine
48

Comb. Next State Logic Comb.Output Logic Moore

process (state)
process (state, X)
begin
begin case state is Y
case state is when S0 => Y <= ‘1’;
when S0 => when S1 => Y <= ‘0’;
if(X=‘0’) then Seq. Present State Logic when others => Y <= ‘0’;
next_state <= S0; end case;
else(X=‘1’) then end process;
X next_state <= S1; process (clk, rst)
end if; begin Comb. Output Logic - Mealy
when S1 => if(rst = ‘1’) then
if …. process (state, X)
state <= S0;
next_state <= .. ; begin
elsif (rising_edge(clk)) then
…. case state is
state <= next_state;
when others => when S0 =>
end if;
…. if (X = ‘0’) then
end process;
end case; Z <=…;
end process; ... Z
end if;
when S1 =>
if (X = ‘1’) then
.... ;
end if;
Clock when others =>
Z<=‘0’;
Reset
end case;
end process;
Hypothetical case
FSM - DSDA Cristian Sisterna
 Style B - Moore State Machine
49 Seq. State, Next State and Output Logic

process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
X state <= S0; Z
elsif (X=’1’) then
state <= S1;
end if;
Z <=‘0’;
when S1 =>
if (X = ‘0’) then
...
end if;
Z <= ‘1’ ;
end case;
end if;
end process;

Clk
Rst

FSM - DSDA Cristian Sisterna

 Style B - Mealy State Machine
50
Seq. State, Next State and Output Logic

process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
state <= .... ;
Z <= ... ;
Z
X
elsif (X=’1’) then
state <= .... ;
Z <= ... ;
end if;
when S1 =>
if (X = ‘0’) then
...
end if;
end case;
end if;
end process;

Reset
Clock

FSM - DSDA Cristian Sisterna

 Style B – Moore Synthesis
51

FSM - DSDA Cristian Sisterna

 Style B – Mealy Synthesis
52

FSM - DSDA Cristian Sisterna

 Style C - Moore State Machine
53

Seq. Present State and Next State Logic

process (clk, rst)

begin Comb. Output Logic
if(rst = ‘1’) then
State <= S0;
process (state)
elsif (rising_edge(clk)) then
begin
case state is
case state is
when S0 => Z
X when S0 => Z <=‘0’;
if(X =’1’) then
when S1 => Z <=‘1’;
state <=S1;
when others Z <=‘0’
end if;
end case;
when S1 =>
end process;
if( X = ‘1’) then
state <=S0;
end if;
end case;
end if;
end process;

Clk

Rst

FSM - DSDA Cristian Sisterna

 Style C - Mealy State Machine
54

Seq. Present State and Next State Logic

Comb. Output Logic

process (clk, rst) process (state, X)

begin begin
if(rst = ‘1’) then case state is
State <= S0; when S0 =>
elsif (rising_edge(clk)) then if(X=’1’) then
case state is Z <= ... ;
when S0 => else
X if(X =’1’) then Z <= ... ; Z
state <=S1; end if;
end if; when S1 =>
when S1 => if(X=’1’) then
if( X = ‘1’) then Z <= ... ;
state <=S0; else
end if; Z <= ... ;
end case; end if;
end if; end case;
end process; end process;

Clk
Rst

FSM - DSDA Cristian Sisterna

 Style C – Moore State Machine
55

FSM - DSDA Cristian Sisterna

 Style C - Mealy State Machine
56

FSM - DSDA Cristian Sisterna

 Style D - Moore State Machine
57

Comb. Next State and Output Logic

process (state, X)
begin Z
next_state <= state;
case state is
when S0 => Seq. Present State Logic
if(X =’1’) then
X next_state <=S1;
end if; process (clk, rst)
Z <=‘0’; begin
when S1 => if(rst = ‘1’) then
if( X = ‘1’) then state <= S0;
next_state <=S0; elsif (rising_edge(clk)) then
end if; state <= next_state;
Z <=‘1’; end if;
end case; end process;
end process;

Clk
Rst

FSM - DSDA Cristian Sisterna

 Style D - Mealy State Machine
58

Comb. Next State and Output Logic

Z
process (state, X)
begin
next_state <= state;
Z <= ... ; Seq. Present State Logic
case state is
when S0 => process (clk, rst)
X if(X =’1’) then begin
next_state <= ... ; if(rst = ‘1’) then
Z <= ... ; state <= S0;
end if; elsif (rising_edge(clk)) then
when S1 => state <= next_state;
if( X = ‘1’) then end if;
next_state <= ... ; end process;
Z <= ... ;
end if;
end case;
end process;

Clk
Rst

FSM - DSDA Cristian Sisterna

 Style D – Moore State Machine
59

FSM - DSDA Cristian Sisterna

 Style D - Mealy State Machine
60

FSM - DSDA Cristian Sisterna

FSM Example

FSM - DSDA Cristian Sisterna

 Another Example: Memory Controller FSM
62

Let’s try to obtain an state diagram of a hypothetical memory controller FSM that has the
following specifications:
The controller is between a processor and a memory chip, interpreting commands from the
processor and then generating a control sequence accordingly. The commands, mem, rw and
burst, from the processor constitute the input signals of the FSM. The mem signal is asserted to
high when a memory access is required. The rdwr signal indicates the type of memory access,
and its value can be either ’1’ or ’0’, for memory read and memory write respectively. The
burst signal is for a special mode of a memory read operation. If it is asserted, four
consecutive read operations will be performed. The memory chip has two control signals, oe
(for output enable) and we (for write enable), which need to be asserted during the memory
read and memory write respectively. The two output signals of the FSM, oe and we, are
connected to the memory chip’s control signals. For comparison purpose, let also add an
artificial Mealy output signal, we_mealy , to the state diagram. Initially, the FSM is in the idle
state, waiting for the mem command from the processor. Once mem is asserted, the FSM
examines the value of rdwr and moves to either the read1 or the write state. The input
conditions can be formalized to logic expressions, as shown below:
 mem’ : represents that no memory operation is required (mem=‘0’)
 mem.rdwr: represents that a memory read operation is required (mem=rdwr=‘1’).
 mem.rdwr’: represents that a memory write operation is required (mem=‘1’; rdwr=‘0’)
Based on an example from the “RTL Hardware Design Using VHDL” book, By Pong Chu

FSM - DSDA Cristian Sisterna

 Memory Controller FSM
63

Address Bus

Data Bus

Processor mem Memory IC

burst
oe
rdwr
FPGA Memory we
Controller FSM
we_mealy

FSM - DSDA Cristian Sisterna

 Memory Controller FSM
64
mem’

idle
burst’

mem.rdwr’
mem.rdwr we_mealy
read1
oe

write
burst
we
read2
oe

read3
oe

read4
oe

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 Memory Controller FSM
65

idle

mem

rdwr
read1

oe we_mealy

burst write

read2
we
oe
read3

oe
read4

oe

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 Memory Controller FSM – VHDL Code
66

 Entity-Architecture Declarations
 FSM enumeration type declaration, FSM signal declarations
library ieee ;
use ieee.std_logic_1164.all;
entity mem_ctrl is
port (
clk, reset : in std_logic;
mem, rdwr, burst: in std_logic;
oe, we, we_mealy: out std_logic
);
end mem_ctrl ;
architecture mult_seg_arch of mem_ctrl is
type fsm_states_type is
(idle, read1, read2, read3, read4, write);
signal crrnt_state, next_state: fsm_states_type;
begin

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 Memory Controller FSM – VHDL Code
67

 Current state process

−− current state procesee

cs_pr: process (clk, reset)
begin
if(reset = ’1’) then
crrnt_state <= idle ;
elsif(rising_edge(clk))then
crrnt_state <= next_state;
end if;
end process cs_pr;

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 Memory Controller FSM – VHDL Code
68

 Next state process (1)

−− next−state logic
nxp:process(crrnt_state,mem,rdwr,burst)
begin
case crrnt_state is
when idle =>
if mem = ’1 ’ then
if rw = ’1’ then
next_state <= read1;
else
next_state <= write;
end if;
else
next_state <= idle;
end if;
when write =>
next_state <= idle;

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 Memory Controller FSM – VHDL Code
69

 Next state process (2)

when read1 =>
if (burst = ’1’) then
next_state <= read2;
else
next_state <= idle;
end if;
when read2 =>
next_state <= read3;
when read3 =>
next_state <= read4;
when read4 =>
next_state <= idle;
when others =>
next_state <= idle;
end case;
end process nxp;

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 Memory Controller FSM – VHDL Code
70
−− Moore output logic
 Moore outputs process moore_pr: process (crrnt_state)
begin
we <= ’0’; −− default value
oe <= ’0’; −− default value
case crrt_state is
when idle => null;
when write =>
we <= ’1’;
when read1 =>
oe <= ’1’;
when read2 =>
oe <= ’1’;
when read3 =>
oe <= ’1’;
when read4 =>
oe <= ’1’;
when others => null;
end case ;
end process moore_pr;
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 Memory Controller FSM – VHDL Code
71

 Mealy output process

−− Mealy output logic
mly_pr: process(crrt_state,mem,rdwr)
begin
we_me <= ’0’; −− default value
case state_reg is
when idle =>
if (mem=’1’)and(rdwr =’0’)then
we_me <= ’1’;
end if;
when write => null;
when read1 => null;
when read2 => null;
when read3 => null;
when read4 => null;
end case;
end process mly_pr;

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 Memory Controller FSM – VHDL Code
72

 Mealy output statement

−− Mealy output logic

we_me <= ’1’ when ((crrnt_state=idle) and (mem=’1’) and(rdwr=’0’))
else
’0’;

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Another Example

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 FSM Example – RS232
74

Realizar la descripción en VHDL de un receptor y transmisor serie

tipo RS-232. El dato recibido y el dato a transmitir debe tener el
siguiente formato:

1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.

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 FSM Example – RS232
75

RS-232 Tx format

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 FSM Example – RS232
76

SysClock Div. Parity

En
Frec.

SysReset

Dato(7:0)

DatoSent
FSM DatoSerie
RS232 Tx Controller
StartTx
??

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 FSM Example – RTL Synthesis View
77

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 FSM Example – Quartus State diagram
78

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 FSM Example: Solution 2 - RTL Viewer
79

RTL Viewer
Double click

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 FSM Example: Solution 2- RTL Viewer
80
Double click

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 FSM Example: Solution 2 – FSM Viewer
81

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 Synpsys FSM Viewer
82

In this case a clock enable is used.

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 FSM Example – RS232 Other Approach
83

SysClock Div.
Parity 00
Frec. En

SysReset DatoSerie
01
Dato(7:0)

E1 Reg
E0 Desplaz 10
amiento
DatoSent

Done
StartTx FSM
?? RS232 Tx Controller
StartStopBit

Sel1, Sel0

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Interacting State Machines
 Interacting FSM
85

Controller FSM Transmitter FSM

Ld_Tx’

CS1
TS1

Tx_busy’
TS4
CS2 Tx_busy
Ld_Tx
TS2
Tx_busy

CS3

Tx_busy’ TS3
Tx_busy
Tx_busy
Ld_Tx’

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 Interacting FSM
86
Controller
Inputs FSM
Processes
Next Current Output
State Next
State Process
Process Process Outputs
State
Current
State

Tx_busy
Clk
Rst Ld_Tx ctrl_tx.vhd

Inputs
Current Outputs
Next Current State Output
State Next
State Process
Process State Process

Transmitter
FSM
Processes
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 Interacting FSM
87

cntrl_fsm.vhd
Inputs

Next Current Outputs

Output
State Next State Process
Process State Process
Current
State Ld_Tx

Clk
Rst

Tx_busy

Inputs
Current Outputs
Next Current State Output
State Next
State Process
Process State Process

tx_fsm.vhd
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88

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ADVANCED VHDL DESIGN
TECHNIQUES

Coding State Machines

State Machine Coding
 Enumerated data type is used to define the different states in the state
machine
 Using constants for states may not be recognized as state machine
TYPE state_type IS (idle, fill, heat_w, wash, drain);

 One or two signals assigned to the name of the state-variable :

SIGNAL current_state, next_state : state_type;

 Use CASE statement to do the next-state logic, instead of IF-THEN statement

 Synthesis tools recognize CASE statements for implementing state machines
 Use CASE or IF-THEN-ELSE for output logic

90
 Quartus II Software State Machine Viewer

 Use to verify correct coding of state machine

State Flow Diagram Tools Menu 

State Machine Viewer
Use Drop-Down to
Select State Machine

Highlighting State in State

Transition Table Highlights
Corresponding State in State
Flow Diagram

State Transition/Encoding Table

91
 State Declaration
ENTITY wm IS
PORT (
clk, reset, door_closed, full : in std_logic;
heat_demand, done, empty : in std_logic;
water, spin, heat, pump : out std_logic);
END ENTITY wm;

ARCHITECTURE behave OF wm IS
TYPE state_type IS
(idle, fill, heat_w, wash, drain); Empty = 1
IDLE
Door_closed = 1
Water = 0
SIGNAL current_state, next_state : Spin = 0
Heat = 0
state_type; Pump = 0

BEGIN DRAIN FILL

Water = 0 Water = 1
Spin = 1 Spin = 0
Heat = 0 Heat = 0
Pump = 1 Pump = 0

Full = 1
Heat_demand = 1

WASH HEAT_W
Done = 1
Water = 0 Water = 0
Spin = 1 Spin = 1
Heat = 0 Heat = 1
Pump = 0 Pump = 0

Heat_demand = 0

92
 Next State Logic
PROCESS (clk, reset) Empty = 1
IDLE
Door_closed = 1
Water = 0
BEGIN Spin = 0
Heat = 0
IF reset = '1' THEN Pump = 0

current_state <= idle; DRAIN FILL

ELSIF rising_edge(clk) THEN Water = 0

Spin = 1
Water = 1
Spin = 0

current_state <= next_state; Heat = 0

Pump = 1
Heat = 0
Pump = 0

END IF; Heat_demand = 1

Full = 1

END PROCESS;
WASH HEAT_W
Done = 1
Water = 0 Water = 0
PROCESS (current_state, door_closed, Spin = 1
Heat = 0
Spin = 1
Heat = 1
full, heat_demand, done, empty) Pump = 0 Pump = 0

BEGIN
next_state <= current_state; Heat_demand = 0

CASE current_state IS Sequential state

WHEN idle => transitions
IF door_closed = '1' THEN
next_state <= fill;
END IF; Default next state is
WHEN fill => current state
IF full = '1' THEN
next_state <= heat_w; Combinatorial next
END IF; state logic

93
Moore Combinatorial Outputs
Default output conditions
PROCESS (current_state)
BEGIN
water <= '0';
IDLE
spin <= '0'; Empty = 1
Water = 0
Door_closed = 1
heat <= '0'; Spin = 0
Heat = 0
pump <= '0'; Pump = 0
DRAIN FILL
CASE current_state IS
Water = 0 Water = 1
WHEN idle => Spin = 1 Spin = 0
Heat = 0 Heat = 0
WHEN fill => Pump = 1 Pump = 0

water <= '1'; Heat_demand = 1

Full = 1

WHEN heat_w =>

spin <= '1'; Done = 1
WASH HEAT_W

Water = 0 Water = 0
heat <= '1'; Spin = 1 Spin = 1
Heat = 0 Heat = 1
WHEN wash => Pump = 0 Pump = 0

spin <= '1';

WHEN drain => Heat_demand = 0

spin <= '1';

pump <= '1';
END CASE; – Output logic is a function of
END PROCESS; the current state only

94
 Mealy Combinatorial Outputs
PROCESS (current_state, heat_demand)
BEGIN
water <= '0'; IDLE
spin <= '0'; Empty = 1
Water = 0
Door_closed = 1

heat <= '0'; Spin = 0

Heat = 0
pump <= '0'; Pump = 0

CASE current_state IS DRAIN FILL

WHEN idle => Water = 0 Water = 1

WHEN fill => Spin = 1

Heat = 0
Spin = 0
Heat = 0

water <= '1'; Pump = 1 Pump = 0

WHEN wash => WASH

Water = 0
spin <= '1'; Spin = 1
Heat =
heat <= heat_demand; Heat_demand
Full = 1

Pump = 0
WHEN drain => Done = 1

spin <= '1';

pump <= '1';
WHEN OTHERS =>
END CASE;
END PROCESS; – Output logic is a function of the
current state and the input(s)

95
 State Machine Encoding Styles
Grey-
Binary One-Hot Custom
State Code
Encoding Encoding Encoding
Encoding
Idle 000 000 00001 ?

Fill 001 001 00010 ?

Heat_w 010 011 00100 ?
Wash 011 010 01000 ?

Drain 100 110 10000 ?

 Quartus II default encoding styles for Altera devices

 One-hot encoding for look-up table (LUT) devices
 Architecture features lesser fan-in per cell and an abundance of registers
 Binary (minimal bit) or grey-code encoding for product-term devices
 Architecture features fewer registers and greater fan-in

96
Quartus II Encoding Style

Options:
Apply Assignment to • Auto
State Variable • Gray
• Johnson
• Minimal Bits
• One-Hot
• Sequential
• User-Encoded
97
Undefined States

 Noise and spurious events in hardware can cause state

machines to enter undefined states
 If state machines do not consider undefined states, it can cause
mysterious "lock-ups" in hardware
 Good engineering practice is to consider these states
 To account for undefined states
 Explicitly code for them (manual)
 Use "safe" synthesis constraint (automatic)

98
 'Safe' Binary State Machine?
TYPE state_type IS IDLE
Empty = 1 Door_closed =
(idle, fill, heat_w, wash, drain); Water = 0
1
Spin = 0
SIGNAL current_state, next_state : state_type; Heat = 0
BEGIN Pump = 0
DRAIN FILL
PROCESS (current_state, door_closed, full,
Water = 0 Water = 1
heat_demand, done, empty) Spin = 1 Spin = 0
BEGIN Heat = 0 Heat = 0
Pump = 1 Pump = 0
next_state <= current_state;
Full = 1
CASE current_state is Heat_demand = 1

WHEN idle =>

WASH HEAT_W
IF door_closed = '1' THEN next_state <= fill; Done = 1
Water = 0 Water = 0
END IF; Spin = 1 Spin = 1
WHEN fill => Heat = 0 Heat = 1
Pump = 0 Pump = 0
IF full = '1' THEN next_state <= heat_w;
END IF;
Heat_demand = 0
WHEN heat_w =>
IF heat_demand = '0' THEN next_state <= wash;
END IF;
WHEN wash => – This code does not consider
IF heat_demand = '1' THEN next_state <= heat_w;
ELSIF done = '1' THEN next_state <= drain;
undefined states
END IF; – The "when others" statement
WHEN drain =>
IF empty = '1' THEN next_state <= idle;
only considers other
END IF; enumerated states
WHEN others => – The states "101", "110" &
next_state <= idle;
END CASE; "111" are not considered
END PROCESS;

99
Creating "Safe" State Machines

 WHEN OTHERS clause does not make state machines "safe"

 Once state machine is recognized, synthesis tool only accounts for explicitly defined states
 Exception: Number of states equals power of 2 AND binary/grey encoding enabled

 Safe state machines created using synthesis constraints

 Quartus II software uses
 SAFE STATE MACHINE assignment applied project-wide and to individual FSMs
 VHDL synthesis attribute
 May increase logic usage

100
 Registering Outputs

 Removes glitches which can reduce power

 Improves timing by reducing layers of logic
 Adds a stage of latency
Current State

Next State

Outputs
Next
Inputs State Output Output
State
Registers Logic Registers
Logic

101
 Registered Outputs w/o Latency
 Base outputs on next state vs. current state
 Output logic uses next state to determine what the next
outputs will be
 On next rising edge, outputs change along with state registers
Current State

Next State

Next
State
Inputs State
Registers
Logic

Next
State Output Outputs
Output Registers
Logic

102
 Registered Outputs w/o Latency
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN IDLE
Empty = 1
water <= '0'; Water = 0
Door_closed = 1
Spin = 0
spin <= '0'; Heat = 0
Pump = 0
heat <= '0'; DRAIN FILL

pump <= '0'; Water = 0 Water = 1

CASE next_state IS Spin = 1

Heat = 0
Spin = 0
Heat = 0

WHEN idle => Pump = 1 Pump = 0

WHEN fill => Heat_demand = 1

Full = 1

water <= '1'; WASH HEAT_W

WHEN heat_w => Done = 1
Water = 0 Water = 0
spin <= '1'; Spin = 1
Heat = 0
Spin = 1
Heat =
heat <= heat_demand; Pump = 0 Heat_demand
Pump = 0
WHEN wash =>
spin <= '1'; Heat_demand = 0

WHEN drain =>

spin <= '1'; – Base output logic case statement
pump <= '1'; on next state variable (instead of
WHEN others => current state variable)
END CASE;
– Wrap output logic with a clocked
END IF;
END PROCESS; process

103
 Using Custom Encoding Styles

 Remove glitches without

output registers Outputs
Custom

Pump
Water
State
Eliminate combinatorial

Spin
Heat
 Encoding

output logic Idle 0 0 0 0 0000

 Outputs mimic state bits Fill 1 0 0 0 1000
 Use additional state bits for
states that do have exclusive Heat_w 0 1 1 0 0110
outputs Wash 0 1 0 0 0100
 Reduces Registers (i.e. Drain 0 1 0 1 0101
Register sharing)

104
 Quartus II Custom State Encoding

IDLE
ENTITY wm IS Empty = 1 Door_closed =
PORT ( Water = 0
Spin = 0
1

clk, reset, door_closed, full : in std_logic; Heat = 0

Pump = 0
heat_demand, done, empty : in std_logic; DRAIN FILL
water, spin, heat, pump : out std_logic); Water = 0 Water = 1
END wm; Spin = 1
Heat = 0
Spin = 0
Heat = 0
Pump = 1 Pump = 0

ARCHITECTURE behave OF wm IS Heat_demand = 1

Full = 1

TYPE state_type IS (idle, fill, heat_w, wash, drain);

ATTRIBUTE syn_encoding : STRING; Done = 1
WASH HEAT_W

ATTRIBUTE syn_encoding OF state_type : TYPE IS Water = 0 Water = 0

Spin = 1 Spin = 1
"0000 1000 0110 0100 0101"; Heat = 0 Heat = 1
SIGNAL current_state, next_state : state_type; Pump = 0 Pump = 0

BEGIN
Heat_demand = 0

– Output assignments are coded per previous examples

– Synthesis automatically handles reduction of output logic
– Some tools use VHDL attributes like enum_encoding OR
syn_enum_encoding to perform custom state encoding

105
Writing Efficient State Machines

 Remove counting, timing, arithmetic functions from

state machine & implement externally
 Reduces overall logic & improves performance

106
 Precision State Encoding Techniques
107

Possible values: Declare the attribute as follows:

• Binary attribute type_encoding_stype string;

• Onehot
• Twohot
• Gray
• Random
-- Declare the (state-machine) enumerated type
type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding_style of the state type
attribute type_encoding_style of my_state_type:type is ONEHOT;

Note: precision is a synthesis tool available in some FPGA vendor’s software

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 Precision State Encoding Techniques
108

type_encoding_style allows to fully control the state

encoding hard code the state code in the source code

-- Declare the (state-machine) enumerated type

type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding attribute
attribute type_encoding_style of my_state_type:type is
("0001","01--","0000","11--","0010");

State
Table

Note: Precision allows to use ‘-’. It can be used to reduce the size of the circuit

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109

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