NCC 2009, January 16-18, IIT Guwahati 15

Design and Implementation of Early-Late Gate Bit

Synchronizer for Satellite Communication
P.N.Ravichandran1, Satish Sharma2, Sunil Kulkarni3 and P.Lakshminarsimhan4
Digital Systems Group, ISRO Satellite Centre, Bangalore-5600171
Digital Systems Group, ISRO Satellite Centre, Bangalore-5600172
Digital Systems Group, ISRO Satellite Centre, Bangalore-5600173
Digital Systems Group, ISRO Satellite Centre, Bangalore-5600174

Email: [email protected], [email protected], [email protected], [email protected]

Abstract—The paper presents hardware design of digital signal From From

processing (DSP) based Early-Late gate Bit Synchronizer. The RX GCO
system is developed for onboard 4KBPS Telecommand system. It is
designed and integrated with BPSK demodulator to recover the Data
clock. Apart from the implementation, paper describes the
mathematical modeling of bit synchronizer. The whole design is Op-Amp BPSK Inv
accommodated in a XILINX xc2v3000-4fg676 FPGA. the design is Buffer Demodulator Data
tested in real dime for 4KBPS data rate and simulation results are
presented here. Paper also highlights the programmable nature of Clk
the design and methods to reduce the hardware requirement. Ant-aliasing Inv
Filter Clk
Index Terms— Field programmable gate arrays, Signal Bit
Synchronizer Demod
processing, Bit Synchronizer, Satellite communication. Lock
8 bit A/D Bit Sync
I. INTRODUCTION
Xilinx FPGA Lock
Power–efficient digital receivers generally require the existence
of a digital clock synchronized to the received bit stream to Analog Portion Digital Portion
control the integrated–and–dump detection filters or to control
otherwise the timing of the output bit stream and therefore Fig 1. Implementation of Complete System.
synchronization concept plays a major role in the fields of
communications engineering, digital data transmission, radar
sonar and navigation. The Bit Synchronizer is fundamentally a First, the complete system is described, followed by separate
Phase Locked Loop(PLL). The synchronizer is designed to descriptions of bit synchronizer. Next section deals with the y
provide phase lock between an internally generated data clock Xilinx implementation with emphasis on hardware reduction.
and an input data steam. Moreover, it can perform the traditional Finally test setup and results are discussed.
task of providing phase lock between two clocks. Bit
synchronizers are also required when a nearly synchronous bit II. COMPLETE SYSTEM
stream is received over a cable transmission system and must be The complete system consists of the input OP-AMP buffer,
detected and perhaps multiplexed with other parallel bit streams. which can receive the BPSK, modulated input from either
The bit synchronizer can be classified in to two categories open receiver or ground checkout system (GCO)[2]. An antialiasing
and closed loop [1]. The former one is used for high SNR filter follows this, which is a low pass analog filter. The output
application. In closed loop there are mainly two bit synchronizer of antialiasing filter is digitized using a 8-bit A to D converter.
In-phase / Mid-phase bit synchronizer and Early-Late Gate bit The digitized signal from A to D converter is fed to Xilinx
synchronizer. Because of its simplicity in implementation and FPGA, where the input signal is demodulated using Costas loop
less sensitivity towards DC offset early-late gate is first choice demodulator and clock is recovered using Early-Late Gate bit
for on-board Telecommand system. synchronizer. In addition the corresponding bit-sync lock &
 NCC 2009, January 16-18, IIT Guwahati 16

carrier lock signals are also generated. Figure 1 gives the top-
level implementation block diagram for complete system.
The complete digital design is written in VHDL code. As in case
of any DSP based design the basic unit involved is multiplier and
adder. To overcome the problem of overflow and also to limit
the word-length in multiplier, overflow detection & saturation
algorithm is implemented [3] .

III. EARLY-LATE GATE BIT SYNCHRONIZER

The block diagram of the analog domine early-late gate bit
synchronizer is shown in Figure 2 The circuit contains a pair of
gated integrators called early and late gates, each performing its
integration over a time interval of T/2. The input bit stream is Fig 3. Typical waveforms of early-late gate clock recovery
circuit.
∑ an P(t-nT)
In this case, the data transition falls not on the boundary of
where T is the symbol duration and p(t) denotes a rectangular
operation of the early and late gates, but occurs within the
pulse width duration T. Integration by the early and late gates are
operation interval of one of gates. Since the input signal changes
performed over the time intervals T/2, just before and after,
its polarity during the gate operation, the associated integration
respectively, the estimated location of data transition. Gate
reaches a smaller magnitude than for the other gate, where a
intervals adjoin each other, but do not overlap.
Received transition does not occur. Comparing the magnitudes of the two
Early gate clock integrators gives the error voltage vd(t) which is used after low-
pass filtering to control the VCO frequency.
Early
integrator
. The bit synchronizer can be modeled as a PLL with feedback
system as shown in figure 4. Given the requirement of bit
I/P Bit CH + synchronizer in terms of natural frequency ωn and damping
stream factor ξ, system can be modeled in terms of Kpd , Kvco, K1 and
Timing VCO F(S) K2 which are defined below. The close loop transfer function
- [2] is given by.
-
Phase Loop
Detector Gain VCO
Late
integrator
. fi
Filter
F(s)
(k) fo
•
CH H(s) =1
Late gate
Fig 4. Phase locked loop.
Figure 2 Early-Late gate Bit Synchronizer
()
F s
The operation of clock recovery is explained in figure 3. If the K pd .K vco
S
timing error is zero, then the data transition falls just on the CLTF(s) = (1)
boundary between the operation of the early and late gates. In 1 + K pd Kvco
()
F s
this case, the estimated and incoming data transitions coincide S
with each other, and the output of the two integrators, stored in
the hold capacitors CH, are equal. As a result, the error voltage Where K pd = Phase detector gain in Volts /radian
vd(t) becomes zero. Because the error voltage is produced from
Kvco = Sensitivity of VCO in rad/sec/volts
the absolute values of the integrator outputs, it is also zero if the
data transition is missing. If a transition of input data does not F(s) = Loop filter transfer function
coincide with the estimated time instant of a transition, then a
Depending on the choice of F(s) the CLTF(s) can be of either
timing error denoted by in Figure 3 appears. first or second order system. For example, for type 2 systems [4],
loop filter structure is shown in figure 5. The equation (1) can be
rewritten as
 NCC 2009, January 16-18, IIT Guwahati 17

()
F s software, the design is coded in VHDL and ported in to Xilinx
K FPGA. The Early-Late gate bit synchronizer FPGA
S ()KF s
= = (2) implementation is shown in figure 6.
1+ K
F s ( ) S + KF (s ) Sin _clock
S
14
Where F(s) = K1 + K2/s
K1 14 14
Early Phase Early gate
Accumulator Register

To VCO
Phase detector
32 +
output Input 32 Loop
Data Timing DCO
Filter
Circuit
Accumulator 1/fs -

K2
14 14
Figure 5. Loop filter structure. Late Phase Late gate
Register
Accumulator
The equation (2) becomes
Cos _clock
CLTF(s) = K * K1s +K * K 2 (3)
2
s + K * K1s + K * K 2 Fig 6. FPGA implementation of Bit synchronizer
The same design can be used for different specification by
changing the design parameter. The system is tested for different
Which is of type 2, 2nd order system. Using servo theory, (3) is data rates. The maximum frequency that system can support
of the form depends on the loop delay and filter operating frequency. The
complete system with demodulator takes 14% while standalone
2ξω n s +ω n2 bit synchronizer takes 2% of xc2v3000-4fg676 FPGA.
= 2 (4)
s + 2ξω n s +ω n2 A noticeable hardware reduction can be achieved by
implementing loop filter multipliers using shifting technique and
where K = K pd Kvco , The value of K pd and Kvco depends on phase detector by Multiplexer. The hardware can be further
reduced by choosing the number of bits of accumulator
f and the magnitude of the accumulator. The value of K1 and
s appropriately, as we can calculate the magnitude of accumulator
K2 can be calculated by output depending on sampling rate & data rate. Instead of using
NCO, only digital controlled oscillator (DCO) [4] can be used, to
ω n = K pd K VCO K 2 (5) avoid the large look up table, but this result in little performance
degradation.
K pd K VCO K1
ξ= (6) V. TEST SETUP & RESULTS
2ω n
The Standalone test is carried out on the system by giving NRZ
data at 4 KBPS to the bit synchronizer FPGA from a PN
The equations (1) to (6) are sufficient to model the bit sequence data generator as shown in figure 7, the output of
synchronizer, and by changing the value of K1 and K2 we can FPGA is monitored on oscilloscope. This testing was carried out
control the performance and characteristics of demodulator loop. for different data rates between 125 BPS to 500 KBPS.
The stability of the system can be verified by transforming S-
domain closed loop transfer function to Z-domain. Bit Synchronizer
Data
generator XILINIX FPGA Oscilloscope
IV. FPGA IMPLEMENTATION & HARDWARE REDUCTION
Before FPGA implementation a system level simulation has xc2v3000-4fg676

been carried out on System Vue software tool for fine tuning of
Fig 7. Standalone hardware test setup
the design parameters. After checking the performance on
 NCC 2009, January 16-18, IIT Guwahati 18

The bit synchronizer is integrate with BPSK demodulator and

tested at system level. The input to the bit synchronizer is BPSK
demodulated data as shown in the figure 8.

BPSK Bit
Oscilloscope
Demodulator Synchronize
r
XILINX FPGA xc2v3000-4fg676

Fig 8. Integrated hardware test setup

Figure 9 to 11 shows the system Vue and modelSim output wave
forms of loop filter for 4 KBPS
Fig 11. ModelSim output for 4KBPS data rate

VI. CONCULISION
Clock recovery is important part of a communication system.
The paper presented the design & implementation of Early-Late
Gate Bit synchronizer circuit from equations to FPGA realization
for NRZ data. The developed system can be used for any data
rate, depending on the sampling speed supported by the device.
The paper highlighted the programmable nature of design and
methods for reducing the hardware. The new design circuit is
easily accommodated in RH FPGA. The design is tested for its
performance by interfacing with the demodulator and also
standalone by giving input from PN sequence data generator, and
it found to be working satisfactorily.
Fig 9. ModelSim loop filter output for 4KBPS data rate,
frequency offset=0Hz, Tacq=220 ms REFERENCES
[1] J.J Spilker,Digital Communication by Satellite, Belmont CA, Prientice
Hall Inc, 1977.
[2] Sunil Kulkarni and Satish Sharma “A multiple bit rate BPSK
demodulator with inphase / midphase bit synchronizer –A detail
design Report “ Digital systems group , ISRO, Doc.No.ISRO-
ISAC-TR-0720, Apr. 2005.
[3] A. Landauro and J. Lienard , “On Over Flow Detection And
Correction in Digital Filter”, IEEE transactions on Computers, Vol.C-24,
No.12, pp-1226- 1228, Dec-1975.
[4] Ulrich.L.Rohde, Digital PLL Frequency Synthesizer :Theory & Design,
Printice Hall Inc ,1983

Fig 10. System Vue loop filter output for 4KBPS data rate,
frequency offset=0Hz, Tacq=220 ms