This is the official English development manual published by Nintendo for their Super Nintendo Entertainment System video game console.
Book 1 covers the game approval process and development for the CPU, PPU, and SPC-700. Book 2 covers development for the expansion chips SA-1, Super FX, DSP-1, and accessories such as the Super NES mouse and Super Scope.
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SNES Development Manual
This is the official English development manual published by Nintendo for their Super Nintendo Entertainment System video game console.
Book 1 covers the game approval process and development for the CPU, PPU, and SPC-700. Book 2 covers development for the expansion chips SA-1, Super FX, DSP-1, and accessories such as the Super NES mouse and Super Scope.
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
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TABLE of CONTENTS
1
Table of Contents
BOOKI
SUBJECT
PREFACE...
SECTION 1 - APPROVAL PROCESS vs os 1-1-1
NOA Licensed Software Approval Process...
‘Super NES Software Submission Requirements
SECTION 2 - SUPER NES SOFTWARE ..
Introduction...
Object (OB)...
Background (BG).
Mosaic..... : 2
Rotation/EnlargementReduction 2
Window (Window Mask) 2
Main/Sub Screen 2
CG Direct Select... 2
H-Pseudo 512.. . 2
Complementary Multiplication (iene Matiphietion) 21
: : 2
2
2
2
2
2
2
HV Counter Latch...
Offset Change
Standard Controller...
Programmable VO Pott...
Absolute Multiplication/Division .
HIV Count Timer
Direct Memory Access (DMA) .
Interlace..... .
H.512 Mode (BG Mode 5 & 6) .
OBJ 33°s Lines Over & Priority Order..
CPU Clock and Address Map.
‘Super NES Functional Operation.
System Flowchart... .
Programming Cautions
Documented Problems.
Register Clear (Initial Settings).
PPU Registers =
CPU Rey
areecess
PERRLELETETABLE of CONTENTS
Table of Contents (Continued)
SUBJECT PAGE
SECTION 3 - SUPER NES SOUND
SNES Sound Source Outline ...
BRR (Bit Rate Reduction)...
VO Ports...
Control Register
Timers
DSP Interface Register.
Register Used
CPU Organization... :
Sound Programming Cautions...
SECTION 4 - SUPER NES CPU DATA
Outline.
Explanation of CPU Terminal Functions
Explanation of Functions
Addressing Mode...
Command Set (Alphabetical Order).
Command Set (Matrix Display)...
Cycles and Bytes of Addressing Modes
Differences Among 65C816, 65C02, and 6502.
Restrictions Upon Use & Application Information
Details of Command Functions
Description of Commands .
AC Characteristics
TABLES OF APPENDIX
Appendix A - PPU Registers
Appendix B - CPU Registers 0...
Appendix C - SPC700 Commands...
Appendix D - Data Transfer Procedure...
INDEXTABLE of CONTENTS
1
Table of Contents (Continued)
BOOK II
SUBJECT PAGE
SECTION 1 - SUPER ACCELERATOR (SA-1).....
Super Accelerator System Functions
Configuration of SA=1 snncnnnen
Super Accelerator Memory Map ...
SA-1 Internal Register Configuration
Multi-Processor Processing
Character Conversion...
Arithmetic Function
Variable-Length Bit Processing,
DMA =
SA-I Timer.
SECTION 2 - SUPER FX®
Introduction to Super FX.....
GSU Functional Operation ..
‘Memory Mapping ...
GSU Internal Register Configuration ..
GSU Program Execution...
Instruction Execution ....nsnsnnnnnnnnnnn
Data Access...
GSU Special Functions.....
Description of Instructions...
SECTION 3 - DSP/DSP1.
Introduction to DSP1
‘Command Summary...
Parameter Data Type.
Use of DSPI..... ses
Description of DSP1 Commands.
Math Fun:
's and Equations,
3-61TABLE of CONTENTS
Table of Contents (Continued)
SUBJECT PAGE
SECTION 4 - ACCESSORIES....... olL
‘The Super NES Super Scope® System...
Principles of the Super NES Super Scope 42-1
Super NES Super Scope Functional Operation 43-1
‘Super NES Super Scope Receiver Functions. 4-4-1
Graphics ...esecscesnesetseeneensenee 4-5-1
‘Super NES Mouse Specifications 4-6-1
Using the Standard BIOG.............. 4-7-1
Programming Cautions seseretscenetserneteesttncinenenseeneenereeseeeneBel
MultiPlayer 5 Specifications....... ADI
MultiPlayer 5 Supplied BIOS 410-1
SUPPLEMENTAL INFORMATION
Super NES Parts List 1.
Game Content Guidelines ...smsnnnnsnnnnnnnnnnn
Guidelines Concerning Commercialism and Promotion of Licensee
Products or Services in Nintendo Licensed Games 5
Super NES Video Timing Information : : 10
INDEX
BULLETINS
ElUsT of FIGURES
J
List of Figures
BOOKI
TITLE
Software Approval Process...
Picture Image...
Scanning Pattern for Interlace.
‘Super NES Functional Block Diagram...
System Block Diagram
Memory Map...
Sound Signal Flow...
BRR Data String.....
BRR Range Data......
Example Data When Filter
VO Diagram...
Port Clear
Clear Timing
Timer Control.
Timer Section...
4-Bit Counter
Timing...
Timer Related Registers.
Interface Register...
Interface Register Flow.
Bent Line Mode «......n
CPU Registers.
Boolean Bit Operation Commands,
Memory Access Addressing Effective Address.
Wave-form Overflow...
SNES CPU Block Diagram
SNES CPU Terminal Interface Diagram
SNES CPU Timing Chart...
S-PPU Main/Sub Screen Window .
PRR Ob bbb bbb bbb bow
=
>UsT of FIGURES
c 1
List of Figures (Continued)
BOOK IIT
TITLE
Super Accelerator System Configuration
SAS Bus Image...
SA-I Block Diagram...
Bitmap Register Files 0-7 ...
Bitmap Register Files 8-F
Accelerator Mode.
Parallel Processing Mode.
Mixed Processing Mode ....
Character Conversion 1
Character Conversion 2.....
Compressed Bitmap Data ..
Bitmap Image Projection
Bitmap Data Expansion
Memory Addresses for the Bitmap Area...
Character Conversion Buffers...
Fixed Mode Process Flow Diagram. =
‘Auto-increment Mode Process Flow Diagram
Barrel Shift Process.
Normal DMA
Character Conversion DMA ..
Super FX System Configuration
Game Pak ROM/RAM Bus Diagram
GSU Functional Block Diagram.....
‘Super NES CPU Memory Map....
‘Super FX Memory Map...
Example of General Register
128 Dot High BG Character Array
160 Dot High BG Character Array
192 Dot High BG Character Array
OBJ Character Array
Plot Operations Assigned by CMODE.
‘System Block Diagram (DSP1)...
‘Super NES CPU and DSP1 Communications
DSPI Command Execution
Mode 20/DSP Memory Map.
Mode 21/DSP Memory Map.
Super NES/DSP1 Memory Mapping (Mode 21)
DSPI Status Register Configuration.UST of FIGURES
1
List of Figures (Continued)
FIGURE
TITLE NUMBER PAGE
DSPI Operations Flow Diagram ....ccsnnsnnnsnnnnnnnnnnnnnn oa
Super NES CPU/DSP!1 Operational Timing : — Bhd
Trigonometric Calculation 3-5-3
Vector Calculation 3-5-4
Vector Size Comparison 35-6
Vector Absolute Value Calculation 35-7
Two-Dimensional Coordinate Rotation.. 3-5-8
Examples of Three-Dimensional Rotation... 3-5-1
Assignment of Projection Parameter... 35-13
Relationship of Sight and Projected Plane.
Calculation of Raster Data...
BG Screen and Displayed Area
Calculation of Projected Position of Object.
Projection Image of Object... :
Calculation of Coordinates for the Indicated Point on the Sereen..
Attack Point and Position Indicated on Screen (Side View)
Attitude Computation ..
Object Coordinate Rotated on Y Axis
Object Coordinate Rotated on X Axis...
Object Coordinate Rotated on Z Axis
Conversion of Global to Objective Coordinates.
Conversion of Object to Global Coordinates... :
Calculation of Inner Product with Forward Attitude.
Position of Aircraft and Vector Code...
Calculation of Rotation Angle After Attitude Change
Signal Flow
Optical Alignment.
Virtual Screen Alignment...
‘Address and Bit Assignments...
Picture Tube
‘Scanning.
Area Seen by Super NES Super Score.
Vertical Positioning
Horizontal Positioning .
Horizontal/Vertical Counter.
Super NES Super Scope Block Diagram.
Super NES Super Scope Flow Diagram -_
Raster Signal
Definition of One Bit
Output Signal Code...
Definitions of Codes
BREE R REUST of FIGURES
c a
List of Figures (Continued)
TITLE
Raster Signal Transmission Timing.....
Receiver Block Diagram.
Operation Flow Diagram...
Receiver/Transmitter Interface Schematic.
One Bit Code Detection. =
Cursor Mode Raster Detection Cycle...
Trigger Mode, Single Shot.
Trigger Mode, Multiple Shots.
Noise Flag... :
Null Bit.
Pause Bit...
‘Trigger, Single Shot...
‘Trigger, Multiple Shots...
Optical Color Sensitivity Chart
Valid Hyper Mouse Data String ...
Serial Data Read Timing....
Explanation of Data Strings 2 Bits or Longer.
Super NES Hyper Mouse Dimensions.
Standard BIOS, Output Register.
Examples of Speed Switching Program Subroutine Call...
MultiPlayer 5 Device Hardware Connections «1.0.0
MultiPlayer 5 Read Timing Chart, SP Mode.
Data Read Timing for Dissimilar Devices...
Valid Controller Data String...
Sample Program Display Format.UST of TABLES:
t 1
List of Tables
BOOKI
TITLE
B-Bus Address Changes ....
A-Bus Addressing...
BRR Filter Values.
Peripherals.
Port0 - Port3 Registers
‘Timer Function...
DSP Register Map.
ADSR Parameters...
Gain Parameters.
Noise Generator Clock...
Source Directory
Source Data Block Format
Opcode Matrix...
Address Modes...
Table of Operations.
AC Characteristics
Command Operand Symbols and Meaning...
Symbols and Meaning for Operational
Description Cosssnnnnne-2
Explanation of Symbols in the Status
Flag Column C2
Data Transmission Commands, Group 1 3
Data Transmission Commands, Group 2.. C3
Data Transmission Commands, Group 3
Arithmetic Operation Commands...
8-Bit Logic Operation Commands..
Addition and Subtraction Commands.
Shift Rotation Commands.
16-Bit Data Transmission Command
16-Bit Operation Commands...
Multiplication and Division Commands.
Decimal Compensation Commands C8
Branching Commands...... co
Subroutine Call, Return Commands C9
‘Stack Operation Commands .. co
Bit Operation Commands C10
Program Status Flag Operation Commands C19, C10
Other Commands ..ssnsnnnnsnnnnnnnnne C20. C10