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Full and Fast Sequential

The document summarizes the differences between four TetraMAX ATPG engines: basic scan ATPG, two-clock ATPG, fast-sequential ATPG, and full-sequential ATPG. Basic scan and two-clock ATPG are optimized for full scan designs, while fast-sequential can test RAM shadow logic and full-sequential supports non-full scan designs. Each engine has tradeoffs between runtime, capabilities, and supported fault models.

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926 views4 pages

Full and Fast Sequential

The document summarizes the differences between four TetraMAX ATPG engines: basic scan ATPG, two-clock ATPG, fast-sequential ATPG, and full-sequential ATPG. Basic scan and two-clock ATPG are optimized for full scan designs, while fast-sequential can test RAM shadow logic and full-sequential supports non-full scan designs. Each engine has tradeoffs between runtime, capabilities, and supported fault models.

Uploaded by

deepa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Description

Differences Between TetraMAX ATPG Engines


Question:

What are the differences in capabilities between


basic scan,
two-clock, fast-sequential, and full-sequential
ATPG?
Answer:

The following lists highlight the differences


between the four
TetraMAX ATPG engines, as of the E-2010.12 release:

Basic Scan ATPG


---------------
- Combinational ATPG algorithm
- Single scan load and single capture cycle per
pattern
- Very fast runtimes
- High pattern merging
- Good for full scan designs (with exceptions
noted below)
- Requires complete control of clock
- Supports dynamic and disturb clock grouping
- Nonscan sequential elements are treated as a
black box by default
(i.e., non-scan flip-flops, RAMS, and non-
transparent latches)
- Latches and flip-flops that are disturbed during
shift can be considered as
controllable by enabling the loadable nonscan
cell support feature
- Power-Aware ATPG support for shift and capture
- Supported for all fault models except path delay
testing
- Only used for launch on shift transition testing

Two-Clock ATPG
--------------
- Optimized ATPG algorithm for launch on capture
(system clock launch)
transition fault detection with many
similarities to basic scan ATPG
- Single scan load and two capture cycles per
patten (launch and capture)
- Fast runtimes
- High pattern merging
- Good for full scan designs (with exceptions
noted below)
- Requires complete control of clock
- Supports dynamic and disturb clock grouping
- Nonscan sequential elements are treated as a
black box by default
(i.e., nonscan flip-flops, RAMS, and non-
transparent latches)
- Latches and flip-flops that are disturbed during
shift can be considered as
controllable by enabling the loadable nonscan
cell support feature
- Power-Aware ATPG support for shift and capture
- Supported for all at-speed fault models except
path delay testing
- Not used for launch on shift transition testing
- Patterns generated with two-clock ATPG will be
stored and handled
as fast-sequential patterns

Fast-Sequential ATPG
--------------------
- Capable of testing shadow logic around RAMs and
ROMs
- Nonscan flip-flops and RAMS must be non-
destructive during load/unload for
state to be maintained for a multiple load
pattern
- Able to understand TetraMAX ATPG models for
RAMs/ROMs
- Faster runtime than Full-Sequential ATPG
- Clocks may be gated but not generated
- Supports dynamic and disturb clock grouping
- Limited to up to 10 capture cycles and/or 10
scan loads per pattern
- Able to test tri-state buses that have bus
holders
- Pattern merging not as efficient as basic scan
or two-clock ATPG
- Recommended for full scan or almost full scan
with lots of RAMs
- Can simulate the value of flip-flops or latches
that are disturbed during scan
shifting if the loadable nonscan cell support
feature is enabled
- Power-Aware ATPG support for shift and capture
- Supported for all fault models except IDDQ and
IDDQ bridging

Full-Sequential ATPG
--------------------
- Full support for gated and generated clocks
- Dynamic and disturb clock grouping not supported
- No capture limit
- Able to understand TetraMAX ATPG models for
RAMs/ROMs
- Supports user-defined sequential capture
procedures
- Able to test tri-state buses that have bus
holders
- Good for partial scan designs or to pick up
faults missed by fast-sequential ATPG
- Power-Aware ATPG is not supported except for low
power fill
- The loadable nonscan cell feature is not
supported
- Supported for all fault models except IDDQ, IDDQ
bridging, static or dynamic
bridging faults, and small delay defect
transition faults
Former article name: Test-574

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