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Memory

The document discusses memory concepts including RAM, ROM, SRAM, DRAM and their basics. It also covers common memory faults like stuck-at faults, transition faults and coupling faults. Finally, it describes several memory testing algorithms like zero-one algorithm, checkerboard algorithm, MATS algorithm and March algorithms.

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deepa
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119 views29 pages

Memory

The document discusses memory concepts including RAM, ROM, SRAM, DRAM and their basics. It also covers common memory faults like stuck-at faults, transition faults and coupling faults. Finally, it describes several memory testing algorithms like zero-one algorithm, checkerboard algorithm, MATS algorithm and March algorithms.

Uploaded by

deepa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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MEMORY CONCEPT BASICS

By
Vamsy
INTRODUCTION

• Till now we have seen Coverage and patterns for ATPG which mainly deals with combinational
, sequential circuits along with wires
• There are other very important modules in digital circuit like memories which also need to
tested.
• High storage capacity is obtained by increasing the density, which implies decrease in the size
of circuit (capacitor) used to store bits.
• Memory Architecture , redundancy cells.
MEMORY BASICS
RAM: Random Access Memory
•– historically defined as memory array with individual bit access
•– refers to memory with both Read and Write capabilities
ROM: Read Only Memory
•– no capabilities for “online” memory Write operations
•– Write typically requires high voltages or erasing by UV light
Volatility of Memory :
•– volatile memory loses data over time or when power is removed
•RAM is volatile
•– non-volatile memory stores date even when power is removed
•ROM is non-volatile
Types of RAMS:

SRAM
DRAM

Static RAM: holds data as long as power is applied (SRAM)

Dynamic RAM: must be refreshed periodically (DRAM)

MEMORY SRAM = Static Random Access Memory


- Static: holds data as long as power is applied

BASICS - Volatile: can not hold data if power is removed


MEMORY
BASICS

6T SRAM CELL:
DRAM = Dynamic Random Access Memory
– Dynamic: must be refreshed periodically
– Volatile: loses data when power is removed

MEMORY BASICS Comparison to SRAM


– DRAM is smaller & less expensive per bit
– SRAM is faster
– DRAM requires more peripheral circuitry
MEMORY BASICS
1T DRAM Cell:
• single access nFET
storage capacitor
• control input: word line, WL
• data I/O: bit line
MEMORY BASICS
MEMORY FAULTS

• Stuck At fault
• Transition fault

• Coupling fault
• NPS fault
• Address decoder fault
Stuck-At Fault (SAF) :

• The logic value of (a line or) a


cell is always 0 (SA0) or 1 (SA1)

MEMORY To detect memory cell's


SAFs:
FAULTS
• SA0: Write 1 Read 1 (w1 r1)
• SA1: Write 0 Read 0 (w0 r0)
Transition Fault (TF):

• A cell fails to undergo a 0 -> 1


transition ( Tfrise ) or a 1 -> 0
transition (TFfall) when it is
MEMORY written
FAULTS
To detect transition
fault:
• TFrise : w0 w1 r1
• TFfall : w1 w0 r0
Coupling Fault (CF):

• A write operation to one cell changes


the content of a second cell.

Implies two cells:


MEMORY
FAULTS • The victim(coupled) cell and the
aggressor(coupling) cell

Different kinds of coupling


faults:
• Inversion coupling faults
• Idempotent coupling faults
MEMORY FAULTS
Inversion Coupling Fault (CFin):

• The content of the victim cell is inverted if the aggressor cell has a transition
• To detect CFin between cell x (victim) and y (aggressor)
• CFin (y rise → x inverted): w0x w0y w1y r0x.
• CFin (y fall → x inverted): w0x w1y w0y r0x.
MEMORY FAULTS
Idempotent Coupling Fault (CFid):
The victim is forced to 0 or 1 if the aggressor has a 0 → 1 or 1 → 0 transition

To detect CFid between cell x (victim) and cell y (aggressor)


CFid (y rise → x=0): w1x w0y w1y r1x
CFid (y fall → x=1): w0x w1y w0y r0x
CFid (y rise → x=1): w0x w0y w1y r0x
CFid (y fall → x=0): w1x w1y w0y r1x
MEMORY FAULTS
Neighborhood Pattern Sensitive Fault(NPSF):
The content of a cell, or the ability to change its content, is influenced by the contents of
some other cells in the memory.
Active NPSF (ANPSF):
Change of the base cell due to a transition in the neighborhood cells
Each base cell must be read in state 0 and in state 1, for all possible changes in the
neighborhood pattern
Passive NPSF (PNPSF):
The change of the base cell is impossible due to a certain neighborhood cells
configuration
Each base cell must be written and read in state 0 and in state 1, for all permutations in
the neighborhood pattern
Static NPSF (SNPSF):
The content of the base cell is forced to a certain state due to a certain neighborhood
pattern
Each base cell must be read in state 0 and in state 1, for all permutations in the
neighborhood pattern
MEMORY FAULTS

Base cell Base cell


Type-1 neigh- Type-2 neigh-
borhood cell borhood cell

In practice two types of NPSF are used


The type-1 NPSF with 4 neighborhood cells (north, west, south, east)
The type-2 NPSF with 8 neighborhood cells
MEMORY FAULTS
Address Decoder Fault (AF) :

• Any fault that affects address decoder


• With a certain address, no cell will be
accessed.
• A certain cell is never accessed.
• With a certain address, multiple cells are
accessed simultaneously.
• A certain cell can be accessed by multiple
addresses.
MEMORY ALGORITHMS

A test algorithm (or simply test) is a A test element contains a number of


finite sequence of test elements memory operations (access commands)
MEMORY ALGORITHMS

Classical Test Algorithms:

Zero-one Algorithm

Checker board Algorithm


ZERO-ONE ALGORITHM :
This minimal test consists of writing 0s and 1s in the memory

Fault Coverage :
Not all AFs detected
SAFs detected if the address decoder is fault free Not all TFs and CFs detected
CHECKERBOARD ALGORITHM
Cells are divided in two groups

Fault coverage:
Not all AFs detected
SAFs detected if the address decoder is fault free
Not all TFs and CFs detected
This test is able to detect bridging faults
MATS ALGORITHM
MATS ( modified algorithmic Test Sequence)
(w0); (r0,w1); (r1);
s1: write 0 to all cells
s2: for each cell
read 0 ;
write 1;
s3: read 1 from all cells
This algorithm will find AFs
MATS+ ALGORITHM:
MATS+

{ (w0); (r0, w1); (r1, w0)}

This algorithm will find AFs and SAF


MATS++ ALGORITHM:

{(w0); (r0,w1); (r1,w0,r0)}

 This Algorithm will find AF, SAF, and TF


MARCHING 1/0 ALGORITHM:
Marching 1/0:
{ (w0); (r0, w1,r1); (r1,w0,r0);
 (w1); (r1,w0,r0); (r0, w1,r1)}

This Algorithm will find AF, SAF, and TF


MARCH ALGORITHM:
March X:
Step1: write 0 with up addressing order;
Step2: read 0 and write 1 with up addressing order; Step3:
read 1 and write 0 with down addressing order;
Step4: read 0 with down addressing order.
This Algorithm will find AF, SAF,TF, & CFin
MARCH C :
{ (w0); (r0,w1);(r1,w0);(r0 ); (r0,w1);(r1,w0);(r0)}

This Algorithm will find AF, SAF,TF, & all CFs---irredundant


ROM Architecture
RAM ARCHITECTURE

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