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Lmk05028 Configuration Worksheet: Orange

This document is a configuration worksheet for an LMK05028 device. It contains 8 steps to configure the oscillator inputs, clock inputs, clock output selection, DPLL settings, input validation, lock detection thresholds, and tuning word history for the device. The customer and FAE are instructed to complete the orange cells with their specific configuration details so TI applications can generate a setup file to configure the EVM.

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132 views14 pages

Lmk05028 Configuration Worksheet: Orange

This document is a configuration worksheet for an LMK05028 device. It contains 8 steps to configure the oscillator inputs, clock inputs, clock output selection, DPLL settings, input validation, lock detection thresholds, and tuning word history for the device. The customer and FAE are instructed to complete the orange cells with their specific configuration details so TI applications can generate a setup file to configure the EVM.

Uploaded by

Tu Phí
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLSX, PDF, TXT or read online on Scribd
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LMK05028 CONFIGURATION WORKSHEET

CUSTOMER: <enter customer name>


PROJECT: <enter project name>
DATE: <enter date>
REVISION: <enter revision>

INSTRUCTIONS: The following worksheet can be completed by Customers/FAEs, so TI Applications can generate a TICS Pro
Please complete the orange cells. If needed, add extra info or questions into the User Remarks cells.

STEP 1 Oscillator Inputs


Max freq. PPM
XO Frequency (Hz) Input type error vs. PVT
48,004,800 AC-DIFF 50
Frequency (Hz)
TCXO
10,000,000 4.6

STEP 2 Clock Inputs


DPLL Mux Input type
Input Frequency (Hz)
IN0 25,000,000 DPLL 1,2 AC-DIFF
IN1 25,000,000 DPLL 1,2 AC-DIFF
IN2 25,000,000 DPLL 1,2 AC-DIFF
IN3 25,000,000 DPLL 1,2 AC-DIFF

STEP 3 Clock Input Selection


Input Auto Priority
Input select mode
IN0 1st
Auto non-revertive IN1 2nd
DPLL1
IN2 3rd
Manual select register
IN3 4th
IN0 APLL2 Loopback Ignore
Input Auto Priority
Input select mode
IN0 1st
Auto non-revertive IN1 2nd
DPLL2
IN2 3rd
Manual select register
IN3 4th
IN0 APLL1 Loopback Ignore

STEP 4 Clock Outputs


Chan Mux
Output Frequency (Hz) <1>, <2> Output type
OUT0 122,880,000 PLL 2 AC-LVPECL
OUT1 122,880,000 PLL 2 AC-LVPECL
OUT2 AC-LVPECL
122,880,000 PLL 2
OUT3 AC-LVPECL
OUT4 AC-LVPECL
156,250,000 PLL 1
OUT5 AC-LVPECL
OUT6 156,250,000 PLL 1 AC-LVPECL
OUT7 156,250,000 PLL 1 AC-LVPECL

STEP 5 DPLL Configuration


Market Segment
DPLL Loop Mode <3> DPLL BW (Hz)

DPLL1 3 loop: DPLL+TCXO+APLL SyncE/SONET 1

DPLL2 3 loop: DPLL+TCXO+APLL Wireless/BTS 10


Range: 0.01 - 4000

STEP 6 Input Validation Enter "0" for any setting if Input Detect mode is not required (i.e. detector will be bypass
Frequency Detector <4>
Validation Timer (s)
Input Valid (ppm) Invalid (ppm)

IN0 0.1 55 60

IN1 0.1 55 60

IN2 0.1 55 60

IN3 0.1 55 60
Min: 0.1 ppm

STEP 7 DPLL Frequency Lock Detector Thresholds <8>


DPLL Lock (ppm) Unlock (ppm) User remarks
DPLL1 1 3
DPLL2 1 3
Min: 0.1 ppm

STEP 8 DPLL Tuning Word History

History Delay/
Ignore Time (s)
DPLL History Timer (s) <9> User remarks
DPLL1 0.001 0.0005
DPLL2 0.001 0.0005

<#> NOTES
1 At least one PLL2 clock output must be present on OUT[0:3] bank
2 At least one PLL1 clock output must be present on OUT[4:7] bank
3 SyncE/SONET: Hitless switch enabled. Wireless BTS: Hitless sw enabled, best in-band noise performance. O
4 Invalid ppm must be greater than Valid ppm
5 Window detector flags input as Invalid when any input clock period (Tper) arrives earlier than (1/Fin - T_ea
6 T_late can be set greater than one or more missing clock periods (e.g. gapped clock)
7 T_early cannot be set greater than the nominal input clock period (max Tearly = 1/Fin - 0.002 us)
8 Unlock ppm must be greater than Lock ppm
9 History delay time must be less than History timer
plications can generate a TICS Pro setup file to configure the LMK05028 EVM.
s into the User Remarks cells.

User remarks

Max freq. PPM


error vs. PVT
4.6
4.6
4.6
4.6

User remarks

User remarks

Slew rate User remarks


Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast

DCO Mode DCO Step size (ppb) User remarks

No 0.001

No 0.001
Min: 0.001

equired (i.e. detector will be bypassed)


Window Detectors <5>
Late window, Early window, T_early
T_late (us) <6> (us) <7> User remarks
Allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector

best in-band noise performance. OTN/JitterAttn: Hitless switch disabled.


er) arrives earlier than (1/Fin - T_early) or later than (1/Fin + T_late), where 1/Fin = nominal input frequency
apped clock)
Tearly = 1/Fin - 0.002 us)
LMK05028 CONFIGURATION WORKSHEET
CUSTOMER: <enter customer name>
PROJECT: <enter project name>
DATE: <enter date>
REVISION: <enter revision>

INSTRUCTIONS: The following worksheet can be completed by Customers/FAEs, so TI Applications can generate a TICS Pro
Please complete the orange cells. If needed, add extra info or questions into the User Remarks cells.

STEP 1 Oscillator Inputs


Max freq. PPM
XO Frequency (Hz) Input type error vs. PVT
48,004,800 AC-DIFF 50
Frequency (Hz)
TCXO
10,000,000 4.6

STEP 2 Clock Inputs


DPLL Mux Input type
Input Frequency (Hz)
IN0 25,000,000 DPLL 1,2 AC-DIFF
IN1 25,000,000 DPLL 1,2 AC-DIFF
IN2 25,000,000 DPLL 1,2 AC-DIFF
IN3 25,000,000 DPLL 1,2 AC-DIFF

STEP 3 Clock Input Selection


Input Auto Priority
Input select mode
IN0 1st
Auto non-revertive IN1 2nd
DPLL1
IN2 3rd
Manual select register
IN3 4th
IN0 APLL2 Loopback Ignore
Input Auto Priority
Input select mode
IN0 1st
Auto non-revertive IN1 2nd
DPLL2
IN2 3rd
Manual select register
IN3 4th
IN0 APLL1 Loopback Ignore

STEP 4 Clock Outputs


Chan Mux
Output Frequency (Hz) <1>, <2> Output type
OUT0 122,880,000 PLL 2 AC-LVPECL
OUT1 122,880,000 PLL 2 AC-LVPECL
OUT2 AC-LVPECL
122,880,000 PLL 2
OUT3 AC-LVPECL
OUT4 AC-LVPECL
156,250,000 PLL 1
OUT5 AC-LVPECL
OUT6 156,250,000 PLL 1 AC-LVPECL
OUT7 156,250,000 PLL 1 AC-LVPECL

STEP 5 DPLL Configuration


Market Segment
DPLL Loop Mode <3> DPLL BW (Hz)

DPLL1 3 loop: DPLL+TCXO+APLL SyncE/SONET 1

DPLL2 3 loop: DPLL+TCXO+APLL Wireless/BTS 10


Range: 0.01 - 4000

STEP 6 Input Validation Enter "0" for any setting if Input Detect mode is not required (i.e. detector will be bypass
Frequency Detector <4>
Validation Timer (s)
Input Valid (ppm) Invalid (ppm)

IN0 0.1 55 60

IN1 0.1 55 60

IN2 0.1 55 60

IN3 0.1 55 60
Min: 0.1 ppm

STEP 7 DPLL Frequency Lock Detector Thresholds <8>


DPLL Lock (ppm) Unlock (ppm) User remarks
DPLL1 1 3
DPLL2 1 3
Min: 0.1 ppm

STEP 8 DPLL Tuning Word History

History Delay/
Ignore Time (s)
DPLL History Timer (s) <9> User remarks
DPLL1 0.001 0.0005
DPLL2 0.001 0.0005

<#> NOTES
1 At least one PLL2 clock output must be present on OUT[0:3] bank
2 At least one PLL1 clock output must be present on OUT[4:7] bank
3 SyncE/SONET: Hitless switch enabled. Wireless BTS: Hitless sw enabled, best in-band noise performance. O
4 Invalid ppm must be greater than Valid ppm
5 Window detector flags input as Invalid when any input clock period (Tper) arrives earlier than (1/Fin - T_ea
6 T_late can be set greater than one or more missing clock periods (e.g. gapped clock)
7 T_early cannot be set greater than the nominal input clock period (max Tearly = 1/Fin - 0.002 us)
8 Unlock ppm must be greater than Lock ppm
9 History delay time must be less than History timer
plications can generate a TICS Pro setup file to configure the LMK05028 EVM.
s into the User Remarks cells.

User remarks

Max freq. PPM


error vs. PVT
4.6
4.6
4.6
4.6

User remarks

User remarks

Slew rate User remarks


Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast

DCO Mode DCO Step size (ppb) User remarks

No 0.001

No 0.001
Min: 0.001

equired (i.e. detector will be bypassed)


Window Detectors <5>
Late window, Early window, T_early
T_late (us) <6> (us) <7> User remarks
Allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector
allow 1 missing input clock cycle (T_late = 40
0.04 0 us), bypass early window detector

best in-band noise performance. OTN/JitterAttn: Hitless switch disabled.


er) arrives earlier than (1/Fin - T_early) or later than (1/Fin + T_late), where 1/Fin = nominal input frequency
apped clock)
Tearly = 1/Fin - 0.002 us)

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