Chemical and Process Engineering 2014, 36 (2), 627-642

Special Issue

DESIGN AND SIMULATION OF DVB-S2/T2 BASEBAND

DIGITAL RECEIVERS WITH USING PROCESSORS &
SOFTWARE DEFINED RADIO TECHNIQUES WITH LOWEST
POWER

Nematolah Tajbakhsh*, M.A. Pourmina, A. Khademzadeh

Science and Research Branch, Islamic Azad University, Tehran, Iran

Science and Research Branch, Islamic Azad University, Tehran, Iran
Science and Research Branch, Islamic Azad University, Tehran, Iran

Abstract. The DVB-S2 standard is the second generation of DVB-S European standard
for satellite wave’s digital broadcasting that introduced in 1995 and generated latest
edition in 2008.DVB-T is the European standard for digital TV broadcasting. This system
was used in British in 1997 for the first time. The next DVB-T standard has a higher
flexibility for pictures broadcasting with HD resolution that it introduced whit DVB-T2
title. The advantage of these standards to former versions is having higher thirty
percentage performance. In this project DVB-S2 and DVB-T2 standards are analyzed.
For mentioned standards only sending part has standard protocol and design of the
receiving parts respected to related individuals and designers. In this article the receiving
parts of above standards are designed according to sending parts and the various parts of
receiving section are analyzed. For this reason that one of the purposes of this project is
building common platform for these two standards, the various parts of these two digital
receivers divided to two common block and uncommon block according to their
performance. The parts of common block have unique performance for two digital
receivers. The parts of uncommon block have various performances for two digital
receivers. According as flexibility is one of the other purposes of this project, the common
block with ASIC chip and the uncommon block with DSP chip are designed. The
respected system can perform the mentioned standards with above chips and SDR
techniques. The new capability of this system is smart to perform the other standards.
This technique with switching between ASIC/DSP and full DSP architecture will achieve.
This system performs the updating capability for various standards. The other new
technique in this architecture designing is respecting system control operations to general
processor replace to other chips. For analyzing the designed architectures in this article,

* Corresponding author

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the simulation and analyzing the achieved data with Matlab Simulink software are
performed, and at the end conclusion, purposes and future works are mentioned.

Keywords: DVB-S2/T2 standards, SDR, ASIC and DSP chips, Matlab Simulink.

INTRODUCTION

DVB standard was first introduced in Europe by the project after completion will become the
European standard by the Standards Institute ETSI, was developed. This standard is divided into
three main branches (DVB-S, DVB-T and DVB-C). End letter of any words indicating the type of
sending signal. DVB-S, based on satellite (S = satellite), DVB-C, according to the cable network
in Home (C = cable) and DVB-T based on a signal from Earth Station (T = terrestrial) have been
built. Standard regarding how to send audio data and digital image and only the sender referred to
Section DVB receiver solution has been developed. Hence, according to the standards established
for the sender, the receiver portion should be design. DVB Standard using the integrated signal
converter, the converter ring (convolution coding) and forward error correction (with adding extra
information to sending signal for repairing it in error situation).Manner with the introduction of
the chip can be programmed as chip DSP, FPGA and CPLD it is possible to design such systems
as flexible as possible, using the technique (radio software) SDR different standards in a chips that
use of the occupied area, power consumption and cost reduced. DVB Decoder Can be converted
into analog and digital sections. Analog part on the received signal from the antenna will perform
the necessary processing to extract data bit digital signals to analog and digital part of the deliver.
Section digital Parts of this Decoder refers to a digital data processing to zero and a cluttered data
and code, to be distributed data interfaces to achieve images. optimize this part of the system
Digital receiver makes a significant optimization in a base-band system (a technique in which only
one signal at any moment can be sent over the transmission medium.) that reduce the power
consumption of digital as well as reducing the area occupied, will be followed. Another key issue
is the main focus of this paper is on a flexible hardware design. Another key issue is the main
focus of this paper is on a flexible hardware design. As we know, today the software and hardware
technology are growing, and digital broadcasting standards are no exception. For example, shortly
after the introduction of a standard DVB-S Standard DVB-S2 And also introduced the standard DVB-
T Standard DVB-T2 Was introduced. In DVB standards field, different changes were creating in
these standards different versions that using the former systems will be inefficient and designers
and buyers will be force to modify and replace the old systems. However, this change could be
provided, if admitted into maintaining the functionality of the system software provided with the
ability to update the system can be held and used to this technique, the radio went Software. In
figure 1 DVB-S2 transmitter system block diagram is shown. As can be seen, DVB-S2 system has
implemented to mode adaption, stream adaption, FEC coding, mapping, physical layer and
modulation subsystems. The mode matching system Pricing inbound interface, the sync input
(optional), remove the empty packets (for TS formats in the case ACM System), encoded incoming
packet error detection, integration of incoming packets in case we have some kind of input data

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and the segmentation of incoming packets into the data field enforces. Signaling the end of this
section is added to the base-band receiver According to formats that can adapt itself by system.
Diagram of this part of the system in case there is only one input is shown in Figure 2. As can be
seen in the current implementation of the system after the system has been mode adaption. Input
interface subsystem, the electrical input format makes the system a bit into logical form. Received
the first bit as the most valuable bits (MSB) be considered.

Fig 1. DVB-S2 transmitter system block diagram

Fig 2. Main parts of mode adaption and stream adaption subsystems

After mode adaption subsystem, the stream adaption subsystem is underway. This section is to
obtain a fixed-length frame-based band as well as providing input to the Baseband Scrambler is
designed to consist of two parts: Padding and BB Scrambling. In padding part the dummy records
in the data field and so long as it’s fixed frame-based band brings. In the Baseband Scrambling to
complete framing bits it should be randomly placed. Frame for a random sequence of bits into the
most valuable and will continue until the last bit. Random sequences were read using a feedback
shift register takes place. Pseudo-random binary sequence generator polynomial is 1+𝑋 4 +
𝑋15 equal to the random mechanism. FEC encoded subsystems using of two encoding algorithm.
Outer encoding (BCH) and inner encoding (LDPC) that after the coding operation, leaf, leaf out
(bit interleaving) that runs on the modulation format of 8PSK, 16APSK and 32APSK output

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encoder LDPC should interleave by interleave block. Data serially into block columns and rows
as well as the serial If it is empty, the first bit is the most valuable bit of extra rows (MSB) Frame-
based band, except in cases where a modulation is 8PSK with rate of 5/3.The most valuable bit of
the frame is a bit of a third runway exits. Sub-band coding system based FEC frame is placed after
the FEC frame is formed. According to the figure given BCH Coding and LDPC coding is done
in the frame of the base band. Insert blocks in Figures 3, 4 are shown.

Fig 3. 8psk with normal length all except rate 3.5

Fig 4. 8psk with normal length only rate 3.5

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The mapping subsystem is for both formats, short base band frame (bit 16200) and regular (bit
64800) to convert incoming serial to parallel. Most valuable bit of the base band frame mapping
to the most valuable bits of trail input parallel. In this conversion the two bits into modulation
QPSK, three for modulation 8PSK, four bits for modulation 16APSK and five bits for modulation
32APSK be considered. Mapping action must be done in parallel on each sequence that the value
of the bit allocation is dependent on the selected modulation. Input sequence of this mapping is
FEC frame (FECFRAME) and output sequence is complex FEC (XFECFRAME) that in
conventional longitudinal frame size (number of bits allocated / 64800) symbol and short frame
mode against (16200 / number of bits allocated) is a symbol that represents the vector (I, Q) is
determined. The physical layer subsystem frame format called PLFRAME will produce the
following procedure 1 - generate extra frames when no XFECFRAME as input for processing or
transmission 2 - share XFECFARME to S slots Each slot is the length of 90 symbols 3- generate
physical layer header and putting it before FECFRAME to configure the receiver. The length of
physical layer header is 90 symbols 4 - put the pilot block (which modes require to the pilot block)
inside the slots. To be a pilot for every 16 slots to help synchronize the receiver is placed. Size of
the pilot block is 36 symbols. This point should be considered in the frame of the physical layer
block is not terminated to Pilot block. 5- Random (I, Q) symbols of modulated to strengthen the
physical layer. The input of physical layer formatting subsystem is FECFRAME and the output of
this subsystem is PLFRAME. Latest DVB-S2 standard subsystem is modulation subsystems.
Practical modulation technique in which multiple bits of information to be superimposed on the
carrier wave. Quadrature amplitude modulation (QAM) is a signaling popular technique in DVB-
S2 standard. This technique is a combination of ASK and PSK .QAM can also be considered as a
logical development of QPSK. QAM takes advantage of the fact that send two different signals
simultaneously on there is a carrier frequency. Two copies of the practice of using carrier
frequency, one shift of 90 degrees relative to the other is done. For QAM, each carrier, is
modulated by ASK. Two independent signals are sent simultaneously on a single media. Within
the receiver, the two signals are demodulated and combined and results the original binary input
to be obtained. In this part we consider the various parts of DVB-T2 standard. In Figure 5 DVB-
T2 standard overview is shown. Entry system can be one or more MPEG-2 TS format. The input
preprocessing is not considered part of the T2 system, is a service provider may be a slit or an
input streams demultiplexer to separate different services to be input. Output unit is usually a signal
that is transmitted using a single RF channel. Outputs MISO mode, the system can also support
the transfer.

Fig 5. DVB-T2 standard overview

The first systems were then digitized video and audio are compressed to reduce the data volume.
The information obtained from the audio and video packets in the data stream between the

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clustered together and form submissions. To protect against possible errors in the data transmission
channel, they added some information, error correction and multi-carrier COFDM modulation
method are sent.DVB-T2 system has the following mode adaptive systems, adaptive streaming,
encoding FEC, mapping, physical layer and modulation. In this standard work of mode adaption,
stream adaption, LDPC Encoder and BCH Encoder subsystem of FEC encoding is same as mode
adaption, stream adaption, LDPC Encoder and BCH Encoder subsystem of FEC encoding from
DVB-S2 standard. In DVB-T2 standard Bit interleaving is performed on the output from the LDPC
encoder is a balance that includes insertion of the insert bits are obtained by rotating column. The
output of parity bits interleaver specify with U and the output of column circular bit interleaver
specify with V. In this standard for mapping each FEC frame (average = 64,800 bits short = 16200
bytes) should be modulated and coded block from input bits to multiplexer, convert to words that
obtain parallel from the output of demultiplexer. Then these words are mapped to their spectral
values. Standard formats for DVB-T2 physical layer signaling using L1 (first layer) takes place.
L1 signaling receptor provides the opportunity to track the physical layer in terms of T2 frames.
These signaling are divided into three main parts: signaling P1, L1 pre-signaling and signaling L1.
Purpose of signaling P1 carries the symbol is determined by the type of transmission and the
transmission parameters. Signaling remains are shipped using P2 symbols, which may also carry
data. Already received L1 signal to decode the L1 signaling the parameters necessary for achieving
physical layer transmits to the receiver activates. The signaling is divided into two main parts:
configurable and dynamic, which may be associated with a field extension. Then L1 signaling and
insert a CRC field (if required) ends. DVB-T2 standard can be used OFDM modulation. OFDM
(orthogonal frequency division modulation disruption, Orthogonal Frequency-Division
Multiplexing) is a baseband modulation. This modulation, as the name implies, the multiplexing
operation using orthogonal frequency division course to run. Orthogonal frequency division
concept of orthogonality (plumb) refers to a signal which is a mathematical definition of the sine
function where you can multiply the integral of this product over any period is equal to zero.

DESIGN AND SIMULATION

By studying the different parts of the standard DVB-S2 and DVB-T2 receiver system on an
inpatient unit designed to be flexible and analysis under the two standard systems explains and to
design and simulate our proposed architecture. Digital receiver acts inversely in compare to Digital
Transmitter. With analyzing the DVB-S2 standard, the subsystems to 1 - Quadrature
Demodulation (Demodulation Quadrature) 2 - PL Framing (physical layer format) 3 - Demapping
4 - Bit Deinterleaving 5 - FEC Decoding (decoded FEC) 6 - Stream Adaption (adaptive streaming)
7 - Mode Adaption (adaptive mode) are classified. In Quadrature Demodulation Subsystem two
independent signals are sent simultaneously on a single media. Within the receiver, these two
signals are demodulated and the results are combining for obtaining the original binary input.
Primary task PL Framing become physical layer FEC frame is reinforced. In this section the
Descrambling action takes place on the input data that Input bit from being accidentally removed
from original form to be converted. Demapping subsystem acts inversely in compare to mapping
subsystem. Demapping for both short base-band frame format (16200 bit) and regular (64,800

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bytes) form parallel to serial conversion is placed in the account. The most valuable bit parallel
input sequence is mapped to the most valuable bits of based band frame. The two bits into
modulation QPSK, three bits into modulation 8PSK, four bits for modulation 16APSK and five
bits for modulation 32APSK are considered. This section is then serves as the input sequence
frames, complex FEC (XFECFRAME) and the output frame (FECFRAME) FEC, which is typical
in longitudinal frame size (64,800 / number of bits allocated) to incorporate and short frame mode
(16200 / number of bits allocated) is a symbol that represents the vector (I, Q) is determined. In
bit deinterleaving subsystem for modulation with 16APS, 8PSK and 32APSK formats, the
demapper output should insert with bit interleaver block. Data serially into block columns and
rows as well as the series of empty rows to be inserted if the first bit is the least bit (LSB) frame
XFECFRAM except in cases where a modulation 8PSK A rate of 5/3 are the most valuable bits
of frame XFECFRAM the third bit entered.FEC Decoding subsystem uses two encryption
algorithms. Foreign coding (BCH) and internal coding (LDPC) that after this coding runs the bit
interleaving operation. FEC decoding subsystem is performed after FEC frame to creating the FEC
frame. Sender part runs at first BCH coding and then LDPC coding after baseband frame. Receiver
part after Bit Deinterleaving at first runs LDPC inner decoding and then BCH outer decoding. FEC
decoding subsystem is following FEC frame that can be obtained baseband frame and detect and
correct them if error will be occurred in sending packets. In receiver part stream mode is following
FEC decoding subsystem and purpose of it is at first input packets descrambling and delete the
extra field that added to input packets in padding subsystem. In this subsystem padding field is
placing after data field that after execution of this subsystem will delete this field from data frame
and remaining data will enter to descrambling subsystem. The receiver mode adaption subsystem
is adapted to accommodate the incoming packet format and synchronize the receiver with the
received packet input rate is used. Header identifying the base band and the detection rate and
adapt to synchronize the input format of the incoming packets will be dropped. Later stage CRC
decoding operation is performed on the remains closed and the authentication code decoded with
the CRC field if the packet is compared to error detection, error correction and thus the received
packet will be obtained depending on the initial data. With analyzing the DVB-T2 standard, the
subsystems to 1- OFDM demodulation 2- physical later detection 3- Demapping 4- Bit
Deinterleaving 5- FEC decoding 6- stream adaption 7- mode adaption are classified. Modulated
signal using carrier frequencies detection retrieval and initial signal obtain from modulated signal
in OFDM demodulation subsystem that include sending frames physical layer. In physical layer
detection that it is mentioned L1 signaling receptor provides the opportunity to track the physical
layer in terms of T2 frames. These signaling are divided into three main parts: signaling P1, L1
pre-signaling and signaling L1. Purpose of signaling P1 carries the symbol is determined by the
type of transmission and the transmission parameters. Signaling remains are shipped using P2
symbols, which may also carry data. Already received L1 signal to decode the L1 signaling the
parameters necessary for achieving physical layer transmits to the receiver activates. The signaling
is divided into two main parts: configurable and dynamic, which may be associated with a field
extension. Then L1 signaling and insert a CRC field (if required) ends. Every FEC frame
(normal=64800 bits, short=16200 bits) should convert into modulated coded block words from
input bits to demultiplexer that exit parallel from output of demultiplexer. Then this words map

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into their spectrum values. In receiver part acts inversely, it means that words after obtaining from
their spectrum values input parallel to multiplexer and output serially. In Bit Deinterleaving
subsystem that is mentioned Bit interleaving is performed on the output from the LDPC encoder
is a balance that includes insertion of the insert bits are obtained by rotating column. The output
of parity bits interleaver specify with U and the output of column circular bit interleaver specify
with V. In receiver part procedure of bits interleaving is inversely. FEC decoding uses two coding
algorithms, outer decoding (BCH) and inner decoding (LDPC) that after this coding stream
adaption operation will be performed. In the sender part at first BCH coding and then LDPC coding
after baseband frame will be performed. In the receiver part stream adaption subsystem is
following FEC decoding subsystem to descrambling the input packets and delete the extra field
that added to input packets in padding subsystem. Padding field is following the data field that
after execution of this subsystem this field deleted from data field and surplus data are entering to
descrambling subsystem. The receiver mode adaption subsystem is adapted to accommodate the
incoming packet format and synchronize the receiver with the received packet input rate is used.
Header identifying the base band and the detection rate and adapt to synchronize the input format
of the incoming packets will be dropped. Later stage CRC decoding operation is performed on the
remains closed and the authentication code decoded with the CRC field if the packet is compared
to error detection, error correction and thus the received packet will be obtained depending on the
initial data.
Design of DVB-S2/T2 standard shared and non-shared parts
Comparing the base-band digital receiver blocks both DVB-S2 and DVB-T2 standards shared
block for these two standards (blocks that have the same function) to 1 - LDPC DECODER 2 -
BCH DECODER 3 - STREAM ADAPTION 4 – MODE ADAPTION are divided. These four
blocks in terms of performance, the same operations are performed on two standards, one block at
a higher level and we call it a shared block. The shared block in Figure 6 is shown.

Fig 6. DVB-S2 and DVB-T2 standards baseband digital receivers shared block

Analysis and comparisons were made, non-shared blocks (blocks that have not the same function)
to 1 - Demodulation 2 - PL Framing 3 - Demapping 4 - Bit Deinterleaving are divided. These four
blocks in terms of performance have different operations at a higher level and put a block on it and
we call non-shared block. The non-shared block in Figure 7 is shown.

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Fig 7. DVB-S2 and DVB-T2 standards baseband digital receivers non-shared block

Initial design of the overall diagram of the DVB-X2 (S2-T2) base-band digital receivers to
support the implementation of the DVB-X2 digital receivers
To provide an outline of the DVB-S2/T2 digital receiver, according to the results of the previous
section, two shared and non-shared blocks from the previous section in a block at a higher level
and put it as a plans put the initial design. According to the performance of shared and non-shared
blocks and the mentioned performance of digital receivers, shared block is placed after non-shared
block. This section is the foundation of the design criteria based on the shared and non-shared
blocks. DVB-S2/T2 base-band digital receivers initial diagram in Figure 8 is shown.

Fig 8. DVB-S2/T2 base-band digital receivers initial diagram

Given that a shared block for both standards has the same performance we use ASIC chips to
implement this block. Selected chip for shared block, while increasing processing speed, the power
consumption reduces and given that every non-shared block parts have different operation for these
two blocks we use a DSP chip to implement this block. Using DSP chip it made flexibility for
system. The communication between ASIC chip and DSP chips made by a multilayer bus. A
shared-memory that named system memory and includes algorithms for non-shared block is
connected to the bus. There is also a Microcontroller chip to control the connection between the
chips and the bus. This microcontroller chip is connected to ROM system that can receive control
information from the system. RF interfaces are connected to the bus. The bus of this architecture
is highway connection between control system and memory with system components. In figure 9
Initial architecture of DVB-S2/T2 base-band digital receiver is shown. As shown in the basic
architecture for the implementation of non-shared components 4 DSP is used. Every one of these
four DSPs can according to own action select from special series that can perform dedicated
processing block needs. The shown ASIC chip in this architecture performs two mentioned
standards processing shared blocks.

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Fig 9. DVB-S2/T2 baseband digital initial architecture

Microcontroller using control signals shown in the figure, control DSP and ASIC chips for
scheduling, memory access and processing of orders. After being digitized input RF signal with
RF interfaces is inserted to start the input data processing operations and then these bits are
sequentially processed by other DSP and exit original data from ASIC chip.

Ultimate design
The final architecture uses 1GB shared memory. This shared memory is a place for storing radio
algorithms and input giving bits from RF interfaces. This shared memory is a dedicated memory
for DSP and ASIC chips and system working memory. The same as initial architecture RF
interfaces are connected to bus. Peripheral devices also added to system by bus in final
architecture. Their operation is controlled by system general processor. An external flash memory
with 2G bytes of the volume is devoted to the system through a multi-layer bus. This memory is a
place for storing operating system, radio algorithms, application programs and required data of
system permanently. This memory is a basis for updating data and different programs. The final
architecture according to the basic architecture, hardware selection and specific objectives for the
project is designed. In figure 10 Ultimate architecture of the system is shown. In this architecture
the multilayer bus is a connecting highway of the input, output components and this system
processing. Processing algorithms, operating system, applications and data are located in the
system's internal Flash memory. With using different methods can load required data in this
memory that for example can mention to On Air loading, load with USB terminal and load by
internet. Shared memory is imaged work memory for this system. This shared memory is including
special memory of ASIC and DSP chips.

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Fig 10. DVB-S2/T2 baseband digital receiver final architecture

ASIC chip perform LDPC / BCH decoders and Stream / Mode Adaption that are common
algorithm for these standards. Each of the four cores in a DSP chip performs Demodulation
algorithms, PL Framing, Demapping and Bit Deinterleaving. As mentioned, this architecture can
performs different standards with switching between ASIC and DSP chips. For standards
implementation that does not use the common block full implementation of DSP used in the
design. Peripheral devices are including multimedia decoders and input devices that connected to
system via a bus. RF interfaces convert accepted signals from the antenna into bits to be processed
into system chips. General CPU in addition to perform system and application programs control
the different components of this system.

Simulation and analysis of data and results

According to given architecture and designs we will simulate baseband digital receivers with
Matlab Simulink software. In addition to the simulation of the receiver section parts, the
transmitter section parts also simulated clearly to analyze the accuracy of receiving data in
compare to sending data and compare between them. This simulation for product the sending
packets from Bernoulli generator is used. By this generator can generate sending data in frame
format and according to length of DVB-S2/T2 standards. Receiver section and sender section
blocks with using suitable and present algorithms of Matlab Simulink software are shown in this
design clearly. Other blocks that to present input and output signal spectrum, calculate the error
rate, switch, presentation and data framing are used are shown in this model. Also model has a
block for generating noise in propagation environment to simulate real situations and can analyze
the results correctly. In this simulation QPSK modulation at a rate of 1/2 for DVB-S2 standard and
Rectangular 256-QAM modulation for DVB-T2 Standard is used. During of this simulation is 10
seconds as intended. To simulate the transmission part we use the binary Bernoulli distribution to
generate DVB-S2/T2 Standards frames. Generated buffers in this block are leaved from buffer
mode through the unbuffer block and after discrete time function integration will be showing with
Scope block. Generated frames for creating defined signaling are buffered and will ready to
sending to BCH encoder after padding operating. Padding and buffering operations are designed
in BBFRAME Buffering block. Operation of BBFRAME Buffering block in Figure 11 are shown.

Fig 11. Operation of BBFRAME Buffering block

BCH Encoder, LDPC Encoder and Bit Interleaver blocks are designed according to DVB-S2/T2
standards algorithms. The output of these two blocks are sent to QPSK modulator with a rate of
1/2 for DVB-S2 Standard and Rectangular 256-QAM modulator for DVB-T2 standard. Because
of in real environment the noise exists and to correct analysis the result of our simulation model
from sending and receiving data the Gaussian noise generator block is used to creating noisy

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environmental situation. Simulation results for the spectrum of the transmitted signal in Noisy
Environments for DVB-S2 Standard with QPSK-1/2 modulation and DVB-T2 Standard with
Rectangular 256-QAM modulation are shown in 12 and 13 Figures. For a comparison between the
signal to noise ratio of the transmitted signals and the signal to noise ratio of the received signals
from the transmitters and receivers of DVB-S2/T2 standards in given modulations a block is used
that this block is named comparator block and the operations of this blocks is shown in Figure 14.
The results of the simulation to calculate the difference between the signal to noise ratio of
transmitted and received signals in the simulation model are shown and here only will be to express
the amount of the difference between the two standards. Different levels of signal to noise ratio for
DVB-S2 standard in modulation QPSK-1/2 value of 1.007 dB and for DVB-T2 standard in
Rectangular 256-QAM modulation value of 1.142 dB is obtained.

Fig 12. DVB-S2 Sent signal spectrum Fig 13. DVB-T2 Sent signal spectrum
QPSK-1/2 in noisy environment Rectangular 256-QAM in noisy environment

To simulate the receiver part of transmitted signals by the transmitter of the mechanism of noise
after passing through the block, the blocks are demodulator. The output of the DVB-S2/T2
standard demodulator is designed to support architecture entered into a Switcher are and the output
of Switcher entered into Deinterleaver block. Switcher blocks, demodulators and Deinterleaver
using appropriate algorithms, DSP blocks beds are designed to simulate the architecture. The
obtained result from Deinterleaver block inputs LDPC Decoder that in addition to this function
block, error rate of parity bits in this block is designed that the results indicate the absence of the
parity bits error rate is in the process of sending and receiving signals of DVB-S2/T2 standards.

Fig 14. Sending and receiving signal to noise ratio comparator operation

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The output of the LDPC decoder entered into BCH decoder is based on DVB-S2/T2 standard
algorithms is designed. Then the output of this block is entered to BBFRAME Unbuffering block
that operations of this block in Figure 15 is Shown that unlike of the BBFARME Buffering block
at first padding operation and then buffering operation is done to obtain basic data frame format.
To display the signal spectrum generated in this block, output buffers in the block is entered into
unbuffer block check out buffer mode and after the integration of discrete time function via the
Scope block will be display.

Fig 15. BBFRAME Unbuffering block operation

LDPC and BCH decoder blocks and BBFRAME Unbuffering using appropriate algorithms, matrix
blocks are designed ASIC architecture simulation. To properly analyze the results of data sent and
received data in the frame format and ensure the accuracy of the simulation, comparisons were
made between data frames sent and received, as well. To calculate the packet error rate, we have
developed a PER block as containing subsystems are shown in Figure 16. This block calculates
the error rate of sending and receiving packets, which deals with the setting of frame and bit
comparison is done.

Fig 16. Subsystems of packet error rate comparator block

The results of the simulations conducted in this field indicates no error occurred in sending and
receiving data packets that this block will be shown in the simulation model. Another important
comparison is the bit error rate of LDPC block. Using the Error Rate Calculation block the Output
bit error rate of the LDPC encoder block and the Output bit error rate of the LDPC decoder block
is obtained that Simulation results indicate absence of the bit error in this comparison. Another
comparison that the simulation is conducted to compare the signal range and receive data frames
together that are displayed on a Scope. To do this, send and receive signals output after passing
through the Unbuffer block, Discrete-Time Integrator and a Multiplexer shown by one Scope and
the results of this simulation are shown in Figure 17. In this spectrum, the purple color represents
a transmitted data signal and yellow is color of the incoming data signal. The difference in the
amount of sent and received frames as shown in the simulation, which is shown with respect to the
equivalent of one second. This figure indicates that the incoming frames are transmitted frames
and this procedure demonstrates the accuracy of the simulation for the DVB-S2/T2 baseband
digital receivers. Simulations perfect model were done for the architecture is shown in Figure 18.

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Fig 17. Compare the signal range and receive data frames together that are displayed on a Scope

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 Design and simulation of dvb-s2/t2 baseband digital receivers with using processors & software …

Fig 18. Perfect model of DVB-S2/T2 baseband digital receivers for final architecture

CONCLUSION

In this article design and simulation of DVB-S2/T2 baseband digital receivers with the goal of
creating unified and flexible admission system functionality has been preserved. Compare new
architecture designed according to the literature and represents the work done achieving the goals
of this project. In fact, the key design conducted in this paper is the efficient use of hardware and
software resources. The ultimate architecture design shown is a flexible architecture for the design
of DVB-S2/T2 base-band digital receiver. This architecture is flexible and also fulfills the
admission unit for mentioned standards, has ability to perform other standards whit switching from
DSP/ASIC state to full DSP state and Such an approach to the control this system is done using
general CPU that this is a smart design for digital processing systems. This architecture reduces
the size of area and power consumption significantly. Because this achievement is that instead of
using multiple chips on a programmable chip is used. According to the DSP chip's processing
speed ASIC chips to the limit is reached, it will not compromise system design capabilities. It can
be said that the area and power consumption of this architecture, it is half full ASIC, because
without reducing the capacity of the system, the chip is used to optimize the system And instead
of using several ASIC chips for different standards, a flexible chip with high operating frequency
is used. This applies particularly in the case of a standard based on DVB standards or more, or
what other standards are used, it would be more dramatic. The results of simulations performed
using Simulink Matlab software and simulation model for the DVB-S2/T2 standards blocks
algorithms indicates that the design of such a system with the aim of realizing the system as
possible is good. For future work on this project can be Review, analysis and simulation of other
standards that are created from DVB-S2/T2, for examples DVB-C2 (second generation digital
broadcasting standard cable) and DVB-H2 (second generation digital mobile television
broadcasting standard) - This standard is an urgent need for research on - Can be offered that
Architecture made in this article as a basis for future designing can be good.

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