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CA Assignment 3

A multi-cycle data path architecture breaks up instructions into smaller steps that each take one clock cycle to complete. This allows functional units to be reused across clock cycles. It reduces hardware costs compared to a single-cycle architecture. Each instruction is divided into stages like fetch, decode, execute, and writeback that occur over multiple clock cycles. Intermediate registers store results between stages. While performance is slower than a single-cycle design, a multi-cycle approach allows for shorter clock cycles and more balanced instruction timing.

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59 views4 pages

CA Assignment 3

A multi-cycle data path architecture breaks up instructions into smaller steps that each take one clock cycle to complete. This allows functional units to be reused across clock cycles. It reduces hardware costs compared to a single-cycle architecture. Each instruction is divided into stages like fetch, decode, execute, and writeback that occur over multiple clock cycles. Intermediate registers store results between stages. While performance is slower than a single-cycle design, a multi-cycle approach allows for shorter clock cycles and more balanced instruction timing.

Uploaded by

INAM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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COMSATS INSTITUE OF INFORMATION TECHNOLOGY

COMPUTER ARCHITECTURE – ASSIGNMENT 2

COMPUTER ARCHITECTURE

ASSIGNMENT 3

Submitted By
Inaam Ullah Khan
FA19-BCS-061

Submitted To
Sir Muhammad Ali Faisal

Date
03-05-2021

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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2
QUESTION
Describe The “Multi-Cycle” Machine Data-Path Architecture

Multi Cycle:
By definition, a multi-cycle path is one in which data launched from one
flop is allowed (through architecture definition) to take more than one
clock cycle to reach to the destination flop. Multi-cycle data paths
break up instructions into separate steps. Each step takes a single clock
cycle Each functional unit can be used more than once in an instruction,
as long as it is used in different clock cycles. It reduces the amount of
hardware needed. It reduces average instruction time.
Features Of Multi Cycle:
 Divide the instructions into smaller steps
 Execute each step (instead of the entire instruction) in one cycle
 Control is specified by finite state diagram
 (Microprogramming is used for complex instruction set)
 The most widely used machine implementation
 Instructions are divided into artistry number of steps.
 Clock cycles are short but long enough for the lowest instruction.
 There are only 1 instruction that can be executed at the same
time.
 There is a variable number of clock cycles per instructions.
 Control unit generates signals for the instruction’s current step
and keeps track of the current step.
 There is no duplicate hardware, because the instructions generally
are broken into single FU steps.
 Extra registers are required to hold the result of one step for use
in the next step.

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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2
 Performance is slightly slower to moderately faster than single
cycle, later when the instructions steps are well balanced and a
significantly fractions of the instructions take less than the
maximum number of cycles.
Multi-Cycle Implementation:
We can get around some of the disadvantages by introducing a little
more complexity to our data-path. Instead of viewing the instruction as
one big task that needs to be performed, in multi-cycle the instructions
are broken up into smaller fundamental steps. As a result, we can
shorten the clock period and perform the instructions incrementally
across multiple cycles.
The basic idea of the multicycle implementation is to divide the one
long cycle of the single cycle implementation into 3 to 5 shorter cycles.
The number of cycles depends on the instruction.
General Steps For Implementation:
Generally, we can say we need to perform the following steps for
implementation:
 Instruction fetch.
 Instruction decode and register fetch.
 Execution, memory address computation, branch completion, or
jump completion.
 Memory access or R-type instruction completion.
 Memory read completion.
Multi Cycle Architecture:
 Each instruction is executed in several clock cycles
 Instruction execution time (machine cycle) is variable

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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2
 Instructions can store intermediate results (in intermediate
registers) to be used in next stages of execution of this instruction
 The final instruction results are stored either in register file,
memory or PC
 Reduction of dedicated architecture elements in favor of
intermediate registers

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