’The 1a*” International Conference on Microelectronics Tehran, Oct. 31- Nov.

2,2000

A Parallel Genetic Approach to The Gate Sizing Problem Of VLSI

Integrated Circuits

S. Benbider*, F. Boumghar & A.R Baba-ali

Electronics Institute / System Architecture Lab.
* T.S. Institute.
USTHB , BP 32 Bab-Ezzouar, Alger

Abstract : complexity which is incompatible with the resolution

This paper describes the implementation of a of problems with large size data. Unfortunately the
software CAD (Computer Aided Design) tool, size of VLSI circuits is huge (several million of
applied to the sizing problem of standard cells transistors). This fact has motivated the choice of
VLSI integrated circuits. Unfortunately the sizing heuristic approaches such as genetic algorithms for
problem belongs to the class of NP-complete the resolution of the sizing problem.
problems, and the size of VLSI circuits may be
huge. As a consequence, we studied heuristic
solutions in order to solve this problem. This 2 The genetic alporithms :
software performs circuit timing optimization,
based on an evolutionary approach. The genetic 2.1 Introduction :
algorithm is a meta-heuristic which gives near- Genetic algorithms [ 4 1, [ 5 ] are exploration methods
optimal solutions with polynomial running times. based on the natural selection mechanisms in genetic
field. The natural selection mechanisms avoid one of
1 Introduction the main constraint for program design. That is the
-
The sizing VLSI integrated circuits’ problem [ 2 3 ] specification of all the problem characteristics as well
consists in determining for a given circuit a as the precise tasks needed to solve it. Despite the
configuration which realizes the desired fact that genetic algorithms use a random-based
specifications. In order to achieve this aim, one must search of solutions, they are not purely random. In
choose for each circuit component (ie : gates), the fact they make an intelligent search exploiting
parameters which enables faster circuit operations efficiently the previously obtained informations in
with a minimum power consumption and cost penalty. order to deduce new and better solutions to explore.
The main considered parameter for optimization
methods based on the sizing approach is the
elementary component’s size. Basically each circuit
2.2 Basic principles :
Genetic algorithms are fkndamentaly different from
/
component is available in several functionally classical optimization methods as :
equivalent versions, each one having a different size.
As a result, each version has also different 0 They use a coding of the problem parameters
performances. More precisely, the greater is a instead of the parameters themselves.
component, the faster is its speed [ 6 1. However 0 They work on a population of solutions instead
greater components are also more expensive and have of amique current solution.
greater power consumption. On the other hand, 0 They only use the values of the studied function,
smaller circuit components are cheaper but also and never its derivative which needs complex
significantly slower. Thus the dilemma consist in analytical or numerical computations, nor any
choosing for each circuit component the optimal size other auxiliary computations.
in order to obtain a circuit faster enough with a They use probabilistic transition rules instead of
minimum area. deterministic ones.
This problem belongs to the class of NP-complete
problems. It means that there is no efficient known All these characteristics contribute together to the
algorithms to solve this problem. The only known robustness of the genetic algorithm.
exact algorithms enumerate all the possible solutions
of the problem in order to find optimal solutions. The As specified previously, genetic algorithms use a
drawback of these methods is the exponential coding of the problem parameters. Consequently,

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 The 12” International Conference on Microelectronics Tehran; Odt. 31- Novt 2,2000

they deal with what is called chromosoms or chains, Reproduction and crossover mechanisms are thus
representing each a possible solution. A chromosom simple. However, their combined actions ‘ ~ v eto
is constituted with a set of genes representing each a genetic algorithms their power. The crossover is just
parameter of the problem. With the binary coding, the memorisation of actions that gave good results in
each gene or parameter is represented by one bit (a 0 the past.
or 1).
2.3.3 Mutation
2.3 Genetic operators In a simple genetic algorithm, the mutation is a
Basic operators of the genetic algorithms implement random eventual modification (with a weak
chains manipulations such as copies and subchains probability) of the value of a character chain. It is
exchanges. At the begining a chain generation is simply equivalent using binary coding to change a 1
randomly created. Subsequently, the following to 0 and vice versa.
genetic operators are applied : When used in conjunction with reproduction and
0 reproduction crossover operators, the mutation represents an
0 crossover insurance mechanism that avoids the lost of good
mutation solution properties.
These operators are applied in order to generate a new
generation of solutions 3- VLSI integrated circuits description :
2.3.1 The reproduction 3.1 Introduction
It’s a process where each chain is copied according to An integrated circuit [ 6 3 is a device totally realized
the values of the function to optimize. This function on a semiconductor substract such as the silicon.
is called the adaptation function. In other words it Integrated circuit elementary components are gates,
means that chains with greater adaptation function interconnected with several level metal wires.
value are given a greater probability to contribute to Nowadays, due to their size and complexity, the
the following generation by creating descendents. design of state of art integrated circuits is only
This operator is an artificial version of the natural possible with the help of CAD software tools. These
selection where the adaptation is determined by the tools enable circuit designers to visualize, simulate
ability of individuals to survive. In our artificial and verify their circuits before their manufacture. For
environment, the adaptation function is the unique this reason, a memory representation of circuits, by
way to decide wether each chain will survive or not. the mean of a data structure is necessary in order to
In practice, this operator is implemented by the mean enable CAD programs to make the needed
of a biased wheel, where each chain of the current processings.
population has an associated place in the wheel with
an area proportional to its adaptation.

2.3.2 Crossover 3.2 VLSI circuits representation:

During this phase, new chains produced by the The most popular integrated circuit representation is
reproduction phase are first matched. Subsequently probably graph data structure. In this description,
pairs of chromosoms are crossed as follows : an graph nodes represent circuit gates, while graph
integer k which represents a chain location, is edges represent wires. With each node are associated
randomly choosen between 1 and L-1 (L is the size of two weights :
the chain). Two new chains are created by exchanging 0 ’The silicon area Si or size of each gate i.
all the genes between the (k+l) and L locations. 0 The gate delay Dj of each gate j.

Example : Lets consider the A1 and A2 chains 3.3 Problem’Position:

representing the initial population : The optimization problem performance of integrated
A1 = 011\0101 circuits, is generally stated as the total circuit area
A2 = 110\1110 minimisation, with user constraints on the total circuit
For k=3, the A’1 and A’2 resulting chains after a delay. The area determine a measure of the circuit
crossover are : cost. This problem can be summarized as follows :
A’1 = 01 1\1110 The different possible implementations of a circuit
A’2 = 110\0101 define what is called a design space, which is
constituted by a set of design points representing each

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 U The 12” International Conference on Microelectronics Tehran, Oct. 31- Nov. 2,2000

one a possible circuit implementation. Each point has

a set of values associated corresponding to the )t
different performance values.

The greater is a gate size, the faster is that gate or the Size
Of
smaller is its delay Di, and at the same time the higher Gate
is its cost. The problem consists of finding a 1
U1

compromise between these conflicting objectives (ie : Circuit Graphe chromosoms

speed and area). The total circuit area is generally
modeled as the sum of all component areas, while the
total circuit delay is the sum of the component delays Figure 1 : Coding: of the sizing problem
along the longest circuit path (or critical path).
When the crossover operator is applied, the result is a
fusion of two parts fi-om two different circuits that
(IMinwith D < user constraint gave good performances in a current circuit
generation (see fig. 2). This operation creates two
new circuits for the future generation. The mutation
where D = C Dj on the critical path. consists of creating one new circuit after a
S = C Si for all the circuit modification of the size of a given gate with a weak
probability though. This is done in order to explore
The problem can be transformed in an unconstrained new circuits. When all the operators have been
minimization problem with the mean of a penalization applied to the current generation, a new generation is
function regarding to the delay constraint, to obtain obtained. The last phase consists of evaluating each
the following evaluation function : new obtained circuit, using the evaluation function
previously described.
Min ( S - + h* (T - D) )
with h as a penalty factor

Problem variables, are in fact the individual size of

each circuit gate. The choice of each gate size is
performed in a cell library of available circuits.
Since the number of available cells is finite, the
problem is thus a combinatorial one.
This problem is called in the litterature “Gate sizing”
or ”cell selection problem” [ 2-3 1. Chan[2] first
demonstrated that this problem belongs to the NP-
Complete class, by showing a polynomial reduction of Figure 2 :Illustration of
the problem to the satisfiability problem. crossover circuit
Subsequently, Moon [ 3ldemonstrated that the
problem actually belongs to the NP class in the strong
sense.

3.4 Codinp and Application of the genetic 3.5 Algorithm implementation ’

owrators: Initially, a population (a set of circuits here) is

generated randomly. Let summarized the common
In the genetic algorithm framework, problem working scheme of an evolutionary algorithm in
parameters are coded as a chromosom. More pseudo-code notation, in figure 3 :
precisely for the gate sizing problem, a chromosom
represents a possible circuit implementation. Each
generate initial population Pt
chromosom gene represents the size of the
evaluate P t ;
corresponding gate (see fig. 1).
WHILE not terminate DO
select individuals :

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perform crossover and mutation; best served not by a single, monolithic machine but
evaluate new population P ' ;~ by a variety of distributed computing ressources,
END DO linked with high-speed networks using a system such
as PVM (Parallel Virtual Machine) [ 1 1. The
package allows a heterogeneous collection of
Fipure 3 : General Evolutionarv algorithm. computers linked together through a network to be
used as a'single large parallel computer. Thus large
As a final result, the algorithm usually yields the best computational problems can be solved more cost
individual which was encountered during the effectively by using the aggregate power and memory
evolution process. of many computers.

3.4 Tests We propose as an extension of our work, a

As test vehicles (see tablel), we have analyzed many master/slave scheme. The main program located on
different circuits, among them we have choosen the main machine, selects the chains and manage the
several combinatorial circuits from the ISCAS-85 genetic operators. Subsequently, the evaluation of
benchmarks [9]. Within the cell library, each cell is each chain is performed in parallel by the slave
available in two versions for the same logic. The first processors. Therefore each slave processor waits for
one is designed in BiCMOS technology while the chromosoms in order to compute the adaptation
second is designed in CMOS technology. BiCMOS function value. Finally the computed values are sent
technoloy is very attractive because of its high speed back to the main processor. The evaluation h c t i o n
compared to CMOS technology. On the other hand parallelisation [lo ] is motivated by the fact that
CMOS technology has smaller size (typically 3-5 computing the evaluation function of a population
times smaller) and better power consumption [ 8 1. requires about 95% of the total running time needed
The problem is : given a delay constraint, how to by the genetic algorithm program. This work is
choose for each circuit gate, the best cell version currently in adaptation.
(CMOS or BiCMOS) in order to achieve the timing
goal while maintaining a minimal area.
5 Conclusion

Circuit 1 1
I
of I
Num Num.of Speed Area
BiCMOS improv penalty
gates I gates I
1 I The .first obtained results indicates that the power of
the genetic algorithms is confirmed with their
application to a complex problem such as the gate
C1355 I 620 I 58 I 11,2% I 10,1% sizing of VLSI integrated circuits. The problem size,
the difficulty to model accurately all the
14,3% 30,8%
characteristics of integrated circuits, have been
C1908 442
efficiently handled using the genetic algorithm. This is
due to its great flexibility.
C432 40,9% 6,2% Besides, due to the intrinsec parrallel nature of the
C499 400 191,0?' 11,8% genetic alggrithm, its parallel version promises to
(2880 263 57 12,3% 10,5% substantially improve the time performances of the
Table1 algorithm .

The results of the tests show that : the achieved speed

improvements of the analyzed circuits, as compared to
their pure CMOS versions range from about 1 1 to 40
% while the area penalty is typically of 10 % with
running times of just few seconds.
The next tests will consist of optimizing circuits with
a library containing several versions for each cell
library.
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4 Futurework
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