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Combinational Circuits Program

The document describes several combinational logic circuits including basic gates, half and full adders, ripple carry adders, multiplexers, demultiplexers, encoders, decoders, array multipliers, and priority encoders. Code examples in Verilog are provided to demonstrate how to implement each of these circuits using basic logic gates like AND, OR, XOR, etc.

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chitra Manickam
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58 views14 pages

Combinational Circuits Program

The document describes several combinational logic circuits including basic gates, half and full adders, ripple carry adders, multiplexers, demultiplexers, encoders, decoders, array multipliers, and priority encoders. Code examples in Verilog are provided to demonstrate how to implement each of these circuits using basic logic gates like AND, OR, XOR, etc.

Uploaded by

chitra Manickam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Combinational Circuits

PROGRAM:
module gate(out,a,b);
output [6:0]out;
input a,b;
and (out[0],a,b);
or (out[1],a,b);
nand (out[2],a,b);
nor (out[3],a,b);
xor (out[4],a,b);
xnor (out[5],a,b);
not (out[6],a,b);
endmodule

OUTPUT:
HALF ADDER:
PROGRAM:
module halfadd(s,c,a,b);

output s,c;

input a,b;

xor (s,a,b);

and (c,a,b);

endmodule

OUTPUT:
HALF SUBTRACTOR
PROGRAM:
module hs(d,br,a,b);

output d,br;

input a,b;

wire abnot;

xor (d,a,b);

not (abnot,a);

and (br,abnot,b);

endmodule

OUTPUT:
FULL ADDER
PROGRAM:
module fa(sum,cout,a,b,cin);

output sum,cout;

input a,b,cin;

wire s1,c1,c2;

halfadd ha1(s1,c1,a,b);

halfadd ha2(sum,c2,s1,cin);

or (cout,c1,c2);

endmodule

OUTPUT:
RIPPLE CARRY ADDER
PROGRAM:
module rca(s0,s1,s2,s3,cout,a0,a1,a2,a3,b0,b1,b2,b3,cin);

output s0,s1,s2,s3,cout;

input a0,a1,a2,a3,b0,b1,b2,b3,cin;

wire c1,c2,c3;

fa fa0(s0,c1,a0,b0,cin);

fa fa1(s1,c2,a1,b1,c1);

fa fa2(s2,c3,a2,b2,c2);

fa fa3(s3,cout,a3,b3,c3);

endmodule

OUTPUT:
MULTIPLXER
PROGRAM:
mux8con:

module mux8con(out,i,s);

output out;

input[7:0]i;

input[2:0]s;

assign out=s[2]?(s[1]?(s[0]?i[7]:i[6]):(s[0]?i[5]:i[4])):(s[1]?(s[0]?i[3]:i[2]):(s[0]?i[1]:i[0]));

endmodule

OUTPUT:
DEMUX
PROGRAM:
module dem(out,s,in,e);
output [3:0]out;
input [1:0]s;
input in,e;
wire s1b,s0b;
not (s1b,s[1]);
not (s0b,s[0]);
and (out[0],s1b,s0b,in,e);
and (out[1],s1b,s[0],in,e);
and (out[2],s[1],s0b,in,e);
and (out[3],s[1],s[0],in,e);
endmodule

OUTPUT:
ENCODER
PROGRAM:
module encoo(o,i);

output [1:0]o;

input [3:0]i;

assign o[1]=i[3]|i[2];

assign o[0]=i[3]|i[1];

endmodule

OUTPUT:

DECODER
PROGRAM:
module decoo(y,x);

output[3:0]y;

input[1:0]x;

assign y[0]=~x[1]&~x[0];

assign y[1]=~x[1]&x[0];

assign y[2]=x[1]&~x[0];

assign y[3]=x[1]&x[0];

endmodule

OUTPUT:

ARRAY MULTIPLAYER
PROGRAM:
module arymul(a,b,p);

output [7:0]p;

input [3:0]a,b;

wire [15:0]t;

wire [11:1]c;

wire [7:1]s;

and(p[0],a[0],b[0]);

and(t[0],a[1],b[0]);

and(t[1],a[0],b[1]);

and(t[2],a[2],b[0]);

and(t[3],a[1],b[1]);

and(t[4],a[0],b[2]);

and(t[5],a[3],b[0]);

and(t[6],a[2],b[1]);

and(t[7],a[1],b[2]);

and(t[8],a[0],b[3]);

and(t[9],a[3],b[1]);

and(t[10],a[2],b[2]);

and(t[11],a[1],b[3]);

and(t[12],a[3],b[2]);

and(t[13],a[2],b[3]);

and(t[14],a[3],b[3]);

ha a1(p[1],c[1],t[0],t[1]);

fa a2(s[1],c[2],c[1],t[2],t[3]);
ha a3(p[2],c[3],s[1],t[4]);

fa a4(s[2],c[4],c[2],t[5],t[6]);

fa a5(s[3],c[5],c[3],t[7],s[2]);

ha a6(p[3],c[6],s[3],t[8]);

fa a7(s[5],c[7],c[4],c[5],t[9]);

fa a8(s[6],c[8],c[6],t[10],t[11]);

ha a9(p[4],c[9],s[5],s[6]);

fa a10(s[7],c[10],c[9],c[7],t[12]);

fa a11(p[5],c[11],c[8],s[7],t[13]);

fa a12(p[6],p[7],c[10],c[11],t[14]);

endmodule

OUTPUT:
PRIORITY ENCODER
PROGRAM:
module prien(x,y,d0,d1,d2,d3);

output x,y;

reg x,y;

input d0,d1,d2,d3;

always@(d0,d1,d2,d3)

begin

casex({d0,d1,d2,d3})

4'b1000:begin x=0;y=0; end

4'bx100:begin x=0;y=1; end

4'bxx10:begin x=1;y=0; end

4'bxxx1:begin x=1;y=1; end

endcase

end

endmodule

OUTPUT:

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