Combinational Logic

Md. Zubair Alam Emon

https://youtu.be/OKtkWVhKLXg
Combinational Circuits
• Consists of input variables, logic gates, and output variables
• Outputs are determined from the present combination of inputs.
• A combinational circuit with n input can be specified with 2n entry
truth table.
• It can also be described by a number of Boolean functions equivalent
to the number of output variables.
Boolean Function
• Analysis of a combinational circuit requires that we determine the
function that the circuit implements.
• Label all gate outputs with arbitrary symbols based on inputs or other
assigned symbols. Determine their Boolean function.
• Repeat the above process until output of the circuit is obtained.
• By repeated substitution of previously defined function, obtain the output
Boolean functions in terms of input variables
Truth Table
• To obtain the truth table directly from the logic diagram w/o going
through the derivation of Boolean function:
• Determine the number of input variables
• For n inputs, list binary numbers from 0 to 2n – 1 in a table
• Label the outputs of selected gates with arbitrary symbols
• Obtain the truth table for the outputs of those gates that are a function of the
input variables only
• Proceed to obtain the truth table for the outputs of those gates that are a
function of previously defined values until the columns for all outputs are
determined
TT w/o Boolean function
Design Procedure
• From the specification of the circuit, determine the required number
of inputs and outputs and assign a symbol to each.
• Derive the truth table that defines the required relationship between
inputs and outputs.
• Obtain the simplified Boolean functions for each output as a function
of the input variables.
• Draw the logic diagram and verify the correctness of the design.
Example: BCD to Excess-3
• Inputs: A, B, C, D
• Outputs: w, x, y, z
• Truth Table
• K-map
• Boolean Functions
w = A + BC + BD = A + B(C + D)
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
y = CD + C’D’ = CD + (C + D)’
z=D
TT

• #10-#15 decimals are don’t care for BCD

Logic diagram for BCD-to-excess-3 code converter
Binary Adder
• Half Adder performs the addition of 2-bits.
• Full Adder performs the addition of 3-bits.
• two significant bits and a previous carry.

Half Adder truth table

x y C S S = x’y+xy’
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0 C = xy
Full Adder
Full Adder Truth Table

x y z C S S = x’y’z + x’yz’ + xy’z’ + xyz

0 0 0 0 0 S  x yz
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0 C = xy + xz + yz
C  xy  xy' z  x' yz  xy  z ( x  y)
1 1 0 1 0
1 1 1 1 1
Full Adder
Block diagram of HA FA from HA

SH
x S x SF
HA HA CH HA
y C y z
CF

Block diagram of FA
x y Ai Bi

x
S
y FA C  z FA C  CIN FA COUT
z

S Si
Binary Adder (4-bit RCA)
A3 B3 A2 B2 A1 B1 A0 B0

COUT = C4 C3 C2 C1 C0 = CIN
FA FA FA FA

S3 S2 S1 S0

Ai Bi Ai Bi

Ci+1 Ci COUT CIN

FA
 FA

Si Si
Example
4-bit Adder (CLA)
• Carry propagation path is the longest delay path in RCA.
• Carry Look Ahead (CLA) adder help solve the delay problem by
generating the carry for all 4-bits at the same time.
• CLA utilizes carry generate (Gi) and carry propagate (Pi) which are
defined as:

Pi  Ai  Bi Gi  Ai Bi
• Sum (S) and Carry (C) for CLA can be defined using Gi and Pi as:

S i  Pi  Ci Ci 1  Gi  Pi Ci
CLA
CLA Generator
• Boolean functions for the carry outputs of each stage:

C0  input carry

C1  G0  P0 C0
C2  G1  P1C1  G1  P1G0  P1 P0C0
C3  G2  P2C2  G2  P2 G1  P2 P1G0  P2 P1 P0C0
C3  G2  P2C2  G2  P2 G1  P2 P1G0  P2 P1 P0C0

C2  G1  P1C1  G1  P1G0  P1 P0C0

C1  G0  P0 C0
C0  input carry
Co
Subtractor
• A – B = A + 2’s complement of B
= A + 1’s complement of B + 1 = A + B’ + 1

B3 B2 B1 B0 M
● ● ● ●

A3 A2 A1 A0

COUT = C4 C3 C2 C1
● FA FA FA FA
C0

S3 S2 S1 S0
over
flow
Overflow
• An addition overflows if the signs of the addends are the same and
the sign of the sum is different from the addend’s sign.
• OR, an addition overflows if the carry in and carry out of the sign bit
are different.
• Same rule applies to subtraction.
 BCD Adder
• Use 4-bit binary adder to add the digits of two BCD number.
• Result requires correction if the sum of the two digits is larger than 9
• Add six to make the sum comply with the BCD format.
• Why six ?

https://youtu.be/j6NkCO_WY98
Binary Multiplier
• Array Multiplier B1 B0
A0 A0
B1 B 0 + +
S S
A1 A 0 C C P0
B1 B0
B1A0 B0A0 A1 A1
+ +
B1A1 B0A1 S S
P1
C C

P3 P2 P1 P0
Adders

P3 P2
4-bit by 3-bit Multiplier
A0 ● ● ●
B3 B2 B1 B0
A1 ● ● ●
B3 B2 B1 B0

Addend Augend
A2 ● ● ●
B3 B2 B1 B0 4-bit adder

sum and output carry

Addend Augend

4-bit adder

sum and output carry

P6 P5 P4 P3 P2 P1 P0
Magnitude Comparator
• Magnitude comparator compares two numbers, A (A3A2A1A0) and B (B3B2B1B0), to
determine if A>B, A=B or A<B
• A = B if each positional bits of A and B are equal i.e. A3=B3 and A2=B2 and A1=B1
and A0=B0
xi = AiBi + Ai’Bi’ for i = 0, 1, 2, 3

• (A = B) = x3x2x1x0
• (A > B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1A0B0’
• (A < B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1A0’B0

https://youtu.be/1ee9VJktMq8
Comparator Circuit
A3
x3
B3

A2

B2
x2
A<B
A1

B1
x1
A>B
A0 x0
B0
A=B
Decoder
• Decoder converts binary information from n input lines to a maximum
of 2n unique output lines, each representing one of the minterms of
the n input variables.
• A decoder may operate with complemented or un-complemented
outputs.
• Decoders are usually called n-to-m line decoder where m ≤ 2n. For
example:
3-to-8 decoder, 2-to-4 decoder etc.
• Enable line(s) may be used to control outputs.
• When disabled, all outputs become high (1) or low (0)
 2-to-4 decoder without enable
D0

2x4
decoder D1

D2
Fig: Block diagram

D3
X Y Outputs
0 0 D0
Fig: Logic diagram
0 1 D1
1 0 D2
1 1 D3
Fig: Truth Table https://youtu.be/84hi88pH9pY
3-to-8 Decoder without enable
3-to-8 Decoder without enable
2-to-4 Decoder
B /Y3
A
/Y2

/Y1
E

/Y0

E B A /Y3 /Y2 /Y1 /Y0

1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
• 2-to-4 decoder with enable
0 1 0 1 0 1 1 using NAND gates
0 1 1 0 1 1 1
Decoder Expansion
Expanding 2-to-4 decoder to create a 3-to-8 decoder

MSB ?

A
B
/Y0 /Y4

/Y1 /Y5

/Y2 /Y6

/Y3 /Y7
Decoder Expansion
• When w=0, the top decoder is enabled and the other is disabled.
The bottom decoder outputs are all 0’s, and the top eight outputs
generate minterms 0000 to 0111.
• When w =1, the enable conditions are reversed: The bottom
decoder outputs generate minterms 1000 to 1111, while the outputs
of the top decoder are all 0’s.
Example
Implement F1, F2, F3 using a decoder with NAND gates and NAND or
AND gates connected to the decoder outputs.
F1=∑(2,4,7)
F2=∑(0,3)
F3=∑(0,2,3,4,7)
Decoder/Demultiplexer
• Demultiplexer circuit receives data from a single line and directs it to
one of 2n output lines controlled by n selection lines.
• A decoder with enable input can function as a demultiplexer.
• Enable is taken as data input line which is directed to one of 2n output lines
selected by n input variables of the decoder.
Logic by Decoders
• Implement combinational logic circuits using decoders.
• Use a 3-to-8 decoder to implement FA
• S(x, y, z) = Σ(1, 2, 4, 7)
• C(x, y, z) = Σ(3, 5, 6, 7)
Encoders
• Performs inverse operation of a decoder
• Encoder has ≤ 2n inputs and n outputs
Example: Octal-to-binary encoder:

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Encoder Example
• Boolean Functions of octal-to-binary encoder:
z = D 1 + D3 + D5 + D7
y = D 2 + D 3 + D 6 + D7
x = D 4 + D5 + D6 + D7
• Can be implemented with 3 OR gates.
• Only one input can be active at any given time.
• If two inputs are active simultaneously, the output
produces an undefined combination
• To resolve this ambiguity, encoder circuits must
establish an input priority to ensure that only one
input is encoded.
Priority Encoder
• Priority encoder includes D0
Inputs
D1 D2 D3 x
Outputs
y V
the priority function 0 0 0 0 X X 0
• Input having the highest 1 0 0 0 0 0 1

priority takes precedence X 1 0 0 0 1 1

X X 1 0 1 0 1
• 4-input priority encoder has X X X 1 1 1 1
a third output V (valid) D2 D3
• V = 0 when all inputs are D0 D1 00 01 11 10 00 01 11 10
invalid i.e. 0; it’s 1 otherwise. X 1 1 1 00 X 1 1 0

• D3 has highest priority 1 1 1 01 1 1 1 0

1 1 1 11 1 1 1 0
1 1 1 10 1 1 0

x = D 2 + D3 y = D3 + D1 D ‘2
Priority Encoder
x = D2 + D3
y = D3 + D1 D’2
V = D0 + D1 + D2 + D3

D3 ●
D2 ● y
D1 ●

● x

D0 V
Multiplexer (MUX)
• Has many (≤ 2n) input lines, only one output line and n selection lines.
• n selection lines select 1 of the (≤ 2n) input lines to be transferred to the single
output line.
• Selection lines choose which input will go to the output line
• Also known as the data selector.
• May operate with primed or unprimed inputs/outputs.
• They are usually called m-to-1 line MUX where m ≤ 2n, n is the number of select
lines. For example:
8-to-1 multiplexer, 2-to-1 multiplexer etc.
• Enable line(s) may be used to control outputs.
• When disabled, the output becomes inactive.
2-to-1 & 4-to-1 MUX
I0
Sel f
Sel
f 0 I0

I1 1 I1
f=I0Sel’+I1Sel

I0 S1 S0 f
S1
I1
0 0 I0
S0 f
0 1 I1
I2 1 0 I2
I3
1 1 I3
4-to-1 MUX
I0

I0
I1 ● I1
f
f I2
I2
● I3

I3 S1
●
S1 ● ● S0
S0 ●
Quadruple 2-to-1 MUX
E S B3 B2 B1 B0 A3 A2 A1 A0

Y3 Y2 Y1 Y0
Logic by MUX
Combinational logic circuits using MUX
– Use a 4-to-1 MUX to implement the function:
• F(x, y, z) = Σ(1, 2, 6, 7)

x y z F
4X1 MUX
0 0 0 0
F=z y S0
0 0 1 1
x S1
0 1 0 1
F = z’
0 1 1 0
F
1 0 0 0 z I0
F=0
1 0 1 0 z’ I1
1 1 0 1 0 I2
F=1
1 1 1 1 1 I3
Boolean Function implementation using MUX
• First n - 1 variables in the table are applied to the
selection inputs of the multiplexer.
• For each combination of the selection variables, we
evaluate the output as a function of the last variable. This
function can be 0, 1, the variable, or the complement of
the variable.
• These values are then applied to the data inputs in the
proper order.
Logic by MUX
Use an 8-to-1 MUX to implement the function:
• F(A, B, C, D) = Σ(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Three-State Gates
• A 3-state gate is a digital circuit that exhibits three states:
• Logic 0, logic 1 and high-impedance (hi-Z) states
• High-impedance state behaves like an open circuit.
• 3-state gates may perform any logic such as AND or NAND but most
common usage is buffer.
Three-State Gates
• Each 3-state gate has a control input i.e. Enable (En) signal in addition
to normal inputs/outputs.
• When En is asserted, 3-state gates acts normally i.e. output depends
on the inputs.
• When En is unasserted, output of 3-state gates become hi-Z
irrespective of the value of the inputs.
Three-State Buffers
• Output = LOW, HIGH, or Hi-Z.

• Different Flavors.
MUX using 3-State Gates
2-to-1 MUX 4-to-1 MUX

I0 ● Y I0 ● Y

I1 ●
I1
S ●
I2 ●

I3

S1 0
Select S0 2-to-4 1
decoder 2
Enable En 3
HDL
• Verilog module can be described in any of the following modeling
techniques:
• Gate level modeling using instantiation of primitive gates and user defined
modules.
• Dataflow modeling using continuous assignment statements with keyword
assign.
• Behavioral modeling using procedural assignment statements with keyword
always.
• Used to describe digital systems at a higher level of abstraction.
Gate Level Modeling
• Specifies circuit by its logic gates and their interconnections.
• Provides textual description of schematic diagram.
• Verilog recognizes 12 basic gates as predefined primitives.
and, nand, or, nor, xor, xnor, not, buf
4 are tri-state type: bufif1, bufif0, notif1, notif0
• Output is listed first, followed by inputs.
Primitive Gates
• Two more logic values other than 0 and 1
• Unknown (x)
• Unassigned or ambiguous value
• High Impedance (z)
• Unconnected wire or output of a disabled tri-state gate

and 0 1 x z or 0 1 x z xor 0 1 x z not input output

0 0 0 0 0 0 0 1 x x 0 0 1 x x 0 1

1 0 1 x x 1 1 1 1 1 1 1 0 x x 1 0

x 0 x x x x x 1 x x x x x x x x x

z 0 x x x z x 1 x x z x x x x z z
Example
// gate level description of a 2-to-4 decoder

module decoder_2to4 (Yb, A, B, E);

input A, B, E; Multiple bit widths
output [3:0] Yb; are called vectors
wire Abar, Bbar, Ebar;
First number is the
not n1 (Abar, A), MSB of the vector
n2 (Bbar, B),
n3 (Ebar, E);
Multiple instances
nand n4 (Yb[0], Abar, Bbar, Ebar), of same gate
n5 (Yb[1], A, Bbar, Ebar), separated by ,
n6 (Yb[2], Abar, B, Ebar),
n7 (Yb[3], A, B, Ebar);
endmodule
Hierarchical Design
// description of a half adder // description of a 4-bit adder
module halfadder (S, C, x, y);
input x, y; module _4bit_adder (S, C4, A, B, C0);
output S, C; input [3:0] A, B;
xor (S, x, y); input C0;
and (C, x, y); output [3:0] S;
endmodule output C4;

// description of a full adder wire C1, C2, C3;

module fulladder (S, C, x, y, z);
input x, y, z; fulladder FA0 (S[0], C1, A[0], B[0], C0),
output S, C; FA1 (S[1], C2, A[1], B[1], C1),
wire S1, D1, D2; FA2 (S[2], C3, A[2], B[2], C2),
halfadder HA1 (S1, D1, x, y), FA3 (S[3], C4, A[3], B[3], C3);
HA2 (S, D2, S1, z); endmodule
or g1 (C, D1, D2);
endmodule
Three State Gates
// description of a 2-to-1 MUX
module muxtri (OUT, A, B, Select); A ● out
input A, B, Select;
output OUT;
tri OUT;
bufif1 (OUT, A, Select); B
bufif0 (OUT, B, Select); Select ●
endmodule

Nets represent connections between hardware elements.

• wire and tri are examples of net data type

Net represents the data types of wire, wor, wand, tri, suply1 and supply0
wire takes values of 0 or 1 tri takes values of 0, 1 or z
wor is wired-OR wand is wired-AND
supply1 is power supply supply0 is ground
Verilog HDL Operators
Operator Operation Operator Operation
Symbol Symbol
Type Performed Type Performed
+ Addition >> Shift Right
– Subtraction Shift << Shift Left
Arithmetic * Multiplication {,} Concatenation
/ Division > Greater than
% Modulus < Less than
~ Complement == Equality
Logic
& AND != Inequality
(reduction) Relational
| OR Greater than
(bit-wise) >=
^ XOR or equal
! Negation Less than or
<=
Logical && AND equal
|| OR Conditional ?:
Dataflow Modeling
// description of a 2-to-4 decoder // description of a 4-bit adder
module decoder_2to4 (Yb, A, B, E); module _4bit_adder (S, C4, A, B, C0);
input A, B, E; input [3:0] A, B;
output [3:0] Yb; input C0;
assign Yb[0] = ~(~A & ~B & ~E), output [3:0] S;
Yb[1] = ~(~A & B & ~E), output C4;
Yb[2] = ~(A & ~B & ~E), assign S = A ^ B ^ C0,
Yb[3] = ~(A & B & ~E); C4 = A&B | B&C0 | C0&A;
endmodule endmodule

// description of a 4bit comparator

module magcomp (ALTB, AGTB, AEQB, A, B);
input [3:0] A, B; // description of a 2-to-1 MUX
output ALTB, AGTB, AEQB; module mux_2to1 (OUT, A, B, Select);
assign ALTB = (A < B), input A, B, Select;
AGTB = (A > B), output OUT;
AEQB = (A == B); assign OUT = Select ? A : B;
endmodule endmodule
// 4x1: assign y = s[1] ? (s[0] ? A : B) : (s[0] ? C : D);
 Behavioral Modeling
// description of a 2-to-1 MUX // description of a 4-to-1 MUX
module mux_2to1(A, B, select, Y); module mux_4to1 ( i0, i1, i2, i3, select, y);
input A, B, select; input i0, i1, i2, i3;
output Y; input [1:0] select;
reg Y; output reg y;
always @ (select or A or B) always @ (i0, i1, i2, i3, select)
if (select == 0) Y = A; case ( select )
else Y = B; 2’b00: y = i0;
endmodule 2’b01: y = i1;
2’b10: y = i2;
2’b11: y = i3;
endcase
endmodule

https://youtu.be/1ee9VJktMq8
Test Bench
• module testname.
• declare local reg and wire identifiers.
• instantiate the design module under test.
• generate stimulus using initial and always statements.
• display the output response.
• endmodule

Design Module Testbench Module

module circuit (C, A, B); module test_bench
input A, B; reg TA, TB;
output C; wire TC;
circuit cr (TC, TA, TB);
Test Bench
• initial block executes only once starting at time = 0 to provide
stimulus to the design module.
• Multiple statements within initial block are enclosed between
begin and end.
• repeat specifies a looping statement to repeat the next
statement n number of times after specified time units.

initial initial
begin begin
A = 0; B = 0; D = 3’b000;
#10 A = 1; repeat (7)
#20 A = 0; B = 1; #10 D = D + 3’b001;
end end
Test Bench System Tasks
• Built in system functions begin with the symbol $
• System tasks useful for display are:
$display
• display values of variables or strings and goes to next line
$write
• Same as $display w/o going to next line
$monitor
• Display variables whenever a value changes
$time
• Displays simulation time
$finish
• Terminates the simulation
Test Bench
// stimulus for mux_2to1
module testmux;
reg TA, TB, TS; // inputs for mux
wire Y; // output from mux Simulation log
// instantiate mux
mux_2to1 mx (TA, TB, TS, Y); select = 1 A = 0 B = 1 Y = 0 time = 0
initial select = 1 A = 1 B = 0 Y = 1 time = 10
begin select = 0 A = 1 B = 0 Y = 0 time = 20
TS = 1; TA = 0; TB = 1; select = 0 A = 0 B = 1 Y = 1 time = 30
#10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB = 1;
end
initial
$monitor(“select = %b A = %b B = %b Y = %b time = %0d”,
TS, TA, TB, Y, $time);
endmodule
Test Bench
Assuming design module for circuit of Fig 4-2 is defined as:
module analysis (F1, F2, A, B, C);

// testbench for ckt of Fig 4-2 Simulation log

module test_circuit;
reg [2:0] D; ABC = 000 F1 = 0 F2 = 0
wire F1, F2; ABC = 001 F1 = 1 F2 = 0
analysis fig42 (F1, F2, D[2], D[1], D[0]); ABC = 010 F1 = 1 F2 = 0
initial ABC = 011 F1 = 0 F2 = 1
begin ABC = 100 F1 = 1 F2 = 0
D = 3’b000; ABC = 101 F1 = 0 F2 = 1
repeat (7) ABC = 110 F1 = 0 F2 = 1
#10 D = D + 1’b1; ABC = 111 F1 = 1 F2 = 1
end
initial
$monitor (“ABC = %b F1 = %b F2 = %b”, D, F1, F2);
endmodule
HW
• 4.2, 4.4(b), 4.5, 4.6, 4.7, 4.9, 4.10, 4.12, 4.13, 4.14, 4.18, 4.19, 4.21,
4.22, 4.39, 4.41, 4.42, 4.44(b,d), 4.49, 4.53, 4.55, 4.57, 4.58

• 4-21, 4-31, 4-33~4-39, 4-41, 4-45, 4-46, 4-53, 4-58