Alternate Additional

LQFP100
WLCSP49
UFBGA100
UQFN48

Pin name

LQFP64
functions functions

I/O structure
Notes
Pin type
- VDD S - - -

1 VBAT S - - -
EVENTOU RTC_TAMP
2 C13 I/O (2) (3)
T, 1,
EVENTOU
3 C14- I/O (2) (3) OSC32_IN
T
EVENTOU OSC32_OU
4 C15- I/O (2) (3)
T T
PH0-
EVENTOU
5 OSC_IN I/O -4 OSC_IN
T
(PH0)
EVENTOU
6 PH1- I/O -4 OSC_OUT
T
EVENTOU
7 NRST I/O - -
T
VSSA/VRE
8 S - - -
F-
VDDA/VRE
9 S - - -
F+
USART2_ ADC1_IN0,
10 A0 I/O -5
CTS, WKUP

USART2_
11 A1 I/O - RTS, ADC1_IN1
TIM2_CH2,

USART2_T
12 A2 I/O - X, ADC1_IN2
TIM2_CH3,

USART2_
13 A3 I/O - RX, ADC1_IN3
TIM2_CH4,
FLQ

GSP
LQFP64L

BCF

AP1
40
090
UW

No
structure
10
UQFN48

type

te
s
Pin

14 A4 I/O - SPI1_NSS, ADC1_IN4

I/O

15 A5 I/O - SPI1_SCK, ADC1_IN5

SPI1_MIS
O,
16 A6 I/O - ADC1_IN6
TIM1_BKI
N,

SPI1_MOS
I,
17 A7 I/O - ADC1_IN7
TIM1_CH1
N,

TIM1_CH2
18 B0 I/O - N, ADC1_IN8
TIM3_CH3,
 TIM1_CH3
19 B1 I/O - N, ADC1_IN9
TIM3_CH4,

EVENTOU
20 B2 I/O - BOOT1
T

No
WLCSP49
LQFP100
UFBGA100
LQFP64

te
s
SPI2_SCK/
21 B10 I/O - -
I2S2_CK,

22 VCAP_1 S - - -
23 VSS S - - -
24 VDD S - - -

SPI2_NSS/
25 B12 I/O - -
I2S2_WS,

SPI2_SCK/
26 B13 I/O - -
I2S2_CK,

SPI2_MIS
O,
27 B14 I/O - -
I2S2ext_S
D,

SPI2_MOS RTC_REFI
28 B15 I/O -
I/I2S2_SD, N
FLQ

GSP
LQFP64L

BCF

AP1
40
090
UW

No
10

structure
UQFN48

type

te
s

I2C3_SCL,
Pin

29 A8 I/O - USART1_ -
CK,
I/O

I2C3_SMB
A, OTG_FS_V
30 A9 I/O -
USART1_T BUS
X,

USART1_
31 A10 I/O - RX, -
TIM1_CH3,

USART1_
CTS,
32 A11 I/O - -
USART6_T
X,

USART1_
RTS,
33 A12 I/O - -
USART6_
RX,

JTMS-
A13
SWDIO,
34 (JTMSSW I/O - -
EVENTOU
DIO)
T
35 VSS S - - -
36 VDD S - - -
 JTCK-
A14
SWCLK,
37 (JTCKSW I/O - -
EVENTOU
CLK)
T

JTDI,
38 A15 (JTDI) I/O - -
SPI1_NSS,
FLQ

GSP
LQFP64L

BCF

AP1
40
090
UW

No
10

structure
UQFN48

JTDO-
type

te
s
Pin
B3 (JTDO-
39 I/O - SWO, -
SWO)
SPI1_SCK,

I/O
NJTRST,
B4
40 I/O - SPI1_MIS -
(NJTRST)
O,
SPI1_MOS
41 B5 I/O - -
I,

I2C1_SCL,
42 B6 I/O - USART1_T -
X,

I2C1_SDA,
43 B7 I/O - USART1_ -
RX,

44 BOOT0 I - - VPP

I2C1_SCL,
45 B8 I/O - -
TIM4_CH3,

SPI2_NSS/
46 B9 I/O - -
I2S2_WS,

47 VSS S - - -
48 VDD S - - -
SP49
LQF
UFBG
WLC
P10
LQFP64
A100
0
 Table 7. Legend/abbreviations used in the pinout table
Abbreviati
Name Definition
on
below the pin name,
Pin name the pin function during
and after reset is the
S Supply pin
Input only
Pin type I
pin
Input/
I/O
output pin

5 V tolerant
FT
I/O

Dedicated
B
BOOT0 pin
I/O
structure
Bidirection
al reset pin
with
NRST
embedded
weak pull-
up resistor
specified by a note, all
Notes I/Os are set as floating
inputs during
Functions and after
selected
Alternate
through GPIOx_AFR
functions
registers
Functions directly
Additional selected/enabled
functions through peripheral
registers
finitions
Pin # Pin Name Type Alternate Function Additional Function
1 VBAT S -
2 C13 I/O EVENTOUT, RTC_TAMP1,
3 C14 I/O EVENTOUT, OSC32_IN
4 C15 I/O EVENTOUT, OSC32_OUT

PH0-OSC_IN
EVENTOUT,
(PH0)
5 I/O
6 PH1- I/O EVENTOUT,
7 NRST I/O EVENTOUT,

8 VSSA/VREF- S
VDDA/VREF+
9 S
10 A0 I/O USART2_CTS, ADC1_IN0, WKUP
USART2_RTS,
A1 ADC1_IN1
11 I/O TIM2_CH2,
USART2_TX,
A2 ADC1_IN2
12 I/O TIM2_CH3,
USART2_RX,
A3 ADC1_IN3
13 I/O TIM2_CH4,
14 A4 I/O SPI1_NSS, ADC1_IN4
15 A5 I/O SPI1_SCK, ADC1_IN5
SPI1_MISO,
A6 ADC1_IN6
16 I/O TIM1_BKIN,
SPI1_MOSI,
A7 ADC1_IN7
17 I/O TIM1_CH1N,
TIM1_CH2N,
B0 ADC1_IN8
18 I/O TIM3_CH3,
TIM1_CH3N,
B1 ADC1_IN9
19 I/O TIM3_CH4,
20 B2 I/O EVENTOUT BOOT1
21 B10 I/O SPI2_SCK/I2S2_CK, -
22 VCAP_1 S - -
23 VSS S - -
24 VDD S - -
25 B12 I/O SPI2_NSS/I2S2_WS,
26 B13 I/O SPI2_SCK/I2S2_CK,
SPI2_MISO,
B14 I/O
27 I2S2ext_SD,

B15 I/O SPI2_MOSI/I2S2_SD, RTC_REFIN

28
I2C3_SCL,
A8 I/O
29 USART1_CK,
I2C3_SMBA,
A9 I/O OTG_FS_VBUS
30 USART1_TX,
USART1_RX,
A10 I/O
31 TIM1_CH3,
USART1_CTS,
A11 I/O
32 USART6_TX,
 USART1_RTS,
A12 I/O
33 USART6_RX,

A13 JTMS-SWDIO,
I/O
(JTMSSWDIO) EVENTOUT
34
35 VSS S -
36 VDD S -

A14 JTCK-SWCLK,
I/O
(JTCKSWCLK) EVENTOUT
37
38 A15 (JTDI) I/O JTDI, SPI1_NSS,
JTDO-SWO,
B3 (JTDO-SWO) I/O
39 SPI1_SCK,
40 B4 (NJTRST) I/O NJTRST, SPI1_MISO,
41 B5 I/O SPI1_MOSI,
I2C1_SCL,
B6 I/O
42 USART1_TX,
I2C1_SDA,
B7 I/O
43 USART1_RX,
44 BOOT0 I - VPP

B8 I2C1_SCL, TIM4_CH3,
45 I/O
46 B9 I/O SPI2_NSS/I2S2_WS,
47 VSS S -
48 VDD S -

Name Abbreviation Definition

brackets below the pin
Pin name name, the pin function during
and after reset is the same
S Supply pin
Input only
Pin type I
pin
Input/
I/O
output pin

5 V tolerant
FT
I/O

Dedicated
B
BOOT0 pin
I/O
structure
Bidirection
al reset pin
with
NRST
embedded
weak pull-
up resistor
 by a note, all I/Os are set as
Notes
floating inputs during and
Alternate Functions selected through
functions GPIOx_AFR registers
Additional Functions directly
selected/enabled through
functions peripheral registers
 PH0-
OSC_IN EVENTOUT
5 (PH0) I/O
6 PH1- I/O EVENTOUT
7 NRST I/O EVENTOUT
VSSA/VRE
8 F- S
VDDA/VRE
9 F+ S
A0 USART2_CTS
10 I/O
A1
11 I/O USART2_RTS TIM2_CH2
A2
12 I/O USART2_TX TIM2_CH3
A3 USART2_RX
13 I/O TIM2_CH4
A4
14 I/O SPI1_NSS
A5 SPI1_SCK
15 I/O
A6
16 I/O SPI1_MISO TIM1_BKIN
A7
17 I/O SPI1_MOSI TIM1_CH1N
29 A8 I/O USART1_CK I2C3_SCL

A9 I/O I2C3_SMBA
30 USART1_TX
31 A10 I/O USART1_RX TIM1_CH3
32 A11 I/O USART1_CTS USART6_TX
A12 I/O USART1_RTS
33 USART6_RX
A13
(JTMSSW I/O JTMS-SWDIO
34 DIO) EVENTOUT
A14
(JTCKSW I/O JTCK-SWCLK
37 CLK) EVENTOUT
38 A15 (JTDI) I/O JTDI SPI1_NSS
23 VSS S GND
 5V
GND
3.3
-
1 VBAT S
EVENTOUT RTC_TAMP1,
2 C13 I/O
ADC1_IN0,
EVENTOUT OSC32_IN
WKUP 3 C14 I/O
ADC1_IN1
4 C15 I/O EVENTOUT OSC32_OUT
ADC1_IN2 B15 I/O SPI2_MOSI RTC_REFIN
28 I2S2_SD
ADC1_IN3 B14 I/O SPI2_MISO
27 I2S2ext_SD
ADC1_IN4 B13 I/O SPI2_SCK
26 I2S2_CK
ADC1_IN5 B12 I/O SPI2_NSS
25 I2S2_WS
ADC1_IN6 B10
21 I/O SPI2_SCK I2S2_CK
ADC1_IN7 B9
46 I/O SPI2_NSS I2S2_WS
45 B8 I/O I2C1_SCL TIM4_CH3
OTG_FS_V
B7 I/O I2C1_SDA
BUS 43 USART1_RX
42 B6 I/O I2C1_SCL USART1_TX
41 B5 I/O SPI1_MOSI
B4
40 (NJTRST) I/O NJTRST SPI1_MISO
B3 (JTDO-
I/O JTDO-SWO
SWO)
39 SPI1_SCK -

B2 EVENTOUT BOOT1
20 I/O
19 B1 I/O TIM1_CH3N TIM3_CH4 ADC1_IN9
18 B0 I/O TIM1_CH2N TIM3_CH3 ADC1_IN8
Legend
Power
Ground

CPU Pin

Pin Name

Control

Analog

Timer & Channel

USART

SPI

I2S

I2C

Board Hardware