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Interleave Memory

1. Memory interleaving is a technique that interleaves successive memory addresses across multiple memory banks. This allows one bank to service a memory request while another bank recovers from a prior request. 2. With interleaving, when the first memory bank is sending data to the CPU, the second bank will receive the address from the CPU, and vice versa. This reduces the delay between successive memory accesses. 3. Interleaving can be implemented at different levels of memory organization, including at the rank, chip, or bank level. Bank-based interleaving divides the main memory into banks and interleaves memory addresses across the banks.

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332 views2 pages

Interleave Memory

1. Memory interleaving is a technique that interleaves successive memory addresses across multiple memory banks. This allows one bank to service a memory request while another bank recovers from a prior request. 2. With interleaving, when the first memory bank is sending data to the CPU, the second bank will receive the address from the CPU, and vice versa. This reduces the delay between successive memory accesses. 3. Interleaving can be implemented at different levels of memory organization, including at the rank, chip, or bank level. Bank-based interleaving divides the main memory into banks and interleaves memory addresses across the banks.

Uploaded by

Joem Gutierrez
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© © All Rights Reserved
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1.

memory interleaving is a technique to Interleave successive memory addresses across


multiple memory units. This consecutive cause in the address space at assign assigned to
different memory banks. After a memory chips access to usually there's a delay before that chip
can be access again. This delay is long enough to put a v state in a fast CPU. However, with
memory interleaving as a subsequent address are Interleave among the memory units each unit
take tons to handle the request from CPU while the other is recovering from the access.
2. So, when the first memory is sending data to the CPU. The second unit will receive the
address from CPU similarly with the second unit will send data the first unit can be exist again.
As a result, the delivery between access in the subsequent word is reduced considerably. 
3. Before we begin into memory interleaving let's have a quick look at the memory units. The
main memory comprises of these kinds of sticks for a DIMM based SDRAM and the front view
and back view the forms their DIMM that is Dual In-line Memory Module. 
4.Collection of chips on each side of state is known as rank and these ranks consist of DRAM
Chips. 
5. Each DRAM Chips can further be divided into memory banks in these memory banks are the
two-dimension array that consist of rows and columns. The intersection of row and column is
called cell. where data is being stored in a matrix form. The memory interleaving can be
implemented at various levels of memory organization they can be ranked based memory
interleaving, chip based memory interleaving.
6. All mu there are channel based memory in delivering. 
7. But the most basic unit from there, this memory interleaving started their with banks. For the
rest of this video I'll be focusing on bank-based memory interleaving. 
8. So in bank-based memory interleaving the main memory is divided into memory banks and
the abstract Architecture will look like this, where in the memory addresses are interleaved
across these banks. 
9. Now let's look at an example to understand the difference between non interleave memory
and interleave memory access. As you can see it in non-interleaved memory access the
memory addresses are access only when the previous memory access is completed, however
in interleave memory access the access of subsequent memory addresses interleave across
banks can be overlap. As the result the overall access time for same amount of data is reduced
considerably.
10. Let’s understand this by considering cycle DIMMS. 1 cycle to send address to DRAM. 5
cycles to access one word from DRAM and 1 cycle to return the data. To fetch one word from
DRAM it would require seven clock cycles and shown in this calculation. So, in non-interleaved
memory access if you are fetching forwards from DRAM it would take twenty-eight clocks cycle
like that shown you. 
11. However, the same forward fetch in an interleaved memory access would take only ten
clock cycles this shows that the access time is reduced considerably in an interleaved access.
12. Now the next concept to understand this is n -Way Memory Interleaving, the way of memory
interleaving is determined by the number of the units or banks in which the main memory gets
divided for example the first figure shows two way interleaving as memory is divided into two
banks the second one is a 4 – way memory interleaving this the memory divided into four banks
similarly for n – way interleaving the whole main memory will be divided into n banks.
13. Now let's see the different types of memory Interleaving there are two types of memory
interleaving lower order interleaving and High order interleaving. In low interleaving the least
significant bits of the of the address is used to select the bank and higher the bit are used to
select the word in the selected bank in this type of interleaving subsequent memory addresses
as cleared it cross the banks. 
14. However, in higher interleaving the most significant bits of the address are used is used to
select a banks and low order bits are used to select a word in the selected bank. in this time of
interleaving block of successive at memory addresses are interleave across banks.

15. now let's look at the types in detail with the help of an example consider that the memory is
divided into four banks sure near being a law order intensely subsequent memory addresses in
billion because the banks so when the CBO is in the address the law because of the address
was selected back in the remaining higher bit then select the work that needs to be fixed in this
example. As there are for banks so do bits will be required to select the bank. The law order but
zero zero in the first game then select bank zero. And the remaining bids for select award within
bank zero. So after the forsaken the state of the system will look like this. In subsequent cycles
the fading of data and the selection of banking work over back for higher intelligence that's
going to do the same for bandwidth with the only difference that block of successive memory
addresses in Delhi gross the banks. So when the CBO will send address the more significant
billboards will select the bank should. The image via the address that is zero zero then select
bank zero and the remaining law order Bates will select the word from the selected banks here
in an example. Hi Lauren delivering is best suited for C. shared memory systems when the. In
the first process is accessing a bank. And the same guy. In a different server can access into
the bank. Vantage's and it's a. For lowering delivery in both more visits from sequence in
location can overlap latency spirited with accessing each work as we have seen in the example
really dealt with the clock seconds also in law order delivery as sequence addresses at NW but
don't know sharing between banks is a jeep. And its disadvantages are not sequential V. V.
million bank and flicked. And failure of single bank milieu to failure and died. And I don't have
the advantages of higher order. But I listen as possible since she CBA was in shared memory
system access is banks simultaneously. It also provides better resilience to entire system
feeling. And its disadvantages it does not support by plane block access of continuous many
locations. So can we combine border types of intelligence for the performance. Dances yes hi
all day delivering. Live in the provide budget balances and lowering the living can be done and
the link bank living over lack leading sees for secret children to conclude some of the key points
the machine delivering technique is using main memory in logger into living memory conflict
arise if subsequent memory address exes based CB reason the same back with a Scottish bank
on that conflict. For shared memory the pilot. Memory configured arise if my double process of
trying to seem back. In currently in memory technologies lady DR memory indenting is avaliable
as optional techniques basically for both more a wider memory advisor cash was considered as
I. Finally these are the differences and I would also like to thank my professors optical stuff to
share for his explanation during the plus and that's all folks for any further queries or feedback
you can reach me at ari how good I'd be exaggerating thank you.

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