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Topic:: Continous and Procedural Assignment and Operators

This document provides an overview of continuous and procedural assignment operators in Verilog. It discusses continuous assignment statements, which represent logic derived from an expression driving a net. It also covers blocking and non-blocking procedural assignments, with blocking assignments using = and non-blocking using <=. The document describes various arithmetic, relational, equality, logical, and shift operators in Verilog.

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122 views11 pages

Topic:: Continous and Procedural Assignment and Operators

This document provides an overview of continuous and procedural assignment operators in Verilog. It discusses continuous assignment statements, which represent logic derived from an expression driving a net. It also covers blocking and non-blocking procedural assignments, with blocking assignments using = and non-blocking using <=. The document describes various arithmetic, relational, equality, logical, and shift operators in Verilog.

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Effecure Healthcare
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TOPIC: Continous and procedural

assignment and operators


COURSE: VLSI design using Verilog
CHAPTER: - Three

PPT SL.NO.: - 01

VERSION: - 01 LAST UPDATED ON: 04/09/2020

Presentation By: Pragya Sharma


Continuous Assignment Statement
 A continuous assignment statement represents, in hardware,
logic that is derived from the expression on RHS of
assignment statement driving the net that appears of LHS of
assignment.
module continuous(sin,sout);
input sin;
output sout;
assign sout=~sin; //continuous assingnment
endmodule
Procedural Assignment Statement
 A procedural assignment statement represents, in hardware,
logic that is derived from the expression on RHS of
assignment statement driving the variable that appears of
LHS of assignment. The procedural assignments can appear
within an always statement.
 Two kinds of procedural assignments:
 Blocking
 Non-Blocking
Blocking Procedural Assignment
 A blocking statement must be executed before the execution
of the statements that follow it in a sequential block.
 Blocking assignment statements are assigned using =.
However, this will not prevent execution of statement that run
in parallel.
module block_nonblock();
reg a, b, c;

// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
endmodule
Non-Blocking Procedural Assignment

 Non-blocking assignments allows assignments to be


scheduled without blocking the execution of following
statements and is specified by <= symbol.
module block_nonblock();
reg d , e, f ;

// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end

endmodule
Arithmetic
There are five arithmetic operators in Verilog.
module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);
input [2:0] A, B;
output [3:0] Y1;
output [4:0] Y3;
output [2:0] Y2, Y4, Y5;
reg [3:0] Y1;
reg [4:0] Y3;
reg [2:0] Y2, Y4, Y5;
always @(A or B)
begin
Y1=A+B;//addition
Y2=A-B;//subtraction
Y3=A*B;//multiplication
Y4=A/B;//division
Y5=A%B;//modulus of A divided by B
end
endmodule
Relational
Relational operators compare two operands and returns an indication of
whether the compared relationship is true or false. The result of a comparison
is either 0 or 1. It is 0 if the comparison is false and 1 if the comparison is true.
module Relational (A, B, Y1, Y2, Y3, Y4);
input [2:0] A, B;
output Y1, Y2, Y3, Y4;
reg Y1, Y2, Y3, Y4;
always @(A or B)
begin
Y1=A<B;//less than
Y2=A<=B;//less than or equal to
Y3=A>B;//greater than
if (A>B)
Y4=1;
else
Y4=0;
end
endmodule
Equality and inequality
Equality and inequality operators are used in exactly the same way as
relational operators and return a true or false indication depending on
whether any two operands are equivalent or not.
module Equality (A, B, Y1, Y2, Y3);
input [2:0] A, B;
output Y1, Y2;
output [2:0] Y3;
reg Y1, Y2;
reg [2:0] Y3;
always @(A or B)
begin
Y1=A==B;//Y1=1 if A equivalent to B
Y2=A!=B;//Y2=1 if A not equivalent to B
if (A==B)//parenthesis needed
Y3=A;
else
Y3=B;
end
endmodule
Logical
Logical comparison operators are used in conjunction with relational and
equality operators as described in the relational operators section and
equality and inequality operators section. They provide a means to perform
multiple comparisons within a a single expression.
module Logical (A, B, C, D, E, F, Y);
input [2:0] A, B, C, D, E, F;
output Y;
reg Y;
always @(A or B or C or D or E or F)
begin
if ((A==B) && ((C>D) || !(E<F)))
Y=1;
else
Y=0;
end
endmodule
Shift
Shift operators require two operands. The operand before the operator
contains data to be shifted and the operand after the operator contains the
number of single bit shift operations to be performed. 0 is being used to fill
the blank positions.
module Shift (A, Y1, Y2);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B=3; reg [7:0] Y1, Y2;
always @(A)
begin
Y1=A<<B; //logical shift left
Y2=A>>B; //logical shift right
end
endmodule
Thank you!

www.nielit.gov.in/haridwar

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