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    Mealy and Moore Machines: Topic

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    This document provides information about Mealy and Moore machines. It defines Mealy machines as finite state machines where the outputs depend on both the present input and state. Moore machines are defined as machines where the outputs depend only on the present state. It includes state diagrams, state tables, and examples to illustrate the differences between Mealy and Moore machines.

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    Mealy and Moore Machines: Topic

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    This document provides information about Mealy and Moore machines. It defines Mealy machines as finite state machines where the outputs depend on both the present input and state. Moore machines are defined as machines where the outputs depend only on the present state. It includes state diagrams, state tables, and examples to illustrate the differences between Mealy and Moore machines.

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    This document provides information about Mealy and Moore machines. It defines Mealy machines as finite state machines where the outputs depend on both the present input and state. Moore machines are defined as machines where the outputs depend only on the present state. It includes state diagrams, state tables, and examples to illustrate the differences between Mealy and Moore machines.

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    © All Rights Reserved
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    41 views12 pages

    Mealy and Moore Machines: Topic

    Uploaded by

    Effecure Healthcare
    This document provides information about Mealy and Moore machines. It defines Mealy machines as finite state machines where the outputs depend on both the present input and state. Moore machines are defined as machines where the outputs depend only on the present state. It includes state diagrams, state tables, and examples to illustrate the differences between Mealy and Moore machines.

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    of 12

    TOPIC: Mealy and Moore Machines

    COURSE: VLSI design using Verilog


    CHAPTER: - Eight

    PPT SL.NO.: - 01

    VERSION: - 01 LAST UPDATED ON:


    18/09/2020

    NIELI Presentation By: Pragya


    Finite State Machines
    ◻ Synchronous sequential circuits change affect their states for
    every positive or negative transition of the clock signal based on
    the input. So, this behavior of synchronous sequential circuits
    can be represented in the graphical form and it is known as
    state diagram.
    ◻ A synchronous sequential circuit is also called as Finite State
    Machine FSM, if it has finite number of states. There are two
    types of FSMs.
    Mealy State Machine
    ⮚

    Moore State Machine


    ⮚
    Mealy Machines
    ◻ A Finite State Machine is said to be Mealy state machine, if
    outputs depend on both present inputs & present states. The
    block diagram of Mealy state machine is shown in the following
    figure.
    Mealy Machines
    ◻ The state diagram of Mealy state machine is shown in the
    following figure. In the given figure, there are three states, namely
    A, B & C. These states are labelled inside the circles & each circle
    corresponds to one state.
    ◻Transitions between these states are represented with directed

    lines. Here, 0/0, 1/0 & 1/1 denotes input/output. In the above
    figure, there are two transitions from each state based on the value
    of input, x.
    Mealy Machines
    ◻ The state table of a Mealy Machine is shown below −
    Next state
    Present
    input = 0 input = 1
    state
    State Output State Output
    →a b x1 c x1
    b b x2 d x3
    c d x3 c x1
    d d x3 d x2

    /x2

    The state diagram of the above Mealy Machine is − /x3


    /x1

    a /x3 d
    /x1 c
    /x1
    Example of Mealy Machine
    module mealy( clk, rst, inp, outp); 2'b01: begin
    input clk, rst, inp; if( inp ) begin
    state <= 2'b00;
    output outp;
    outp <= 1;
    reg [1:0] state; end
    reg outp; else begin
    always @( posedge clk, posedge rst state <= 2'b10;
    ) begin outp <= 0;
    if( rst ) begin end
    end
    state <= 2'b00;
    2'b10: begin
    outp <= 0; if( inp ) begin
    end state <= 2'b01;
    else begin outp <= 0;
    case( state ) end
    2'b00: begin else begin
    state <= 2'b00;
    if( inp ) begin
    outp <= 1;
    state <= 2'b01; end
    outp <= 0; end
    end default: begin
    else begin state <= 2'b00;
    state <= 2'b10; outp <= 0;
    end
    outp <= 0;
    endcase
    end end
    end end
    endmodule
    Moore Machine
    ◻A Finite State Machine is said to be Moore state machine, if
    outputs depend only on present states.
    ◻The block diagram of Moore state machine is shown in the

    following figure.
    Moore Machine
    ◻In the given figure, there are four states, namely A, B, C & D.
    These states and the respective outputs are labelled inside the
    circles. Here, only the input value is labeled on each transition. In
    the given figure, there are two transitions from each state based on
    the value of input, x.
    Moore Machine
    In the moore machine shown in Figure, the output is repr
    esentedwith each input state separated by /. The length
    of output for a moore machine is greater than input by 1.
    Input: 11
    Transition: δ (q0,11)=> δ(q2,1)=>q2
    Output: 000 (0 for q0, 0 for q2 and again 0 for q2)
    Moore Machine
    ◻ The state table of a Moore Machine is shown below −
    Next State
    Present state Output
    Input = 0 Input = 1
    →a b c x2
    b b d x1
    c c d x2
    d d d x3

    The state diagram of the above Moore


    Machine is −
    Example of Moore Machine
    2'b10:
    module fsm( clk, rst, inp, outp); begin
    input clk, rst, inp; if( inp ) state <= 2'b01;
    output outp; else state <= 2'b11;
    reg [1:0] state; end
    reg outp; 2'b11:
    always @( posedge clk, posedge rst begin
    ) if( inp ) state <= 2'b01;
    begin else state <= 2'b10;
    if( rst ) end
    state <= 2'b00; endcase
    else end
    begin end
    case( state ) always @(posedge clk, posedge rst)
    2'b00: begin
    begin if( rst )
    if(inp) state <= 2'b01; outp <= 0;
    else state <= 2'b10; else outp <= 1;
    end end
    2'b01: endmodule
    begin
    if( inp ) state <= 2'b11;
    else state <= 2'b10;
    end
    Thank you!

    NIELI www.nielit.gov.in/haridwar

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