Six Channel, 20-Bit Codec: Features Description
Six Channel, 20-Bit Codec: Features Description
Six Channel, 20-Bit Codec: Features Description
Voltage
PDN Control Port Reference CMOUT
SDIN1
Digital Filters
Serial Audio Data Interface
Output Stage
ADC
OVL AIN1L
MUX Left
Input
Gain
AIN1R
Input MUX
ADC
Right AIN2L
ADC AIN2R
DEM DEM AIN3L
Clock Osc/ AIN3R
Auxiliary Input
Divider AGND1
AGND2
CLKOUT XTI XTO HOLD DATAUX LRCKAUX SCLKAUX DGND1 DGND2
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ANALOG CHARACTERISTICS ................................................................................................ 4
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT........................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ..................................................................... 10
DIGITAL CHARACTERISTICS ............................................................................................... 10
2. FUNCTIONAL DESCRIPTION ............................................................................................... 12
2.1 Overview .......................................................................................................................... 12
2.2 Analog Inputs ................................................................................................................... 12
2.2.1 Line Level Inputs ................................................................................................. 12
2.2.2 Adjustable Input Gain .......................................................................................... 13
2.2.3 High Pass Filter ................................................................................................... 13
2.3 Analog Outputs ................................................................................................................ 13
2.3.1 Line Level Outputs .............................................................................................. 13
2.3.2 Output Level Attenuator ...................................................................................... 14
2.4 Clock Generation ............................................................................................................. 14
2.4.1 Clock Source ....................................................................................................... 14
2.4.2 Master Clock Output ........................................................................................... 14
2.4.3 Synchronization ................................................................................................... 14
2.5 Digital Interfaces .............................................................................................................. 15
2.5.1 Audio DSP Serial Interface Signals ..................................................................... 15
2.5.2 Audio DSP Serial Interface Formats ................................................................... 15
2.5.3 Auxiliary Audio Port Signals ................................................................................ 15
2.5.4 Auxiliary Audio Port Formats ............................................................................... 15
2.6 Control Port Signals ......................................................................................................... 17
2.6.1 SPI Mode ............................................................................................................ 17
2.6.2 I2C® Mode ........................................................................................................... 18
2.6.3 Control Port Bit Definitions .................................................................................. 18
2.7 Power-up/Reset/Power Down Mode ................................................................................ 18
2.8 DAC Calibration ............................................................................................................... 19
2.9 De-Emphasis ................................................................................................................... 19
2.10 Hold Function ................................................................................................................. 19
2 DS281PP2
CS4227
LIST OF FIGURES
Figure 1. Audio Ports Master Mode Timing..................................................................................... 7
Figure 2. Audio Ports Slave Mode and Data I/O Timing ................................................................. 7
Figure 3. Control Port SPI Mode ..................................................................................................... 8
Figure 4. Control Port I2C Mode...................................................................................................... 9
Figure 5. Recommended Connection Diagram............................................................................. 11
Figure 6. Optional Line Intput Buffer ............................................................................................. 12
Figure 7. Butterworth Filters.......................................................................................................... 13
Figure 8. Audio DSP and Auxiliary Port Data Input Formats ........................................................ 16
Figure 9. Audio DSP Port Data Output Formats ........................................................................... 16
Figure 10. One Data Line Modes .................................................................................................. 16
Figure 11. Control Port Timing, SPI Mode .................................................................................... 17
Figure 12. Control Port Timing, I2C® Mode................................................................................... 18
Figure 13. De-emphasis Curve. .................................................................................................... 19
Figure 14. Suggested Layout Guideline........................................................................................ 20
Figure 15. 20-bit ADC Filter Response ......................................................................................... 21
Figure 16. 20-bit ADC Passband Ripple ....................................................................................... 21
Figure 17. 20-bit ADC Transition Band ......................................................................................... 21
Figure 18. DAC Frequency Response .......................................................................................... 21
Figure 19. DAC Passband Ripple ................................................................................................. 21
Figure 20. DAC Transition Band ................................................................................................... 21
LIST OF TABLES
Table 1. Single-ended vs Differential Input Pin Assignments .............................................................. 12
Table 2. High Pass Filter Characteristics ............................................................................................ 13
Table 3. DSP Serial Input Ports........................................................................................................... 15
DS281PP2 3
CS4227
ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = +5 V; Full Scale Input Sine wave, 997 kHz;
Fs = 44.1 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figure 5; SPI mode,
Format 3, unless otherwise specified.)
CS4227-KQ CS4227-BQ
Parameter Symbol Min Typ Max Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified.
ADC Resolution Stereo Audio channels 16 - 20 16 - 20 Bits
Mono channel 16 - 20 16 - 20 Bits
Total Harmonic Distortion THD 0.003 - 0.003 - %
Dynamic Range (A weighted, Stereo) 92 95 - 90 93 - dB
(unweighted, Stereo) - 92 - - 90 - dB
(A weighted, Mono) 89 - - 87 - - dB
Total Harmonic -1 dB, Stereo (Note 1) THD+N - -88 -82 - -86 -80 dB
Distortion + Noise -1 dB, Mono (Note 1) - - -72 - - -70 dB
Interchannel Isolation - 90 - - 90 - dB
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Programmable Input Gain Span 8 9 10 8 9 10 dB
Gain Step Size 2.7 3 3.3 2.7 3 3.3 dB
Offset Error (with high pass filter) - - 0 - - 0 LSB
Full Scale Input Voltage (Single Ended): 0.90 1.0 1.10 0.90 1.0 1.10 Vrms
Gain Drift - 100 - - 100 - ppm/°C
Input Resistance (Note 2) 10 - - 10 - - kΩ
Input Capacitance - - 15 - - 15 pF
CMOUT Output Voltage - 2.3 - - 2.3 - V
A/D Decimation Filter Characteristics
Passband (Note 3) 0.02 - 20.0 0.02 - 20.0 kHz
Passband Ripple - - 0.01 - - 0.01 dB
Stopband (Note 3) 27.56 - 5617.2 27.56 - 5617.2 kHz
Stopband Attenuation (Note 4) 80 - - 80 - - dB
Group Delay (Fs = Output Sample Rate) (Note 5) tgd - 15/Fs - - 15/Fs - s
Group Delay Variation vs. Frequency ∆ tgd - - 0 - - 0 µs
4 DS281PP2
CS4227
DS281PP2 5
CS4227
SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = +5 V ±5%; outputs loaded with 30 pF.)
Parameter Symbol Min Typ Max Unit
Audio ADC’s and DAC’s Sample Rate Fs 4 - 50 kHz
XTI Frequency XTI = 256, 384, or 512 Fs 1.024 - 26 MHz
XTI Pulse Width High XTI = 512 Fs 10 - - ns
XTI = 384 Fs 21 - -
XTI = 256 Fs 31 - -
XTI Pulse Width Low XTI = 512 Fs 10 - - ns
XTI = 384 Fs 21 - -
XTI = 256 Fs 31 - -
XTI Jitter Tolerance - 500 - ps
CLKOUT Jitter (Note 9) - 200 - psRMS
CLKOUT Duty Cycle (high timer/cycle time) (Note 10) 40 50 60 %
PDN Low Time (Note 11) 500 - - ns
SCLK Falling Edge to SDOUT Output Valid DSCK = 0 tdpd - - Note 12 ns
LRCK edge to MSB valid tlrpd - - 40 ns
SDIN Setup Time Before SCLK Rising Edge DSCK = 0 tds - - 25 ns
SDIN Hold Time After SCLK Rising Edge DSCK = 0 tdh - - 25 ns
Master Mode
SCLK Falling to LRCK Edge DSCK = 0 tmslr - ±10 - ns
SCLK Period (Note 14) - - - - -
SCLK Duty Cycle - 50 - %
Slave Mode
SCLK Period tsckw Note 13 - - ns
SCLK High Time tsckh 40 - - ns
SCLK Low Time tsckl 40 - - ns
SCLK Rising to LRCK Edge DSCK = 0 tlrckd 20 - - ns
LRCK Edge to SCLK Rising DSCK = 0 tlrcks 40 - - ns
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN should be held low for 1 ms to allow the power supply to settle.
1
12. --------------------- + 20
( 384 )Fs
1
13. ---------------------
( 128 )Fs
14. 1
-------------------
( 256 )Fs
6 DS281PP2
CS4227
SCLK*
SCLKAUX*
(output)
t mslr
LRCK
LRCKAUX
(output)
SDOUT1
SDOUT2
LRCK
LRCKAUX
(input) t lrckd t lrcks t sckh t sckl
SCLK*
SCLKAUX*
(input)
t sckw
SDIN1
SDIN2
SDIN3
DATAUX
t lrpd t ds t dh t dpd
DS281PP2 7
CS4227
Notes: 15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For FSCK < 1 MHz.
CS
t css t scl t sch t csh
CCLK
t r2 t f2
CDIN
t dsu t t pd
dh
CDOUT
8 DS281PP2
CS4227
Repeated
Stop Start Start Stop
SDA
t buf t hdst t high t tf
hdst t susp
SCL
t t t sud t sust tr
low hdd
DS281PP2 9
CS4227
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltage with respect to 0 V.)
Parameter Symbol Min Max Unit
Power Supplies Digital VD+ -0.3 6.0 V
Analog VA+ -0.3 6.0
Input Current (Note 19) - ±10 mA
Analog Input Voltage (Note 20) -0.7 (VA+) + 0.7 V
Digital Input Voltage (Note 20) -0.7 (VD+) + 0.7 V
Ambient Temperature (Power Applied) -55 +125 °C
Storage Temperature -65 +150 °C
Notes: 19. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
20. The maximum over or under voltage is limited by the input current.
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
10 DS281PP2
CS4227
Ferrite Bead
2.0 Ω
+5V
Supply + 1 µF 0.1 µF + 1 µF 0.1 µF
19 40
VA+ VD+
16 21 ANALOG
To Optional CMOUT AOUT1
Input and 1 µF + FILTER
Output Buffers
22 ANALOG
AOUT2
10 µF * 14 FILTER
AIN1L
10 µF * 13
AIN1R
CS4227
From Optional Input Buffer
23 ANALOG
AOUT3
10 µF * 11 FILTER
AIN2L
10 µF * 12
AIN2R
24 ANALOG
AOUT4
10 µF * 10 FILTER
AIN3L
10 µF * 9
AIN3R
25 ANALOG
AOUT5
10 µF * 15 FILTER
AINAUX
26 ANALOG
AOUT6
FILTER
27
DEM
2
HOLD
3
Digital SCL/CCLK
Audio 1 4
DATAUX SDA/CDOUT
Source RS 44 6
LRCKAUX AD0/CS Microcontroller
RS 43 5
SCLKAUX AD1/CDIN
8
Mode PDN
Setting 7 34
SPI/I2C SDIN1
33
SDIN2
32
SDIN3
36
SDOUT1 Audio
35 DSP
SDOUT2
37 RS
LRCK
38 RS
R S = 50 Ω SCLK
31
CLKOUT
30
OVL
All unused digital inputs
should be tied to 0V.
AGND1, 2 DGND1, 2 NC XTO XTI
Unused analog inputs
should be left unconnected. 18 20 41 39 17 29 28
DS281PP2 11
CS4227
2. FUNCTIONAL DESCRIPTION
2.1 Overview 100 pF
The CS4227 has 2 channels of 20-bit analog-to-
digital conversion and 6 channels of 20-bit digital- 3.3 µF
20 k 10 k
Line In -
to-analog conversion. A mono 20-bit ADC is also Right
AINxR
provided. All ADCs and DACs are delta-sigma +
Example
converters. The stereo ADC inputs have adjustable Op-Amps are
5k
MC34074 or
input gain, while the DAC outputs have adjustable MC33078
CMOUT
2.2 Analog Inputs The analog inputs may also be configured as differ-
ential inputs. This is enabled by setting bits
2.2.1 Line Level Inputs
AIS1/0 = 3. In the differential configuration, the
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L left channel inputs reside on pins 10 and 11, and the
and AINAUX are the line level input pins (See Fig- right channel inputs reside on pins 12 and 13 as de-
ure 5). These pins are internally biased to the scribed in the table below. In differential mode, the
CMOUT voltage (nominally 2.3 V). A 10 µF DC full scale input level is 2 Vrms.
blocking capacitor allows signals centered around
0 V to be input. Figure 6 shows an optional dual op Single-ended Pin # Differential Inputs
amp buffer which combines level shifting with a AIN3L Pin 10 AINL+
AIN3R Pin 9 unused
gain of 0.5 to attenuate the standard line level of
AIN2L Pin 11 AINL-
2 Vrms to 1 Vrms. The CMOUT reference level is AIN2R Pin 12 AINR-
used to bias the op-amps to approximately one half AIN1L Pin 14 unused
the supply voltage. With this input circuit, the AIN1R Pin 13 AINR+
10 µF DC blocking caps in Figure 5 may be omit-
ted. Any remaining DC offset will be removed by Table 1. Single-ended vs Differential Input Pin
Assignments
the internal high-pass filters.
The analog signal is input to the mono ADC via the
Selection of the stereo input pair for the 20-bit AINAUX pin.
ADC's is accomplished by setting the AIS1/0 bits,
Independent Muting of both the stereo ADC's and
which are accessible in the ADC Control Byte. On-
the mono ADC is possible through the ADC Con-
chip anti-aliasing filters follow the input mux, pro-
trol Byte (#11) with the MUTR, MUTL and
viding anti-aliasing for all input channels.
MUTM bits.
12 DS281PP2
CS4227
5 kΩ
CMOUT
0.47 µF
DS281PP2 13
CS4227
14 DS281PP2
CS4227
DS281PP2 15
CS4227
M SCLKs M SCLKs
M SCLKs M SCLKs
64 SCLKS 64 SCLKS
FORMAT 5: LRCK
SCLK
SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
DAC #1 DAC #3 DAC #5 DAC #2 DAC #4 DAC #6
20 clks 20 clks 20 clks 20 clks 20 clks 20 clks
SDOUT1 SDOUT1 SDOUT2 SDOUT1 SDOUT2
20 clks 20 clks 20 clks 20 clks
FORMAT 6: LRCK
(Master Mode Only) SCLK
SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
16 DS281PP2
CS4227
CS
CCLK
CHIP CHIP
ADDRESS MAP DATA ADDRESS
0010000 R/W MSB LSB 0010000
CDIN R/W
byte 1 byte n
DS281PP2 17
CS4227
Note 1
ADDR DATA DATA
SDA 00100 R/W ACK ACK 1-8 ACK
AD1-0 1-8
SCL
Start Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
18 DS281PP2
CS4227
DS281PP2 19
CS4227
> 1/8"
20 DS281PP2
CS4227
Figure 15. 20-bit ADC Filter Response Figure 16. 20-bit ADC Passband Ripple
Figure 17. 20-bit ADC Transition Band Figure 18. DAC Frequency Response
Figure 19. DAC Passband Ripple Figure 20. DAC Transition Band
DS281PP2 21
CS4227
22 DS281PP2
CS4227
RS Chip reset
0 - No Reset
1 - Reset
DS281PP2 23
CS4227
MUTL, MUTR, MUTM - Left, right and mono channel mute control
0 - Normal output level
1 - Selected ADC output muted
24 DS281PP2
CS4227
These bits are ’sticky’. They constantly monitor the ADC output for the peak levels and hold the max-
imum output. They are reset to 0 when read.
DS281PP2 25
CS4227
26 DS281PP2
CS4227
DS281PP2 27
CS4227
28 DS281PP2
CS4227
3. PIN DESCRIPTIONS
DGND2
VD+ SCLK
DGND1 LRCK
NC SDOUT1
SCLKAUX SDOUT2
LRCKAUX SDIN1
DATAUX SDIN2
HOLD 44 43 42 41 40 39 38 37 36 35 34 SDIN3
1 33
SCL/CCLK 2 32 CLKOUT
SDA/CDOUT 3 31 OVL
4 30
AD1/CDIN XTO
5 29
CS4227-KQ
AD0/CS 6
44-pin TQFP
28 XTI
7 27
SPI/I2C DEM
8 Top View 26
PDN 9 25 AOUT6
AIN3R 10 24 AOUT5
11 23
AIN3L 12 13 14 15 16 17 18 19 20 21 22 AOUT4
AIN2L AOUT3
AIN2R AOUT2
AIN1R AOUT1
AIN1L AGND2
AINAUX VA+
CMOUT AGND1
NC
Power Supply
DS281PP2 29
CS4227
Analog Inputs
Analog Outputs
30 DS281PP2
CS4227
DS281PP2 31
CS4227
Miscellaneous Pins
NC - No Connect
32 DS281PP2
CS4227
4. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the
measurement to full scale. This technique ensures that the distortion components are below the noise
level and do not effect the measurement. This measurement technique has been accepted by the Audio
Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter’s output with no
signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Frequency Response
A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Gain Error
The deviation from the nominal full scale output for a full scale input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For
the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units
are in volts.
DS281PP2 33
CS4227
5. PACKAGE DIMENSIONS
44L TQFP PACKAGE DRAWING
E1
D D1
e B
∝ A
A1
L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.000 0.065 0.00 1.60
A1 0.002 0.006 0.05 0.15
B 0.012 0.018 0.30 0.45
D 0.478 0.502 11.70 12.30
D1 0.404 0.412 9.90 10.10
E 0.478 0.502 11.70 12.30
E1 0.404 0.412 9.90 10.10
e 0.029 0.037 0.70 0.90
L 0.018 0.030 0.45 0.75
∝ 0.000 7.000 0.00 7.00
JEDEC # : MS-026
34 DS281PP2
• Notes •