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VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK
SUBJECT : CS6303-COMPUTER ARCHITECTURE
SEM / YEAR: VI SEM/III YEAR

UNIT I - OVERVIEW AND INSTRUCTIONS

Eight ideas – Components of a computer system – Technology – Performance – Power wall – Uniprocessors to
multiprocessors; Instructions – operations and operands – representing instructions – Logical operations – control operations
– Addressing and addressing modes.
PART - A
Q.No Questions BT Level Competence
1. Define Amdahl’s law. BTL1 Remember
2. Analyze the general characteristics of Relative addressing mode with an BTL4 Analyze
example.
3. Discuss the eight great ideas in computer architecture. BTL2 Understand
4. List the five classic components of a computer. BTL1 Remember
5. Summarize the function of data path and control path. BTL2 Understand
6. Interpret the representation of instruction in a computer system. BTL2 Understand
7. Differentiate DRAM and SRAM. BTL4 Analyze
8. Distinguish volatile and non volatile memory. BTL2 Understand
9. What is meant by VLSI? BTL1 Remember
10. Calculate throughput and response time. BTL3 Apply
11. Compose the CPU performance equation. BTL6 Create
12. Measure the performance of the computers: BTL5 Evaluate
If computer A runs a program in 10 seconds, and computer B runs the same
program in 15 seconds, how much faster is A over B?
13. Formulate the equation of CPU execution time for a program. BTL6 Create
14. Examine instruction set architecture. BTL1 Remember
15. Show the formula for CPU clock cycles required for a program BTL3 Apply
`
16. Quote – Stored Program Concept. BTL1 Remember
17. Tabulate the fields in an MIPS instruction. BTL1 Remember
18. Compare multi processor and uniprocessor. BTL4 Analyze
19. Illustrate relative and indirect addressing mode with example. BTL3 Apply
20. Measure which computer has the higher MIPS rating? BTL5 Evaluate
Measurement Computer A Computer B
Instruction
Count 10 billion 8 billion
Clock rate 4GHz 4GHz
CPI 1.0 1.1

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PART B
1. (i)Summarize the eight great ideas of computer Architecture. (8) BTL 5 Evaluate
(ii) Explain the concept of powerwall processor. (8)
2. List and explain the various components of computer system with neat BTL 1 Remember
diagram. (16)
3. (i) Define addressing mode. (4) BTL 1 Remember
(ii) Describe the basic addressing modes with an example for each. (12)
4. (i) Identify the various operations in computer system. (8) BTL 1 Remember
(ii) Examine the operands of computer hardware. (8)
5. (i)Differentiate uni-processors and multi-processors (8) BTL 2 Understand
(ii) Describe the technologies for Building Processors and Memory. (8)
6. Analyze the performance of processors: BTL 4 Analyze
Consider three different processors P1, P2, and P3 executing the same
instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz
clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2
a) Which processor has the highest performance expressed in
instructions per second? (4)
b) If the processors each execute a program in 10 seconds, find the number of
cycles and the number of instructions? (6)
c) We are trying to reduce the execution time by 30% but this leads to an
increase of 20% in the CPI. What clock rate should we have to get this
time reduction? (6)
7. Solve : BTL 3 Apply
Assume a program requires the execution of 50 × 106 FP istructions,110 × 106
INT instructions, 80 × 106 L/S instructions, and 16 × 106 branch instructions
The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that
the processor has a 2 GHz clock rate
a) By how much must we improve the CPI of FP instructions if we want the
program to run two times faster? (4)
b) By how much must we improve the CPI of L/S instructions (4)
c) if we want the program to run two times faster? (4)
d) By how much is the execution time of the program improved if the CPI of
INT and FP Instructions are reduced by 40% and the CPI of L/S and
Branch is reduced by 30%? (4)
8. Interpret the branching operations with suitable example. (16) BTL 2 Understand
9. (i)Formulate the performance equation of CPU (8) BTL 6 Create
(ii)Compose the factors that affect performance. (8)

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10. (i)Examine the following sequence of instructions and identify the BTL 3 Apply
addressing modes used and the operation done in
every instruction
(1) Move (R5)+, R0
(2) Add(R5)+, R0
(3) Move R0, (R5)
(4) Move 16(R5),R3
(5) Add #40, R5 (10)

(ii)Calculate which code sequence will execute faster according to execution time
for the following conditions:
The c The computer with three instruction classes and CPI measurements as given below
and instruction counts for each instruction class for the same program from two
different compilers are given. Assume that the computer’s clock rate is 1GHZ.
Code from CPI for the instruction class
A B C
CPI 1 2 3
Code from CPI for the instruction class
A B C
Compiler1 2 1 2
Compiler2 2 1 1 (6)

11. Describe the various techniques to represent instructions in a computer system.(16) BTL 1 Remember
12. (i) Explain the logical operations and control operations of computer (8)
(ii) Pointout the impact on dynamic power: BTL4 Analyze
Suppose we develop a new simpler processor that has 85% of the capacitative load
of the more complex older processor. Further assume that it has adjustable voltage
ao that it can reduce voltage 5% compressed to processor B, which results in a 15%
compressed to processor B, which results in a 15% shrink in frequency. (8)

13. Classify the different types of computer hardware and software used in computer BTL4 Analyze
architecture. (16)
14. Summarize the compilation of assignment statements into MI PS with examples. BTL 2 Understand
(16)
UNIT II - ARITHMETIC OPERATIONS
ALU – Addition and subtraction – Multiplication – Division – Floating Point operations – Subword parallelism.

PART - A
Q.No Questions BT Level Competence

1. Calculate the following: BTL 3 Apply

Add 510 to 610 in binary and Subtract -610 from 710 in binary
2. Analyze overflow and underflow conditions for addition and subtraction? BTL 4 Analyze
3. Demonstrate the Multiplication hardware diagram. BTL 3 Apply
4. List the steps of multiplication algorithm. BTL 1 Remember
5. What is fast multiplication? BTL 1 Remember
6. Define ALU. BTL 1 Remember
7. Illustrate scientific notation and normalization with example. BTL 3 Apply
8. Interpret single precision floating point number representation with example. BTL 2 Understand
9. Contrast overflow and underflow with examples. BTL 2 Understand

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10. Give the representation of double precision floating point number. BTL 2 Understand
11. Tabulate floating point instructions in MIPS? BTL 1 Remember
12. Formulate the steps of floating point addition? BTL 6 Create
13. Evaluate the sequence of floating point multiplication. BTL 5 Evaluate
14. Examine – Guard and Round bit. BTL 1 Remember
15. BTL 2 Understand
Express the IEEE 754 floating point format.
16. Describe sub-word parallelism. BTL 1 Remember
17. Multiply 100011 * 100010. BTL 4 Analyze
18. Divide 1,001,010 by 1000. BTL 4 Analyze
19. Compose the corresponding MIPS assembly code for the following C BTL 6 Create
statement,
f = g + (h − 5)
20. BTL 5 Evaluate
Consider the following MIPS assembly instruction, what is a corresponding C
statement?
add f, g, h
add f, i, f
PART - B
1. i)Discuss the multiplication algorithm in detail with diagram (10) BTL 2 Understand
ii)Express the steps to Multiply 2*3 (6)

2. BTL 1 Remember
i) Describe the division algorithm with diagram. (8)
ii)Tabulate the steps to divide 00000111 by 0010 (8)
3. i)Examine how floating point addition is carried out in a computer system?(10) BTL 1 Remember
ii)Quote an example for a binary floating point addition. (6)
4. Summarize in detail the floating point multiplication algorithm. (16) BTL 2 Understand
5. Analyze the multiplication of signed 2’s complement numbers with algorithm BTL 4 Analyze
and example. (16)
6. BTL 6 Create
Develop an algorithm to implement A*B. Assume A and B for a pair of signed
2’s complement numbers with values : A = 010111, B = 101100. (16)
7. i)Explain floating point addition algorithm with diagram. (8) BTL 5 Evaluate
ii)Assess the result of the numbers 0.510 +( -0.437510) using binary Floating
point Addition algorithm. (8)
8. Solve using Floating point multiplication algorithm BTL 3 Apply
i)1.10 10X 1010and 9.200X10-5 (8)
ii)0.5 10 X 0.4375 10 (8)
9. Calculate the division of A and B: BTL 3 Apply
A=3.264 X 103 and B= 6.52 X 102 (16)
10. Tabulate the IEEE 754 binary representation of the number - 0.75 10 BTL 1 Remember
i) single precision (8)
ii) double precision (8)
11. Explain subword parallelism (8) BTL 2 Understand
Explain 1’s complement and 2’s complement methods of subtraction (8)
12. Describe about basic concepts of ALU design. (16) BTL 1 Remember

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13. Arrange in single precision IEEE 754 representation. BTL4 Analyze
i) 32.75 (8)
ii)18.125 (8)
14. Arrange the given number 0.0625 BTL4 Analyze
i) in single precision and (8)
ii) double precision formats (8)
UNIT III PROCESSOR AND CONTROL UNIT
SYLLABUS

Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining Pipelined
datapath and control – Handling Data hazards & Control hazards – Exceptions.
PART - A
Q.No Questions BT Level Competence
1 Describe data path element? BTL 2 Understand
2
Summarize the use of PC register. BTL 2 Understand
3 Define register file. BTL 1 Remember
4
List the state elements needed to store and access an instruction. BTL 1 Remember
5 Interpret R-Type instruction. BTL 2 Understand
6
Differentiate Sign Extend and Vector interupts . BTL 2 Understand
7
What is meant by branch target address? BTL 1 Remember
8 Evaluate branch taken and branch not taken in instruction execution? BTL 5 Evaluate
9 Examine delayed branching? BTL 1 Remember
10 Design the instruction format for the jump instruction. BTL 6 Create
11
Classify the different types of hazards with examples. BTL 4 Analyze
12
Illustrate data forwarding method to avoid data hazards. BTL 3 Apply
13 Assess the methods to reduce the pipeline stall. BTL 5 Evaluate
14 Describe branch prediction? BTL 1 Remember
15 Show the 5 stages pipeline. BTL 3 Apply
16 Point out the concept of exceptions and interrupts. BTL 4 Analyze
17 Identify the features of pipelining? BTL 1 Remember
18 Illustrate the five steps used in MIPS instruction execution. BTL 3 Apply
19 Classify the types of instruction classes and their instruction formats. BTL 4 Analyze
20 Generalize the calculation of branch target address BTL6 Create
16 MARK QUESTIONS
1 Discuss the basic MIPS implementation of instruction set (16) BTL 2 Understand
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2 Describe MIPS implementation with necessary multiplexers and control
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lines. (16)
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3 i)List the types of hazards. (4)
ii) Tabulate the methods for dealing with control hazards in detail. (12)
4 BTL 6 Create
Design and develop an instruction pipeline working under various situations of
pipeline stall. (16)
5 i)What is data hazard? How do you overcome it? (10) BTL 1 Remember
ii)What are its side effects? (6)

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6 i)Summarize control implementation scheme. (10) BTL 2 Understand
ii)Distinguish the data and control path methods in pipelining. (6)
7 i) Differentiate between sequential execution and pipelining? (8) BTL 4 Analyze
ii) Select the model for building a datapath (8)
8 Recommend the techniques for BTL 5 Evaluate
i)dynamic branch prediction (8)
ii)static branch prediction (8)
9 Examine the approaches would you use to handle exceptions in MIPS. (16) BTL 3 Apply
10 Analyse control path implementation in pipelining. (16) BTL 4 Analyze
11 (i)Give ALU control with suitable truth table. (12) BTL 2 Understand
(ii)Differentiate R type instruction and memory instruction. (4)
12 (i)Explain single cycle and pipelined performance with examples. (12) BTL 4 Analyze
(ii)Point out the advantages of pipeline over single cycle. (4)
13 Show with a suitable set of sequence of instructions what happens when the BTL 3 Apply
branch is taken,assuming the pipeline is optimized for branches that are not
taken and that we moved the branch execution to the ID stage. (16)
14 Identify the units needed to implement load and store instruction. (16) BTL 1 Remember
UNIT IV PARALLELISM
Instruction-level-parallelism – Parallel processing challenges – Flynn’s classification – Hardware multithreading –
Multicore processors

PART - A
Q.No Questions BT Level Competence
1 Describe the main idea of ILP. BTL 2 Understand
2 Express how to organize a multiple issue processor. BTL 2 Understand
3 List the three important properties of vector instructions? BTL 1 Remember
4 Analyze the characteristics of SMT processor. BTL4 Analyze
5 Quote the importance of loop unrolling technique? BTL1 Remember
6 Define VLIW processor. BTL1 Remember
7 Illustrate what is anti-dependence. How is it removed? BTL 3 Apply
8 Examine the efficiency of superscalar processor. BTL 1 Remember
9 Differentiate between strong scaling and weak scaling. BTL 2 Understand
10 Show the performance of cluster organization. BTL 3 Apply
11 Compare SMT and hardware multithreading. BTL 5 Evaluate
12 Describe the Flynn classification. BTL 1 Remember
13 Integrate the ideas of in-order execution and out-of-order execution? BTL 6 Create
14 Discriminate UMA and NUMA. BTL 5 Evaluate
15 What is fine grained multithreading.? BTL 1 Remember
16 Summarize sub-word parallelism. BTL 2 Understand
17 Formulate the various approaches to hardware multithreading BTL 6 Create
18 Classify the various multithreading methods. BTL 4 Analyze
19 Point out the features of multicore processor. BTL 4 Analyze
20 Demonstrate the approaches used to improve the performance of a processor. BTL 3 Apply
PART - B
1 i)Define parallelism and its types . (4) BTL 1 Remember
ii)List the main characteristics of Instruction level parallelism. (12)
2 i) Give the concept of parallel processing. (4) BTL 2 Understand
ii) Summarize the facts or challenges faced by parallel processing
Programs. (12)
3 Describe hardware multithreading concept. (16) BTL 2 Understand

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4 Solve: suppose you want to achieve a speed up to 90 times faster with 100 BTL 3 Apply
processors. What percentage of the original computation can be sequential?
(16)
5 Describe data level parallelism in BTL 1 Remember
i)SIMD and (8)
ii)MISD machine . (8)
6 i) Point out how will you use shared memory concept in multi-processor? (8) BTL4 Analyze
ii). Compare and contrast Fine grained and Coarse grained
multithreading. (8)
7 Evaluate the features of Multicore processors. (16) BTL 5 Evaluate
8 i)Classify the types of multithreading. (10) BTL 4 Analyze
ii)Analyse the advantages in multithreading (6)
9 Formulate the ideas of Flynn’s classification of parallel hardware. (16) BTL 6 Create
10 i). Tabulate the concept of vector processor. (8) BTL 1 Remember
ii).Examine about SIMD processor. (8)
11 i) Explain static multiple issue processors. (8) BTL 4 Analyze
ii)Infer what you understand from dynamic multiple issue processor? (8)
12 Describe the Dynamic pipeline scheduling. (16) BTL 1 Remember
13. i)Show the Loop unrolling for multiple issue pipelines. (8) BTL3 Apply
ii). Illustrate the Concept of speculation and its difficulty. (8)
14. i). Discuss about Synchronization (8) BTL 2 Understand
ii). Express about Superscalar processor (8)

UNIT V MEMORY AND I/O SYSTEMS

Memory hierarchy – Memory technologies – Cache basics – Measuring and improving cache performance – Virtual
memory, TLBs – Input/output system, programmed I/O, DMA and interrupts, I/O processors.

PART - A
Q.No Questions BT Level Competence
1 Distinguish the types of locality of references. BTL 2 Understand
2 Define the structure of memory hierarchy. BTL 1 Remember
3 Summarize the various memory technologies? BTL 2 Understand
4 Compare and contrast SRAM and DRAM. BTL 4 Analyze
5 What is flash memory? BTL 1 Remember
6 Describe Rotational Latency. BTL 1 Remember
7 Identify what is direct-mapped cache? BTL 1 Remember
8 Evaluate the following instance wherein the cache size is 64 blocks and block BTL 5 Evaluate
size is 16 bytes. What block number does byte address 1200 map?

9 Formulate how many total bits are required for a direct-mapped cache with 16 BTL 6 Create
KB of data and 4-word blocks, assuming a 32-bit address?

10 Analyze the writing strategies in cache memory. BTL 4 Analyze

11 Integrate the functional steps required in an instruction cache miss. BTL 6 Create
12 Quote what is hit rate and miss rate. BTL 1 Remember
13 Express the various block placement schemes in cache memory. BTL 2 Understand
14 Examine Mean Time to Failure rate. BTL 1 Remember
15 Point out how DMA can improve I/O speed. BTL 4 Analyze
16 Show the role of TLB in virtual memory? BTL 3 Apply
17 Illustrate the advantages of virtual memory. BTL 3 Apply
18 Assess the relationship between physical address and logical address? BTL 5 Evaluate

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19 Give the idea of address mapping? BTL 2 Understand
20 Calculate Hit ratio. BTL 3 Apply
PART - B
1 (i)List the various memory technologies and examine its relevance in BTL 1 Remember
architecture design. (8)
(ii)Identify the characteristics of memory system (8)
2 Describe in detail the memory hierarchy with neat diagram. (16) BTL 1 Remember
3 (i)Give the advantages of cache (4) BTL 2 Understand
(ii)Summarize the basic operations of cache in detail with diagram. (12)
4 Express mapping schemes used in cache memory. BTL 2 Understand
(i) Direct (4)
(ii) Associate (6)
(iii) Set associate (6)
5 (i)Analyze the given problem: BTL 4 Analyze
A byte addressable computer has a small data cache capable of holding eight
32-bit words. Each cache block contains 132-bit word. When a given program
is executed, the processor reads data from the
following sequence of hex addresses – 200, 204, 208, 20C, 2F4,
2F0,200,204,218, 21C, 24C, 2F4. The pattern is repeated four times.Assuming
that the cache is initially empty, show the contents of the cache at the end of
each pass, and compute the hit rate for a direct mapped cache. (8)

(ii)) infer what are the methods used to measure and improve the performance
of the cache. (8)
.
6 (i)Define virtual memory and its importance. (6) BTL 1 Remember
(ii)Examine TLB with necessary diagram. (10)
.(i)Demonstrate the DMA controller (8) BTL 3
7 Apply
(ii)Illustarate how DMA controller is used for direct data transfer between
memory and peripherals? (8)
8 (i)Evaluate the advantages of interrupts. (4) BTL 5 Evaluate
(ii)summarize the concept of interrupts with neat diagrams. (12)
9 Design standard input and output interfaces required to connect the I/O device BTL 6 Create
to the bus. (16)
10 Classify the bus arbitration techniques in DMA. (16) BTL 4 Analyze
11 (i)Analyse Programmed I/O (8) BTL4 Analyze
(ii)point out the Instructions executed by IOP. (8)
12 Tabulate the methods used to reduce cache misses? Describe it. (16) BTL 1 Remember
13 Discuss the implementation of virtual memory with neat diagram. (16) BTL 2 Understand
14 Calculate the performance the processor: BTL 3 Apply
Assume the miss rate of an instruction cache is 2% and the miss rate
of the data cache is 4%. If a processor has a CPI of 2 without any
memory stalls and the miss penalty is 100 cycles for all misses,
estimate how much faster a processor would run with a perfect cache
that never missed. Assume the frequency of all loads and stores is
36%. (16)

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