Allegro ADS Design Tutorial

Flow Integration
(Allegro ADFI)

ADFI Tutorial
1 March, 2011
Allegro ADS Design Flow Integration (Allegro ADFI)

Design Flow Integration Market Segments

SAgilent • Board/Package/SiP
Allegro SPB ADS

• Selective transfer of nets (traces,

power/gnd planes)
– „cookie cutter‟ feature
• Substrate stackup
• Automatic port generation

ADFI Tutorial
2 March, 2011
Allegro to ADS Flow

Export To ADS/EMPro Select Critical Nets

Setup in Allegro or Entire Layout Select Stackup Layers

Cookie-cut Power and

Export to
Ground Planes Create Ports
ADS Layout
Portion

Ground Ref Port Verify Layout using

Import in ADS Layout Adjustments if 3-D Preview and
required Simulate

ADFI Tutorial
3 March, 2011
What’s New in ADFI version 4.1.5

This tutorial has been updated for

Allegro ADFI skill code version 4.1.5 &
ADS ADFI import kit version 3.4

• Export of Allegro shapes, clines as arced polygons, paths

• Circles and arc definitions kept when possible
• Export to Empro checks compatibility
• Blind and buried vias in substrate generated directly
• Substrate extraction direct from Allegro xsection function
• Generates only .adfi file in hierarchical mode
• Import in ADS can generate schematics
• Discrete components imported as schematic with ideal component
• Order of magnitude faster on large designs in hierarchical mode

ADFI Tutorial
4 March, 2011
Software Versions

Cadence Allegro SPB

• Versions 15.7, 16.01, 16.2, 16.3 and 16.5
• Allegro ADFI skill code version 4.1.5
• Tools: PCB Editor, Package Designer (APD), SiP

Installation
• Allegro: configuration script provided to enable „Export To ADS/EMPro‟
– Use 4.1.5 versions for export to ADS 2011 (optimized for ADS 2011.10)
• ADS 2011: import design kit (version 3.4) must be loaded to enable import
into ADS
– This import design kit works also with ADS 2009U1

ADFI Tutorial
5 March, 2011
Installation

• Replay the installation script in Allegro, APD, Cadence SiP

$HPEESOF_DIR/ial/scripts/eemLocalConfig.scr

Enable the
change directory flag
in the file browser !!!

ADFI Tutorial
6 March, 2011
Installation
• Replay opens Allegro ADFI setup
• Form to specify config preferences
– Local configuration location
• %HOME%/pcbenv or $HOME/pcbenv
– Check boxes for Allegro based tools
• Use general allegro.ilinit when possible
• Flag for apd.ilinit for cdnsip.ilinit
• Enabled when these files exist
• Other field for ilinit files for less common
tools
– Radio button to select ADS integrated
install or Standalone use
• Needs ADS2008 Update2 or later
• Looks for existing HPEESOF_DIR setting
• Standalone will be hidden when Ads is
available
• Standalone needs Python 2.5 or 2.6
• Looks for existing Python in path

ADFI Tutorial
7 March, 2011
Installation

– Automatic load of menu fragment is

default behavior
• Default just in front of Allegro <Help>
• Setup allows to select any existing
menu item position in Allegro menu
hierarchy through highlighted active list
item.
• Placement before or after the item
• Caution: if ADFI items present in the
menu list take item from Allegro

• ADS can start from the Export Menu if

integrated with ADS.
– Enable flag
– Need ADS licensing to be setup
correctly (will try to find if present)

ADFI Tutorial
8 March, 2011
Installation

• Setup runs the configuration script

– Removes old local ADFI configuration
information
– Setup makes up to four backup files
with <name>.<ext>,[1,2,3,4]
– Creates eemAdfiSetup.il with actual
configuration settings in ~/pcbenv
– Add (load ~/pcbenv/ eemAdfiSetup.il)
command to the selected <tool>.ilinit
files

ADFI Tutorial
9 March, 2011
Installation Tips

Make sure Allegro performance features are available (full scripting interface)
•Lowest tier versions of Allegro, Allegro Viewer and Orcad cannot work with ADFI
Delete the $HOME/pcbenv if you weren‟t using ADFI since ADS 2008U2.
After restart, verify that one and only one
Momentum Allegro Integration (Version n.n.n) is loaded.
The most recent version (Version 4.1.5)
If you see multiple instances, check your allegro.init (and <tool>.ilinit) files!

ADFI Tutorial
10 March, 2011
Installation Tips
Cadence SiP and Package Designer specific setups

ADFI configuration not picked up by apd and cdnsip after the

restart usually when Ansoft Links is also present
• The apd and cdnsip tools only load the allegro.ilinit with the ADFI
configuration if no apd.ilinit and cdnsip.ilinit exists in the ~/pcbenv directory
and/or directories defined by the localpath Allegro variable
• Use the new configuration script to update the *.ilinit files
• Or copy the line from the allegro.ilinit containing the ADFI load code to
{apd|cdnsip}.ilinit files to solve this.
(load "C:/Users/mbrunfau/pcbenv/eemAdfiSetup.il") ; Agilent EEsof EDA, Allegro DFI load

Versions after 3.1.5 of configuration script check this!!!

• Automatically recognizes such setups & enable of the config flags

ADFI Tutorial
11 March, 2011
Lab Outline

• Allegro Basics
– Is the board ready? Let‟s do some basic checks…
• ADFI Setup
– All the things you thought you didn‟t want to know…
• ADFI Selection
– Let‟s have some fun…

We will be using the cds_routed.brd for this…

%CDSROOT%\share\pcb\examples\board_design\cds_routed.brd

Launch the Allegro PCB Editor and choose the Performance

version (or higher)

ADFI Tutorial
12 March, 2011
Allegro Basics – Configure Your Allegro UI

Pin down Options, Find and Visibility palettes into the Allegro UI
 the tool belt which you really need permanently

ADFI Tutorial
13 March, 2011
Allegro Basics – Class / SubClass

Many database objects are organized

classes in a class/subclass hierarchy

Visibility
• Class/subclasses used in cross-section
will be listed here
• Can be (de)activated by class/subclass
subclasses hierarchy

Options
• Context is linked to the active operation

ADFI Tutorial
14 March, 2011
Allegro Basics – Selection

• Allegro uses the following operational model

– Choose operation
– Select object
– Apply operation, next object, cancel,
reject, etc
– Done
• Application mode may change depending
command context. We typically need
„General Edit‟ (right-click outside design to
switch)
• Filters apply while selecting  inspect the
„Find‟ window
– When choosing an action, last used filter
settings get loaded automatically!!!
• Also check the window/dialog focus

ADFI Tutorial
15 March, 2011
Allegro Basics – Cross Section

• Open Setup > Cross Section…

– Negative Artwork: equivalent to Momentum slot mask but the display
shown is always positive
– Shield: indicates that this is a plane, typically for pwr/gnd distribution.
• Informs the router to stay away from it
• Always exported as sheet conductor by ADFI if strip export is chosen.

ADFI Tutorial
16 March, 2011
Allegro Basics – Cross Section

• Open Setup > Cross Section…

– TOP to BOTTOM define a physical stack
– Conducting layers (CONDUCTOR/PLANE) must be
separated by dielectric!
Somehow, Allegro doesn‟t always enforce this. If this is not the case,
always check the exported substrate stack!!!
– In traditional Allegro PCB, only conducting layers get subclass names. In
APD/SiP, dielectric layer can get a name used to define e.g. blind or
buried vias.

ADFI Tutorial
17 March, 2011
Allegro Basics – Cross Section

This example has positive layers only

ADFI Tutorial
18 March, 2011
Allegro Basics – Padstacks

• Open Tools > Padstack > Modify Design Padstack…

– Note that the options window updates.
– Select a via in the design
– Right click Edit (or Edit … from the Options window) to open the
padstack definition dialog. See next slide…

– Don‟t forget to end command: Right click > Cancel

ADFI Tutorial
19 March, 2011
Allegro Basics – Material database

• Two variants: materials.dat in Allegro PCB; mcmmat.dat in APD and SiP

• Can be located in multiple locations but only one file is actually used
• If cross-section contains material names not in the materials list:
– Check if the correct material database is loaded or is available with design
– Reload the materials if needed
– Make sure FR-4, COPPER, GOLD, SILICON exist  defaults for Allegro ADFI

ADFI Tutorial
20 March, 2011
Allegro Basics – Padstack Definition

• Are the drill holes correctly

defined?
– Those become the Momentum via
– If diameter == 0  ignored in export
– Be afraid of dummy drills holes!!!
• „Allow suppression of unconnected
catch pads‟ checked?
– ADFI cannot get to this setting. See
option in eemom.option file
(explained later)
• Multi-drill with staggered holes is not
supported in ADFI
• Plating info is missing
– Electrical properties must be
specified in eemom.option file!

ADFI Tutorial
21 March, 2011
Allegro Basics – Padstack Definition

How „regular pad‟, „thermal relief‟ or „anti-

pad‟ are used depends on the nets of the
shapes that the via crosses.

Thermal relief is added when via connects

to a plane shape.
• If plane is „all positive‟  relief is created by
dynamic routing mechanism
• If plane is „negative‟  relief shape is
inserted in the plane.
Be very cautious with this when you
switch between neg/pos in cross section.
E.g. Thermal relief as circle is ok on
positive plane but may disconnect the via
when switching to negative.

ADFI option allows to ignore thermal relief

on negative layers.

ADFI Tutorial
22 March, 2011
Allegro Basics – End Padstack Editing

Mouse pop-up is re-defined per active

command
Following actions are often present
– Done or End: apply and close command
– Oops: cancel transaction and continue
command
– Cancel: cancel and close command

•Don‟t try to open Skill based actions like

Export to ADS > Select with an earlier UI
edit command still active
•Allegro‟s event processing doesn‟t like this
and UI can behave very unpredictable
•If you get stuck try to start a native Allegro
command and use Cancel or F9

ADFI Tutorial
23 March, 2011
Allegro Basics – Display Parameters

Open Display > Color/Visibility…

• ADFI uses a scratch layer for cookie
cutter, etc…
(MANUFACTURING/EEM_SCRATCH)
• TIP: When you get an error message
related to the scratch layer, go into this
dialog  toggle visibility of the
Manufacturing layers and click Apply.

• Scratch layer is the only object that we

don‟t remove at end of a session

ADFI Tutorial
24 March, 2011
Allegro Basics – Display Parameters

Open Display > Color/Visibility…

• Display bundles Shadow mode, Shapes
transparency, etc…
• On some graphics cards, OpenGL fails.
In such case, go to
– Setup > User Preferences…
– Under Display – Opengl, disable
opengl and restart Allegro.

ADFI Tutorial
25 March, 2011
Allegro Basics – Design Parameters

Open Setup > Design Parameters…

• Display – Enhanced Display Modes
– controls how padstacks are
displayed. Play with these check
boxes.
Don‟t forget to hit Apply!
– Notice the difference on a board with
all positive layers (DDR2 example)
versus negative layers (cds_routed
example)
– Connect line endcaps have
significant impact on how arced
traces are behaving during export

ADFI Tutorial
26 March, 2011
Allegro Basics – Design Parameters

Open Setup > Design Parameters…

• Design
– Accuracy setting corresponds with
ADS layout resolution.

In this example:
Unit in ADS will be mil with a
resolution of 0.01.

No need to change it here. Use the

options file to increase the export
resolution (see later).
– Accuracy setting also controls
substrate export  trouble if there is
a unit mismatch for material heights

ADFI Tutorial
27 March, 2011
Allegro Basics – Design Parameters

Open Setup > Design Parameters…

• Shapes
– Click Edit global dynamic shape
parameters… Check the number of
„out of date shapes‟. This must be 0!!!
An example of dynamic shape
processing is the creation of thermal
reliefs and anti-pads on postive
shapes.
Operations on big or incomplete
designs may disable the dynamic
shape update what causes incorrect
shapes/connectivity.

ADFI Tutorial
28 March, 2011
Allegro Basics – Design Parameters

Open Setup > Design Parameters…

• Shapes
– Xhatch: style determine how
shape objects are hatched
Export of hatched shapes is not
supported in the Allegro ADFI
– Very expensive to process in Skill
– ADS has no representation for this
– Usually sufficient to change material
parameters to have similar behavior
Filled shape with outer contour is
exported

ADFI Tutorial
29 March, 2011
Allegro Basics – Constraint Manager (version 16.x)

Controls requirements for a design:

• Spacing, wiring, delay, etc rules are here somewhere
• The pad and padstack definitions for blind and/or buried vias and bondfingers are
also defined here
Typically no need to look there for an ADFI export but important resource for
designers. E.g. delay constraints for a line can be found in here. A tool that
checks electrical design rule violations has to get the specs from here…

ADFI Tutorial
30 March, 2011
Working with Skill and Canvas…

Skill (~ ADFI GUI) and canvas (~ layout

window) coexist, but do not cooperate
well sometimes 
• Make sure all commands are ended in
layout before working with ADFI menu.
• When error „complete command first‟ or
similar pops up, go to canvas, right click,
select End or Done
• Make sure you are in General Edit
Application Mode
• If this doesn‟t help, go to Export to ADS >
Setup… and click Reset / reload All
This resets ADFI and reloads all options.
Selections, etc will be lost but the last saved
state may allow to restore some.

ADFI Tutorial
31 March, 2011
 Allegro Basics ADFI Setup is next…
Done…

ADFI Tutorial
32 March, 2011
ADFI Flow

ADFI targets to transfer data targeted at doing an EM simulation. It doesn‟t transfer all
possible database information. If that is your goal, use other standard mechanisms.
The ADFI export setup and selection is tailored towards gathering the relevant information
for setting up an EM simulation.
Invest time in the ADFI selection and export! Go back and adjust the export if necessary. It
can save you significant time later on when performing the EM simulations in ADS.
A typical export takes 3 steps:
• Setup
• Selection
• Export
The simple „Export > All Artwork‟ is not the best option. It is an expensive operation,
provides no control, and exports flat EGS + main substrate only. There is little or no other
Allegro database information passed, e.g. no pins/components/nets.  You‟re loosing a
lot of knowledge about the design.

ADFI Tutorial
33 March, 2011
Export To ADS > Setup…

• Determines the way primitives are processed during export.

– “Vias/Padstacks”, “Signal Nets” and “RF ground nets” can be treated
independently.
• Defines layer mapping information
• Provides defaults for the ADS export dialog
– Including port generation options

Six sample setups are provided. Customized setups can be

defined.
Tip: use „Sample Fine Setting B‟ for a first time transfer. The
transferred design will be very „look-alike‟…

ADFI Tutorial
34 March, 2011
Sample Export Setups

Sample Fine Setting A: use Strips and Vias Sample Medium Setting
Default values: Default values:
Signal viaType asDefined, padType asDefined Signal viaType square, padType square
Ground viaType asDefined, padType asDefined Ground viaType square, padType square
Signal and Ground arcResolution 15 degrees Signal and Ground arcResolution 30 degrees
Convert negative planes to Strip objects

Sample Fine Setting B: use Strips, Slots and Vias Sample Coarse Setting
Default values: Default values:
Signal viaType asDefined, padType asDefined Signal viaType diamond, padType diamond
Ground viaType asDefined, padType asDefined Ground viaType diamond, padType diamond
Signal and Ground arcResolution 15 degrees Signal and Ground arcResolution 45 degrees
Export negative plane objects as Slots Simplify thermal via connections

ADFI Tutorial
35 March, 2011
Sample Export Setups

Sample Board setting using Strips, Slots and Vias Sample setup for export to EMPro
Default values: Default Values:
Signal viaType asDefined, padType asDefined Export mode version 4.0
Ground viaType square, padType asDefined Egs for layout masks and use facetted polygons
Signal and Ground arcResolution 30.0 degrees Ports in EMPro require valid + and - pin setup
Export negative plane objects as Slots Use Strip/Slot/Via representations on negative layers
Simplify thermal reliefs on negative shapes Keep negative layers as slot layers during export
Remove unconnected catch pads No slot contour around design exported
Remove holes not under traces Drop the unconnected pads except on top/bottom layer
Use cutter polygon as board outline boundary Ground vias will be exported as squares
Signal and Ground use 15 degrees arc resolution

ADFI Tutorial
36 March, 2011
Customizing the Export Setups

Options are defined in eemom.option file. Files are read (in order) from:
• $HPEESOF/ial/config  default file with full documentation at the end
• $HOME/pcbenv  copy eemom.option here and modify as needed
For design specific options, you can also place such file in the directory of a
design, with the name of the design. E.g.
• <name>.eemom for a design <name >.{brd|mcm|sip} file

A setting read later will override a previous value.

At least one option file must exist otherwise ADFI will not work.
Tip: The eemom.option file is your friend !!!
After making modifications, click „Reload Options‟.

ADFI Tutorial
37 March, 2011
Option File Sections

Each option file is a Skill “list expression” stored inside a file.

• Must start with “(setupData” and end with “)”
– Use an editor which checks balance of (…)
• Uses the Skill syntax for a hierarchical list of (name value(s))
• At least one of these option files must start with the general preferences
(requires restart of Allegro to update)
– (scratchLayerName "MANUFACTURING/EEM_SCRATCH")  cutter
layer
– (cutterExpansion 5.0)  initial cutter oversize distance
– (firstEgsLayerNum 1001)  first layer number used on ADS side
• The export options have the form (simulationSettings (setting …))

Let‟s review a couple of the most frequently used options…

ADFI Tutorial
38 March, 2011
Option File Sections – drillProps

This section allows to specify the

conductivity of the plating.
• Drill -1 means DRILL_THROUGH
• Drill -2 means DRILL_<i1i2>, the inter-
layer vias.

ADFI Tutorial
39 March, 2011
Option File Sections – simulationSettings

The options part contains a global list of settings, followed by

gnd and/or signal specific settings.

ADFI Tutorial
40 March, 2011
Option File Sections – simulationSettings (cont.)

Frequently (sometimes) used global settings:

Following is usefull for strip designs with many complex voids

Distance  distance to rect-bbox of line segments!

This void is ignored

This would
become void

Result is that cutter contour is kept as design contour as much as possible

ADFI Tutorial
41 March, 2011
Option File Sections – simulationSettings (cont.)

Frequently (sometimes) used global settings:

Export with target EMPro needs to use exporterMode 4.0 (default 4.5 with 4.1.5)
EMPro ADFI doesn‟t allow arcs without facetting to the given arc. resolution

Export to ADS use arced object representation when possible

Arced representation uses arced polygons or path/trace representation

Allow reuse of negative reference pins in multiple ports during export

ADFI Tutorial
42 March, 2011
Option File Sections – simulationSettings (cont.)

Frequently (sometimes) used global settings:

• A contour slot is created by default on negative layers exported as “SLOT” to keep

split ground structures separated
• This introduces an non-existent split/discontinuity in the ground plane structure that
can disturb the EM simulations
• This option set to “TRUE” asks the exporter to skip the
generation of this contour slot during the export
• Avoids editing the slot structure on the ADS
side, but, shorts split plane structures together
onto a perfect conducting plane
• If the split plane structure must be kept use
(negativeMasksToStrip “TRUE”)

ADFI Tutorial
43 March, 2011
Option File Sections – simulationSettings (cont.)

Never change these settings… unless as workaround by EEsof support

Problem observed when > 0!

Obsolete setting in 2009 version

ADFI Tutorial
44 March, 2011
Option File Sections – simulationSettings (cont.)

Frequently/Sometimes used gnd/signal specific settings

• padType: recommended „asDefined‟. Layout simplification will handle this.
• viaType: usefull if exact via model is not needed (e.g. for gnd vias).
• pathType: recommended „rounded‟. Layout simplification will handle this.
Tip: use „mitered‟ when you have problems with missing segments or flipped arcs
on traces (clines)
• Do you remember the padstack definition: „Allow suppression of
unconnected catch pads‟? Because ADFI can‟t get to this via property,
following option allows you to specify what to do:

ADFI Tutorial
45 March, 2011
 Enough on setup… Let‟s get to the real stuff…

ADFI Tutorial
46 March, 2011
Get some practice…

• Open cds_routed.brd
• Choose „Sample Fine Setting B‟ as
export setup
• Experiment with “CLK<i><+|->” signal
nets, and “VCC”/”GND” RF ground nets
• Upcoming slides bundle tips when
going through the steps.
• Try to add a large net (PCLK) keeping
the cookie cutter

ADFI Tutorial
47 March, 2011
Trace Select Hints

• When in a list area, type a character to go to first match.

• Hit TAB key in net filter with wildcards to update selectable net pool
• Multi-select lists shift, ctrl + mouse action work
• When using Pick Nets or Pick Nets by Comps:
– Watch out for the window / dialog focus!!!
– Start / End state button indicates if canvas is still in selection mode (End
indicates selection mode is active).
– When in selection mode, watch the Design Object Find Filter settings!!!
– Turn off visibility of planes if needed. Pick all nets of
Single Net Pick a component

ADFI Tutorial
48 March, 2011
Trace Select Hints

Electrical objects like vias, traces,

shapes not attached to a named net
can all be selected as RF Ground
objects
Cookie Cutter will cut through them

ADFI Tutorial
49 March, 2011
Layer Select Hints

• Export all layers unless there is a clear split of nets in the board.
• Adding infinite layers will cut substrate structure and adjusts via
connectivity
– RF Signal vias are cut one layer before
– RF Ground vias are shorted with the infinite plane
• Making just a sub selection of layers here will cut away pieces of the board
layout and may invalidate the connectivity

• So, use with care or stay away from it…

ADFI Tutorial
50 March, 2011
Cookie Cutter Hints

• Reuse allows to pick an earlier defined cutter

• Use Pick Shape and Build when you know the contour you want to use
or you have a large signal list and want to avoid the build delay
• Build for Signal Nets generic cutter operation if expensive use limited
set of nets and return

ADFI Tutorial
51 March, 2011
Cookie Cutter Hints

Move cookie cutter segments/vertices

• Select the cutter shape
– Verify the Filter settings!!!
– If wrong shape is selected, right click  Reject gives you a list of possible
shapes choose the scratch layer object.
– Once selected, you can move segment, vertices, delete vertices,…
– Don‟t forget to end your edit command with a Done or Cancel. This is visible by
a change in the display line width of the cutter polygon
Still in edit mode -> thin line Done  thick line

Avoid having to Edit the cookie cutter. Polygon editing is complicated.

ADFI Tutorial
52 March, 2011
Cookie Cutter Hints

Example: include a large signal net without enlarging the cookie

cut (e.g. add PCLK net)
• First make your selection without the large net
• Build the cookie cut
• Go back to net selection, add the large net to the signal nets. This will
invalidate the cookie cut
• Go back to cookie cutter, and click Reuse.
• You can now choose what to do with the large net: keep it or cut it.

ADFI Tutorial
53 March, 2011
Component/Pin Select Hints

Select the components to be transferred in a hierarchical export

• Available components have at least 1 pin on the selected nets (both signal
or RF ground) and are within the cookie cutter.
• Wildcard filtering can be done based on component name or attached nets

Select the pins that will be used for EM port generation

• Available pins are on the selected nets (both signal or RF ground) and
within the cookie cutter.
• The Selected Pins can be grouped by component export selection
• Wildcard filtering can be done based on pin or net names

ADFI Tutorial
54 March, 2011
Component/Pin Select Hints

• By default, all available pins on RF Signal nets

will be inserted in the selected set.
• Add RF Ground net pins manually
• When adding a component to the selection, e.g. Modifiable
pin set
R5, all available pins of that component (on
signal or RF ground nets and within the cookie
Can‟t modify
cut) will be added to the selection (and can be grouped pin lists
shown as grouped).
• If you want to remove pins of selected
components, disable Group by component
• Reset will clear the entire selected pin list.
Entire pin list
Go back to cookie cutter and return to re-initialize can change

the default selection.

ADFI Tutorial
55 March, 2011
Ports Generation Hints
An S-parameter port has a positive and a negative terminal (or reference) . Each terminal connects to
one or more pins. In the absence of a pin connection, the terminal is assumed to be connected to the
reference pin of the S-parameter model.
AutoPlace will generate S-parameter ports from the selected pin list automatically, which is sufficient
for standard cases.
Three flags control the port generation:

• Do not add negative reference pins: In case there is no infinite ground (no negative layer), the standard and
automatic creation of negative reference pins on the RF ground nets is suppressed by enabling this flag.
Tip: Enable this flag when:
– Proper S-parameter port references will be defined once in ADS. Make sure that RF ground pins were added to
the Selected pins so that can serve as reference pins once in ADS.
– You know that an infinite ground will be added in the ADS substrate. In such case, that infinite ground plane will
give a physical meaning to the reference pin of the S-parameter model.
• Combine on discrete: when the two pins of a discrete component are added to Selected pins, a single S-
parameter port will generated from these two pins.
• Start port name with ref. des.: will start the automatic port generation with instance name at start and sort
accordingly
TIP: Port editor in ADS2011.10 is much more advanced. For export to ADS 2011.10 just
create top pins and use the ADS port editor to combine these pins into ports after import.

ADFI Tutorial
56 March, 2011
Ports Generation Hints

You can refine the setup, e.g. combine 2 pins to define a port with a positive and negative
reference pin.
• Delete a port to free up the pin(s)

• Go to the port you want to add the pin to,

select Positive or Negative Reference Pins,
click Add, select the free pin you want to add,
click Apply.
• After editing the ports, click Verify/Update.

• Notes:
– Multiple pins can be grouped as positive or negative reference pins of a port.
– Manually create special ports first. This keeps their position at the start of the port list.
– A single pin cannot be used to define multiple S-parameter Ports. E.g. two S-parameters ports
sharing a common reference pin. Not supported in ADS 2009U1 and before by Momentum/FEM .

ADFI Tutorial
57 March, 2011
Flat export without components
Export To ADS/EMPro > Export > Selected
• Export > Selected As… allows you to specify an export file name. Be
careful with special characters in a name EGS importer can rename them
• During the export, Allegro can generate warnings/errors about shape
creation and boolean operations. These can often be ignored.
Errors like „unbound variable‟ or „fprintf wrong type of parameter nil‟ „E-
*Error* ilRplacd: Illegal operation: first argument in static space - (nil)‟
should not be ignored. They are almost always an export problem. When
this occurs, try a slightly different selection or setup setting i.e. (pathType
“mitered” for traces is a common problem)

ADFI Tutorial
58 March, 2011
Flat export without components
Export To ADS/EMPro > Export > Selected
• The export generates multiple files: 4 are used during the import of a flat
export/import
– <name>.ads : import control file
– <name>.slm : substrate stack for Momentum/EMDS
– <name>_a : EGS file with geometries
– <name>_ports.ael : ports definitions

• The <name>.ltd file is the substrate stack in Momentum technology format 

view/edit with the $HPEESOF_DIR/bin/eesofsubed(.exe) subtrate editor and
export slm from here.
Since 2009:
• Like other layers, drill holes get color
• Layers are ordered according to the cross section.

ADFI Tutorial
59 March, 2011
Hierarchical export with selected components
Export To ADS/EMPro > Export > Selected Hierarchy &
Export To ADS/EMPro > Export > To EMPro As …
• Export > Selected Hierarchy As… allows you to specify an export file
name.
• A hierarchical (assembly) design with <name>_adfi is created. That top-
level design contains:
– An instance of the board or package design (similar to the flat export
version)
– Instances of all selected components, including their selected pins, and
parameters attached to them.
– Layout Pins with properties that define the S-parameter Port setup
needed for an EM simulation.
– Transfers Allegro layer colors settings as rgb values. Picked up in the
workspace preferences but not in library because internal EGS import
defines library color mappings and has no public color map interface

ADFI Tutorial
60 March, 2011
Hierarchical export with selected components
Export To ADS/EMPro > Export > Selected Hierarchy &
Export To ADS/EMPro > Export > To EMPro As …

• The export generates one file during a hierarchical export for ADS or export
for EMPro
– <name>.adfi : xml descriptions with hierarchical export
• Still working with ADS 2009U1 but only when using exportMode < 4.2

ADFI Tutorial
61 March, 2011
 Finally… Let‟s see what we get into
ADS…

ADFI Tutorial
62 March, 2011
Import into ADS Hints

• When creating an ADS 2011 workspace, not longer needed to use technology
with a length unit that corresponds with the design units in Allegro!
• Not longer a must because importer creates a new
library with the correct units but still a good idea
 you should know where to find them in Allegro 

• ADS Import Design Kit can be found under $HPEESOF_DIR/ial/design_kit.

Always use the most recent version. When loaded, the Allegro Tools menu in a
Layout Window will be available.
– ADS 2011.10 shipped with ADFI version 4.1.4 and import kit version 3.3
– ADFI update version 4.1.5 ships with import kit 3.4.
– Check www.agilent.com/find/eesof-knowledgecenter and search for „Design
Flow Integeration‟ to find out about updates.
E.g. following slides are based on design kit version 3.5 with ADS 2011.10

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63 March, 2011
Allegro Import Preferences

The Ports section controls

• How pins and ports will be named, and
• What the text and port size will be.
After import, allows to update the ports,
either all or a selected subset.
A unit mismatch between ADS and
Allegro  wrong display sizes here!
The Substrate section allows to
override the substrate that gets loaded
during the import.
Connectivity can selectively be enabled
Schematic generation possible for
entire hierarchical design using net
labels

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64 March, 2011
Layer View Utilities

These menus toggle layer visibility

based on their location in the
substrate.
Tip: Assign hotkeys!

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65 March, 2011
Import Flat Allegro Layout from .ads file
Adfi > Import Allegro Layout…
• Layers and substrate get loaded. Layer binding is updated, cutter shape is
available on EEM_CUTTER:drawing layer.
• In case of slot layers, auxiliary slot shapes are passed that will support the
conversion of split ground planes from slot to strip.

Tip: switch to hierarchical transfer using adfi format

ADFI Tutorial
66 March, 2011
Split ground planes on negative layers
Allegro negative shield layers keep their cutouts in the plane  slots

can export
as slot layer

A slot contour is added to create isolated areas.

CAUTION: an isolated gnd shape cannot be electrically large for an
accurate Momentum simulation. The whole shape will be considered as
1 cell!
Pre ADS2009 ADS2009

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67 March, 2011
Ports Hints

• In case some, but not all, S-parameter

ports have a negative reference pin, a
warning is issued…

• Relevant Allegro information is attached

as properties to the Pins. E.g. net
name, pin name, number, etc.
• Port editor in ADS picks these up.

ADFI Tutorial
68 March, 2011
Port Hints

Enable filters The Ports Editor helps to manipulate

ports
• Provides an overview of S-parameter
Refresh
ports and Layout pins
Push column • Allows to sort on columns and filter
to sort
rows
• Select and multi-select in the layout
Right Click >
Cross select • Shows Allegro/APD/SiP net/pin
with layout
Property View properties if available on pins
Tip: Moving pins in layout from one
layer to another is easier…
– Select from (sorted) list in the port viewer
– In layout window
Edit >Properties
• Layer = use drop down list
• Hit Apply

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69 March, 2011
ADS Net Explorer (since ADS 2011.10)

Net Explorer replaces the ADFI Net

Viewer tool
• Uses net names from OA libraries
• Recognizes ADFI net properties
• Provides cookie cut functionality
• Powerfull highlight and select tool in
combination with PCE.

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70 March, 2011
Allegro Net View Hints (before ADS 2011.10)

Lists Allegro nets found from port properties!

Note: PCE must be enabled.

Check Tools > Use Physical Connectivity Engine

ADS net name(s) is between „(„ ‟)‟.

When there is more then 1, bullet will color red. Possible causes:

• ADS design is hierarchial (*_adfi.dsn). An ADS net (aka logical interconnect)

does not go into hierarchy! Hierarchy splits a net.
• PCE does not recognize connectivity
– Between shapes that are in touch with an infinite ground plane (slot layer).
– Through wire bonds
• Allegro net was cut
In such case, hit Enter to toggle over the Allegro pins. The ADS net
connected of the pin will be highlighted/selected.

When Auto Highlight is enabled, the physical interconnect which goes

through hierarchy will be highlighted.

When Auto Select is enabled, seleced ADS nets (logical interconnect) with
the connected component instances are selected.

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71 March, 2011
Allegro Net View Hints (before ADS 2011.10)

Selection Option
• S-parameter port
– All Allegro pins (= ADS Layout Pins)
connected to the S-parameter port are
selected.
• Layout port
– Allegro pin (= ADS Layout Port) is
selected.

S-parameter
port

ADFI Tutorial
72 March, 2011
Convert between strip and slot layers

Convert back and forth between strip

and slot layer representation
• Cutter layer used as boundary for
boolean operations on layer
(layer with “cutter” in the name)
• Oversize setting sometimes needed to
remove slivers
• From layers are existing strip/slot layers
• To layer must exist in layer list
• Substrate automatically adjusted
between strip and slot setting
Note: slot layers are ideal infinite
layers  conversion looses material
properties

ADFI Tutorial
73 March, 2011
Create Cadence IML file from simulation results

Transfer simulation results back to

Cadence analysis tools through an
IML file
• Touchstone file format with special
header
• Need dataset file of S-parameter
simulation with matching port setup of
the current design
• <datasetname>.iml file created in data
directory of the workspace allongside
the dataset
• Can be used by Cadence PI/SI option
in Allegro 16.3

ADFI Tutorial
74 March, 2011
Import with hierarchy from .adfi file
Adfi > Import Adfi File…
Import design: Select .adfi or .ads file
•cds_routed_16_adfi:Layout hierarchical
• Import kit will automatically import if a
<exportname>.adfi file exists when .ads is
selected
• Error, warning, info and debug messages
message windows and
in eemAdfiImport.log
• Main top level design <exportname>_adfi
• Board, Package, SiP design
[{brd_|sip_|apd_}]<allegro design>
• Instances of exported components are sub
designs using the reference designator from
Allegro platform
– No reuse with re-occurrence of cmp
– Pins lists can be incomplete

ADFI Tutorial
75 March, 2011
Import with hierarchy from .adfi file (ADS2011.10)
Adfi > Import Adfi File…
Select .adfi or .ads file (cont‟d)
• Figure objects in .adfi files use native
ADS path and primitive polygon
representation including arcs
• Area pins on all component pins
• Parameters and properties are
transferred where available
• Black box or look-alike symbol or R/L/C/D
symbol attached when recognized
• Default schematic for all discrete R/L/C
two pin components with ideal component
connected in schematic
• Import of hierarchical Layout with
Automatic schematic matching schematic possible in
generation during import ADS2011.10
• emSetup created for top level design

ADFI Tutorial
76 March, 2011
Import with hierarchy

Example 1: discrete SMD Capacitor

• Component designs have fixed layout
as extracted from Allegro with the
exported pins as area pins

• Default symbol attached if know

• Relevant parameters from Allegro are
picked up

ADFI Tutorial
77 March, 2011
Import with hierarchy

Example 2: multi-pin IC Pins limited to selected subset

(name/number issues possible)
• Allegro uses names and the number is
not relevant. For ADS it is generated
from name in export/import using
heuristic but not always correct.
• Footprint is correct pin name property is
matches with Allegro
• Pin numbering must be checked!!!
• Especially important when generating
Momentum/EMDS layout lookalike
symbols because can have renumber
issues

ADFI Tutorial
78 March, 2011
Import with hierarchy

Example design synchronisation with manual wiring for

cds_routed

ADS Design Synchronisation:

Place Components from
Layout to Schematic
+ Manual Wiring

Tip: Check symbol pin numbering if wiring error occur.

Symbol generation can get confused if components are partially exported

ADFI Tutorial
79 March, 2011
 Allegro PCB Let‟s have a look at Cadence
Done… SiP…
Allegro Package Designer …

ADFI Tutorial
80 March, 2011
Supported Allegro SPB Versions

SiP/Package Designer from Allegro SPB 16.01 and 16.[2-5]

– Partial stack support for Package Designer (APD) as there is no
guarantee for correct layer stack conversion
Skill 2011.10 ADFI has version 4.1.4 now update to 4.1.5

Use eemLocalConfig.scr to configure

Automatic menu load always enabled

ADFI Tutorial
81 March, 2011
SiP Basics – Cross Section

• Red = package substrate  a physical stack

• Blue above/below = die stack  only layer ordering is relevant.
No physical properties are attached. (!!! Different for APD !!!)
– DIESTACK is a conductor layer (DIE is name used in APD)
Where to find the physical information for the diestack???

ADFI Tutorial
82 March, 2011
SiP Basics – Rules for cross section

Define the Package Cross-Section (CDN SiP manual)

Choose Setup - Cross-Section from the menu in SiP Digital
Layout to open the stackup editor.
– Add the appropriate layers between the surfaces:
– Each flipchip die requires a CONDUCTOR layer and a DIELECTRIC
layer above and below it. Generally, you place flipchip dies on the top
package substrate or bottom package substrate, or both.
– Each wire bond die requires a DIESTACK layer outside the package
substrate with a DIELECTRIC layer above and below it.
– Each interposer requires a DIE layer outside the package substrate with
a DIELECTRIC layer above and below it.
– Each spacer requires a DIELECTRIC layer that is named to allow the
placement of geometry on it.

ADFI Tutorial
83 March, 2011
SiP Basics – Die Stack

Open Edit > Die Stack…

• Die stacks are always shown upwards.
• Die starts either from SUBSTRATE TOP or BOTTOM.
• Die uses only one conductor (ETCH) layer (Die placement layer)!
Die is a single layer pad stack.

ADFI Tutorial
84 March, 2011
SiP Basics – Another Cross Section

• SPACER: etch subclass in DIELECTRIC  how interpreted?

– When in substrate (red)  as plated via. Check if there is no padstack at
same XY. Right now, both will be exported!!!
– When in diestack (blue)  as dielectric via (brick)

ADFI Tutorial
85 March, 2011
SiP Basics – Ambiguous Cross Section

• This is flip-chip. IC pads are on TOP layer. In SiP database, die pads are
unconnected…  trouble stack!!!
– There must be DIELECTRIC in between.
– Solder bumps must be defined on L1 instead of TOP
• Such stack is typical after import of a version 15.x design into 16

ADFI Tutorial
86 March, 2011
SiP Basics – Wire Bond

Open Route > Wire Bond >

Settings… and choose View/Edit
wire profiles…
Or use toolbar buttons.

ADFI Tutorial
87 March, 2011
SiP Basics – View 3D Model

Open View > 3D Model… and click View.

Solder ball spheres and

soldermask info is added by
Cadence 3D viewer

ADFI Tutorial
88 March, 2011
 SiP Basics Next …
Done… The differences between SiP
and Package Designer (APD)

ADFI Tutorial
89 March, 2011
APD Differences – Cross Section

• Red = package substrate  a physical stack package

• Blue above/below = die level
Physical properties of layers are attached. (!!! Different for SiP !!!)
– DIE is a conductor layer (DIESTACK is name used in SiP)
All physical properties of the single component stack are found here

ADFI Tutorial
90 March, 2011
APD Differences – no special module elements

• Die stacks don‟t exist

– removed when importing SiP design in APD
– importing mcm into SiP may require update of cross section and layout
• Spacers and Interposers are mechanical symbols that exist between
dies in die stacks. Just as die stacks do not exist within APD, neither
do these elements. As a result, they are removed from the database
completely.
• Cross section layer stacking rules are identical to SiP
• Interpretation of cross section not uniquely defined
– APD allows definition of molding, solder mask properties in physical cross
section. SiP misses this capability in 16.01 to 16.5.
– APD cross section translation is difficult (user intervention needed to clear up
interpretation problems)

ADFI Tutorial
91 March, 2011
APD & SiP – Common Cross Section Problems

DIE layers HIWIRE and LOWIRE

should be separated by DIELECTRIC
Named solder mask layers like 5 in the
package substrate cause trouble
because of interpretation problems with
current interface
• Via layers like V12, V23 conducting are
blind and buried vias
• SOLD-TOP must be interpreted as
dielectric layer
Solder mask layers like13 ok for
bondwire design but will disconnect
dies in flip chip components
 Need more extensive mechanism to
properly represent these structures or
user must clean up before and after
transfer

ADFI Tutorial
92 March, 2011
 SiP/APD Basics ADFI is next…
Done…

ADFI Tutorial
93 March, 2011
Export to ADS

Setup…
• Nothing different from PCB Editor.
Select Traces…
• Nothing different from PCB Editor, except in the Layer Select tab. See next
slide
Flat Export
• Nothing different from PCB Editor. Wire bonds are exported as polygons on
special unmapped layer. Solder balls are ignored or created on special
unmapped mask layer.

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94 March, 2011
Layer Select
These are not the DIE balls!!!

Add package pin layer information

• Exports package pin shape on dedicated layer.
• With hierarchical export
– Mapped in substrate
– Package pins are connected at the board
level.
• Not mapped with flat export!!!

Add BGA solder ball data

• BGA ball data not accessible through Allegro
database API
• Exports package ball shape on dedicated layer.
– If specified diameter is bigger than contact
area above/below, diameter is clipped! This
is done to create valid Momentum via setup.
• Special component with ball properties as
parameters of component in hierarchical export

ADFI Tutorial
95 March, 2011
Component Select

Selection of components is identical as in

Allegro PCB
– The package/module is a named component
in SiP/APD, e.g. BGA
– Each die is also a component instance
– SiP diestacks: hidden component grouping
for stacked chips
• Created/picked up during export when
multiple chips are stacked or stack contains
bondwires
• Hidden if only one flip chip component is part
of a die stack
– Export of selected components
• Interposers and spacers are implicit
components added when needed
• add automatically all die shape as dielectric
brick if needed to have the correct diestack
structures
– Ports generated for the selected pins

ADFI Tutorial
96 March, 2011
Hierarchical export

Behaves as for Allegro PCB but adds

SiP and APD specific structures.
• Bondwires translated with profile and
grouped inside a component for each
diestack
 (GOLD wire if undefined material)
• Non-standard Bondwires supported
• Add flip chip die ball info from diestack
properties
• Material properties for dies added
Make sure you have  (SILICON when unknown)
these in materials in the
• Component based layer names added
mcmmat.dat (APD & SiP) when needed.
materials.dat (Allegro) The SiP/APD cross section layers are
used by the design!!!! insufficient for complex die structures.
• Hierarchical design stored in
<name>.adfi

ADFI Tutorial
97 March, 2011
 And Finally… Let‟s see what we get into
ADS…

ADFI Tutorial
98 March, 2011
ADS – Import into layout

Allegro Tools > Import Allegro

Layout picks up flat and hierarchical
export when the .ads and .adfi exist
-nn_b cell is a flat version
–nn_b_adfi is the hierarchical version
•BGA is package layout
•DIESTACKi contain stacked structures
•WB_<instance name> wire bond
component
•DIE<i> chip die instances

ADFI Tutorial
99 March, 2011
ADS – View the flat layout

Open <name>_lib:<name>:layout cellview Wire bonds are exported as polygons

or <name>.dsn pre ADS 2011 on special unmapped layer in flat
design
BGA balls added if enabled on
special unmapped layers (_Ppin and
_Pball)
Essentially just the package routing is
defined no 3D features above and
below

ADFI Tutorial
100 March, 2011
ADS – View the hierarchical layout

Open <name>_lib:<name>_adfi:layout All available 3D info is converted

cellview
Hierarchical import of components
View > 3D View > All
• Bondwires / Bonding ball / BGA solder
balls / Die stacks
• Dies are dielectric bricks in substrate
• Bondwires are combined SBOND
• Discrete components (RLC)
• Footprints of other components
• Parameters and properties attached when
possible
Schematic generation possible during import.
Design sync. from Layout to schematic
possible: go bottom through all hierarchy
levels (not recommended)

ADFI Tutorial
101 March, 2011
ADS – Symbol, item def + netlist CB for bondwires

Open a schematic window Bondwire WB_<die> components

Place a WB_<die> component • FEM and Momentum simulation
automatically picked on the SBOND
instances
• Also have a Philips model attached
Symbol +
Item definition + – Can be used directly from schematic
Netlist callback
– Netlists in real coordinates of design
– Height from ground needs to be set!

Netlist

ADFI Tutorial
102 March, 2011
ADS – Solder Ball component for BGA pins

Place in Layout or Schematic Solder ball properties derived from Layer

<package>_PIN_{TOP|BOTTOM} Select Tab in export
See parameter list: User can replace the simple via by a ball
3D component for FEM simulations if
needed by using these parameters
Ball substrates have been merged behind
the scenes with cross section substrate

ADFI Tutorial
103 March, 2011
ADS – flip chip Dies include bump info from SiP

From nn1_adfi:layout double click on For flip chip components die and bump
DIE5 instance attributes are translated from Cadence
SiP to ADS.
Ex. flip chip die on bottom of package (Not for APD as the info is not there)

Note: Pin shapes on the chip die are

defined by the pad shape on package
routing layer not by the IC mount pads
as they exist on the chip
– often results in strange substrate
because user tried to fix this in by
adding layers in SiP cross section.
– cause of many unconnected pins
problems
Always verify substrate !!!!

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104 March, 2011
 THE END…

ADFI Tutorial
105 March, 2011