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Lab 3 Combinational Logic Design (Canonical Form)

This lab manual document provides instructions for Lab 3 on combinational logic design. Students will analyze and implement combinational logic networks using canonical forms by: 1) writing the min terms and max terms for three input variables, 2) deriving the 1st and 2nd canonical forms, 3) constructing the circuits using ICs, and 4) testing the circuits and reporting the results. The objectives are to become familiar with combinational logic analysis and implementing networks in canonical forms using trainer boards, AND/OR gates, and inverters.

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Ifthakharul Alam Shuvo
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404 views3 pages

Lab 3 Combinational Logic Design (Canonical Form)

This lab manual document provides instructions for Lab 3 on combinational logic design. Students will analyze and implement combinational logic networks using canonical forms by: 1) writing the min terms and max terms for three input variables, 2) deriving the 1st and 2nd canonical forms, 3) constructing the circuits using ICs, and 4) testing the circuits and reporting the results. The objectives are to become familiar with combinational logic analysis and implementing networks in canonical forms using trainer boards, AND/OR gates, and inverters.

Uploaded by

Ifthakharul Alam Shuvo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical & Computer Engineering Lab Manual for CSE231

LAB 3: Combinational Logic Design


A. Objectives

 Become familiarized with the analysis of combinational logic networks.


 Learn the implementation of networks using the two canonical forms.

B. Theory
Min terms and max terms
Analysis of combinational logic design
Canonical Forms

C. Apparatus

 Trainer Board
 1 x IC 4073 Triple 3-input AND gates
 2 x IC 4075 Triple 3-input OR gates
 1 x IC 7404 Hex Inverters (NOT gates)

D. Procedure
1. Write down all the min terms and max terms of three inputs 𝐴𝐵𝐶 in Table F.1.
2. Write down the function 𝐹 in 1st and 2nd Canonical Forms in in Table F.2
3. Draw the circuits for the 1st and 2nd canonical forms of function in Figure F.1, clearly indicating the pin
numbers corresponding to the relevant ICs.
4. Construct the 1st canonical form of the circuit and test it with the truth table.
i. Connect one min term at a time and check its output.
ii. Once all min terms have been connected and verified, OR the min terms for the function output.
5. Construct the 2nd canonical form of the circuit and test it with the truth table.
i. Connect one max term at a time and check its output.
ii. Once all max terms have been connected and verified, AND the max terms for the function output.

E. Report
1. Draw the IC diagram for the 1st canonical form of the circuit in Figure F.1
2. Simulate the circuit for the 2nd canonical form in Figure F.1 in Logisim. Provide a screenshot of the
Logisim circuit schematic and truth table with your report.

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Department of Electrical & Computer Engineering Lab Manual for CSE231

F. Experimental Data

Experiment conducted by:

Name ID

Input
𝑨𝑩𝑪 𝑭 Min term Max term
Reference
0 000 0

1 001 1

2 010 1

3 011 0

4 100 0

5 101 0

6 110 1

7 111 0

Table F.1 Truth table to a combinational circuit

Shorthand Notation Function


1st Canonical
𝐹=Σ 𝐹=
Form
2nd Canonical
𝐹=Π 𝐹=
Form

Table F.2 1st and 2ndcanonical forms of the combinational circuit of


Table F.1

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Department of Electrical & Computer Engineering Lab Manual for CSE231

1st Canonical Form

2nd Canonical Form

Figure F.1 1st and 2nd canonical circuit diagrams of the combinational circuit of
Table F.1

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