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    Expt No.:5 Verilog Program For 3 To 8 Decoder Date

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    Sandhya Raghunath
    The document describes the development of a Verilog program for a 3-to-8 decoder circuit. It includes the theory of decoders, truth table, logic implementation using structural, behavioral and dataflow modeling in Verilog. Test benches are created to simulate and test the different Verilog models of the decoder. The simulation outputs verify the correct functionality of the 3-to-8 decoder circuit.

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    Expt No.:5 Verilog Program For 3 To 8 Decoder Date

    Uploaded by

    Sandhya Raghunath
    334 views11 pages
    The document describes the development of a Verilog program for a 3-to-8 decoder circuit. It includes the theory of decoders, truth table, logic implementation using structural, behavioral and dataflow modeling in Verilog. Test benches are created to simulate and test the different Verilog models of the decoder. The simulation outputs verify the correct functionality of the 3-to-8 decoder circuit.

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    Expt No5 1703099 Fpga

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    The document describes the development of a Verilog program for a 3-to-8 decoder circuit. It includes the theory of decoders, truth table, logic implementation using structural, behavioral and dataflow modeling in Verilog. Test benches are created to simulate and test the different Verilog models of the decoder. The simulation outputs verify the correct functionality of the 3-to-8 decoder circuit.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    334 views11 pages

    Expt No.:5 Verilog Program For 3 To 8 Decoder Date

    Uploaded by

    Sandhya Raghunath
    The document describes the development of a Verilog program for a 3-to-8 decoder circuit. It includes the theory of decoders, truth table, logic implementation using structural, behavioral and dataflow modeling in Verilog. Test benches are created to simulate and test the different Verilog models of the decoder. The simulation outputs verify the correct functionality of the 3-to-8 decoder circuit.

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    © All Rights Reserved
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    Expt No.

    :5

    Date: Verilog program for 3 to 8 Decoder

    AIM:

    To develop a Verilog program for a 3x8 decoder and to simulate and test the program using appropriate test bench
    Verilog program.

    Software used:

    • https://www.edaplayground.com/

    THEORY:

    Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n One of these outputs will be active
    High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a
    particular code. The outputs of the decoder nothing but the min terms of ‘n’ input variables lines, when it is
    enabled.

    TRUTH TABLE :
    LOGIC IMPLEMENTATION:

    VERILOG PROGRAM:

    STRUCTURAL MODELLING :

    DESIGN:

    module Decoder(A,B,C,D0,D1,D2,D3,D4,D5,D6,D7);

    input A,B,C;

    output D0,D1,D2,D3,D4,D5,D6,D7;

    wire Abar,Bbar,Cbar; not g1(Abar,A);

    not g2(Bbar,B); not g3(Cbar,C);

    and a0(D0,Abar,Bbar,Cbar); and a1(D1,Abar,Bbar,C); and a2(D2,Abar,B,Cbar); and a3(D3,Abar,B,C);


    and a4(D4,A,Bbar,Cbar); and a5(D5,A,Bbar,C);

    and a6(D6,A,B,Cbar);

    and a7(D7,A,B,C);

    endmodule

    TEST BENCH:

    module TestModule;

    // Inputs reg A; reg B; reg C;

    // Outputs wire D0; wire D1; wire D2; wire D3; wire D4; wire D5; wire D6; wire D7;

    // Instantiate the Unit Under Test (UUT)

    Decoder

    uut(.A(A),.B(B),.C(C),.D0(D0),.D1(D1),.D2(D2),.D3(D3),.D4(D4),.D5(D5), .D6(D6),.D7(D7));

    initial begin

    //Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    // Initialize Inputs

    A = 0;B = 0;C = 0;#10; A = 0;B = 0;C = 1;#10; A = 0;B = 1;C = 0;#10; A = 0;B = 1;C = 1;#10; A = 1;B = 0;C = 0;#10; A =
    1;B = 0;C = 1;#10; A = 1;B = 1;C = 0;#10; A = 1;B = 1;C = 1;

    end

    endmodule
    WAVEFORM:
    SIMULATION OUTPUT:

    BEHAVIOURAL MODELLING:

    DESIGN:

    module decoder3to8(x, enable, y);

    input [2:0] x; //this is my decoder input input enable;

    output [7:0] y;

    reg [7:0] y;

    always @(x, enable ) // begin

    if(enable==0)

    y = 8'b11111111;

    else //if enable is high...

    if (x == 3'b000) //...then we check our inputs and give corresponding outputs y = 8'b00000001;

    if (x == 3'b001)

    y = 8'b00000010;
    if (x == 3'b010)

    y = 8'b00000100;

    if (x == 3'b011)

    y = 8'b00001000;

    if (x == 3'b100)

    y = 8'b00010000;

    if (x == 3'b101)

    y = 8'b00100000;

    if (x == 3'b110)

    y = 8'b01000000;

    if (x == 3'b111)

    y = 8'b10000000;

    end endmodule

    TEST BENCH:

    module testbench_3to8decoder;

    reg [2:0] x; //use reg not wire to assign values wire [7:0] y; //for the outputs

    reg enable;

    decoder3to8 uut(x,enable,y); initial begin

    x = 3'b000;

    enable = 1'b0; //keep it off #10;//wait some time

    enable = 1'b1; //turn enable on #10; //wait some time

    x = 3'b001;

    #10; //wait some time x = 3'b010;

    #10; //then x = 3'b011; #10;

    x = 3'b100;
    #10; //wait some time x = 3'b101;

    #10; //then x = 3'b110; #10;

    x = 3'b111; #10;

    enable = 1'b0; //turn it off #10;

    end

    initial

    begin

    $dumpvars(0,testbench_3to8decoder);

    $dumpfile("my.vcd");

    $display ("value is %b %b", x,y); end

    endmodule
    WAVEFORM:

    SIMULATION OUTPUT:

    DATAFLOW MODELLING:

    DESIGN:

    module decoder(d,x,y,z); output [7:0] d;


    input x,y,z;

    assign d[0] = ~x & ~y & ~z; assign d[1] = ~x & ~y & z; assign d[2] = ~x & y & ~z; assign d[3] = ~x & y & z; assign d[4] =
    x & ~y & ~z; assign d[5] = x & ~y & z; assign d[6] = x & y & ~z; assign d[7] = x & y & z; endmodule

    TEST BENCH:

    module stimulus; wire [7:0]d;

    reg x,y,z;

    decoder my_decoder(d,x,y,z); initial

    begin

    $dumpfile("dump.vcd");

    $dumpvars(1); x=0;y=0;z=0;

    #10 x=0; y=0; z=1; #10 x=0; y=1; z=0; #10 x=0; y=1; z=1; #10 x=1; y=0; z=0; #10 x=1; y=0; z=1; #10 x=1; y=1; z=0; #10
    x=1; y=1; z=1;

    End

    endmodule
    WAVEFORM:

    S IMULATION OUTPUT :
    RESULT: Thus the verilog program for 3x8 decoder was implemented and results were obtained.

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