Digital System Design LAB 2

Spring 2021
Lab Report 2
IMPLEMENTATION OF COMBINATIONAL CIRCUITS

Course: Digital System Design (EE 320L)

Resource Persons: Sir Awais Saeed

Prepared By:
Shahzaib Ahmad Qureshi: F2016019065
Digital System Design LAB 2

IMPLEMENTATION OF COMBINATIONAL CIRCUITS

OBJECTIVES

• To write Verilog module for digital circuits at behavioral level

• To use case statements in Verilog HDL.
• To use if else statements in Verilog HDL.
• To write Verilog module for Decoders.
• To write Verilog module for Priority Encoders.
• To write Verilog module for Multiplexers.

INTRODUCTION

A number of standard combinational logic functions have been developed for digital circuits
that represent many of the useful tasks that can be performed with digital circuits.

Decoders detect the presence of particular binary states and can activate other circuits based
on their input values or can convert an input code to a different output code.

Encoders generate a binary or binary coded decimal (BCD) code corresponding to an active
input.

Multiplexers and de-multiplexers are used for data routing. They select a transmission path
for incoming or outgoing data, based on a selection made by a set of binary-related inputs.

DECODERS

The general function of a decoder is to activate one or more circuit outputs upon detection of
a particular digital state. The simplest decoder is a single logic gate, such as a NAND or AND,
hose output activates when all its inputs are HIGH. When combined with one or more
inverters, a NAND or AND can detect any unique combination of binary input values. An
extension of this type of decoder is a device containing several such gates, each of which
responds to a different input state. Usually, for an n-bit input, there are 2n logic gates, each
of which decodes a different combination of input variables. Some types of decoders translate
binary inputs to other forms, such as the decoders that drive seven-segment numerical
displays. The decoder has one output for every segment in the display. These segments
Digital System Design LAB 2

illuminate in unique combinations for each input code. Figure 1 shows the logic circuit of a 2-
line-to-4-line decoder.

Task1: 2-line-to-4-line Decoder with Enable (Gate Level Description)

Figure 1 2-line-to-4-line Decoder with Enable

A Verilog module is shown below. Create a new project using Xilinx ISE. Add this module to
project and verify it by simulating its behavior.

Verilog Module for 2X4 Decoder

module decoder_2x4_gates (D, A, B, enable);

output [0: 3] D;
input A, B;
input enable;
wire A_not,B_not, enable_not;
not
G1 (A_not, A),
G2 (B_not, B),
G3 (enable_not, enable);
nand
G4 (D[0], A_not, B_not, enable_not),
G5 (D[1], A_not, B, enable_not),
G6 (D[2], A, B_not, enable_not),
G7 (D[3], A, B, enable_not);
Endmodule
Digital System Design LAB 2

Test Bench for 2X4 Decoder

module decoder_2x4_gates_tb;

//
Inputs
reg A;
reg B;
reg enable;

// Outputs
wire [0:3] D;

// Instantiate the Unit Under Test (UUT)

decoder_2x4_gates uut (
.D(D),
.A(A),
.B(B),
.enable(enable)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
enable = 0;

// Wait 100 ns for global reset to finish

#100;

A = 1;
B = 0;
enable = 0;

// Wait 100 ns for global reset to finish

#100;

A = 0;
B = 1;
enable = 0;

// Wait 100 ns for global reset to finish

#100;
Digital System Design LAB 2

A = 1;
B = 1;
enable = 0;
// Wait
100 ns for global
reset to finish
#100;
// Add stimulus here

end

endmodule
Digital System Design LAB 2

Explain and record results for above Verilog module?

From the output we can see that when the input is 0111 the output is 0. When the
_
Input is 1101 the output is 1. And when the input is 1011 the output is 0. And for 1110 the
_
output is 1.
_

Draw results from Test bench? Indicate Input & Output signals?
Digital System Design LAB 2

Task2: 2-line-to-4-line Decoder with Enable (Data Flow Description)

A Verilog module is shown below. Create a new project using Xilinx ISE. Add this module to
project and verify it by simulating its behavior.

Verilog Module for 2X4 Decoder

module decoder_2x4_df (

output [0: 3] D, input

A, B, enable
);
assign D[0] = !((!A) && (!B) && (!enable)),
D[1] = !((!A) && B && (!enable)),
D[2] = !(A && B && (!enable)),
D[3] = !(A && B && (!enable));
endmodule

1. Test Bench for 2X4 Decoder

initial begin
// Initialize Inputs
A = 0; B = 0; enable = 0; #100;
A = 1; B = 0; enable = 0; #100;
A = 0; B = 1; enable = 0; #100;
A = 1; B = 1; enable = 0; #100;
// Add stimulus here
end
endmodule
Digital System Design LAB 2

Explain and record results for above Verilog module?

From the output we can see that when the input is 0111 the output is 0. When the
_
Input is 1111 the output is 1. And when the input is 1011 the output is 0. And for 1110 the
_
output is 1.

Draw results from Test bench? Indicate Input & Output signals?
Digital System Design LAB 2

MULTIPLEXER

Multiplexers are used for a variety of applications, including selection of one data stream out
of several choices, switching multiple-bit data from several channels to one multiple bit
output, sharing data on one output over time, and generating bit patterns or waveforms.

In Verilog, you must be aware that Case statements can be full or not full, and they can also
be parallel or not parallel. A Case statement is:

• FULL if all possible branches are specified.

• PARALLEL if it does not contain branches that can be executed simultaneously.

Task3: Two To One Line Multiplexer (Behavioral)

Verilog Module for 2X1 Mux

module mux_2x1_beh (m_out, A, B, select);

output m_out;
input A, B, select;
reg m_out;
always @(A or B or select)

if (select ==1) m_out = A; else

m_out = B;

endmodule
Digital System Design LAB 2

Test Bench for mux 2x1

initial begin
// Initialize Inputs
A = 0; B = 1; select = 0; #100;
A = 1; B = 1; select = 0; #100;
A = 0; B = 1; select = 0; #100;
A = 1; B = 0; select = 1; #100;
A = 0; B = 1; select = 1; #100;
A = 1; B = 0; select = 1; #100;
// Add stimulus here
end
endmodule

Draw results from Test bench? Indicate Input & Output signals?
Digital System Design LAB 2

Lab Task: Four to one line Multiplexer

Verilog Module for 4X1 Mux

module mux_4x1_gates(Y, A, B,C,D, S0,S1 );

output Y;
input A, B,C,D, S0,S1;
wire S0_not,S_not, Z1, Z2, Z3,Z4;
not
G1 (S0_not, S0), G2 (S1_not, S1);
and
G3 (Z1, S0_not, S1_not,A), G4 (Z2, S0_not, S1,B), G5 (Z3, S0, S1_not,C), G6 (Z4, S0,
S1,A);
or (Y , Z1, Z2, Z3, Z4);
endmodule
Digital System Design LAB 2

Test Bench for 4x1 Mux

initial begin

// Initialize Inputs

A = 1; B = 0; C = 0; D = 0; S0 = 0; S1 = 0; #100;

A = 0; B = 1; C = 0; D = 0; S0 = 1; S1 = 0; #100;

A = 0; B = 0; C = 1; D = 0; S0 = 0; S1 = 1; #100;

A = 0; B = 0; C = 0; D = 1; S0 = 1; S1 = 1; #100;

A = 0; B = 1; C = 1; D = 1; S0 = 0; S1 = 0; #100;

// Add stimulus here

end

endmodule

Draw results from Test bench? Indicate Input & Output signals?
Observations/Comments/Explanation of Results