DIGITAL SYSTEM DESIGN LAB 1

Spring 2021
Lab Report 1
INTRODUCTION TO THE DESIGNPROCEDURE FOR
COMBINATIONAL CIRCUITS, BASIC SYNTAX OF VERILOG AND
XILINX ISE TOOLS

Course: Digital System Design (EE 320L)

Resource Persons: Sir Awais Saeed

Prepared By:
Shahzaib Ahmad Qureshi: F2016019065
DIGITAL SYSTEM DESIGN LAB 1

INTRODUCTION TO THE DESIGNPROCEDURE FOR COMBINATIONAL

CIRCUITS, BASIC SYNTAX OF VERILOG AND XILINX ISE TOOLS
Objectives:
On successful completion of this lab, students will be able to:
a. Design the combinational digital circuits following the design procedure.
b. Create projects in Xilinx ISE environment.
c. Write Verilog HDL code for basic gates in Xilinx ISE environment.
d. Perform simulation of combinational digital circuits for testing using Xilinx ISE.

DESIGN PROCEDURE FOR COMBINATIONAL CIRCUITS IN

DIGTAL SYSTEM DESIGN:
Task

The design of combinational circuits starts from the specification of the Design
design objective and culminates in a logic circuit diagram or a set of Boolean specification
functions from which the logic diagram can be obtained. The procedure
involves the following steps: Truth Table
1. Identifying the task to perform. Boolean
2. Define the design specification.
functions
3. From the specifications of the circuit, determine the required number
of inputs and outputs and assign a symbol to each. Logic diagram
4. Derive the truth table that defines the required relationship between
inputs and outputs.
HDL code
5. Obtain the simplified Boolean functions for each output as a function
of the input variables.
6. Draw the logic diagram and verify the correctness of the design.
Simulation
7. Write the HDL code in Verilog/VHDL.
Implement
8. Perform simulation to verify the correctness of the design
9. Implementation of the design on FPGA
the design on
10. Testing the outputs FPGA

Testing

Figure 1 Design flow chat

DIGITAL SYSTEM DESIGN LAB 1

Design Problem 1:
Design a digital circuit which perform the adding of two binary bits and does not count the
carry generated in addition.
1. Identifying the Task to perform:
We have to add two binary bits without taking carry in the addition.
2. Define the design specification design specification:
The design circuit should add two binary bits. Simple addition in binary system has four possible
elementary operations: 0 +0=0, 0+1=1, 1+0=1, and 1+1=10. The first three operations produce a
sum of one digit, but when both augend and addend bits are equal to 1, the binary sum consists
of two digits. The higher significant bit of this result is called a carry and a combinational circuit
that performs the addition of two bits is called a half adder.
3. Inputs and outputs and assign a symbol to each:
From the verbal explanation of a half adder, we find that this circuit needs two binary inputs and
two binary outputs. The input variables designate the augend and addendbits; the output
variables produce the sum and carry.

x S

y Half Adder
C

Figure 2 Half Adder

We assign symbols x and y to the two inputs and S(for sum) and C(for carry) to the outputs.
4. Truth table:
The truth table for the half adder is listed in Table1. The Coutput is 1 only when both inputs are
1. The S output represents the least significant bit of the sum.
DIGITAL SYSTEM DESIGN LAB 1
Table 1

5. Simplified Boolean functions:

K-maps:

x x
y 0 1 y 0 1

0 0 0 0 0 1
0 1 0 1

1 0 1 1 1 0
2 3 2 3

C = xy 𝑆 = 𝑥`𝑦 + 𝑥𝑦`

The simplified Boolean functions for the two outputs can be obtained directly from the truth
table or by using the K-maps. The simplified sum-of-products expressions are:

𝑆 = 𝑥`𝑦 + 𝑥𝑦`
C = xy
6. Logic diagram:

Figure 3
DIGITAL SYSTEM DESIGN LAB 1

7. Write the HDL in Verilog:

7.1 Hardware description language

(HDL)?

Manual methods for designing logic

circuits are feasible only when the circuit is
small. For anything else (i.e., a practical
Figure 4
circuit), designers use computer-based
design tools. Coupled with the correct-by-
construction methodology, computer-based design tools. A hardware description language(HDL)
is a computer-based language that describes the hardware of digital systems in a textual form. It
resembles an ordinary computer programming language, such as C, but is specifically oriented to
describing hardware structures and the behavior of logic circuits. It can be used to represent logic
diagrams, truth tables, Boolean expressions, and complex abstractions of the behavior of a digital
system. One way to view an HDL is to observe that it describes a relationship between signals
that are the inputs to a circuit and the signals that are the outputs of the circuit. For example, an
HDL description of an AND gate describes how the logic value of the gate’s output is determined
by the logic values of its inputs.

7.2 Verilog HDL:

Verilog is a hardware description language. It was developed in the mid-1980s and later
transferred to the IEEE (Institute of Electrical and Electronics Engineers). The language is formally
defined by IEEE Standard 1364. The standard was ratified in 1995 (referred to as Verilog- 1995)
and revised in 200 1 (referred to as Verilog-2001). Many useful enhancements are added in the
revised version.Verilog is intended for describing and modeling a digital system at various levels
and is an extremely complex language.Although the syntax of Verilog is somewhat like that of
the C language, its semantics (i.e., "meaning") is based on concurrent hardware operation and is
totally different from the sequential execution of C.
DIGITAL SYSTEM DESIGN LAB 1

// basic templet
module<Module-name > ( <module-terminal-list> ) ;
//………………………….
<module internals >;
//………………………….
endmodule

Verilog Templet

Modules:
Verilog provides the concept of a module. A module is the basic building block in Verilog.
In Example 1 the first line of text is a comment (optional) providing useful information to the
reader. The second line begins with the keyword moduleand starts the declaration (description)

Of the module; the last line completes the declaration with the keyword endmodule. The
keyword moduleis followed by a name and a list of ports.

// Verilog model IEEE 1364–1995 Syntax

module Simple_Circuit (A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
endmodule

Example 1
Identifiers:
Identifiers are names given to modules, variables (e.g., a signal), and other elements of
the language so that they can be referenced in the design.In general, we choose meaningful
names for modules. Identifiers are composed of alphanumeric characters and the underscore (_),
and are case sensitive. Identifiers must start with an alphabetic character or an underscore, but
they cannot start with a number.
Port List:
DIGITAL SYSTEM DESIGN LAB 1
The port list of a module is the interface between the module and its environment. In this
example, the ports are the inputs and outputs of the circuit. The logic values of the inputs to a
circuit are determined by the environment; the logic values of the outputs are determined within
the circuit and result from the action of the inputs on the circuit. The port list is enclosed in
parentheses, and commas are used to separate elements of the list. The statement is terminated
with a semicolon (;). In our examples, port list are(A, B, C, D, E);
Keywords input and output:
The keywords inputand output specify which of the ports are inputs and which are
outputs.
Keyword wires:
Internal connections are declared as wires. The circuit in this example has one internal
connection, at terminal w1, and is declared with the keyword wire.

Keyword endmodule:
The module description ends with the keyword endmodule. Each statement must be
terminated with a semicolon, but there is no semicolon after endmodule.

7.3 Xilinx ISE:

In this part, you will use Xilinx's ISE to design, simulate and implement the design.
Step 1:
DIGITAL SYSTEM DESIGN LAB 1
Double click on the ISE icon to open up the development tools as shown below. There are
five general areas that will be of interest. At the top are the tool bars for file input and output,
for running of the various tools, and symbol inputs for the schematic capture. To the left are
Sources window and the Processes window and at the bottom is the display window. The user
work area is located to the right.

Step 2:
Now that the ISE is open, the next step is to open a project. You have to be careful about
where to save your projectin the computer lab. The computers in the lab run a hard disk
protection program that could interfere with Xilinx. So if you save your project in any folder,

Xilinx might have problem with running the simulation. You havetwo choices: (1) either save the
project directly on your USB flash disk. This option is good since your USB disk have normal
read/write access so Xilinx will run correctly. However, this option can be slow for USB flash disks.
The option (2) is to save the project in a folder that’s in the desktop. Start by creating a folder on
the desktop called ‘temp’. Create this folder in Windows, not from Xilinx. Then, in Xilinx, create a
new project inside temp. If your project is called ‘Lab1’, it will be in the folder
\Desktop\temp\Lab1. When you finish your lab, you can copy your project on yourflash disk.
DIGITAL SYSTEM DESIGN LAB 1
Start new project as follows:
a. File >> New Project

b. Give the project name as: Half_Adder.

Select location to save the project.
Select the top level module type as: HDL.
DIGITAL SYSTEM DESIGN LAB 1

c. Click Next.
d. This will lead to the configuration menu as shown below. The important items on
this menu are the FPGA type and the Preferred Language type. Select the
Preferred language type to VERILOGand the FPGA family to Aritix7, device to
XC7A100T and Speed to -3.

e. Click Next
DIGITAL SYSTEM DESIGN LAB 1

f. Click Finish
g. The screen will be like
DIGITAL SYSTEM DESIGN LAB 1
h. Select Project >> New Source

i. In the ‘New Source’ window:

Select ‘Verilog module’ out of different options available in the left hand
column. Give the file name as: Half_Adder.
DIGITAL SYSTEM DESIGN LAB 1

j. In the next window of ‘Define Verilog Source’:Simply click next. We shall not use
this option.Then click Finish.

k. You will see something like this:

DIGITAL SYSTEM DESIGN LAB 1

l. Enter the following Verilog Code in Half_Adder.v file and save the file

moduleHalf_Adder(S , C, x, y);
output S;
output C;
input x;
input y;
xor x1(S, x, y);
and a1(C, x, y);
endmodule
DIGITAL SYSTEM DESIGN LAB 1
m. In the ‘Processes Window’, located 2nd from the top on the left hand side, locate
the “Synthesize-XST” process and expand it by clicking on the small box containing
+ sign alongside it. Now, in the options available inside the “Synthesize-XST”

process, locate the “Check Syntax” step and click on it. A blue 3D cube will start
spinning and the message window at the bottom will start displaying messages. If
there are errors in the synthesis, a red circle with an X will appear. By clicking on
the Error tab in the message window at the bottom of the screen, the user can
view the error. Likewise, if there are warnings present, the user can view the
warning by clicking the warning tab. If the ISE was able synthesize the schematic,
a green check will appear in front of the Synthesize-XST process.
DIGITAL SYSTEM DESIGN LAB 1
8: Perform simulation to verify the correctness of the design
n. You will read this message in console when there is no syntax error Process
"Synthesize - XST" completed successfully
o. Make sure that Verilog code is free of any Syntax errors and the Check Syntax
process does not give any error. (Of course we are talking about half-adder you
just made.)
p. Moving on to simulating the Verilog module for half adder:
Select Project>> New Source

q. In the New Source Window, select the ‘Verilog Test Fixture’ out of different
options available in the left hand column and give the file name as
“Half_Adder_tb”. Click next and then next.
DIGITAL SYSTEM DESIGN LAB 1

r. Click Finish

s. The screen will look like:

DIGITAL SYSTEM DESIGN LAB 1

t. Now go to simulation tap at the top. Now your screen will become like this
DIGITAL SYSTEM DESIGN LAB 1

u. Uncheck the iSim Simulator and Perform the Behavioral Check Syntax. Then Run the
Simulation.If there are no errors, the simulation window appears showing the inputs as
defined by the test bench file and the appropriate output(s) as shown below. The
magnifying glasses can be used to zoom in or out. The enlarged view of the simulation
window was obtained by closing the Processes and Sources windows. These windows can
be reopened using the View menu and by selecting these windows. The user should check
the output and verify that this output follows the truth table .In this window, make sure
that the simulation time starts at ‘0’ ns, else move the scroll bar to the right and back to
the left. Remember to save a screen shot of this window for your report. When the user
is finished with the simulation window, the user can close it under the File menu - Close
item option.

Important NOTE: All Students should save the projects created for
performing task or design problems they have to implement the
design simulate in Next lab. -5 will be awarded in next lab if someone
does not have his files with him.
DIGITAL SYSTEM DESIGN LAB 1

Implementation of the design on FPGA and Testing the outputs will be cover in next lab.

Example:Verilog code of following circuit:

moduleSimple_Circuit (A, B, C, D, E);

output D, E;

input A, B, C;

wirew1;

and G1 (w1, A, B); // Optional gate instance name

not G2(E, C);

orG3 (D, w1, E);

endmodule
DIGITAL SYSTEM DESIGN LAB 1
Task 1: Design the basic logic gates using Verilog.
1. And,
2. Or,
3. Nand
4. Nor
5. Xor
6. Xnor

Verilog Module File.

module All_Gates_Task(A,O,NA,NO,XO,XN,X,Y);
output A,O,NA,NO,XO,XN;
input X,Y;
and A1(A,X,Y); or O1(O,X,Y); nand N1(NA,X,Y); nor N2(NO,X,Y);
xor X1(XO,X,Y); xnor X2(XN,X,Y);
endmodule
Verilog Module Test Bench File.
Initial begin
X = 0; Y = 0; #100;
X = 0; Y = 1; #100;
X = 1; Y = 0; #100;
X = 1; Y = 1; #100;
end
Verilog Module Output:
DIGITAL SYSTEM DESIGN LAB 1
Task 2: Write the Verilog code of following circuit diagram.

Verilog Module File:

module task2(S,C,x,y);
output S,C;
input x,y;
wire w1,w2;
and A1(w1,x,~y);
and A2(w2,~x,y);
or O1(S,w1,w2);
and A3(C,x,y);
endmodule
Verilog Module TB File:
initial begin
x = 0; y = 0; #100;
x = 0; y = 1; #100;
x = 1; y = 0; #100;
x = 1; y = 1; #100;
end
Verilog Module Output: