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Department of Computer Science and Engineering (CSE) : Islamic University of Technology (Iut)

The document is a final exam for a computer organization and architecture course. It contains 9 questions testing students' knowledge of topics like instruction pipelining, addressing modes, interrupt handling, cache/TLB operation, and disk performance metrics. The exam asks students to define terms, draw diagrams, perform calculations, and describe concepts at varying levels of detail.

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171 views3 pages

Department of Computer Science and Engineering (CSE) : Islamic University of Technology (Iut)

The document is a final exam for a computer organization and architecture course. It contains 9 questions testing students' knowledge of topics like instruction pipelining, addressing modes, interrupt handling, cache/TLB operation, and disk performance metrics. The exam asks students to define terms, draw diagrams, perform calculations, and describe concepts at varying levels of detail.

Uploaded by

Manus Human
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B.Sc. Engg.

in CSE / SWE (3rd Semester) 21 August 2020

ISLAMIC UNIVERSITY OF TECHNOLOGY (IUT)


ORGANISATION OF ISLAMIC COOPERATION (OIC)
Department of Computer Science and Engineering (CSE)
SEMESTER FINAL EXAMINATION WINTER SEMESTER, 2019-2020
DURATION: 1 Hour FULL MARKS: 50
CSE 4305: Computer Organization and Architecture
General Instructions
• Write your Name, Student-ID and Course Code on the top of the first page. Maintain a serial
number on the Top-right corner of each page.
• Answer all the questions. Figures in the right margin indicate marks.
• Sit in proper position and maintain the environment as per the Guidelines.
• No examinee is allowed to scan the file unless 1 hour is finished.
• For any circumstances, follow the instructions of the invigilator.

1 What is the difference between micro-operation and micro-instruction? Write the sequence 3+4
of events (micro-operations) of “interrupt cycle” symbolically employing common processor +3
registers with appropriate data flow diagram.

2 Many processor designs include a register or set of registers, often known as the program 3
status word (PSW) or flags, that contain status information. These flags typically contain
condition codes plus other status information resulted from the immediately last operation. If
the last operation was a subtraction operation between two operands, A and B containing
11110000 and 00010100 (i.e. A-B), what would be the value of any three of the following
flags?
i. Carry iv. Sign
ii. Zero v. Even Parity
iii. Overflow vi. Equal

3 Briefly describe different kinds of data hazards in any instruction pipeline system. 5
(Note: Appropriate examples from each type are highly appreciable).

4 The Intel 8088 consists of a bus interface unit (BIU) and an execution unit (EU), which form 2+3
a 2-stage pipeline. The BIU fetches instructions into a 4-byte instruction queue. The BIU also +3
participates in address calculations, fetches operands, and writes results in memory as
requested by the EU. If the bus is free and there is no outstanding requests and branch
instructions, then answer the following questions:
i. If the tasks done by the both units take equal time, by what factor does pipeline
improve the performance of the 8088?
ii. Draw the timing diagram of instruction pipeline operation for 5 instructions.
iii. If there are 100 instructions in a program to be executed by the 8088, calculate the
total time required to complete this program availing the instruction pipeline
advancement.
5 In a 16-bit processor, at a certain time of the execution of instructions from main memory, 6
following instructions are appeared (figure a):

Figure a: Contents of memory

Where XX denotes the opcode that instructs to load content to the register AC (accumulator),
MM signifies the mode field, YYYY contains the decimal value 500 and WXYZ indicates the
next instruction. For a specific mode, register R1 might be used containing the value 400.
Assume that location 399 contains 999, location 400 contains 1000 and onwards accordingly.
Determine the effective address and the operand to be loaded for any two of the following
address modes represented by MM:
i. Direct
ii. Indirect
iii. PC Relative
iv. Register
v. Register Indirect

6 Convert the following high-level language statement to corresponding machine language 4


program using one-address instruction format:
Y = (A 𝑋 B) + (C 𝑋 D) + E

7 Briefly describe the operation of the TLB and Cache to fetch any appropriate page in virtual 4
memory system following the depiction given in figure b:

Figure b: TLB and Cache operation

8 What are the design issues to implement an interrupt driven I/O if there are multiple I/O 5
devices? Mention the name of the appropriate approaches to overcome those issues.
9 Consider a magnetic disk drive with 10 surfaces, 600 tracks per surface, and 72 sectors per 5
track. Sector size is 512 B. The average seek time is 10 ms, the track-to-track access time is
1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without
head movement.
i. What is the disk capacity?
ii. What is the average access time? Assume this file is stored in successive sectors and
tracks of successive cylinders start at sector 0, track 0 of cylinder i.
iii. Estimate the time required to transfer a 5-MB file.

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