mips

Open RISC Technology

7/12/95

Differences between R10000 and R4400

R10000 R4400

Architecture Implementation Architecture Implementation

Superscaler Superpipeline
Speculative execution (branch No speculation
prediction)
Speculative memory access Execution in sequence
Out of order execution Processor stalls due to cache
Out of order cache miss detection miss
Non blocking Load/Store Pipeline stalls if to cache
miss

ISA ISA
MIPS IV set - Added Prefetch, MIPS III set
Conditional Move I/FP, Index
Load/Store FP, etc.
LL/SC, Sync definition and
Convert Long, Move instructions
different from those in R4400
Caches Caches
PI: 32K, 2-Way, 16Wd block PI: 16K, Direct map, 4 or 8Wd
PD: 32K, 2-Way, 8Wd block PD: 16K, Direct map, 4 or 8Wd

S: 512K-16M, 2-Way, SSRAM, 16 & S: 128K to 16M, Direct Map, 4 or

32 Wd block (no hardware change) 8 or 16 or 32Wd.

Instructions are 36-bits pre- Instructions are 32-bits (not

decoded pre-decoded)

Cache Coherency Cache Coherency

No Dirty Shared state Dirty Shared option

No Link Address Register - Link Address Register needed if

hardware makes sure the link linked line is replaced.
address is never replaced

pg1
 mips
Open RISC Technology

Differences between R10000 and R4400

R10000 R4400
CEx line is owned by memory CEx line is owned by the
processor.

Cache Algorithm Cache Algorithm

No update protocol Update protocol option

Added uncached accelerated No uncached accelerated

CP0 & Memory Management CP0 & Memory Management

TLB has 64 entries TLB has 48 entries

VPN of 44 bits VPN 40 bits

PFN of 40 bits PFN of 36 bits without any

restriction in any mode.
Phys. Addr. space is limited to
238 if TLB is written in the 32-
bit User or Supr. mode.
Prevents same multiple entry in Causes TLB Shutdown if more
TLB. than one match of VPN.
In 64-bit Kernel mode, the xkuseg
access is controlled by UX bit
& the xkseg access is controlled
No such control for the 32-bit
by the SX bit. In 64-bit
& 64-bit programs available
supervisor mode, xsuseg space
access is controlled by UX bit.
This means, the Address Space
Access control and TLB miss
exception vectors support
separate page table for 32-bit
and 64-bit programs
No CP0 hazards Hazards be’t CP0 instructions

CP0 Registers:
LLAddr Register removed because LLAddr Register available &
it is not necessary necessary

Added Diagnostic register Not available

pg2
 mips
Open RISC Technology

Differences between R10000 and R4400

R10000 R4400
Added Frame Mask Register to Framemask not available
masking of write into TLB[PFN]
Added Performance Counter Performance info from State
Registers Output pins.
Context/XContext do not share Context/XContext shares PTE
PTE Base Base
WatchHi adjusted to accommodate WatchHi smaller.
40 bits of physical address.
EntryLo/Hi bigger with new cache
EntryLo/Hi smaller
d coherency attributes
CacheErr & ECC are different
Config Register is different
Status Register is different
Cache Management
Cache Management
Hazards between CACHE/CP0
CACHE Instructions has no
instructions
hazards cause they are
serialized
No support for: Support for -
Create Dirty Exclusive Create Dirty Exclusive

Fill I Fill I

Hit Writeback Hit Write back

Hit Virtual Hit Virtual

Additional Instructions:
Index Load/Store Data (no No Index Ld/St Data
support needed for CE bit) Need CE bit
Read/Write is 36-bits pre- No pre-decode
decoded instructions to PICache
Cache Barrier instruction added Not applicable
Might bring lines in the cache
pg3
 mips
Open RISC Technology

Differences between R10000 and R4400

R10000 R4400
that never get used No speculation; so always gets
used.

System Interface
Four outstanding Processor Req. System Interface
Cluster bus configuration with Single request except if
eight outstanding request. “Cluster Request” selected
Request can depend on the
speculation and might not be
used.
Request can come in different Request always in order
order in different conditions;
but never indeterminate for the
any condition.
No link address retained bit Link retained bit needed
SysIntf & SCIntf de-coupled by No input buffers so speed on
Input Buffers SysIntf dependent on SCIntf.
Data ordering subblock Data ordering programmable
Eliminate Request No Eliminate Request
Open Drain option on System Intf. No open drain
Uncached Attributes added No Uncache Attribute
No output buffer slew rate Output buffer slew rate
adjustment. adjustment possible
“Globally Performed” pin added No “Globally Performed” pin

SCache Interface SCache Interface

Same hardware for 16Wd & 32Wd Need to worry about the LSB of
block size the Tag.
SSRAM, HSTL interface SRAM CMOS/TTL interface
No uncompelled slave state Uncompelled releases of the bus

pg4
 mips
Open RISC Technology

Differences between R10000 and R4400

R10000 R4400

Exceptions Exception
Aliasing prevented by the Aliasing handled by Virtual
hardware so no Virtual Coherency Exception
Coherency Exception
Can identify between the Soft Cannot differentiate be’t Soft
Reset & NMI Reset and NMI
Initialization Initialization
Mode bits entered in parallel Mode bits entered serially
Must write into the logical Not necessary to initialize
registers before reading register files
Interrupts Interrupts
Five hardwares by ext. request Six hardware interrupts via
using single cycle. write req. or pins
No hardware interrupts pins NMI via write or pin
No NMI by write (only pins) Timer Interrupt muxed by an
Timer Interrupt not muxed by external write
external write No Performance Counters (State
Performance counter causes Timer bits at the output)
Interrupt
Error protection Error protection
If DE bit is set, cache hits are If DE bit is set - always takes
taken when error is detected; so cache miss if uncorrectable
cache can get corrupted. Units error is detected.
detects & corrects but
exceptions are not taken. No
real need to set DE bit.
Option for parity check on SCache Data ECC - 8-bits for each DWd
read on the first pass.
Data ECC - 9-bits for QWd Single format Cache Error Reg.

pg5
 mips
Open RISC Technology

Differences between R10000 and R4400

R10000 R4400
Separate Cache Error Reg. format
for each caches & system intf. System Interface has a choice
System Interface has ECC only. of ECC or Parity.
UncorrErr*/CorrErr* signals.
Clocks Clocks
Input clock SysClk is used to RClock & TClock available to
clock external logic clock external logic.
SClkTap to adjust SCClk.
Not applicable SyncIn/SyncOut to adjust T/
RClock

MISC MISC
External Intf. CMOS/TTL or HSTL External Intf. CMOS/TTL

Can bring lines in the cache that Lines in cache will always be
may never be used used

pg6