IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

7, JULY 2014 3131

A Multifunctional DSTATCOM Operating

Under Stiff Source
Chandan Kumar, Student Member, IEEE, and Mahesh K. Mishra, Senior Member, IEEE

Abstract—Loads connected to a stiff source cannot be protected

from voltage disturbances using a distribution static compen-
sator (DSTATCOM). In this paper, a new control-algorithm-based
multifunctional DSTATCOM is proposed to operate in voltage
control mode under stiff source. This scheme provides fast voltage
regulation at the load terminal during voltage disturbances and
protects critical loads. In addition, during normal operation, the
generated reference load voltages allow control of the source cur-
rents. Consequently, DSTATCOM injects reactive and harmonic
components of load currents to make source power factor unity.
Simulation and experimental results are presented to verify the Fig. 1. Single-phase equivalent circuit of DSTATCOM in a distribution
efficacy of the proposed control algorithm and multifunctional network.
DSTATCOM.
Index Terms—Distribution static compensator (DSTATCOM), across the feeder impedance. When a load is connected to
multifunctional, power factor, stiff source, voltage regulation. nearly a stiff source, feeder impedance will be negligible [1]–
[4], [15], [16]. Under these circumstances, DSTATCOM cannot
I. I NTRODUCTION provide sufficient voltage regulation at the load terminal [9].
There is lack of literature addressing the feasibility of the VCM

A distribution static compensator (DSTATCOM) can mit-

igate several power quality (PQ) problems, depending
upon the mode of operation. In current control mode (CCM)
operation of DSTATCOM under stiff source. In present work,
this problem is addressed while ensuring that, during normal
operation, the advantages of CCM are retained.
[1]–[6], it injects harmonic and reactive components of load This paper proposes a new control-algorithm-based
currents to make source currents balanced, sinusoidal, and in DSTATCOM topology for voltage regulation even under stiff
phase with load voltages. In voltage control mode (VCM) source. It is achieved by connecting a suitable external inductor
[7]–[13], it regulates load voltage at a constant value to pro- in series between the load and the source point. The point of
tect sensitive loads from voltage disturbances such as sags, common coupling (PCC) will be the point where external in-
swells, transients, and/or fluctuations. However, the objectives ductor and source are connected. A DSTATCOM connected at
of these two modes are different and cannot be achieved the load terminal provides voltage regulation by indirectly reg-
simultaneously. ulating the voltage across the external inductor. The proposed
Based on the distance between source and load, a source is control algorithm to obtain variable reference load voltages is
termed as stiff or nonstiff. If the distance is long, then source formulated as a function of the desired source current. This
is termed as nonstiff and has high feeder impedance, whereas voltage indirectly controls the current drawn from the source
if the distance is very small, then source is termed as stiff and for a permissible range of source voltage. Therefore, the control
has negligible feeder impedance. Generally, a source (stiff or algorithm makes source currents balanced, sinusoidal, and in
nonstiff) supplies a permissible range of voltage, which is suffi- phase with respective source voltages during normal operation.
cient for satisfactory performance of load [14]. In this situation, During voltage disturbances, a constant voltage is maintained
DSTATCOM should operate in CCM. However, due to grid at the load terminal. Hence, the proposed topology and the
faults, the source voltage (stiff or nonstiff) can change at any control algorithm make the compensator multifunctional, so
time, and then, the VCM operation is required. DSTATCOM that it provides fast voltage regulation at the load terminal
regulates the load voltage by indirectly regulating the voltage and additionally provides advantages of CCM while operating
in VCM. Simulation and experimental results are presented
to verify the efficacy of the proposed control algorithm and
Manuscript received November 28, 2012; revised March 4, 2013 and June 7,
2013; accepted July 19, 2013. Date of publication August 6, 2013; date of
multifunctional DSTATCOM.
current version January 31, 2014. This work was supported by the Department
of Science and Technology, India, under the project grant DST/TM/SERI/
2k10/47(G). II. DSTATCOM C ONFIGURATION
The authors are with the Department of Electrical Engineering, Indian In-
stitute of Technology Madras, Chennai 600 036, India (e-mail: chandan3107@ A neutral-point-clamped voltage source inverter (VSI) topol-
gmail.com; [email protected]). ogy is chosen as it provides independent control of each
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. leg of the VSI [7]. A single-phase equivalent circuit of
Digital Object Identifier 10.1109/TIE.2013.2276778 DSTATCOM in a distribution network is shown in Fig. 1. The

0278-0046 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
3132 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 7, JULY 2014

VSI represented by uVdc is connected to the load terminal the permissible range, it is a sign of voltage disturbance, and a
through an LC filter (Lf − Cfc ). The load terminal is con- fixed voltage magnitude is selected as reference voltage. A two-
nected to the PCC through an external series inductance Lext . loop controller, whose output is load angle δ, is used to extract
Vdc is the voltage maintained across each dc capacitor, and load power and VSI losses from the source. Finally, a discrete
u is a control variable, which can be +1 or −1, depending model is derived to obtain switching pulses. All these steps are
upon switching state. ifi , ift , and ifc are currents through VSI, presented in detail in this section.
DSTATCOM, and Cfc , respectively. vs and vt are source and
load voltages, respectively. Loads have both linear and nonlin-
ear elements with balanced or unbalanced features. Load and A. Computation of Reference Voltage Magnitude (Vt∗ )
source currents are represented by il and is , respectively. During normal operation, load voltage must be regulated in
such a way that the following advantages provided by CCM
III. S ELECTION OF E XTERNAL I NDUCTOR operation are achieved.

Under normal operation, external impedance (Zext ) does 1) Source currents are balanced and sinusoidal.
not have much importance, whereas it plays a critical role 2) Unity power factor (UPF) at PCC.
during voltage disturbances. The value of external impedance 3) Source supplies load average power and VSI losses.
is decided by the rating of the DSTATCOM and amount of sag To achieve all aforementioned objectives, the instantaneous
to be mitigated. At any time, the source current in any phase by symmetrical component theory [15] is used to get reference
assuming balanced source voltage is given as source currents. DSTATCOM makes the load voltages balanced
and sinusoidal, but still may contain some switching harmonics,
Vs ∠0 − Vt ∠ − δ
Is = (1) which will give unacceptable reference source currents when
Rext + jXext directly used. Therefore, positive sequence components of load
+ + +
where Vs , Vt , Rext , Xext , and δ are the RMS source voltage, voltages (vta1 , vtb1 , and vtc1 ) are extracted and used to compute
RMS load voltage, external resistance, external reactance, and reference source currents (i∗sa , i∗sb , and i∗sc ) as follows:
load angle, respectively. For most practical case, Xext  Rext . +
vta1
As a worst case design, the reactive source current (Im[I s ]), i∗sa = (Plavg + Ploss )
which is supplied by the compensator, will be maximum when Δ+1
δ is minimum. For this, the source will supply only losses in +
vtb1
the VSI. Therefore, δ will be very small. Hence, Im[I s ] is i∗sb = (Plavg + Ploss )
Δ+1
given as
+
Vt − Vs vtc1
Im[I s ] = . (2) i∗sc = (Plavg + Ploss ) (4)
Xext Δ+1

During voltage disturbances, the aim is to protect the sensitive 

where Δ+ 1 =
+ 2
j=a,b,c (vtj1 ) , and Plavg is the average load
loads, with focus on improving the DSTATCOM capability to power that is calculated using a moving average filter (MAF).
mitigate deep sag. Therefore, keeping it into account, the load The total losses in the inverter, i.e., Ploss , computed using a
voltage during voltage sag is taken as 0.9 p.u. (per unit), which PI controller, helps in maintaining the averaged dc-link voltage
is sufficient to protect the load. Assuming that the reactive (Vdc1 + Vdc2 ) at a predefined reference value (2Vdcref ) by
current that a compensator can inject is 20 A and the load needs drawing a set of balanced currents from the source and is given
to be protected from sag of 40%, then the value of external as follows:
reactance is found to be 
0.9 − 0.6 Ploss = Kpdc e + Kidc e dt (5)
Xext = × 230 = 3.45 Ω. (3)
20
An external reactance of 3.45 Ω that corresponds to an induc- where Kpdc , Kidc , and e = 2Vdcref − (Vdc1 + Vdc2 ) are the
tance of 11 mH for a 50-Hz supply is used. proportional gain, integral gain, and voltage error of the
PI controller, respectively. Once the reference currents to be
drawn from the source are computed using (4), reference volt-
IV. P ROPOSED C ONTROL A LGORITHM
ages at the load terminal can be derived. Applying Kirchhoff’s
The proposed control algorithm aims to provide fast voltage voltage law in the circuit shown in Fig. 1:
regulation at the load terminal during voltage disturbances,
while retaining the advantages of CCM during normal opera- V s = I s Zext + V t . (6)
tion. First, the currents that must be drawn from the source to
get advantages of CCM are computed. Using these currents, the Source voltage and source current will be in phase for the UPF
magnitude of voltages that need to be maintained at the load operation. In addition, source voltage is taken as reference.
terminal is computed. If this voltage magnitude lies within a Therefore,
permissible range, then the same voltage is used as reference
voltage to provide advantages of CCM. If voltage lies outside Vs = Is (Rext + jXext ) + Vt ∠ − δ.
KUMAR AND MISHRA: MULTIFUNCTIONAL DSTATCOM OPERATING UNDER STIFF SOURCE 3133

represents power flow from load terminal to DSTATCOM. In

steady state, VSI losses are compensated by taking power from
the source. Hence, Psh will be negative in steady state.
Moreover, capacitor voltage decreases from its reference
value in steady state. The deviation of capacitor voltage from
reference voltage represents losses in the VSI. Hence, Ploss will
be negative during steady state. Therefore, at all times, Psh and
Ploss should be equal. Hence, the difference of Psh and Ploss
should be minimized. The output of the inner PI controller,
Fig. 2. Controller to calculate δ and Ploss . as shown in Fig. 2, is delta, which ensures that shunt-link
power Psh drawn from the source equals to losses in the capa-
From the previous equation, the load voltage can be computed citor Ploss .
as follows:

Vt = (Vs − Is Rext )2 + (Is Xext )2 . (7) C. Generation of Instantaneous Reference Voltage
By knowing the zero crossing of phase-a source voltage,
Based on standards, load voltage has a permissible range of
selecting a suitable reference load voltage magnitude from (8),
variations between 0.9 and 1.1 p.u. [14]. Therefore, as long as
and computing load angle δ from (9), the three-phase reference
Vt , obtained using (7), lies between 0.9 and 1.1 p.u., it is used
voltages are given as follows:
as reference load voltage (Vt∗ ), and the advantages of CCM
operation are achieved. Here, Vt is indirectly controlled by the √
vtrefa = 2Vt∗ sin(ωt − δ)
desired source current. During sag and swell, the load voltage
√
magnitude will be between 0.9 and 0.1 p.u. and 1.1 and 1.8 p.u., vtrefb = 2Vt∗ sin(ωt − 2π/3 − δ)
respectively, for half cycle to 1 min [16]. Therefore, reference
√
load voltage magnitude is set to 0.9 and 1.1 p.u. during sag vtrefc = 2Vt∗ sin(ωt + 2π/3 − δ) (11)
and swell, respectively. The reason to keep load voltages at
these values is to maximize the DSTATCOM disturbance with- where ω is the system frequency.
standing ability while keeping load voltage at the safe limits
for satisfactory operation. Therefore, the following conclusions
can be drawn: D. Generation of Switching Pulses
Each phase of the VSI can be controlled independently, and
If 0.9 p.u. ≤ Vt ≤ 1.1 p.u. then Vt∗ = Vt hence, a discrete model of single phase has been derived to
else If Vt > 1.10 p.u. then Vt∗ = 1.1 p.u. generate switching pulses. The dynamics of filter inductor and
capacitor can be presented by the following equations:
else If Vt < 0.9 p.u. then Vt∗ = 0.9 p.u. (8)
dvfc 1 1
= ifi − ift
dt Cfc Cfc
B. Computation of Load Angle (δ) difi 1 Rf Vdc
=− vfc − ifi + u. (12)
The block diagram of a controller to compute load angle δ dt Lf Lf Lf
is shown in Fig. 2. It ensures that the load average power and
losses in the VSI are supplied by the source [7]. Alternately, A matrix representation of (12) is given as follows:
Ploss responsible for maintaining dc-link voltage must be equal
ẋ = Ax + Bz (13)
to shunt-link power Psh . Comparing Ploss and Psh , an error is
generated, which is passed through a PI controller to compute where
δ as follows:    
 0 1/Cfc 0 1/Cfc
A= , B=
δ = Kpa (Ploss − Psh ) + Kia (Ploss − Psh )dt (9) 1/Lf −Rf /Lf Vdc /Lf 0
x = [ vfc ifi ] t , z = [u ift ]t .
where Kpa and Kia are the proportional and integral gains of
the inner PI controller, respectively. The value of shunt-link Equation (13), given in continuous form, can be represented in
power Psh is computed using a MAF as follows: a discrete-time form as follows:
t
1 +T
1 x(k + 1) = Gx(k) + Hz(k) (14)
Psh = (vta ifta + vtb iftb + vtc iftc )dt. (10)
T
t1 where matrices G and H are given as
   
A positive value of Psh represents power flow from G11 G12 H11 H12
G= , H= .
DSTATCOM to load terminal, whereas a negative value of Psh G21 G22 H21 H22
3134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 7, JULY 2014

Fig. 3. Phase-a waveforms before, during, and after load change. (a) Load
current. (b) Source voltage and source current (current is scaled up ten times Fig. 4. Phase-a waveforms before, during, and after sag. (a) Source voltage
for clear visibility). and source current (current is scaled up ten times for clear visibility). (b) Load
voltage.
From (14), capacitor voltage will be

vfc (k + 1) = G11 vfc (k) + G12 ifi (k) + H11 u(k) + H12 ift (k).
(15)
The reference voltage vtref is maintained at the load terminal.
A cost function J is chosen as

J = [vtref (k + 1) − vfc (k + 1)]2 . (16)

Fig. 5. (a) Load angle δ. (b) Voltage across dc bus.
Cost function is minimum when

vfc (k + 1) = vtref (k + 1). (17) 9.6 kW. The increase in load current in phase-a is shown
in Fig. 3(a). The source voltage and current waveforms of
Finally, the reference discrete voltage control law from (15) and phase-a before and after the load change are shown in Fig. 3(b).
(17) is given as It can be seen that both voltage and current are in phase with
each other. The load is brought back to its normal value at
vtref (k + 1)− G11 vfc (k) − G12 ifi (k) − H12 ift (k)
u∗ (k) = . t = 0.32 s. The controller takes one cycle to detect this change
H11 and brings back the source current at its normal value. The
(18)
current is in phase with source voltage. The entire transient is
u∗ (k) is regulated around a hysteresis band h to generate shown in Fig. 3(b). To show the voltage regulation capability
switching pulses of VSI using hysteresis control. of DSTATCOM, at t = 0.8 s, a sag is created by lowering the
source voltage by 30%, as shown in Fig. 4(a). A fast voltage
regulation is provided at the load terminal to protect sensitive
V. S IMULATION R ESULTS loads, while maintaining a voltage of 0.9 p.u., and is shown in
The proposed control algorithm and multifunctional Fig. 4(b). During sag period, source current will increase, as
DSTATCOM make three-phase source currents balanced, shown in Fig. 4(a). Voltage sag is cleared at t = 0.9 s, and then,
sinusoidal, and in phase with respective source voltages at load voltage starts following the source voltage, as illustrated
the PCC, within the permissible range of voltage. In addition, in Fig. 4(a). Consequently, the source current and the source
a fast voltage regulation at the load terminal is provided to voltage slowly come in phase with each other. Fig. 5(a) shows
protect sensitive loads during voltage disturbances. In addition, the load angle δ, which is regulated by a controller to ensure
load harmonic and reactive current components are supplied by that the average load power and inverter losses are taken from
the compensator all the time. All aforementioned advantages the source during normal operation, load change, and voltage
are verified in digital environment using PSCAD software. A disturbances. Fig. 5(b) shows the voltage at dc bus, which is
three-phase stiff source of 230 V rms per phase (1.0 p.u.) is regulated around 1200 V during the entire operation.
considered. Filter parameters are Lf = 20 mH, Cf = 10 μF,
Vdc = 600 V, and Cdc = 3000 μF. External inductance
VI. E XPERIMENTAL R ESULTS
Lext = 11 mH is used.
Initially, a three-phase unbalanced linear and nonlinear load To validate the performance of the proposed control-
of 6.9 kW is connected. At t = 0.2 s, load is increased to algorithm-based multifunctional DSTATCOM, an experimental
KUMAR AND MISHRA: MULTIFUNCTIONAL DSTATCOM OPERATING UNDER STIFF SOURCE 3135

VII. C ONCLUSION
In this paper, a new control algorithm based multifunctional
DSTATCOM has been proposed to protect the load from volt-
age disturbances under stiff source. It has been achieved by
placing an external series inductance of suitable value between
the source and the load. In addition, instantaneous reference
voltage is controlled in such a way that the source currents
are indirectly controlled, and the advantages of CCM opera-
tion are achieved while operating in VCM for a permissible
range of source voltage. The proposed algorithm and mul-
tifunctional DSTATCOM are able to mitigate voltage- and
Fig. 6. Experimental waveforms during normal operation in phase-a. current-related PQ issues, and confirmatory results have been
presented.

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3136 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 7, JULY 2014

Chandan Kumar (S’13) received the B.Sc. degree Mahesh K. Mishra (S’00–M’02–SM’10) received
in electrical engineering from the Muzaffarpur Insti- the B.Tech. degree from the College of Technology,
tute of Technology, Muzaffarpur, India, in 2009 and Pantnagar, India, in 1991, the M.E. degree from
the M.Tech. degree in electrical engineering from the University of Roorkee, Roorkee, India, in 1993,
the National Institute of Technology, Trichy, India, and the Ph.D. degree in electrical engineering from
in 2011. the Indian Institute of Technology, Kanpur, India,
He is currently a Research Student with the De- in 2002.
partment of Electrical Engineering, Indian Institute He has teaching and research experience of about
of Technology Madras, Chennai, India. His research 22 years. For about ten years, he was with the
interests include active power filters, power quality, Department of Electrical Engineering, Visvesvaraya
and renewable energy. National Institute of Technology, Nagpur, India. He
is currently a Professor with the Department of Electrical Engineering, Indian
Institute of Technology Madras, Chennai, India. His interests are in the areas
of power distribution systems, power electronics, microgrids, and renewable
energy systems.
Dr. Mahesh is a Life Member of the Indian Society of Technical Education.