From Discrete Logic to FPGAs

Full Adder
y The second basic
category of adder is the
full-adder. This
combinational circuit
performs the arithmetic
addition of three input
bits. The noticeable
difference between the
full- and the half-adder is
the ability of the former
to handle input carries
(Cin). The logical symbol
for the full-adder is
shown in Figure
Full Adder ‘Sum’ Equation
y By the very nature of the full
adder we know that the two
input bits must be added to
the carry input bit. Recall that
for the half-adder the sum of A
and B is the XOR of those two
variables
We can also use the Full Adder Truth
Table to come up with the same
equation (Recall the XOR Truth Table)
y Similarly, for the three
variables A, B and Cin the
sum becomes
Full Adder Carry Equation
Following are the minterms of Cout:
Cout= A’BCi + AB’ Ci + ABCi’ + ABCi
= Ci(A’B + AB’) + AB (Ci + Ci’)
= Ci(A’B + AB’) + AB
= Ci(A XOR B) + AB
The Full Adder Circuit is made up of
Halves
y Can you recognize
the 2 Half Adders
in this circuit?
Muxes as General-purpose Logic
¾ 2n:1 multiplexer implements any function of n variables
1. With the variables used as control inputs and
2. Data inputs tied to 0 or 1
3. In essence, a lookup table
¾ Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC

1 0
0 1
1 2
0 3
0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0

A B C
 Multiplexers as General-purpose
Logic (cont’d)
y 2n-1:1 mux can implement any function of n variables
y With n-1 variables used as control inputs and
y Data inputs tied to the last variable or its complement
y Example:
y F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC

1 0
0 1 A B C F
1 2 0 0 0 1 C'
0 3 0 0 1 0 C' 0
0 4 8:1 MUX 0 1 0 1 C' 1 4:1 MUX F
C'
0 5 0 1 1 0 0 2
F 1 0 0 0
1 6 0 1 3
S1 S0
1 7 1 0 1 0
S2 S1 S0 1 1 0 1 1
1 1 1 1 A B

A B C
Mux based Full-Adder
(Using 8-1 Mux)
Mux based Full-Adder
(Using two 4-1 Mux)
Mux based Full-Adder
(Using three 2-1 Mux)
The Programmable logic in an FPGA
` This is the essence of FPGA based design and
generally speaking that of VLSI design
` That is we map our large design onto the
available resources, in our case LUTs(Look-up
Tables) in an FPGA which are in essence
Programmable-Multiplexers
 Look Up Table (LUT) in an FPGA

¾ The LUT is used to realize any boolean function.

¾ Assume the function to be realized is y = (a&b) | !c
¾ This could be achieved by loading the LUT with the appropriate
output values
SRAM based Programmable Cell

¾ There are two main versions of semiconductor RAM devices:

dynamic RAM (DRAM) and static RAM (SRAM).
¾ RAM based devices can be used to control NMOS transistors
to be on/off.
¾ This can be very useful to control Multiplexers, Routing, e.t.c.
 Pass Transistor

¾ An SRAM cell can drive the gate (G) terminal of an NMOS

transistor.
¾ If SRAM (M) = 1 then signals passes from S Æ D
¾ An SRAM cell can be attached to the select line of a MUX to
control it.
 Configurable Logic Block

¾ A Configurable logic block consists of lookup table (LUT), a

register that could act as flip flop or a latch, and a mulitplexer,
along with a few other elements.
 Switch Matrix
¾ Connections between CLBs and IOBs are made using wiring
segments in both horizontal and vertical channels lying between
the various blocks.
¾ Four segments meet, on each there is 6 pass transistors.
Xilinx IOB
Xilinx FPGA Internals
¾ The logic within the
FPGA (Field
Programmable Gate
Array) is implemented in
an array of
programmable blocks
called CLBs
¾ Input/Output is handled
by IOBs
¾ The CLBs and IOBs are
interconnected by a
variety of programmable
interconnections (Switch
Matrix)
Spartan2
¾ 4K bit RAM
blocks
¾ Large amt of
logic
¾ Program stored
in SRAM
Xilinx CLB
 2001 – Virtex-II FPGA Family
y Virtex-II FPGA introduced followed by Virtex-II Pro in 2003
y 444 18x18 Multipliers & 18kbit block RAMs introduced
y Gbit Serial I/O Communications & Power PC Processors Introduced
y Complex Floating Point Algorithm Implementation now possible

„ Virtex-II / Pro
‰ 44,000 Logic Slices
‰ 444 18Kbits BRAMs
‰ 444 18x18 Multipliers
‰ 2 PowerPC
Processors
‰ 20 Gbit I/O
‰ 1164 Max User I/O
How to use an FPGA

By Example
IC Options: FPGAs and ASICs
y FPGAs
y A field-programmable gate array (FPGA) is an
integrated circuit designed to be repeatedly
configured by the customer or designer after
manufacturing.

y ASIC
y An application-specific integrated circuit
(ASIC) is an IC customized for a particular use, [1]

rather than intended for general-purpose use.

Both FPGAs and ASICs can be

designed using a Hardware
Description Language (HDL).

ASICS and
FPGAs
Digital Design Methodology
Design Specification
(Can me a functional Logic Synthesis and
model e.g. Simulink/C++ Gate-level Netlist
etc) (Structural Model)

Logic Verification and

Design Partition
Testing

Design Entry Floor Planning, Place

Verilog Behavioral and Route
Model

Tap
Simulation/Functional Physical Layout and e
Verification Verification out

Simplified typical design flow for designing ASICs

Language-Based Design
y Classical design methods relied on schematics.

y Today, computer-based languages are used to design

digital (and analogue) circuits:
y It is impossible to manually design and manage ICs containing
several million gates.

y Language-based designs are portable and technology

independent

y Designs can be easily modified and/or re-used for new

technology.

y Convenient medium for integrating Intellectual Property (IP) from

a variety of sources.

y Working circuit can be synthesized automatically from a

language-based description
HDLs
y An HDL can be viewed as a computer language
y Can print messages on screen
y You can make some simple programs

y But an HDL is NOT a software programming language.

HDL is used to describe and design hardware.

y An HDL needs to be able to model:

y Concurrency and
y Time
to enable it to design hardware.

y Software programming languages like C, C++ do not

inherently possess this capability.
y Note on SystemC; and HDL simulators too work on sequential processors!!
Verilog HDL
y These days there are two main HDLs
y VHDL (or VHSIC)HDL and
y Verilog or VerilogHDL

y Both are popular, though Verilog seems to be increasing

worldwide
y Verilog is easier to learn
y It is a lot like C, which makes it easy to learn but also easier to
confuse with C and make mistakes.
y VHDL is harder to program but its also harder to make mistakes in
VHDL – it is more idiot-proof
Design Abstractions
A Design specification of hardware can be Behavioral and
Structural.

Switch-Level Design
(Structural)
Structural
Modeling
Gate-Level Design (Structural)

Dataflow / RTL Modeling

Behavioral
Modeling

Algorithmic Modeling

Note that a single design (e.g. in Verilog) can contain

multiple design abstractions (Why?)
My First Hardware Description
y Designing a half-adder.
Simulation and Synthesis

• Simulation tools accept full set of Verilog

language constructs.

• Synthesis tools accept only a subset of the

full Verilog language constructs.

• We are going to use Xilinx ISE for both

simulation and synthesis.
• Why?
The Half Adder
y Here is a snapshot of the result of simulation on the
Xilins ISE (10.1)

y And here is the result of Synthesis on Xilinx ISE

RTL Schematic Technology Schematic