From Discrete Logic To Fpgas
From Discrete Logic To Fpgas
Full Adder
y The second basic
category of adder is the
full-adder. This
combinational circuit
performs the arithmetic
addition of three input
bits. The noticeable
difference between the
full- and the half-adder is
the ability of the former
to handle input carries
(Cin). The logical symbol
for the full-adder is
shown in Figure
Full Adder ‘Sum’ Equation
y By the very nature of the full
adder we know that the two
input bits must be added to
the carry input bit. Recall that
for the half-adder the sum of A
and B is the XOR of those two
variables
We can also use the Full Adder Truth
Table to come up with the same
equation (Recall the XOR Truth Table)
y Similarly, for the three
variables A, B and Cin the
sum becomes
Full Adder Carry Equation
Following are the minterms of Cout:
Cout= A’BCi + AB’ Ci + ABCi’ + ABCi
= Ci(A’B + AB’) + AB (Ci + Ci’)
= Ci(A’B + AB’) + AB
= Ci(A XOR B) + AB
The Full Adder Circuit is made up of
Halves
y Can you recognize
the 2 Half Adders
in this circuit?
Muxes as General-purpose Logic
¾ 2n:1 multiplexer implements any function of n variables
1. With the variables used as control inputs and
2. Data inputs tied to 0 or 1
3. In essence, a lookup table
¾ Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
1 0
0 1
1 2
0 3
0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0
A B C
Multiplexers as General-purpose
Logic (cont’d)
y 2n-1:1 mux can implement any function of n variables
y With n-1 variables used as control inputs and
y Data inputs tied to the last variable or its complement
y Example:
y F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
1 0
0 1 A B C F
1 2 0 0 0 1 C'
0 3 0 0 1 0 C' 0
0 4 8:1 MUX 0 1 0 1 C' 1 4:1 MUX F
C'
0 5 0 1 1 0 0 2
F 1 0 0 0
1 6 0 1 3
S1 S0
1 7 1 0 1 0
S2 S1 S0 1 1 0 1 1
1 1 1 1 A B
A B C
Mux based Full-Adder
(Using 8-1 Mux)
Mux based Full-Adder
(Using two 4-1 Mux)
Mux based Full-Adder
(Using three 2-1 Mux)
The Programmable logic in an FPGA
` This is the essence of FPGA based design and
generally speaking that of VLSI design
` That is we map our large design onto the
available resources, in our case LUTs(Look-up
Tables) in an FPGA which are in essence
Programmable-Multiplexers
Look Up Table (LUT) in an FPGA
Virtex-II / Pro
44,000 Logic Slices
444 18Kbits BRAMs
444 18x18 Multipliers
2 PowerPC
Processors
20 Gbit I/O
1164 Max User I/O
How to use an FPGA
By Example
IC Options: FPGAs and ASICs
y FPGAs
y A field-programmable gate array (FPGA) is an
integrated circuit designed to be repeatedly
configured by the customer or designer after
manufacturing.
y ASIC
y An application-specific integrated circuit
(ASIC) is an IC customized for a particular use, [1]
ASICS and
FPGAs
Digital Design Methodology
Design Specification
(Can me a functional Logic Synthesis and
model e.g. Simulink/C++ Gate-level Netlist
etc) (Structural Model)
Tap
Simulation/Functional Physical Layout and e
Verification Verification out
Switch-Level Design
(Structural)
Structural
Modeling
Gate-Level Design (Structural)
Algorithmic Modeling