Digital Voltmeters: Introduction, C Sharmila Suttur

RAMP technique, ECE, RIT

Dual slope integrating type DVM,
Successive approximations, 3 1/2 digit,
Resolution and sensitivity of digital meters,

General specifications of DVM Digital Instruments:

Digital tachometer, Digital PH meter,
Digital phase meter,
Frequency measurement, universal counter, Digital L, C and R measurements
Comparison between analog voltmeter and digital voltmeter (C Sharmila Suttur, ECE, RIT)

It has poor accuracy It has better accuracy

Digital Voltmeters: Introduction (contd)
Digital Multimeter
 Working Principle of Digital Voltmeter  

Explanation of various blocks:

 Input signal: It is basically the signal i.e. voltage to be measured.
 Pulse generator: Actually it is a voltage source. It uses digital, analog or both techniques to generate a
rectangular pulse. The width and frequency of the rectangular pulse is controlled by the digital circuitry
inside the generator while amplitude and rise and fall time is controlled by analog circuitry.
 AND gate: It gives high output only when both the inputs are high. When a train pulse is fed to it along
with rectangular pulse, it provides us an output having train pulses with duration as same as the rectangular
pulse from the pulse generator.
 Decimal Display: It counts the numbers of impulses and hence the duration and displays the value of
voltage on LED or LCD display after calibrating it.
Working of a digital voltmeter as follows:
 Unknown voltage signal is fed to the pulse generator which generates a pulse whose width is proportional
to the input signal.
 Output of pulse generator is fed to one leg of the AND gate.
 The input signal to the other leg of the AND gate is a train of pulses.
 Output of AND gate is positive triggered train of duration same as the width of the pulse generated by the
pulse generator.
 This positive triggered train is fed to the inverter which converts it into a negative triggered train.
 Output of the inverter is fed to a counter which counts the number of triggers in the duration which is
proportional to the input signal i.e. voltage under measurement.
 Thus, counter can be calibrated to indicate voltage in volts directly.
 We can see the working of digital voltmeter that it is nothing but an analog to digital converter which
converts an analog signal into a train of pulses, the number of which is proportional to the input signal. So a
digital voltmeter can be made by using any one of the A/D conversion methods.
 Ramp Technique

Ramp Technique – The operating principle is to measure the time that a linear ramp takes to change the
input level to the ground level, or vice-versa.
This time period is measured with an electronic time-interval counter and the count is displayed as a
number of digits on an indicating tube or display.
The operating principle and block diagram of a ramp type DVM are shown in Figs 

The ramp may be positive or negative; in this case a negative ramp has been selected.
 Ramp Technique (Cont)

At the start of the measurement a ramp voltage is initiated

The sample rate multivibrator determines the rate at which the measurement cycles are initiated. The
sample rate circuit provides an initiating pulse for the ramp generator to start its next ramp voltage. At the
same time a reset pulse is generated, which resets the counter to zero state.
The ramp voltage is continuously compared with the voltage that is being measured. At the instant these
two voltages become equal, a coincidence circuit generates a pulse which opens a gate, i.e. the input
comparator generates a start pulse.
The ramp continues until the second comparator circuit senses that the ramp has reached zero value. The
ground comparator compares the ramp with ground.
 Ramp Technique (Cont)

 When the ramp voltage equals zero or reaches ground potential, the ground comparator generates
a stop pulse. The output pulse from this comparator closes the gate. The time duration of the gate
opening is proportional to the input voltage value.
 In the time interval between the start and stop pulses, the gate opens and the oscillator circuit
drives the counter.
The magnitude of the count indicates the magnitude of the input voltage, which is displayed by the
readout. Therefore, the voltage is converted into time and the time count represents the magnitude
of the voltage.
The sample rate circuit provides an initiating pulse for the ramp generator to start its next ramp
voltage. At the same time a reset pulse is generated, which resets the counter to the zero state.

Advantages and Disadvantages

The ramp technique circuit is easy to design and its cost is low.
The output pulse can be transmitted over long feeder lines.
The single ramp requires excellent characteristics regarding linearity of the ramp and time
measurement.
Large errors are possible when noise is superimposed on the input signal. Input filters are usually
required with this type of converter.
 Dual Slope Integrating Type DVM(Voltage to Time Conversion)
Dual Slope Integrating Type DVM – In ramp techniques, superimposed noise can cause large errors. In the
dual ramp technique, noise is averaged out by the positive and negative ramps using the process of
integration.
Principle of Dual Slope Type DVM
As illustrated in Fig. 3, the input voltage ’ei’ is integrated, with the slope of the integrator output
proportional to the test input voltage.

After a fixed time, equal to t1, the input voltage is disconnected and the integrator input is con­nected to a
negative voltage — er The integrator output will have a negative slope which is constant and proportional to
the magnitude of the input voltage. The block diagram is given in Fig.
 Dual Slope Integrating Type DVM(Voltage to Time Conversion)

At the start a pulse resets the counter and the F/F output to logic level ‘0’.
 Si is closed and Sr is open. The capacitor begins to charge.
As soon as the integrator output exceeds zero, the comparator output voltage changes state, which opens
the gate so that the oscillator clock pulses are fed to the counter.
When the ramp voltage starts, the comparator goes to state 1, the gate opens and clock pulse drives the
counter.
 Dual Slope Integrating Type DVM(Voltage to Time Conversion)
 When the counter reaches maximum count the counter is made to run for a time ‘t1‘, in this case 9999.
 On the next clock pulse all digits go to 0000 and the counter activates the F/F to logic level ‘1’.
 This activates the switch drive, ei is disconnected and –er is connected to the integrator.
The integrator output will have a negative slope which is constant, i.e. integrator output now decreases
linearly to 0 volts.
Comparator output state changes again and locks the gate.
 The discharge time t2 is now proportional to the input voltage.
The counter indicates the count during time t2.
 When the negative slope of the integrator reaches zero, the comparator switches to state 0 and the gate
closes, i.e. the capacitor C is now discharged with a constant slope.
 As soon as the comparator input (zero detector) finds that e0, is zero, the counter is stopped.
The pulses counted by the counter thus have a direct relation with the input voltage.
During charging,

During discharging,
 Subtracting Eqs 2 from 1 we have

If the oscillator period equals T and the digital counter indicates n 1 and n2 counts respectively,

Now, n1 and er are constants.

 Dual Slope Integrating Type DVM (Contd.)
 From Eq.3 it is evident that the accuracy of the measured voltage is independent of the integrator time
constant.
The times t1 and t2 are measured by the count of the clock given by the numbers n1 and n2 respectively
 The clock oscillator period equals T and if n1 and er are constants, then Eq. 4 indicates that the accuracy
of the method is also independent of the oscillator frequency.
The dual slope technique has excellent noise rejection because noise and superimposed ac are averaged
out in the process of integration.
The speed and accuracy are readily varied according to specific requirements; also an accuracy of
± 0.05% in 100 ms is available.
Numericals
 Successive approximation DVM

Vin> vout  comp output  +VE  MSB bit is retained

Else Comp output  -VE  MSB bit is resets
•  A successive approximation type DVM works on the principle of measuring the weight of an object.
• In the case of a successive approximation type DVM it make use of a digital divider. A digital divider is
basically a digital to analog converter.
• Its basic block diagram is shown in Fig. 5.10.
• It consists of input attenuator and amplifier.
• The output of the input amplifier is given to the sample and hold circuit.
• There is a reference supply source whose output is given to the D/A converter.
• The output from the sample and hold circuit Vin and D/A converter output V out is given to a comparator.
• The output from the start stop multi -vibrator is given to the delay circuit.
• The delay circuit's output goes to the gate.
• The output of gate and the ring counter’s output are connected to the control register.
• The ring counter gives its output also to the start stop multi -vibrator.
• The control register's output goes to the digital readout circuitry.
• The ring counter then advances one count, shifting a 1 in the second MSB of the control
register and its reading becomes 11000000.
• This causes the D/A converter to increase its reference output by 1 increment to 1/4 V, i.e.
1/2 V + 1/4 V, and again it is compared with the unknown input.
• If in this case the total reference voltage exceeds the unknown voltage, the comparator
produces an output that causes the control register to reset its second MSB to 0.
• The converter output then returns to its previous value of 1/2 V and awaits another input
from the SAR.
• When the ring counter advances by 1, the third MSB is set to 1 and the converter output
rises by the next increment of 1/2 V + 1/8 V.
• Therefore measurement is completed in 8 cycle, proceeds through a series of successive
approximations.
• Finally, when the ring counter reaches its final count, the measurement cycle stops and
the digital output of the control register represents the final approximation of the
unknown input voltage.
• If the output of the digital to analog converter becomes equal to the unknown voltage in
terms of magnitude, the D/A converter generates the set pattern of voltages successively.
•  
• Our example 8-bit ADC can convert values from 0V to the reference
voltage.
• This voltage range is divided into 256 values, or steps.
• The size of the step is given by: Vref/256
1.09375
1.09375

1.0156

0.97725

0.99609
A typical sample and hold circuit stores electric charge in a capacitor and contains at least
one switching device such as a FET (field effect transistor) switch .
In the sample mode the switch is closed and the capacitor charges for the instantaneous value of
input voltage.
In the hold mode switch is opened and capacitor holds this instantaneous voltage
The actual conversion takes place when S/H circuit is in hold mode.
• When the start pulse signal activates the control circuit, the succes­sive
approximation register (SAR) is cleared.
• The output of the SAR is 00000000.
• Vout of the D/A converter is 0.
• Now, if Vin > Vout the comparator output is positive. Set bit =1
• During the first clock pulse, the control circuit sets the D 7 to 1, and Vout jumps to
the half reference voltage (1/2 Vref).
• The SAR output is 10000000.
• If Vout is greater than Vin the comparator output is negative and the control circuit
resets D7 ,i.e D7=0 set bit = 0,
• Tests the next bit D6.
It means that the most significant digit can be either 0 or 1.
A 3 digit numeric display can display numbers from 000 to 999. A 3.5 digit
display displays numbers from 000 to 1999 or twice as much.
By adding a relatively low cost display to the system the manufacturer
doubles the displayed range