Embedded System On Pci: Abstract
Embedded System On Pci: Abstract
Embedded System On Pci: Abstract
Tejaswini
ECE II year
ABSTRACT:
A split-transaction protocol is
The presentation involves the success of
implemented with attributed packets that
the widely adopted PCI bus and
are prioritized and optimally delivered to
describes a higher performance next
their target. The new PCI Express
generation of I/O interconnect, called
Architecture comprehends a variety of
PCIExpress* Architecture that will serve
form factors to support smooth
as a standard local I/O bus for a wide
integration with PCI and to enable new
variety of future computing platforms.
system form factors. PCI Express
Key PCI attributes, such as its usage
Architecture will provide industry
model and software interfaces are
leading performance and
maintained whereas its bandwidth-
price/performance.
limiting, parallel bus implementation is
replaced by a long-life, fully serial
interface.
The PCI bus has served us well for the last 10
years and it will play a major role in the next
few years. However, today’s and tomorrow’s
processors and I/O devices are demanding
INTRODUCTION: much higher I/O bandwidth than PCI 2.2 or
PCI-X can
deliver and it is time
The multiple, similar parallel buses of performance I/O. The switch is a logical
today’s platform are replaced with PCI element that may be implemented within
Express links with one or more lanes. a component that also contains a host
Each link is individually scalable by bridge, or it may be implemented as a
adding more lanes so that additional separate component. It is expected that
bandwidth may be applied to those links PCI will coexist in many platforms to
where it is required – such as graphics support today’s lower bandwidth
in the desktop platform and bus bridges applications until a compelling need,
(e.g. PCI Express-to-PCI-X) in the such as a new form factor, causes a full
server platform. A PCI Express switch migration to a fully PCI Express based
provides fanout capability and enables a platform
series of connectors for add-in, high
The server platform requires more I/O high bandwidth PCI Express links to
performance and connectivity including PCI-X slots, Gigabit Ethernet* and an
InfiniBand* fabric. Figure 5 shows how PCI Express for “inside the I/O and
PCI Express provides many of the same cluster interconnect, allows servers to
advantages for servers, as it does for transition from “parallel shared buses” to
desktop systems. The combination of a high speed serial interconnect
The remainder of this section will look transmit pair and a receive pair as shown
deeper into each layer starting at the in Figure 8. A data clock is embedded
bottom of the stack. using the 8b/10b-encoding scheme to
achieve very high data rates. The initial
frequency is 2.5 Giga
transfers/second/direction and this is
PHYSICAL LAYER: possible to increase with silicon
The bandwidth of a PCI Express link may be frequency of operation by the two agents at each
linearly scaled by adding signal pairs to form end of the link. No firmware or operating system
multiple lanes. The physical layer supports x1, software is involved.
x2, x4, x8, x12, x16 and x32 lane widths and
splits the byte data as shown in Figure 9. Each
byte is transmitted, with 8b/10b encoding, across Figure 9. A PCI Express Link consists of
the lane(s). This data disassembly and re- one or more lanes
assembly is transparent to other layers. During
initialization, each PCI Express link is set up
following a negotiation of lane widths and
LINK LAYER:
standard. Slated for release later this desktop devices, similar to how USB
year, the NEWCARD standard is devices can be shared. Desktop users
targeted for OEMs seeking small will benefit from NEW Cards plug-n-
footprint for thinner mobile designs and play ease of use, which eliminates the
sealed systems for desktop designs. need to open the chassis to add new
NEWCARD is the next evolution of the features. The new standard is operating
PC Card, combining a smaller form system independent.
factor and faster performance with the
PC Cards reliability and ease of use.
NEWCARD supports hot swappable
device sharing between mobile and
scalable performance will enable it to
CONCLUSION: become a unifying I/O solution across a
broad range of platforms – desktop,
The PCI Express Architecture meets all mobile, server, communications,
of the requirements of a third generation workstations and embedded devices. A
I/O bus. It’s advanced features and PCI Express link is implemented using
multiple, point-to-point connections
called lanes and multiple lanes can be
used to create an I/O interconnect whose
bandwidth is linearly scalable. This
interconnect will enable flexible system
partitioning paradigms at or below the
current PCI cost structure. PCI Express
is software compatible with all existing
PCI-based software to enable smooth
integration within future systems.
BIBILOGRAPHY:
www.softwaresolutions.com
www.embeddedsystems.net
www.pciexpressarchitecture.net
Electronics Maker magazine.
PCI architecture by David H. Albenosi.