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Digital Logic Design (DLD-lab) : M. Hamza Ilyas

This document describes an 8 to 3 encoder circuit designed by M. Hamza Ilyas for the Digital Logic Design lab. The encoder takes 8 input lines labeled Y7 to Y0 and generates a 3-bit binary code on the output lines A2, A1, and A0. It includes the circuit diagram, truth table, and Multisim simulations of the encoder circuit with 8 inputs.

Uploaded by

Hamza Gill
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
40 views

Digital Logic Design (DLD-lab) : M. Hamza Ilyas

This document describes an 8 to 3 encoder circuit designed by M. Hamza Ilyas for the Digital Logic Design lab. The encoder takes 8 input lines labeled Y7 to Y0 and generates a 3-bit binary code on the output lines A2, A1, and A0. It includes the circuit diagram, truth table, and Multisim simulations of the encoder circuit with 8 inputs.

Uploaded by

Hamza Gill
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment

Digital Logic Design


( DLD-lab)

BS-CS
SEC-3B

M. Hamza Ilyas
Bcsm-f19-397

Encoder 8 X 3.
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: Y7 to Y0 and 3 outputs: A2,
A1 & A0. Each input line corresponds to each octal digit and three outputs generate
corresponding binary code.
Circuit Diagram:

Truth table:

Multi-sim circuits:

1
VCC
5.0V

S1
2

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

3
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

4
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

5
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

6
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

7
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

8
VCC
5.0V

S1

X1

U3 2.5V

X2
OR4
U2 2.5V

X3
OR4
U1 2.5V

OR4

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