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VHDL TD - Corrigé

The document contains VHDL code for several digital logic circuits including: 1. A full adder and 8-bit adder circuit 2. A full subtractor and 8-bit subtractor circuit 3. 8-bit AND, OR, and multiplexer circuits 4. A 4-bit arithmetic logic unit (UAL) combining addition, subtraction, AND, and OR functions 5. JK flip-flop, 4-bit asynchronous and synchronous up counters using the JK flip-flop

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Sahsah Abdeslam
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275 views6 pages

VHDL TD - Corrigé

The document contains VHDL code for several digital logic circuits including: 1. A full adder and 8-bit adder circuit 2. A full subtractor and 8-bit subtractor circuit 3. 8-bit AND, OR, and multiplexer circuits 4. A 4-bit arithmetic logic unit (UAL) combining addition, subtraction, AND, and OR functions 5. JK flip-flop, 4-bit asynchronous and synchronous up counters using the JK flip-flop

Uploaded by

Sahsah Abdeslam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Université Sultan Moulay Slimane

Faculté des sciences et Techniques Béni Mellal


Département de Génie Electrique

Filière d’Ingénieur en Génie Electrique Troisième Année


Année Universitaire 2020/2021 – Semestre 5
Systèmes embarqués (DSP) – Travaux dirigés
Série N° : 2
Exercice 1 :
library ieee;
use ieee.std_logic_1164.all;
entity Fulladder is port (
a,b,cin : in std_logic;
s,cout : out std_logic
);
end Fulladder;
architecture my_fulladd of Fulladder is
begin
s <= a xor b xor cin;
cout <= (a and b) or (cin and (a or b));
end my_fulladd;
Exercice 2 :
library ieee;
use ieee.std_logic_1164.all;
entity Add8bits is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0);
cout : out std_logic);
end Add8bits;
architecture arch of Add8bits is
component Fulladder is port (
a,b,cin : in std_logic;
s,cout : out std_logic
);
end component;
signal S1,S2,S3,S4,S5,S6,S7 : std_logic;
begin
Fulladder1 : Fulladder port map (A(0),B(0),'0',S(0),S1);
Fulladder2 : Fulladder port map (A(1),B(1),S1,S(1),S2);
Fulladder3 : Fulladder port map (A(2),B(2),S2,S(2),S3);
Fulladder4 : Fulladder port map (A(3),B(3),S3,S(3),S4);
Fulladder5 : Fulladder port map (A(4),B(4),S4,S(4),S5);
Fulladder6 : Fulladder port map (A(5),B(5),S5,S(5),S6);
Fulladder7 : Fulladder port map (A(6),B(6),S6,S(6),S7);
Fulladder8 : Fulladder port map (A(7),B(7),S7,S(7),cout);
end arch;

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Université Sultan Moulay Slimane
Faculté des sciences et Techniques Béni Mellal
Département de Génie Electrique

Exercice 3 :
library ieee;
use ieee.std_logic_1164.all;
entity FullSub is port (
a,b,cin : in std_logic;
d,cout : out std_logic
);
end FullSub;
architecture arch of FullSub is
begin
d <= a xor b xor cin;
cout <= (not(a) and b) or (cin and (not(a) or b));
end arch;
Exercice 4 :
library ieee;
use ieee.std_logic_1164.all;
entity Sub8bits is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
D : out std_logic_vector(7 downto 0);
cout : out std_logic);
end Sub8bits;
architecture arch of Sub8bits is
component FullSub is port (
a,b,cin : in std_logic;
d,cout : out std_logic
);
end component;
signal S1,S2,S3,S4,S5,S6,S7 : std_logic;
begin
FullSub1 : FullSub port map (A(0),B(0),'0',D(0),S1);
FullSub2 : FullSub port map (A(1),B(1),S1,D(1),S2);
FullSub3 : FullSub port map (A(2),B(2),S2,D(2),S3);
FullSub4 : FullSub port map (A(3),B(3),S3,D(3),S4);
FullSub5 : FullSub port map (A(4),B(4),S4,D(4),S5);
FullSub6 : FullSub port map (A(5),B(5),S5,D(5),S6);
FullSub7 : FullSub port map (A(6),B(6),S6,D(6),S7);
FullSub8 : FullSub port map (A(7),B(7),S7,D(7),cout);
end arch;
Exercice 5 :
library ieee;
use ieee.std_logic_1164.all;
entity And8bits is port(
A,B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0)
);
end And8bits;

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Université Sultan Moulay Slimane
Faculté des sciences et Techniques Béni Mellal
Département de Génie Electrique

architecture arch of And8bits is


begin
S(0) <= A(0) and B(0);
S(1) <= A(1) and B(1);
S(2) <= A(2) and B(2);
S(3) <= A(3) and B(3);
S(4) <= A(4) and B(4);
S(5) <= A(5) and B(5);
S(6) <= A(6) and B(6);
S(7) <= A(7) and B(7);
end arch;
Exercice 6 :
library ieee;
use ieee.std_logic_1164.all;
entity Or8bits is port(
A,B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0)
);
end Or8bits;
architecture arch of Or8bits is
begin
S(0) <= A(0) or B(0);
S(1) <= A(1) or B(1);
S(2) <= A(2) or B(2);
S(3) <= A(3) or B(3);
S(4) <= A(4) or B(4);
S(5) <= A(5) or B(5);
S(6) <= A(6) or B(6);
S(7) <= A(7) or B(7);
end arch;
Exercice 7 :
library ieee;
use ieee.std_logic_1164.all;
entity MUX4x8_8 is port(
E1,E2,E3,E4 : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (1 downto 0);
S : out std_logic_vector (7 downto 0)
);
end MUX4x8_8;
architecture arch of MUX4x8_8 is
begin
With SEL select
S <= E1 when "00",
E2 when "01",
E3 when "10",
E4 when "11";
end arch;

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Université Sultan Moulay Slimane
Faculté des sciences et Techniques Béni Mellal
Département de Génie Electrique

Exercice 8 :
library ieee;
use ieee.std_logic_1164.all;
entity UAL is port(
A,B : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (1 downto 0);
R : out std_logic_vector (7 downto 0);
sout,rout : out std_logic
);
end UAL;
architecture arch of UAL is
component Add8bits is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0);
cout : out std_logic);
end component;
component Sub8bits is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
D : out std_logic_vector(7 downto 0);
cout : out std_logic);
end component;
component And8bits is port(
A,B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0)
);
end component;
component Or8bits is port(
A,B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0)
);
end component;
component MUX4x8_8 is port(
E1,E2,E3,E4 : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (1 downto 0);
S : out std_logic_vector (7 downto 0)
);
end component;
Signal S1,S2,S3,S4 : std_logic_vector(7 downto 0);
begin
AddOp : Add8bits port map (A,B,S1,sout);
SubOp : Sub8bits port map (A,B,S2,rout);
AndOp : And8bits port map (A,B,S3);
OrOp : Or8bits port map (A,B,S4);
MuxOp : MUX4x8_8 port map (S1,S2,S3,S4,SEL,R);
end arch;

-4-
Université Sultan Moulay Slimane
Faculté des sciences et Techniques Béni Mellal
Département de Génie Electrique

Exercice 9 :
library ieee;
use ieee.std_logic_1164.all;
entity JKH is port (
J,K,H,CLR,PRE : in std_logic;
Q,Qb : out std_logic
);
end JKH;
architecture arch of JKH is
signal S : std_logic;
begin
process (H,CLR,PRE)
begin
if (CLR = '0') then S <= '0';
elsif (PRE = '0') then S <= '1';
elsif (H'event and H='0') then
if (J='0' and K='0') then S <= S;
elsif (J='0' and K='1') then S <= '0';
elsif (J='1' and K='0') then S <= '1';
elsif (J='1' and K='1') then S <= not(S);
end if;
end if;
end process;
Q <= S;
Qb <= not(S);
end arch;

Exercice 10 :
library ieee;
use ieee.std_logic_1164.all;
entity CNT4bits_asyn is port (
CLK : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end CNT4bits_asyn;
architecture arch of CNT4bits_asyn is
component JKH is port (
J,K,H,CLR,PRE : in std_logic;
Q,Qb : out std_logic
);
end component;
signal S1,S2,S3,S4,a : std_logic;
begin
JKH1 : JKH port map('1','1',CLK,'1','1',S1);
JKH2 : JKH port map('1','1',S1 ,'1','1',S2);
JKH3 : JKH port map('1','1',S2 ,'1','1',S3);
JKH4 : JKH port map('1','1',S3 ,'1','1',S4);

-5-
Université Sultan Moulay Slimane
Faculté des sciences et Techniques Béni Mellal
Département de Génie Electrique

Q(0) <= S1;


Q(1) <= S2;
Q(2) <= S3;
Q(3) <= S4;
end arch;

Exercice 11 :
library ieee;
use ieee.std_logic_1164.all;
entity CNT4bits_syn is port(
CLK : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end CNT4bits_syn;
architecture arch of CNT4bits_syn is
component JKH is port (
J,K,H,CLR,PRE : in std_logic;
Q,Qb : out std_logic
);
end component;
Signal S1,S2,S3,S4 : std_logic;
Signal J1,J2,J3,J4 : std_logic;
Signal K1,K2,K3,K4 : std_logic;
begin
JKH1 : JKH port map (J1,K1,CLK,'1','1',S1);
JKH2 : JKH port map (J2,K2,CLK,'1','1',S2);
JKH3 : JKH port map (J3,K3,CLK,'1','1',S3);
JKH4 : JKH port map (J4,K4,CLK,'1','1',S4);
J1 <= '1';
K1 <= '1';
J2 <= S1;
K2 <= S1;
J3 <= S1 and S2;
K3 <= J3;
J4 <= J3 and S3;
K4 <= J4;
Q(0) <= S1;
Q(1) <= S2;
Q(2) <= S3;
Q(3) <= S4;
end arch;

-6-

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