VLSI TESTING 17EVE22

Sri AdichunchanagiriShikshana Trust (R)

SJB Institute of Technology

(Affiliated to Visvesvaraya Technological University, Belagavi& Approved by AICTE, New Delhi)
Department of Electronics and Communication

Course Code:
Course Title: VLSI Testing
17EVE22
Semester: vi Academic Year: 2017-18 Total hrs.: 50 Hrs./Week: 04
Int. Exam Hrs.:
Internal Evaluation Max. Marks: 20
01
Ext. Exam Hrs.:
Ext. Exam Max.Marks: 80
03
Lesson Plan Author / Desgn. / Dept.: Dr Ravi Kumar A V/ Asso. Professor/ ECE

Course Objectives:
This course will enable students to:
• Learn various types of faults and fault modeling

• Comprehend the need for testing and testable design of digital circuits

• Illustrate methods and algorithms for testing digital combinatorial networks and
test pattern generation

• Exemplify methods for testing sequential circuits and memory testing

• Inferring testing methods using Boundary scan, Built-in self test and other
advanced topics in digital circuit design.

Course outcomes: After studying this course, students will be able to:
• Analyze the need for fault modeling and testing of digital circuits
• Generate fault lists for digital circuits and compress the tests for efficiency

• Create tests for digital memories and analyze failures in them

• Apply boundary scan technique to validate the performance of digital circuits
• Design built-in self tests for complex digital circuits
Module / Unit Wise Plan

UNIT No. &

DAYS SUB TOPICS CO
Title
1 Failures and Faults, CO1
2 Modeling of faults, CO1

Dept.of ECE, SJBIT !1

VLSI TESTING 17EVE22

3 Temporary Faults. CO1

Logic Simulation: Applications, Problems in
4 CO2
simulation based design verification,
Module-1
5 Faults in types of simulation, CO1
6 digital The unknown logic values,. CO1
circuits:
7 CO1
compiled simulation, event-driven simulation,
8 CO1
Delay models,
9 Element evaluation, Hazard detection, CO2
10 Gate-level event-driven Simulation CO2
11 Fault Diagnosis of digital circuits, CO2
Test generation techniques for combinational
12 CO2
circuits,
Detection of multiple faults in Combinational
13 CO2
logic circuits.
----------------------------
14 CO2
Module-2 do--------------------------------
Testable Combinational logic circuit design:
15 Test generation The Read-Muller expansion technique, CO2
for
16 Combinational ---------------------------- CO2
Logic circuits: do--------------------------------
----------------------------
17 CO2
do--------------------------------
18 Three level OR-AND-OR design, CO2
19 Automatic synthesis of testable logic. CO2
----------------------------
20 CO2
do--------------------------------
Testable design of multilevel combinational
21 CO3
circuits,
Synthesis of random pattern testable
22 CO3
combinational circuits,
----------------------------
23 CO3
do--------------------------------

Module-3 Path delay fault testable combinational logic

24 CO3
Testable design,
Combinational
Dept.of ECE, SJBIT !2
VLSI TESTING 17EVE22
Testable
25 Combinational Testable PLA design. CO3
logic circuit
design: Test generation for Sequential circuits: Testing
26 of sequential circuits as Iterative combinational CO3
circuits,
27 state table verification, CO3
28 Test generation based on Circuit Structure, CO4
29 Functional Fault models, CO4
30 test Generation based on Functional Fault models. CO4
Design of testable sequential circuits:
31 CO5
Controllability and observability
32 Ad-Hoc design rules for improving testability CO5
33 design of diagnosable sequential circuits CO5
the scan-path technique for testable sequential
34 CO5
Module-4 circuit design,
35 Design of Level Sensitive Scan Design(LSSD), CO5
testable
36 sequential Random Access Scan Technique CO5
37 circuits: Partial scan CO5
testable sequential circuit design using Nonscan
38
Techniques,

39
Cross check,
40 Boundary Scan.
41 Test pattern generation for BIST, CO5
42 Output response analysis, CO5
----------------------------
43 CO5
do--------------------------------
44 Circular BIST, CO5
45 Module-5 BIST Architectures. CO5
Built-In Self
46 Test: Testable Memory Design: RAM Fault Models, CO5
47 Test algorithms for RAMs, CO5
48 Detection of pattern-sensitive faults, CO5
49 BIST techniques for RAM chips, CO5
50 Test generation and BIST for embedded RAMs. CO5

Dept.of ECE, SJBIT !3

VLSI TESTING 17EVE22

Reference / Text Book Details

Sl.No
Title of Book Author Publication Edition
.
New York,
. Digital Circuit Testing and
1 Lala Parag K., Academic 1997.
Testability,
Press,.
. Abramovici M,
Digital Systems Testing and
2 Breuer M A and Wiley, 1994
Testable Designǁ,
Friedman A D,

Dept.of ECE, SJBIT !4

VLSI TESTING 17EVE22

Index sheet

Sl No Unit & Topic of Discussion Page no

Module -1: Faults in digital circuits: 7

Failures and Faults,
Modeling of faults,
Temporary Faults.
Logic Simulation: Applications, Problems in
simulation based design verification,
types of simulation,
The unknown logic values,.
Failures and Faults,
compiled simulation, event-driven simulation, Delay
models,
Element evaluation, Hazard detection,
Gate-level event-driven Simulation
Module-2: Test generation for Combinational Logic
20
circuits:
Fault Diagnosis of digital circuits,
Test generation techniques for combinational circuits,
Detection of multiple faults in Combinational logic
circuits.
Testable Combinational logic circuit design: The
Read-Muller expansion technique,
Three level OR-AND-OR design,
Automatic synthesis of testable logic.
Module -3: 34
Testable design of multilevel combinational circuits,
Synthesis of random pattern testable combinational
circuits,
Path delay fault testable combinational logic design,
Testable PLA design.

Dept.of ECE, SJBIT !5

VLSI TESTING 17EVE22

Test generation for Sequential circuits: Testing of

sequential circuits as Iterative combinational circuits,
state table verification,
Test generation based on Circuit Structure,
Functional Fault models,
test Generation based on Functional Fault models.
Module 4: Design of testable sequential circuits 42
Design of testable sequential circuits: Controllability
and observability
Ad-Hoc design rules for improving testability
design of diagnosable sequential circuits
the scan-path technique for testable sequential circuit
design,
Level Sensitive Scan Design(LSSD),
Random Access Scan Technique
Partial scan
testable sequential circuit design using Nonscan
Techniques,

Cross check,
Boundary Scan.
Module-5
68
Built-In Self Test:
Test pattern generation for BIST,
Output response analysis,
Circular BIST,
BIST Architectures.
Testable Memory Design: RAM Fault Models,
Test algorithms for RAMs,
Detection of pattern-sensitive faults,
BIST techniques for RAM chips,
Test generation and BIST for embedded RAMs.

Dept.of ECE, SJBIT !6

VLSI TESTING 17EVE22

Module -1: Faults in digital circuits:

FAULTS IN LoGIC CIrCUITS

A failure is said to have occurred in a logic circuit or system if it deviates from its speci ed
behavior [1]. A fault, on the other hand, refers to a physical defect in a circuit. For example, a
short between two signal lines in the circuit or a break in a signal line is a physical defect. An
error is usually the manifestation of a fault in the circuit; thus a fault may change the value of
a signal in a circuit from 0 (correct) to 1 (erroneous) or vice versa. However, a fault does not
always cause an error; in that case, the fault is considered to be latent.
A fault is characterized by its nature, value, extent, and duration [2]. The nature of a fault can
be classi ed as logical or nonlogical. A logical fault causes the logic value at a point in a
circuit to become opposite to the speci ed value. Nonlogical faults include the rest of the
faults such as the malfunction of the clock signal, power failure, etc. The value of a logical
fault at a point in the circuit indicates whether the fault creates xed or varying erroneous
logical values. The extent of a fault speci es whether the effect of the fault is localized or
distributed. A local fault affects only a single variable, whereas a distributed fault affects
more than one. A logical fault, for example, is a local fault, whereas the malfunction of the
clock is a distributed fault. The duration of a fault refers to whether the fault is permanent or
temporary.
1.1.1 Stuck-At Fault
The most common model used for logical faults is the single stuck-at fault. It assumes that a
fault in a logic gate results in one of its inputs or the output is xed at either a logic 0 (stuck-
at-0) or at logic 1 (stuck-at-1). Stuck-at-0 and stuck-at-l faults are often abbreviated to s-a-0
and s-a-1, respectively.
Let us assume that in Figure 1.1 the A input of the NAND gate is s-a-1. The NAND gate
perceives the A input as a logic 1 irrespective of the logic value placed on the input. For
example, the output of the NAND gate is 0 for the input pattern A=0 and B=1, when input A
is s-a-1 in. In the absence of the fault, the output will be 1. Thus, AB=01 can be considered as
the test for the A input s-a-l, since there is a difference between the output of the fault-free
and faulty gate.
The single stuck-at fault model is often referred to as the classical fault model and offers a
good representation for the most common types of defects [e.g., shorts and opens in
complementary

Dept.of ECE, SJBIT !7

VLSI TESTING 17EVE22

metal oxide semiconductor (CMOS) technology]. Figure 1.2 illustrates the CMOS realization
of the two-input NAND:
The number 1 in the gure indicates an open, whereas the numbers 2 and 3 identify the short
between the output node and the ground and the short between the output node and the VDD,
respectively. A short in a CMOS results if not enough metal is removed by the
photolithography, whereas over-removal of metal results in an open circuit [3]. Fault 1 in
Figure 1.2 will disconnect input A from the gate of transistors T1 and T3. It has been shown
that in such a situation one tran- sistor may conduct and the other remain nonconducting [4].
Thus, the fault can be represented by a stuck at value of A; if A is s-a-0, T1 will be ON and
T3 OFF, and if A is s-a-l, T1 will be OFF and T3 ON. Fault 2 forces the output node to be
shorted to VDD, that is, the fault can be considered as an s-a-l fault. Similarly, fault 3 forces
the output node to be s-a-0.
The stuck-at model is also used to represent multiple faults in circuits. In a multiple stuck-at
fault, it is assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0;
in other

words, a group of stuck-at faults exist in the circuit at the same time. A variation of the
multiple fault is the unidirectional fault. A multiple fault is unidirectional if all of its
constituent faults are either s-a-0 or s-a-l but not both simultaneously. The stuck-at model has
gained wide acceptance in the past mainly because of its relative success with small scale
integration. However, it is not very effective in accounting for all faults in present day very
large scale integrated (VLSI), circuits which mainly uses CMOS technology. Faults in CMOS
circuits do not necessarily produce logical faults that can be described as stuck-at faults [5, 6,
7]. For example, in Figure 1.2, faults 3 and 4 create stuck-on transistors faults. As a further

Dept.of ECE, SJBIT !8

VLSI TESTING 17EVE22

example, we consider Figure 1.3, which represents CMOS implementation of the Boolean
function:
Z = (A + B)(C + D) · EF .
Two possible shorts numbered 1 and 2 and two possible opens numbered 3 and 4 are indi-
cated in the diagram. Short number 1 can be modeled by s-a-1 of input E; open number 3 can
be modeled by s-a-0 of input E, input F, or both. On the other hand, short number 2 and open
number

Dept.of ECE, SJBIT !9

VLSI TESTING 17EVE22

cidentally connected together. Earlier study of bridging faults concentrated only on the
shorting of signal lines in gate-level circuits. It was shown that the shorting of lines resulted
in wired logic at the connection.
Bridging faults at the gate level has been classi ed into two types: input bridging and
feedback bridging. An input bridging fault corresponds to the shorting of a certain number of
primary input lines. A feedback bridging fault results if there is a short between an output and
input line. A feed- back bridging fault may cause a circuit to oscillate, or it may convert it
into a sequential circuit.
Bridging faults in a transistor-level circuit may occur between the terminals of a transistor or
between two or more signal lines. Figure 1.5 shows the CMOS logic realization of the
Boolean function:
Zl =Z2 =AB+CD

A short between two lines, as indicated by the dotted line in the diagram will change the
function of the circuit.
The effect of bridging among the terminals of transistors is technology-dependent. For ex-
ample, in CMOS circuits, such faults manifest as either stuck-at or stuck-open faults,
depending on the physical location and the value of the bridging resistance.

Dept.of ECE, SJBIT !10

VLSI TESTING 17EVE22

1.1.3 delay Faults

As mentioned previously, not all manufacturing defects in VLSI circuits can be represented
by the stuck-at fault model. The size of a defect determines whether the defect will affect the
logic func- tion of a circuit. Smaller defects, which are likely to cause partial open or short in
a circuit, have a higher probability of occurrence due to the statistical variations in the
manufacturing process [8]. These defects result in the failure of a circuit to meet its timing
speci cations without any alteration of the logic function of the circuit. A small defect may
delay the transition of a signal on a line either from 0 to 1, or vice versa. This type of
malfunction is modeled by a delay fault.
Two types of delay faults have been proposed in literature: gate delay fault and path delay
fault. Gate delay faults have been used to model defects that cause the actual propagation
delay of a faulty gate to exceed its speci ed worst case value. For example, if the speci ed
worst case propagation delay of a gate is x units and the actual delay is x+∆x units, then the
gate is said to have a delay fault of size ∆x. The main de ciency of the gate delay fault model
is that it can only be used to model isolated defects, not distributed defects, for example,
several small delay defects. The path delay fault model can be used to model isolated as well
as distributed defects. In this model, a fault is as- sumed to have occurred if the propagation
delay along a path in the circuit under test exceeds the speci ed limit.

LOGIC SIMULA TION

About This Chapter
First we review different aspects of using logic simulation as a tool for design verification
testing, examining both its usefulness and its limitations. Then we introduce the main types
of simulators, compiled and event-driven. We analyze several problems affecting the
accuracy and the performance of simulators, such as treatment of unknown logic values,
delay modeling, hazard detection, oscillation control, and values needed for tristate logic and
MOS circuits. We discuss in detail techniques for element evaluation and gate-level event-

Dept.of ECE, SJBIT 11

!
VLSI TESTING 17EVE22

driven simulation algorithms. The last section describes special-purpose hardware for
simulation.
3.1 Applications
Logic simulation is a form of design verification testing that uses a model of the designed
system. Figure 3.1 shows a schematic view of the simulation process. The simulation
program processes a representation of the input stimuli and determines the evolution in time
of the signals in the model.

The verification of a logic design attempts to ascertain that the design performs its specified
behavior, which includes both function and timing. The verification is done by comparing the
results obtained by simulation with the expected results provided by the specification. In
addition, logic simulation may be used to verify that the operation of the system is
correct independent of the initial (power-on) state; 


not sensitive to some variations in the delays of the components; 


free of critical races, oscillations, "illegal" input conditions, and "hang-up" states. 

Other applications of simulation in the design process are 


evaluation of design alternatives ("what-if' analysis), to improve performance/cost trade-offs; 


evaluation of proposed changes of an existing design, to verify that the intended

modifications will produce the desired change without undesired side effects; 

• documentation (generation of timing diagrams, etc.). 

Traditionally, designers have used a prototype for the verification of a new design. The main
advantage of a prototype is that it can run at operating speed, but building a prototype is
costly and time-consuming. Prototypes built with discrete components lack accuracy as
models of complex ICs. Simulation replaces the prototype with a software model, which is
easily analyzed and modified. Simulation-based design verification benefits from additional
features not available to a prototype-based process, such as 


Dept.of ECE, SJBIT !12

VLSI TESTING 17EVE22

• checking error conditions (e.g., bus conflicts);


• ability to change delays in the model to check worst-case timing conditions; • checking
user-specified expected values during simulation;

• starting the simulated circuit in any desired state;

• precise control of the timing of asynchronous events (e.g., interrupts); 

• the ability to provide an automated testing environment for the simulated circuit, by
coupling it with an RTL model that drives and/or observes the circuit during simulation. 

Interestingly, simulation has also been used during the debugging of the prototype of a new
system. As reported in [Butler et ale 1974], designers found that tracing some problems on
the simulated model was easier than tracing them on the prototype hardware. Although
simulation runs much slower than the hardware, debugging using simulation provides the
user with the ability to suspend the simulation on the occurrence of user-specified conditions
and to display the value of any desired signal, including lines not directly observable on the
hardware. Such a feature becomes more valuable in LSI-based designs, where the number of
signals not directly observable is large. 

Debugging software or microcode to run on hardware still under development can be started
using a simulation model before a prototype is available. 

Another use of logic simulation is to prepare the data base for guided-probe testing,
consisting of the expected values of the lines accessible for probing. 


Types of Simulation
Simulators can be classified according to the type of internal model they process. A simulator
that executes a compiled-code model is referred to as a compiler-driven simulator, or a
compiled simulator. The compiled code is generated from an RTL model, from a functional
model written in a conventional programming language, or from a structural model. A
simulator that interprets a model based on data structures is said to be table-driven. The data
structures are produced from an RTL model or a structural model. The interpretation of the
model is controlled by the applied stimuli, and results in a series of calls to the routines
implementing primitive operators (for an RTL model) or primitive components (for a
structural model).
Let us consider a circuit in operation and look at the signals changing value at some arbitrary
time. These are called active signals. The ratio between the number of active signals and the
total number of signals in the circuit is referred to as activity. In general, the activity of a
circuit is between 1 and 5 percent. This fact forms the basis of activity-directed simulation
[Ulrich 1965, 1969], which simulates only the active part of the circuit.
An event represents a change in the value of a signal line. When such an event on line i
occurs, the elements having i as input are said to be activated. The process of determining the
output values of an element is called evaluation. Activity-directed simulation evaluates only
the activated elements. Some of the activated elements may in tum change their output
values, thus generating new events. As activity is caused by events, activity-directed
simulation is also referred to as event-driven simulation. To propagate events along the
interconnections among elements, an event-driven simulator needs a structural model of a
circuit. Hence event-driven simulation is usually table driven.
Compiled simulation is mainly oriented toward functional verification and is not concerned
with the timing of the circuit. This makes it applicable mostly to synchronous circuits, for
which timing can be separately verified [Hitchcock 1982]. In contrast, the passage of time is

Dept.of ECE, SJBIT !13

VLSI TESTING 17EVE22

central to event-driven simulation, which can work with accurate timing models. Thus event-
driven simulation is more general in scope, being also applicable to asynchronous circuits.
Event-driven simulation can process real-time inputs, that is, inputs whose times of change
are independent of the activity in the simulated circuit. This is an important feature for design
verification testing, as it allows accurate simulation of nonsynchronized events, such as
interrupts or competing requests for use of a bus.

Compiled simulation allows inputs to be changed only when the circuit is stable. This is
adequate when the input stimuli are vectors applied at a fixed rate. Note that real-time inputs
include the fixed-rate vectors as a particular case.
Often, the two simulation types are combined, such that an event-driven algorithm propagates
events among components, and the activated components are evaluated by compiled-code
models.
The level of simulation corresponds to the level of modeling employed to represent the
simulated system. Thus, we can have
• register-level simulation, for systems modeled entirely in RTL or as an interconnection of
components modeled in RTL;
• functional-level simulation, for systems modeled as an interconnection of primitive
functional blocks (sometimes this term is also used when the components are modeled in
RTL);
gate-level simulation; 


transistor-level simulation (we consider only logic-level and not circuit-level analog 

simulation); 


mixed-level simulation. 


Delay Models
Many different variants of the general flow shown in Figure 3.12 exist. The differences
among them arise mainly from different delay models associated with the behavior of the
components in the model. Delay modeling is a key element controlling the trade-off between
the accuracy and the complexity of the simulation algorithm.
3.7.1 Delay Modeling for Gates
Every gate introduces a delay to the signals propagating through it. In modeling the behavior
of a gate, we separate its function and its timing as indicated in Figure 3.13. Thus in
simulation an activated element is first evaluated, then the delay computation is performed.

Dept.of ECE, SJBIT !14

VLSI TESTING 17EVE22

Transport Delays
The basic delay model is that of a transport delay, which specifies the interval d separating an
output change from the input change(s) which caused it.
To simplify the simulation algorithm, delay values used in simulation are usually integers.
Typically they are multiples of some common unit. For example, if we are dealing with gate
delays of 15, 20, and 30 ns, for simulation we can scale them respectively to 3, 4, and 6 units,
where a unit of delay represents the greatest common divisor (5 ns) of the individual delays.
(Then the times of the changes at the primary inputs should be similarly scaled.) If all
transport delays in a circuit are considered equal, then we can scale them to 1 unit; this model
is called a unit-delay model.
The answers to the following two questions determine the nature of the delay computation.
• Does the delay depend on the direction of the resulting output transition?
• Are delays precisely known?
For some devices the times required for the output signal to rise (0 to 1 transition*) and to fall
(1 to 0) are greatly different. For some MOS devices these delays may

differ by a ratio of 3 to 1. To reflect this phenomenon in simulation, we associate different

rise and fall delays, d, and df , with every gate. The delay computation selects the appropriate
value based on the event generated for the gate output. If the gate delays are not a function of
the direction of the output change, then we can use a transition-independent delay model.
Figures 3.14(a) and (b) illustrate the differences between these two models. Note that the
result of having different rise and fall delays is to change the width of the pulse propagating
through the gate.

Dept.of ECE, SJBIT !15

VLSI TESTING 17EVE22

Often the exact transport delay of a gate is not known. For example, the delay of a certain
type of NAND gate may be specified by its manufacturer as varying from 5 ns to 10 ns. To
reflect this uncertainty in simulation, we associate an ambiguity interval, defined by the
minimum (dm ) and maximum (dM ) delays, with every gate. This model, referred to as an
ambiguous delay model, results in intervals (Rl and R2 in Figure 3.14(c)) during which the
value of a signal is not precisely known. Under the assumption that the gate delays are
known, we have a nominal delay model. The rise and fall delay model and the ambiguous
delay model can be combined such that we have different ambiguity intervals for the rise
(drm, drMl and the fall (dIm' djM) delays [Chappel and Yau 1971].

Hazard Detection

Static Hazards
In the circuit of Figure 3.23, assume that Q = 1 and A changes from 0 to 1, while B changes
from 1 to O. If these two changes are such that there exists a short interval during which
A=B=I, then Z may have a spurious pulse, which may reset the latch. The possible
occurrence of a transient pulse on a signal line whose static value does not change is called a
static hazard.

To detect hazards, a simulator must analyze the transient behavior of signals. Let S(t) and
S(t+ 1) be the values of a signal S at two consecutive time units. If these values are different,
the exact time when S changes in the real circuit is uncertain. To reflect this uncertainty in
simulation, we will introduce a "pseudo time unit" t' between t and t+l during which the value
of S is unknown, i.e., Stt') = u [Yoeli and Rinon 1964, Eichelberger 1965]. This is consistent
with the meaning of u as one of the values in the set {O,I}, because during the transition
period the value of S can be independently
observed by each of its fanouts as either 0 or 1. Then the sequence S(t) Stt') S(t+l) = Oul
represents one of the sequences in the set {001,011}. These two sequences can be interpreted,
respectively, as a "slow" and a "fast" transition. Returning now to the example of Figure 3.23,
the corresponding sequences are A =Oul and B =luO. The resulting sequence for Z, computed
by bitwise NAND operations, is luI. This result shows that a possible output sequence is 101,
and thus it detects the unintended pulse.

Dept.of ECE, SJBIT !16

VLSI TESTING 17EVE22

The general procedure for detecting static hazards in a combinational circuit C works as
follows. Assume that C has been simulated for time t and now it is simulated for time t+1. Let
E be the set of inputs changing between t and t+1.

Gate-Level Event-Driven Simulation


Transition-Independent Nominal Transport Delays
Now we will particularize the general simulation algorithm given in Figure 3.12 for gate-
level simulation using a transition-independent nominal transport delay model.
First we consider that the event list is organized as shown in Figure 3.27, where events
scheduled to occur at the same time in the future are stored in the same list. The time order is
maintained by chaining the list headers in appropriate order, i.e., tp < tq < t.. An entry (i, v/)
in the list associated with tq indicates that at time tq the value of line i is scheduled to be set
to Vi'.
We assume that values and delays are kept in tables similar to those depicted in Figure 2.21;
v(i) denotes the current value of gate i and d(i) denotes the nominal delay of i.
Figure 3.28 shows the general structure of the event-driven simulation algorithms discussed
in this section. Algorithm 3.1, given in Figure 3.29, provides a first implementation of the
line "process entries for time t" of Figure 3.28. Algorithm 3.1 employs a two-pass strategy. In
the first pass it retrieves the entries from the event list associated with the current time t and
determines the activated gates. In the second pass it evaluates the activated gates and
schedules their computed values. This strategy assures that gates activated by more than one
event are evaluated only once.
Note that in Algorithm 3.1, an entry (i, v/) in the event list does not always represent a change
in the value of i. The problem of determining when a new output value of an activated gate is
indeed an event is illustrated in Figure 3.30. In response to the

Dept.of ECE, SJBIT !17

VLSI TESTING 17EVE22

event (a,l) at time 0, (z,l) is scheduled for time 8. Since now the gate is in a transition state
(Le., the scheduled output event has not yet occurred), there is a temporary logic
inconsistency between the current output value (0) and the input values (both 1). Thus when
the next inp°ut event (b,O) occurs at time 2, Algorithm 3.1cannot determine whether setting z
=0 strategy employed is to enter in the event list all the new values of the activated gates

Dept.of ECE, SJBIT !18

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !19

VLSI TESTING 17EVE22

Module-2

Test generation for Combinational Logic circuits:

Several distinct test generation methods have been developed over the years for
combinational cir- cuits. These methods are based on the assumptions that a circuit is
nonredundant and only a single stuck-at fault is present at any time.

Truth Table and Fault Matrix

The most straightforward method for generating tests for a particular fault is to compare the
re- sponses of the fault-free and the faulty circuit to all possible input combinations. Any
input combi- nation for which the output responses do not match is a test for the given fault.
Let the inputs to a combinational circuit be x1, x2, ..., xn and let Z be the output of the circuit.
Let Za be the output of the circuit in the presence of the fault α. The test generation method
starts with the construction of the truth tables of Z and Za. Then for each row of the truth
table, Z⊕Za is computed; if the result is 1, the input combination corresponding to the row is
a test for the fault.

Dept.of ECE, SJBIT !20

VLSI TESTING 17EVE22

As an example, let us consider the circuit shown in Figure 2.1a and assume that tests for
faults α s-a-0 and β s-a-l have to be derived. The truth table for the circuit is shown in Figure
2.1b, where column Z denotes the fault-free output, and Zα and Zβ correspond to the circuit
output in presence of faults α s-a-0 and β s-a-l, respectively. The tests for the faults are
indicated as l’s in the columns corresponding to Z⊕Za and Z⊕Zβ. Thus, the test for α s-a-0 is
x1x2x3=110, and the test for β s-a-l is x1x2x3=001. For all other input combinations, the
output of the fault-free circuit is the same as the output in the presence of the fault;
consequently, they are not tests for α s-a-0 and β s-a-l.
The minimum number of tests required to detect a set of faults in a combinational circuit can
be obtained from a fault matrix. The columns in a fault matrix list the single faults to be
tested, and the rows indicate the tests. A fault matrix for the circuit of Figure 2.2a is shown in
Figure 2.2b. A 1 at the intersection of the ith row and the jth column indicates that the fault
corresponding to the jth column can be detected by the ith test. As can be seen from Figure
2.2b, a fault matrix is identical to a prime implicant chart used in logic minimization. Thus,
the problem of nding the minimum number of tests is the same as the problem of nding the
minimum number of prime implicants (i.e., rows) so that every column has a 1 in at least one
row. In Figure 2.2b, rows 110, 101, and 111 are equivalent (i.e., each test detects the same
faults as the other two); hence, 101 and 111 can be omitted. Furthermore, row 000 covers row
100 and row 001 covers row 011; thus, rows 100 and 011 can be omitted. Elimination of rows
100, 101, 011, and 111 yields the minimal test set as shown in Figure 2.2c. These four tests
detect all of the six faults under consideration.
It is obvious from this example that the fault matrix approach to test generation is not prac-
ticable when the number of input variables is large. We now discuss some alternative
techniques developed to solve test generation problems.

Path Sensitization
The basic principle of the path sensitization method is to choose some path from the origin of
the fault to the circuit output. As mentioned earlier, a path is sensitized if the inputs to the
gates along the path are assigned values such that the effect of the fault can be propagated to
the output [1].
To illustrate, let us consider the circuit shown in Figure 2.3 and assume that line α is s-a-1.
Totestforα,bothG3 andCmustbesetat1.Inaddition,DandG6 mustbesetat1sothatG7=1if the fault
is absent. To propagate the fault from G7 to the circuit output f via G8 requires the output of
G4 to be 1. This is because if G4=0, the output f will be forced to be 1, independent of the
value of gate G7. The process of propagating the effect of the fault from its original location
to the circuit output is known as the forward trace.
The next phase of the method is the backward trace, in which the necessary signal values at
the gate outputs speci ed in the forward trace phase are established. For example, to set G3 at
1, A must

Dept.of ECE, SJBIT !21

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !22

VLSI TESTING 17EVE22

be set at 0, which also sets G4=1. In order for G6 to be at 1, B must be set at 0; note that G6
cannot be set at 1 by making C=0 because this is inconsistent with the assignment of C in the
forward trace phase. Therefore, the test ABCD=0011 detects the fault α s-a-1, since the
output f will be 0 for the fault-free circuit and 1 in the presence of the fault.
In general, a test pattern generated by the path sensitization method may not be unique. For
example, the fault α s-a-0 in the circuit of Figure 2.4 can be detected by ABC=01- or 0-0. In
the rst test, C is unspeci ed, and B is unspeci ed in the second test. An unspeci ed value in a
test indicates that the test is independent of the corresponding input.
The main drawback of the path sensitization method is that only one path is sensitized at a
time. This does not guarantee that a test will be found for a fault even if one exists. As an
example, let us derive a test for the fault α s-a-0 in Figure 2.5 [2]. To propagate the effect of
the fault along the path G2−G6−G8 requires that B, C, and D should be set at 0. In order to
propagate the fault through G8, it is necessary to make G4=G5=G7=0. Since B and D have
already been set to 0, G3 is 1, which makes G7=0. To set G5=0, A must be set to 1; as a
result, G1=0, which with B=0 will make G4=1. Therefore, it is not possible to propagate the
fault through G8. Similarly, it is not possible to sensitize the path G2−G5−G8. However, A=0
sensitizes the two paths simultaneously and also

Dept.of ECE, SJBIT !23

VLSI TESTING 17EVE22

makes G4=0. Thus, two inputs to G8 change from 0 to 1 as a result of the fault α s-a-0, while
the remaining two inputs remain xed at 0. Consequently, ABCD=0000 causes the output of
the circuit to change from 1 to 0 in the presence of α s-a-0 and is the test for the fault.
This example shows the necessity of sensitizing more than one path in deriving tests for cer-
tain faults and is the principal idea behind the D-algorithm.

Dept.of ECE, SJBIT !24

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !25

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !26

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !27

VLSI TESTING 17EVE22

2.8b, the consistency operation at step 4 terminates unsuccessfully because the output of G3
has to be set to 1. This can be done only by making input B=0; however, B has already been
assigned 1 in step 1. A similar problem will arise if D is propagated to the output via G3
instead of G2. The only way the consistency problem can be resolved is if the D output of G1
is propagated to the output of the circuit via both G2 and G3 as shown in Figure 2.8c. No
consistency operation is needed in this case, and the test for the given fault is AB=11. This
test also detects the output of G2 s-a-0, the output of G3 s-a-0, and the output of G4 s-a-1.
As a further example of the application of the D-algorithm, let us derive a test for the s-a-0
fault at the output of gate G2 in the circuit shown in Figure 2.9a. The test derivation is as
shown in Figure 2.9b. The test is ABC=011.

Dept.of ECE, SJBIT !28

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !29

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !30

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !31

VLSI TESTING 17EVE22

via the paths AGJ and AHJ; propagation along either path individually will lead to
inconsistency. This feature of the D-algorithm can lead to a waste of effort if a given fault is
untestable. Thus, PODEM is more ef cient than the D-algorithm in terms of computer time
required to generate tests for combinational circuits.

Dept.of ECE, SJBIT !32

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !33

VLSI TESTING 17EVE22

Module-3
Design of testable sequential circuits:
Test generation for sequential circuits is extremely dif cult because the behavior of a
sequential circuit depends both on the present and on the past input values. The mathematical
model of a

synchronous sequential circuit is usually referred to as a sequential machine or a nite state

machine. Henceforth, a synchronous sequential circuit will be referred to as a sequential
circuit.
Figure 2.18 shows the general model of a synchronous sequential circuit. As can be seen from
the diagram, sequential circuits are basically combinational circuits with memory to
remember past inputs. The combinational part of the circuit receives two sets of input signals:
primary (coming from the external environment) and secondary (coming from the memory
elements). The particular combination of secondary input variables at a given time is called
the present state of the circuit; the secondary input variables are also known as state
variables. If there are m secondary input variables in a sequential circuit, then the circuit can
be in any one of 2m different present states. The outputs of the combinational part of the
circuit are divided into two sets. The primary outputs are available to control operations in the
circuit environment, whereas the secondary outputs are used to specify the next state to be
assumed by the memory. It takes an entire sequence of inputs to detect many of the possible
faults in a sequential circuit.

Dept.of ECE, SJBIT !34

VLSI TESTING 17EVE22

Sequential circuits can be tested by checking that such a circuit functions as speci ed by its
state table [9, 10]. This is an exhaustive approach and is practical only for small sequential
circuits. The approach may be summarized as follows: Given the state table of a sequential
circuit, nd an input/output sequence pair (X, Z) such that the response of the circuit to X will
be Z if and only if the circuit is operating correctly. The application of this input sequence X
and the observation of the response, to see if it is Z, is called a checking experiment; the
sequence pair (X, Z) is referred to as a checking sequence.
The derivation of checking sequence for a sequential circuit is based on the following as-
sumptions:

AN INTrodUCTIoN To LoGIC CIrCUIT TeSTING

• The circuit is fully speci ed and deterministic. In a deterministic circuit the next state is
determined uniquely by the present state and the present input. 


• The circuit is strongly connected; that is, for every pair of states qi and qj of the circuit,
there exists an input sequence that takes the circuit from qi to qj. 


• The circuit in the presence of faults has no more states than those listed in its speci cation.
In other words, the presence of a fault will not increase the number of states. 

To design checking experiments, it is necessary to know the initial state of the circuit which 


is determined by a homing sequence or a distinguishing sequence. An input sequence is said

to be a homing sequence for a sequential circuit if the circuit’s response to the sequence is
always suf cient to determine uniquely its nal state. For an example, consider the state table

Dept.of ECE, SJBIT !35

VLSI TESTING 17EVE22

of a circuit shown in Figure 2.19. It has a homing sequence 101, for, as indicated in Figure
2.20, each of the output sequences that might result from the application of 101 is associated
with just one nal state. A homing sequence need not always leave a machine in the same nal
state; it is only necessary that the nal state can be identi ed from the output sequence.
A distinguishing sequence is an input sequence that, when applied to a sequential circuit, will
produce a different output sequence for each choice of initial state. For example, 101 is also a
distinguishing sequence for the circuit shown in Figure 2.19. As shown in Figure 2.20, the
output sequence that the machine produces in response to 101 uniquely speci es its initial
state. Every distinguishing sequence is also a homing sequence because the knowledge of the
initial state and the input sequence is always suf cient to determine uniquely the nal state as
well. On the other hand, not every homing sequence is a distinguishing sequence. For
example, the circuit speci ed by the state table of Figure 2.21a has a homing sequence 010.
As shown in Figure 2.21b, the output sequence produced in response to 010 uniquely speci es
the nal state of the circuit but cannot

distinguish between the initial states C and D. Every reduced sequential circuit possesses a
homing sequence, whereas only a limited number of sequential circuits have distinguishing
sequences.
At the start of an experiment, a circuit can be in any of its n states. In such a case, the initial
uncertainty regarding the state of the circuit is the set that contains all the states of the circuit.
A collection of states of the circuit that is known to contain the present state is referred to as
the un- certainty. The uncertainty of a circuit is thus any subset of the state of the machine.
For example, the state table of Figure 2.19 can initially be in any of its four states; hence, the
initial uncertainty is (ABCD). If an input 1 is applied to the circuit, the successor uncertainty

Dept.of ECE, SJBIT !36

VLSI TESTING 17EVE22

will be (AD) or (BC) depending on whether the output is 0 or 1, respectively. The

uncertainties (C)(DBC) are the 0- successors of (ABCD). A successor tree, which is de ned
for a speci ed circuit and a given initial uncertainty, is a structure that displays graphically the
xi-successor uncertainties for every possible input sequence xi.
A collection of uncertainties is referred to as an uncertainty vector, the individual
uncertainties contained in the vector are called the components of the vector. An uncertainty
vector, the compo- nents of which contain a single state each, is said to be a trivial
uncertainty vector. An uncertainty

AN INTrodUCTIoN To LoGIC CIrCUIT TeSTING

vector, the components of which contain either single states or identical repeated states, is
said to be a homogeneous uncertainty vector. For example, the vectors (AA)(B)(C) and (A)
(B)(A)(C) are homogeneous and trivial, respectively.
A homing sequence is obtained from the homing tree; a homing tree is a successor tree in
which a node becomes terminal if one of the following conditions occurs:
The node is associated with an uncertainty vector, the nonhomogeneous components of
which are associated with the same node at a preceding level. 


The node is associated with a trivial or a homogeneous vector. 


The path from the initial uncertainty to a node in which the vector is trivial or homogeneous
de nes a homing sequence.
A distinguishing tree is a successor tree in which a node becomes terminal if one of the fol-
lowing conditions occurs:
The node is associated with an uncertainty vector, the nonhomogeneous components of
which are associated with the same node at a preceding level. 


The node is associated with an uncertainty vector containing a homogeneous nontrivial

component. 


The node is associated with a trivial uncertainty vector. 


Dept.of ECE, SJBIT !37

VLSI TESTING 17EVE22

The path from the initial uncertainty to a node associated with a trivial uncertainty de nes a
distin- guishing sequence. As an example, the homing sequence 010 is obtained as shown in
Figure 2.22 by applying the terminal rules to state table of Figure 2.21a. The derivation of the

distinguishing sequence 101 for state table of Figure 2.19 is shown in Figure 2.23.

Dept.of ECE, SJBIT !38

VLSI TESTING 17EVE22

TeST GeNerATIoN USING THe CIrCUIT STrUCTUre ANd THe STATe TAbLe
A test generation technique for sequential circuits based on the concept of path sensitization
used in combinational circuit test generation has been proposed in Ref. [11]. This technique
takes into account both the structure and the state table of a sequential circuit. It is assumed
that the circuit under test has a reset state. A test sequence is applied to the circuit with the
reset state as the starting state. The test generation process consists of the following steps:
• Generate a test vector for the assumed single stuck-at fault such that the effect of the fault is
propagated to the primary outputs or to the secondary outputs, i.e., the outputs of the ip-
ops. Each primary output as well as each secondary output is considered an indepen- dent
output of a combinational circuit. A test vector for a fault is identi ed as an excitation
vector, and the present state part of an excitation vector is called the excitation state.

• Derive an input sequence to take the circuit from the reset state to the excitation state; this
input sequence is called the justi cation sequence. Obviously, a justi cation sequence is not
necessary if the excitation state part of a test vector is the reset state. If the effect of a fault
can be propagated to the primary outputs by the derived test vector, and the justi cation se-
quence can take the faulty circuit from the reset to the excitation state, then the test vector
is valid. However, if the test vector can propagate the effect of the fault only to the outputs
of the ip- ops, i.e., the next state is different from the one expected, the following step is
also necessary for successful test generation for the assumed fault. 


• Derive an input sequence such that the last bit in the sequence produces a different output
for the fault-free and the faulty states of the circuit under test. Such an input sequence is
called the differentiating sequence. 


A test sequence for the fault under test is obtained by concatenating the justi cation se- 


quence, the excitation vector, and the differentiating sequence. This test sequence is
simulated in the presence of the fault to check if the fault is detected. If the fault is not
detected, the differentiating sequence is not valid. Moreover, a valid differentiating sequence
cannot be obtained if the fault-free and the faulty states are equivalent in the fault-free
sequential circuit.
Let us illustrate the technique by deriving a test sequence for the fault α s-a-0 in the sequen-
tial circuit shown in Figure 2.25a; the state table of the fault-free circuit is shown in Figure
2.25b. The state are encoded as shown in Figure 2.25c.
A partial test vector for the fault is rst derived:

Dept.of ECE, SJBIT !39

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !40

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !41

VLSI TESTING 17EVE22

Module 4: Design of testable sequential circuits

The phrase design for testability refers to how a circuit is either designed or modi ed so that
the test- ing of the circuit is simpli ed. Several techniques have been developed over the years
for improving the testability of logic circuits. These can be categorized into two categories:
ad hoc and structured.
The ad hoc approaches simplify the testing problem for a speci c design and cannot be gen-
eralized to all designs. On the other hand, the structured techniques are generally applicable
to all designs.

Ad HoC TeCHNIQUeS
One of the simplest ways of improving the testability of a circuit is to provide more tests and
control points. Test points are, in general, used to observe the response at a node inside the
circuit, whereas control points are utilized to control the value of an internal node to any
desired value, 0 or 1. For example, in the circuit shown in Figure 3.1a, the fault α s-a-0 is
undetectable at the circuit output.

Dept.of ECE, SJBIT !42

VLSI TESTING 17EVE22

By incorporating a test point at node α as shown in Figure 3.1b, the input combination 010 or
011 can be applied to detect the fault.
The usefulness of adding a control point can be appreciated from the circuit shown in Fig-
ure 3.2a. If the output of the EX-NOR gate in the circuit is always 1, indicating that both the
outputs of the logic block are the same, it is not possible to say whether the EX-NOR gate is
oper- ating correctly or not. If a control point is added to the circuit, as shown in Figure 3.2b,
the input of the EX-NOR gate and hence the operation of the circuit can be controlled via the
added point. During the normal operation of the circuit, the control point is set at logic 1. To
test for an s-a-1 fault at the output of the EX-NOR gate, the control point is set at logic 0 and
an input combination that produces logic 1 at the outputs has to be applied.
Another way of improving the testability of a particular circuit is to insert multiplexers in
order to increase the number of internal nodes that can be controlled or observed from the
external points. For example, the fault α s-a-0 in Figure 3.1a can also be detected by
incorporating a 2-to-1 multiplexer as shown in Figure 3.3. When the test input (i.e., the select
input of the multiplexer) is

Dept.of ECE, SJBIT !43

VLSI TESTING 17EVE22

at logic 1, the output of the circuit is transferred to the output of the multiplexer. On the other
hand, if the control input is at logic 0 and the input combination 010 or 011 is applied to the
circuit, the state of node α can be observed at the multiplexer output.
A different way of accessing internal nodes is to use tristate drivers as shown in Figure 3.4. A
test mode signal could be used to put the driver into the high-impedance state. In this mode,
the input of the OR gate can be set to logic 0 or logic 1 from an external point. When the
driver is enabled, the same external point becomes a test point.
The test mode signals required by the added components, such as multiplexers, tristate driv-
ers, etc., cannot always be applied via external points, because it is often not practicable to
have many such points. To reduce the number of external points, a test state register may be
included in the

circuit. This could in fact be a shift register that is loaded and controlled by just a few pins.
The test- ability hardware in the circuit can then be controlled by the parallel outputs of the
shift register.
Frequently, ip- ops, counters, shift registers, and other memory elements assume unpre-
dictable states when power is applied, and they must be set to known states before testing can
begin. Ideally, all memory elements should be reset from external points (Figure 3.5a).
Alternatively, a power-up reset may be added to provide internal initialization (Figure 3.5b).

Dept.of ECE, SJBIT !44

VLSI TESTING 17EVE22

A long counter chain presents another test problem. For example, the counter chain in Figure
3.6 requires thousands of clock pulses to go through all the states. One way to avoid this
problem is to break up the long chains into smaller chains by lling jumpers to them; the
jumpers can be removed during testing. A tristate driver can function as a jumper in this case.
The input of the tristate driver is connected to the clock, and the output to the clock input of
the second counter chain. When the control input of the tristate driver is disabled, the clock is
disconnected from the second counter chain; thus, this chain can be tested separately from the
rst chain.
A feedback loop is also dif cult to test because it hides the source of the fault. The source can
be located by breaking the loop and bringing both lines to external points that are shown
during

normal operation. When not shorted, the separate lines provide a control point and a test
point. An alternative way of breaking a feedback loop is to add to the feedback path a gate
that can be inter- rupted by a signal from a control point (Figure 3.7).
On-circuit clock oscillators should be disconnected during test and replaced with an external
clock. The external clock can be single-stepped to check the logic values at various nodes in
the circuit during the fault diagnosis phase. Figure 3.8 shows how the onboard clock can be
replaced by an external one.

Dept.of ECE, SJBIT !45

VLSI TESTING 17EVE22

SCAN-PATH TeCHNIQUe For TeSTAbLe SeQUeNTIAL CIrCUIT

deSIGN

The testing of sequential circuits is complicated because of the dif culties in setting and
checking the states of the memory elements. These problems can be overcome by modifying
the design of a general sequential circuit so that it has the following properties [1].
1. The circuit can easily be set to any desired internal state.

2. It is easy to nd a sequence of input patterns such that the resulting output sequence will
indicate the internal state of the circuit.
The basic idea is to add an extra input c to the memory excitation logic in order to control the
mode of a circuit. When c=0, the circuit operates in its normal mode, but when c=1, the
circuit enters into a mode in which the elements are connected together to form a shift
register. This facil- ity is incorporated by inserting a double-throw switch, i.e., a 2-to-1
multiplexer in each input lead of every memory element. All these switches are grouped
together, and the circuit can operate in either its normal or shift register mode. Figure 3.9
shows a sequential circuit using D ip- ops; the circuit is modi ed as shown in Figure 3.10.
Each of the double-throw switches may be realized as

Dept.of ECE, SJBIT !46

VLSI TESTING 17EVE22

LeVeL-SeNSITIVe SCAN deSIGN

One of the best known and the most widely practiced methods for synthesizing testable
sequential circuits is IBM’s level-sensitive scan design (LSSD) [2–5]. The level-sensitive
aspect of the method means that a sequential circuit is designed so that the steady-state
response to any input state change is independent of the component and wire delays within
the circuit. Also, if an input state change involves the changing of more than one-input signal,
the response must be independent of the order in which they change. These conditions are

Dept.of ECE, SJBIT !47

VLSI TESTING 17EVE22

ensured by the enforcement of certain design rules, particularly pertaining to the clocks that
evoke state changes in the circuit. Scan refers to the ability to shift into or out of any state of
the circuit.

Clocked Hazard-Free Latches

In LSSD, all internal storage is implemented in hazard-free polarity-hold latches. The
polarity- hold latch has two-input signals as shown in Figure 3.18a. The latch cannot change
state if C=0. If C is set to 1, the internal state of the latch takes the value of the excitation
input D. A ow table for this sequential circuit, along with an excitation table and a logic
implementation, is shown in Figure 3.18b, 3.18c, and 3.18d, respectively.

Dept.of ECE, SJBIT !48

VLSI TESTING 17EVE22

The clock signal C will normally occur (change from 0 to 1) after the data signal D has be-
came stable at either 1 or 0. The output of the latch is set to the new value of the data signal at
the time the clock signal occurs. The correct changing of the latch does not depend on the rise
or fall time of the clock signal, but only on the clock signal being 1 for a period equal to a
greater than the time required for the data signal to propagate through the latch and stabilize.

A shift register latch (SRL) can be formed by adding a clocked input to the polarity-hold
latch L1 and including a second latch L2 to act as intermediate storage during shifting (Figure
3.13). As long as the clock signals A and B are both 0, the L1 latch operates exactly like a
polarity- hold latch. Terminal I is the scan-in input for the SRL and +L2 is the output. The
logic implemen- tation of the SRL is shown in Figure 3.14. When the latch is operating as a
shift register data from the preceding stage are gated into the polarity-hold switch via I,
through a change of the clock A from 0 to 1. After A has changed back to 0, clock B gates the
data in the latch L1 into the output latch L2. Clearly, A and B can never both be 1 at the same
time if the SRL is to operate properly.

Dept.of ECE, SJBIT !49

VLSI TESTING 17EVE22

double-Latch and Single-Latch LSSd

A sequential logic circuit that is level-sensitive and also has the scan capability is called a
Level Sen- sitive Scan Design ( LSSD). Figure 3.16 depicts a general structure for an LSSD
system, known as a double-latch design in which all system outputs are taken from the L2
latch. In this con guration, each SRL operates in a master–slave mode. Data transfer occurs
under system clock and scan clock B during normal operation and under scan clock A and
scan clock B during scan-path operation. Both latches are therefore required during system
operation.

In the single-latch con guration, the combinational logic is partitioned into two disjoint sets,
Combl and Comb2 (Figure 3.17). The system clocks used for SRLs in Combl and Comb2 are
denoted by Clock 1 and Clock 2, respectively; they are nonoverlapping. The outputs of the
SRLs in Combl are fed back as secondary variable inputs to Comb2, and vice versa. This con
guration uses the output of latch L1 as the system output; the L2 latch is used only for
shifting. In other words, the L2 latches are redundant and represent the overhead for
testability.

Dept.of ECE, SJBIT !50

VLSI TESTING 17EVE22

rANdoM ACCeSS SCAN TeCHNIQUe

The design methods discussed in Sections 3.2 and 3.3 use sequential access scan-in/scan-out
tech- niques to improve testability; that is, all ip- ops are connected in series during testing to
form a shift register or registers. In an alternative approach, known as random access scan,
each ip- op in a logic circuit is selected individually by an address for control and observation
of its state [7]. The ba- sic memory element in a random access scan-in/scan-out network is
an addressable latch. The circuit diagram of an addressable latch is shown in Figure 3.18. A
latch is selected by X–Y address signals, the state of which can then be controlled and
observed through scan-in/scan-out lines. When a latch is selected and its scan clock goes
from 0 to 1, the scan data input is transferred through the circuit to the scan data output,
where the inverted value of the scan data can be observed. The input on the DATA line is
transferred to the latch output Q during the negative transition (1 to 0) of the clock. The scan
data out lines from all latches are then AND-gated to produce the chip scan-out signal: the
scan-out line of a latch remains at logic 1 unless the latch is selected by the X–Y signals.

Dept.of ECE, SJBIT !51

VLSI TESTING 17EVE22

A different type of addressable latch—the set–reset type—is shown in Figure 3.19. The
“clear” signal clears the latch during its negative transition. Prior to scan-in operation, all
latches are cleared. Then, a latch is addressed by the X–Y lines and the preset signal is
applied to set the latch state.

The basic mode1 of a sequential circuit with random access scan-in/scan-out feature is shown
in Figure 3.20. The X- and Y-address decoders are used to access an addressable latch like a
cell in

Dept.of ECE, SJBIT !52

VLSI TESTING 17EVE22

random access memory. A tree of AND gates is used to combine all scan-out signals. Clear
input of all latches are tied together to form a master reset signal. Preset inputs of all latches
receive the same scan-in signal gated by the scan clock however, only the latch accessed by
the X–Y address is affected.

The test procedure of a sequential circuit with random access scan-in/scan-out feature is as
follows:

Set test input to all test points. 


Apply the master reset signal to initialize all memory elements. 


Set scan-in address and data and then apply the scan clock. 


Repeat step 3 until all internal test inputs are scanned in. 


Clock once for normal operation. 


Check states of the output points. 


Read the scan-out states of all memory elements by applying appropriate. 


X–Y signals. 

The random access scan-in/scan-out technique has several advantages: 


The observability and controllability of all system latches are allowed. 


Any point in a combinational circuit can be observed with one additional gate and one ad- 

dress per observation point. 


Dept.of ECE, SJBIT !53

VLSI TESTING 17EVE22

A memory array in a logic circuit can be tested through a scan-in/scan-out circuit. The 

scan address inputs are applied directly to the memory array. The data input and the write- 


random access memory. A tree of AND gates is used to combine all scan-out signals. Clear
input of all latches are tied together to form a master reset signal. Preset inputs of all latches
receive the same scan-in signal gated by the scan clock however, only the latch accessed by
the X–Y address is affected.

The test procedure of a sequential circuit with random access scan-in/scan-out feature is as
follows:

Dept.of ECE, SJBIT !54

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !55

VLSI TESTING 17EVE22

PArTIAL SCAN
In full scan, all ip- ops in a circuit are connected into one or more shift registers; thus, the
states of a circuit can be controlled and observed via the primary input and outputs,
respectively. In par- tial scan, only a subset of the circuit ip- ops is included in the scan chain
in order to reduce the

overhead associated with full scan design [6]. Figure 3.21 shows a structure of partial scan
design. This has two separate clocks: a system clock and a scan clock. The scan clock
controls only the scan ip- ops. Note that the scan clock is derived by gating the system clock
with the scan-enable signal; no external clock is necessary. During the normal mode of
operation, i.e., when the scan-enable signal is at logic 0, both scan and nonscan ip- ops update
their states when the system clock is applied. In the scan mode operation, only the state of the
shift register (constructed from the scan ip- ops) is shifted one bit with the application of the
scan ip- op; the nonscan ip- ops do not change their states.

The disadvantage of two-clock partial scan is that the routing of two separate locks with
small skews is very dif cult to achieve. Also, the use of a separate scan clock does not allow
the test- ing of the circuit at its normal operating speed.

Dept.of ECE, SJBIT !56

VLSI TESTING 17EVE22

A partial scan scheme that uses the system clock as the scan clock is shown in Figure 3.22.
[8]. Both scan and nonscan ip- ops move to their next states when the system clock is applied.
A test sequence is derived by shifting data into the scan ip- ops. This data together with
contents of nonscan ip- ops constitute the starting state of the test sequence. The other
patterns in the sequence are obtained by single-bit shifting of the contents of scan ip- ops,
which form part of the required circuit states. The remaining bits of the states, i.e., the
contents of the scan ip- ops are determined by the functional logic. Note this form of partial
scan scheme allows only a limited number of valid next states to be reached from the starting
state of the test sequence. This may limit the fault coverage obtained by using the technique.

The selection ip- ops to be included in the partial scan is done by heuristic methods. It has
been shown that the fault coverage in a circuit can be signi cantly increased by including 13–
23% of the ip- ops ops in the partial scan [9].

Dept.of ECE, SJBIT !57

VLSI TESTING 17EVE22

TeSTAbLe SeQUeNTIAL CIrCUIT deSIGN USING

NoNSCAN TeCHNIQUeS
Full and partial scan techniques improve the controllability and observability of ip- ops in se-
quential circuit, and therefore the test generation for such circuits is considerably simpli ed.
How- ever, a scan-based circuit cannot be tested at its normal speed, because test data have to
be shifted in and out via the scan path.

Figure 3.23 shows the con guration of a testable sequential circuit that employs nonscan ip-
ops [10]. The original sequential circuit is augmented with a test mode input. If this input is at
logic

Dept.of ECE, SJBIT !58

VLSI TESTING 17EVE22

1, each ip- op from a selected subset of ip- ops in the circuit is connected directly to a
primary input. This enables data to be shifted directly into these ip- ops from the primary
inputs; at the same time, previous data from these ip- ops are shifted into the ip- ops that do
not belong to the subset. The contents of the ip- ops in the selected subset are available on the
primary outputs when the test mode signal is at logic 1. To illustrate, let us consider the two-
input and two-output sequential circuit with four ip- ops shown in Figure 3.23. The primary
inputs w and x are used to shift data into selected ip- ops 1 and 2, respectively, when the test
mode signal is at logic 1. The previous contents of ip- ops 1 and 2 are shifted into ip- ops 3
and 3, respectively, while the contents of ip- ops 3 and 3 are observable via primary outputs
z1 and z2.

Several techniques similar to that in Ref. [10] have been proposed in Ref. [11] to enhance
controllability and observability in sequential circuits so that the testing of the circuits can be
done at normal speed. The controllability of a circuit is improved by selecting a subset of ip-
ops such that the number of cycles in the circuit’s state diagram is minimized and each
selected ip- op can be loaded directly from one primary input line during the test mode. Such
ip- ops are identi ed as controllable ip- ops. Figure 3.24 shows a sequential circuit modi ed
for enhanced controllability. When the test input is at logic 0, all the ip- ops in a circuit are
driven by their original next state logic. In other words, the circuit operates in its normal
mode. When the test input is at logic 1, each controllable ip- op is driven by a primary input
line via a 2-to-1 multiplexer. The observability is improved by selecting a set of internal
nodes that are untestable because faults at such nodes cannot

Dept.of ECE, SJBIT !59

VLSI TESTING 17EVE22

be propagated to the primary outputs. The signals at these nodes are compressed by an EX-
OR tree, the output of which is available on an additional output line as shown in Figure 3.25.

CroSSCHeCK
The CrossCheck approach incorporates test circuitry into the basic cells used to implement
VLSI circuits [12, 13]. This is done by connecting the output of a cell to the drain of a pass
transistor. The gate of the transistor is connected to a probe line P and the source to a sense
line S, as shown in Figure 3.26. The output of the cell can be observed via the S-line by
controlling the probe line P. In other words, the controllability and the observability of the
cells can be guaranteed.

Dept.of ECE, SJBIT !60

VLSI TESTING 17EVE22

This approach can be used to enhance testability of VLSI chips by using cells with Cross-
Check test points to implement logic. The individual test points are routed into an orthogonal
grid of probe and sense lines as shown in Figure 3.27.

Appropriate test patterns are rst applied to the circuit under test via the primary inputs. The
probe lines are then enabled, allowing logic values at internal test points to be transferred to
the sense lines. These values are stored in a parallel-in/serial-out shift register. Alternatively, a
multiple- input signature register (MISR) can be used to compress the test values into a
signature. It should be clear from this discussion that the CrossCheck approach allows
parallel scanning of test points.

Dept.of ECE, SJBIT !61

VLSI TESTING 17EVE22

The CrossCheck testability approach simpli es the detection of stuck-open faults in logic
cells. To illustrate, let us consider a two-input NOR gate augmented by a transistor having a
P-line and an S-line (Figure 3.28). Let us assume the NOR gate has a stuck-open fault as
shown in Figure 3.28. The fault can be activated by applying the test pattern AB=10. The
sense line is precharged to a weak logic 1. When the probe line P is set at logic 1, the logic
value on the S-line will be 0 in the absence of the assumed stuck-open fault; otherwise, the
logic value will be 1. Thus, a stuck-open fault can be detected with a single test pattern.

The CrossCheck approach enhances the controllability of sequential circuits by using a D ip-
op implementation called cross-controlled latch (CCL). A CCL consists of a master–slave
edge- triggered ip- op augmented by two transistors t1 and t2 (Figure 3.29). Transistor t1 is
controlled by a test-write-enable (TWE) signal. When TWE =1, and also probe line P and the
clock are set at logic 1, the value on node Y is observable on the sense line S via transistor t2;
this value is also observable at the Q output. When the TWE signal is set at logic 0, transistor
t1 is turned off and the feedback path is disabled. A CCL functions as a D ip- op when the
TWE signal is at logic 1. The overhead due to the extra transistors is around 3%; also there is
a slight increase in the mini- mum clock pulse width. On the plus side, the setting of ip- ops
to speci c values can be done in parallel; thus the test generation process for sequential
circuits may be faster than in scan-based circuits.

The CrossCheck approach allows high observability of test points in a circuit. This, in con-
junction with the enhanced controllability resulting from the use of CCLs, makes the
CrossCheck approach a powerful design for testability technique. The drawback of the
approach is that the

Dept.of ECE, SJBIT !62

VLSI TESTING 17EVE22

boUNdAry SCAN
Boundary scan methodology was initially developed to control and observe the input and
output pins of chips used in assembling a system on a printed circuit board (PCB), it is now
used to simplify testing of a system-on-a-chip (SOC). An international consortium, the Joint
Test Action Group ( JTAG), proposed a boundary scan architecture that was adopted by the
IEEE Standards Board as IEEE Std. 1149.1 [14]. This architecture provides a single serial
scan path through the input/out- put pins of individual chips on a board. The scan path is
created by connecting the normal inputs/ outputs of the chip logic to the input/output pins of
the chip through boundary scan cells.

Figure 3.30 shows an implementation of a boundary scan cell. The operation of boundary
scan cells is controlled by the test access pat (TAP), which has four inputs: test clock (TCK),
test mode select (TMS), test data input (TDI), and test data output (TDO). During normal
operation, data at the input (Data in) is transferred to the internal logic via the second
multiplexer by setting Mode=0; the data can also stored in the rst ip- op by setting Shift=0
and clocking the ip- op. During the test mode, data at the TDI is scanned in by setting Shift=1
and clocking the rst ip- op; the scanned data is available at TDO. The data captured in rst ip-
op during the normal or the scan mode can be transferred to the output (Data out) by setting
Mode =1 and clocking the Update clock.

Dept.of ECE, SJBIT !63

VLSI TESTING 17EVE22

A chip with boundary scan cells placed next to the pins is shown in Figure 3.31a. These cells
can be interconnected to form a continuous shift register (the boundary scan path) around the
bor- der of the chip. This shift register, as shown in Figure 3.31b, can be used to shift, apply,
or capture test data. During normal operation of a chip, the boundary scan cells are
transparent, and data ap- plied at the input pins ows directly to the circuit. The corresponding
output response of the circuit ows directly to the output pins of the chip.

Dept.of ECE, SJBIT !64

VLSI TESTING 17EVE22

During the scan mode test patterns are shifted in via the TDI pin, and the captured responses
are shifted out via the TDO pin. Thus, the controllability and observability of the pins of a
chip can be achieved without making the pins physically accessible. In addition to the TAP,
the boundary scan architecture includes a controller for the TAP, an instruction register (IR),
and a group of test data registers (TDRs).

Figure 3.32 shows a JTAG boundary scan architecture. The TAP controller is a nite state
machine that generates various control signals—update, shift, or capture data—required in
the boundary scan architecture. The state transitions in the TAP controller occur on the rising
edge of the clock pulse at the TCK pin. The IR is a serial-in/serial-out shift register; the
contents of the shift register are stored in a parallel output latch. Once the contents of the shift
register, i.e., the current instruction, is loaded into the output latch, it can only be changed
when the TAP controller is in either update-IR or test-logic-reset state. In the update-IR state,

Dept.of ECE, SJBIT !65

VLSI TESTING 17EVE22

the newly shifted instruc- tion is loaded into the output latch, whereas in the test-logic-reset
state, all test logic is reset and the chip performs its normal operation. The TAP controller can
be put in the test-logic-reset state from any other state by holding the TMS signal at logic 1
and by applying the TCK pulse at least ve times.

The boundary scan architecture, in addition to the boundary scan register, contains another
DR called the bypass register. The bypass register is only 1 bit wide. As can be seen in Figure
3.32,

Dept.of ECE, SJBIT !66

VLSI TESTING 17EVE22

data at the TDI of a chip can be moved to its TDO through the bypass register in one clock
cycle, rather than the multiple clock cycles required to shift data along the length of the scan
path. Thus, the bypass register is extremely useful if only a small subset of all chips on a
board need to be tested. Optionally, a device identi cation register may be included in a chip
together with the TDRs. It is a 32-bit parallel-in/serial-out shift register and is loaded with
data that identify the chip manufac- ture’s name, part number, and version number when the
TAP controller is in capture-data register (DR) state. The normal operation of a chip is not
affected if either the ID register or the bypass register is in use.

As mentioned previously, boundary scan cells can be interconnected to form a shift register.
This shift register is identi ed as the boundary scan register, the structure of this register is
shown in Figure 3.33. The outputs of all shift register stages are stored in a latch in order to
prevent the change of information while data is being shifted in and out.

A boundary scan register can be con gured to perform three types of tests: external test, in-
ternal test, and sample test. The external test is used to test interconnections for stuck-at and
bridg- ing faults. It is invoked by entering logic 0 into every cell of the IR. Test patterns are
then shifted into the boundary scan register stages at the output pins of a chip via the TDI pin.
These patterns arriving at the input pins of other chips are loaded into their boundary scan
registers, and they are observed via the TDO pins (Figure 3.33).

The internal test allows individual chips in a system to be tested. During this code, test
vectors are shifted into the boundary scan register of the chip under test via the TDI pin. The
correspond- ing test responses are loaded into the boundary scan register and shifted out for
veri cation. Thus, the internal test allows individual chips in a system to be tested. The
sample test allows monitoring of data owing into and out of a chip during its normal
operation. This can aid an external tester in understanding the chip’s performance (Figure
3.34).

Dept.of ECE, SJBIT !67

VLSI TESTING 17EVE22

Module-5
Built-In Self Test:
The task of testing a VLSI chip to guarantee its functionality is extremely complex and often
very time consuming. In addition to the problem of testing the chips themselves, the
incorporation of the chips into systems has caused test generation’s cost to grow
exponentially. A widely accepted approach to deal with the testing problem at the chip level
is to incorporate built-in self-test (BIST) capability inside a chip. This increases the
controllability and the observability of the chip, thereby making the test generation and fault
detection easier. In conventional testing, test patterns are gen- erated externally by using
computer-aided design (CAD) tools. The test patterns and the expected responses of the
circuit under test to these test patterns are used by an automatic test equipment (ATE) to
determine if the actual responses match the expected ones. On the other hand, in BIST, the
test pattern generation and the output response evaluation are done on chip; thus, the use of
expensive ATE machines to test chips can be avoided.

A basic BIST con guration is shown in Figure 4.1. The main function of the test pattern
generator is to apply test patterns to the unit under test (assumed to be a multi-output
combina- tional circuit). The resulting output patterns are transferred to the output response
analyzer. Ideally, a BIST scheme should be easy to implement and must provide a high fault
coverage.

Dept.of ECE, SJBIT !68

VLSI TESTING 17EVE22

exhaustive Testing
In the exhaustive testing approach, all possible input patterns are applied to the circuit under
test. Thus, for an n-input combinational circuit, all possible 2n patterns need to be applied.
The advan- tage of this approach is that all nonredundant faults can be detected; however, any
fault that converts the combinational circuit into a sequential circuit, for example, a bridging
fault, cannot be detected. The drawback of this approach is that when n is large, the test
application time becomes prohibi- tive, even with high clock speeds. Thus, exhaustive testing
is practical only for circuits with a limited number of inputs.

A modi ed form of exhaustive testing is pseudoexhaustive testing [1]. It retains the

advantages of exhaustive testing while signi cantly reducing the number of test patterns to be
applied. The basic idea is to partition the circuit under test into several sub-circuits such that
each sub-circuit has few enough inputs for exhaustive testing to be feasible for it. This
concept has been used in autonomous design veri cation technique proposed in Ref. [2]. To
illustrate the use of the technique, let us consider the circuit shown in Figure 4.2a. The circuit
is partitioned into two sub-circuits C1 and C2 as shown in Figure 4.2b. The functions of the
two added control inputs MC1 and MC2 are as follows:

Dept.of ECE, SJBIT !69

VLSI TESTING 17EVE22

When MC1=0 and MC2=1, sub-circuit C2 is disabled; sub-circuit C1, shown in Figure 4.2c,
can be tested by applying all possible input combinations at a, b, c, and d. Similarly, when
MC1=1 and MC2=0, sub-circuit C1 is disabled. In this mode, the circuit structure is as shown
in Figure 4.2d and sub-circuit C2 can be tested by applying all input combinations at c, d, e,
and f.

When MC1=MC2=0, the circuit functions as the unmodi ed circuit except for the added gate
delay. The advantage of the design method is that any fault in the circuit itself and the testing
circuit is detectable.

A modi ed version of the autonomous testing, called the veri cation testing, has been pro-
posed in Ref. [3]. This method is applicable to multi-output combinational circuits, provided
each output depends only on a proper subset of the inputs. The veri cation test set for a circuit
is derived from its dependence matrix. The dependence matrix of a circuit has m rows and n
columns; each row

Dept.of ECE, SJBIT !70

VLSI TESTING 17EVE22

represents one of the outputs, and each column one of the inputs. An entry [(i, j ): i=1...m,
j=1, n] in the matrix is 1 if the output depends on input j, otherwise the entry is 0, m and n are
the number of outputs and inputs respectively.

To illustrate, the dependence matrix for the circuit of Figure 4.3a is shown in Figure 4.3b.
The dependence matrix is derived by tracing paths from outputs to inputs. A partition-
dependent matrix is then formed by partitioning the columns of dependence matrix into a
minimum number of sets, with each row of a set having at most one 1-entry; there may be a
number of partition- dependent matrices corresponding to a dependent matrix. A partition-
dependent matrix corre- sponding to the dependent matrix of Figure 4.3b is shown in Figure
4.3c.

A veri cation test set is obtained by assigning same values to all inputs belonging to the same
partition of a partition-dependent matrix; any two inputs belonging to different partitions
receive distinct values. Figure 4.3d shows the veri cation test set for Figure 4.3a. A reduced
veri cation test set can be derived from a veri cation test set by removing all repetitions of
identical columns. The reduced veri cation test set for the circuit of Figure 4.3a is shown in
Figure 4.3e.

The veri cation testing is a useful technique for combinational circuits or circuits that can be
transformed into combinational forms during testing (e.g., LSSD structure). However, the
genera- tion of the dependence matrix, which is the most important part of this test strategy,
is a nontrivial task for circuits of VLSI complexity.

Pseudoexhaustive Pattern Generation

A combinational circuit with n inputs can be pseudoexhaustively tested with 2n or fewer
binary pat- terns if none of the outputs of the circuit is a function of more than w out of n

inputs. For example, the following six test patterns can be used to pseudoexhaustively test a
six-input circuit provided no output depends on more than two-input variables:

Dept.of ECE, SJBIT !71

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !72

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !73

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !74

VLSI TESTING 17EVE22

An alternative technique based on LFSR/SR approach called convolved LFSR/SRs uses an n-

stage SR and an LFSR of degree w to generate pseudoexhaustive test patterns for a circuit
with n inputs and m outputs, with no output being a function of more than w input variables
[8] .

The rst step in test pattern generation using a convolved LFSR/SR to assign residues R0
through Ri inputs 0 through i of the circuit under test. The residue of stage i is xi mod P(x)
where P(x) is the primitive polynomial used to implement the LFSR. To illustrate the
computation of resi- dues, let us consider a circuit with ve inputs and ve outputs as shown in
Figure 4.10. The circuit has ve inputs; hence, a ve-stage convolved LFSR/SR is needed.

Dept.of ECE, SJBIT !75

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !76

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !77

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !78

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !79

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !80

VLSI TESTING 17EVE22

The implementation of the CA is shown in Figure 4.15c. Note that a 4-bit LFSR
implementing a primitive polynomial of degree 3 will also generate a sequence of length 16.
CAs based on rules 90 and 160 can generate all primitive and irreducible polynomials of a
given degree [14]. Also, CAs do not require long feedback, which results in smaller delays
and ef cient layouts.

Dept.of ECE, SJBIT !81

VLSI TESTING 17EVE22

4.1.4 deterministic Testing

Traditional test generation techniques may also be used to generate test patterns that can be
ap- plied to the circuit under test when it is in BIST mode. The test patterns and the
corresponding output responses are normally stored in a read only memory (ROM). If the
output responses of the circuit under test do not match the expected responses when the
stored test patterns are applied, the presence of a fault(s) is assumed. Although, in principle,
this is a satisfactory approach for fault detection, it is rarely used because of the high
overhead associated with storing test patterns and their responses.

4.2 oUTPUT reSPoNSe ANALySIS

As stated earlier, BIST techniques usually combine a built-in binary pattern generator with
circuitry for compressing the corresponding response data produced by the circuit under test.
The com- pressed form of the response data is compared with a known fault-free response.
Several compres- sion techniques that can be used in a BIST environment have been
proposed over the years; these include:

Transition count;

Syndrome checking; and

Signature analysis.

4.2.1 Transition Count

The transition count is de ned as the total number of transitions of 1→0 and 0→1 in an output
response sequence corresponding to a given input test sequence. For example, if an output
response sequence Z=10011010, then the transition count c(Z)=4. Thus, instead of recording
the entire out- put response sequence, only the transition count is recorded. The transition
count is then compared with the expected one, and if they differ, the circuit under test is
declared faulty [15].

Figure 4.16a shows the response sequences and the corresponding transition counts at vari-
ous nodes of a circuit resulting from the application of a test sequence of length 4. Let us
suppose there is a fault α s-a-0 in the circuit (Figure 4.16b). The presence of the fault changes
the transition

Dept.of ECE, SJBIT !82

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !83

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !84

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !85

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !86

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !87

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !88

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !89

VLSI TESTING 17EVE22

Dept.of ECE, SJBIT !90

VLSI TESTING 17EVE22

AN INTrodUCTIoN To LoGIC CIrCUIT TeSTING

for simultaneous testing of pipeline structure. For example, in Figure 4.24c circuit, blocks A
and C can be simultaneously tested by operating BILBOs 1 and 3 in the LFSR mode and
BILBOs 2 and 4 in the MISR mode. Circuit block B can be tested individually by making
BILBOs 2 and 3 operate in the LFSR and MISR modes, respectively.

Dept.of ECE, SJBIT !91

VLSI TESTING 17EVE22

Self-Testing Using an MISr and Parallel Shift register Sequence

Generator
Self-testing using an MISR and parallel shift register sequence generator (STUMPS) uses
multiple serial scan paths that are fed by a pseudorandom number generator as shown in
Figure 4.25 [20]. Each scan path corresponds to a segment of the circuit under test and is fed
by a pseudorandom number generator. Because the scan paths may not be of same length, the
pseudorandom generator is run till the largest scan path is loaded. Once data has been loaded
into the scan paths, the system clock is activated. The test results are loaded into the scan
paths and then shifted into the MISR.

Dept.of ECE, SJBIT !92

VLSI TESTING 17EVE22

LSSd on-Chip Self-Test

LSSD on-chip self-test (LOCST) combines pseudorandom testing with LSSD-based circuit
struc- ture [20]. The inputs are applied via boundary scan cells; also, the outputs are obtained
via boundary scan cells. The input and the output boundary scan cells together with the
memory elements in the circuit under test form a scan path. Some of the memory elements at
the beginning of the scan path are con gured into an LFSR for generating pseudorandom
numbers. Also, some memory elements at the end of the scan path are con gured into another
LFSR, which functions as a signature gen- erator. Figure 4.26 shows the LOCST con
guration.

The test process starts by serially loading the scan path consisting of input boundary scan
cells, with pseudorandom patterns generated by the LFSR. These patterns are applied to the
com- binational part of the circuit under test, and the resulting output patterns are loaded in
parallel into the scan path consisting of output boundary scan cells. These output bits are then
shifted into the signature register. The resulting signature is then compared with the reference
signature for veri ca- tion purposes.

Dept.of ECE, SJBIT !93