5 4 3 2 1

TITLE SHEET
COVER SHEET 1
BLOCK DIAGRAM 2
RESET&CLK MAP 3

D
SPEC&CHANGE LIST 4 D

PROCESSOR K8 754 5,6,7,8,9

DDR 1 10
DDR 2 11
DDR ADD/CTL/VTT TERMINATI 12
NORTH BRIDGE(C51G)
SOURTH BRIDGE(MCP51G)
PCI 1&2
13,14,15
16,17,18,19
20
CRU51G+MCP51G
C
FRONT PANEL HEADER
PCI EXPRESS X16 & X1
IDE CONN
21
22
23
VER:1.3A C

POWER CONN & FAN CONTROL 24

FLOOPY / KB / MOUSE / CMOS 25
VGA CONN & TV OUT 26
USB DEVICE 27
SERIAL & PARALLEL 28
AUDIO CODEC 29
AUDIO CONN 30
VCORE POWER SUPPLY 31
MEM_VREG/MEM_VTT 32
B B
LPC SUPER IO(IT8712) 33
FLASH ROM & H/W MON 34
POWER SEQUENCING 35
LAN 10/100/1000 36
OVER VOLTAGE 37
C51 CORE 38
BOM 39

A A

Title
COVER SHEET
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 1 of 39
5 4 3 2 1
 5 4 3 2 1

POWER
D
SUPPLY VREG AMD K8 SOCKET 754 MEMORY D
DDR DIMM(2)
CONN
128-BIT 200/266/333/400 MHZ
HT 16X16 1GHZ

PEX X16 (1) NFORCE VGA

CONN
CRUSH 51G
PEX X1 (1) 468BGA TV OUT
(C51PV ONLY)

HT 4X4 800MHZ
ATA 133
PRIMARY IDE PCI 33MHZ

C NFORCE PCI SLOT (2) C

SECONDARY IDE
MCP 51G
AZALILA/AC97
508BGA
SATA CONN(X4) AUDIO CODEC
INTEGRATED SATA 1/2
LPC BUS 33MHZ USB2.0 (X8)
FLOPPY CONN SIO USB2 PORTS 5-4 BACK PANEL CONN
IT8712 DOUBLE STACK
PS2/KBRD CONN USB2 PORTS 3-2
LAN RJ45
PARALLEL CONN

B USB2 PORTS 1-0 FRONT PANEL HDR B

SERIAL CONN
USB2 PORTS 7-6
H/W MON
RGMII
MII/RGMII
4MB FLASH

A A

Title
SYSTEM BLOCK
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 2 of 39
5 4 3 2 1
 5 4 3 2 1

K8 754 CPU K8 SKT 754

HT_CPU_TXCLK0 MEMORY_A1_CLK[2:0] CHANNEL A1 0-63 CPU RST* CPU_RST*

HT_CPU_TXCLK0* MEMORY_A1_CLK[2:0]*
DIMM 0
RESET MAP CPU PWRGD CPU_PWRGD

HT_CPU_RXCLK0
HT_CPU_RXCLK0* MEMORY_B1_CLK[2:0]
D
CRUSH 51 D
DIMM 1
HT_CPU_TXCLK1 MEMORY_B1_CLK[2:0]* PE_RESET* HT CPU PWRGD HT_CPU_PWRGD
CHANNEL B1 64-127

HT_CPU_TXCLK1* MEMORY_A2_CLK[2:0] CHANNEL A2 0-63 HT CPU RST* HT_CPU_RST*

PEX X16
HT_CPU_RXCLK1 DIMM 2
HT_CPU_RXCLK1* MEMORY_A2_CLK[2:0]* /NI
OPTIONAL HT MCP PWRGD HT_MCP_PWRGD

CPUCLK_IN* MEMORY_B2_CLK[2:0] PEX X1 HT MCP RST* HT_MCP_RST*

DIMM 3
CPUCLK_IN MEMORY_B2_CLK[2:0]* /NI
OPTIONAL
CHANNEL B2 64-127
PEX X1
/NI
MCP 51
CRUSH 51 8712
PWR SWTCH HT_MCP_RST*
CLKOUT_200MHZ PE0_REFCLK PWRBT PWRBTN* HT MCP RST*
CLKOUT_200MHZ* PEX X16 ON* PWR BUTTON
PE0_REFCLK* PWR HT MCP PWRGD HT_MCP_PWRGD
BUTTON* SLP_S3*
HT_CPU_RXCLK1* SLP_S3* SLP S3*
PCI RST0* PCIRST_SLOT1*
HT_CPU_RXCLK1 PE1_REFCLK PWR CONN PS ON
PEX X1 PCI RST1* PCIRST_SLOT2*
HT_CPU_TXCLK1* PE1_REFCLK* POWER_GOOD PWRGD
C HT_CPU_TXCLK1 PS ON PCI RST2* PCIRST_SLOT3-4* C

HT_CPU_RXCLK0* PWR GOOD PCI RST3* PCIRST_IDE*

PE2_REFCLK PWRGD_SB PWRGD_SB
PEX X1 PWRGD SB LPC_RST* LPCRST_FLASH*
HT_CPU_RXCLK0 PE2_REFCLK* /NI
CIRCUIT GPIO_AUX* AC_RESET* LPCRST_SIO* PRI IDE PCI SLOT 3 PCI SLOT2 PCI SLOT1
HT_CPU_TXCLK0* /NI
HT_CPU_TXCLK0

HT_MCP_TXCLK0 SIO FLASH

CLOCK LAN_PHY
RESET*
AUDIO_PHY
RESET*
SEC IDE PCI SLOT4
/NI
HT_MCP_TXCLK0*

HT_MCP_RXCLK0 XTAL_IN
DISTRIBUTION
HT_MCP_RXCLK0*
27 MHZ (TV OUT ONLY)
CLKIN_25MHZ
XTAL_OUT

CLKIN_200MHZ*

CLKIN_200MHZ

MCP 51 PCI SLOT2

B 14MHZ OR 24MHZ B
MCPCLK_OUT BUF_SIO
MCPCLK_OUT*
25MHZ_CLKOUT SUSCLK SIO PCI SLOT1

HT_MCP_RXCLK0*
LPC_CLK0
HT_MCP_RXCLK0 PCI SLOT 3
PCI_CLK0 /NI
HT_MCP_RXCLK0* PCI_CLK1
HT_MCP_RXCLK0 PCI_CLK2
PCI_CLK3 PCI SLOT4
PCI_CLK4 /NI
RTC_XTAL PCI_CLK_FB

32.0 KHZ
FLASH
LPC_CLK1
XTAL_IN AC97/AZALIA LINK
AC_97CLK AC97 CODEC
LPC HEADER
25 MHZ AC_BITCLK

XTAL_OUT BUF_25MHZ LAN PHY

A A

Title
RESET&CLOCK MAP
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 3 of 39
5 4 3 2 1
 5 4 3 2 1

CPU VID TABLE PCI INTERRUPT/IDSEL MAP N51IGP-A7

VID [4..0] VDD VID [4..0] VDD BACK PANEL PCI BUS# DEVICE# IDSEL PIN PCI SLOT PCI SLOT PCI SLOT PCI SLOT REQ/GNT 1. CPU --- AMD Socket 754(3-Phase Power)
0X00000 1.550V 0X10000 1.150V SLOT INTA* INTB* INTC* INTD* 2. CHIPSET --- NF C51 IGP + NF MCP51
D 0X00001 1.525V 0X10001 1.125V 1 01 0X05 27 P_INTZ* P_INTW* P_INTX* P_INTY* 5/5 3. MEMORY --- DDR SDRAM X 2 (Max. 2GB) D

0X00010 1.500V 0X10010 1.100V 2 01 0X06 26 P_INTY* P_INTZ* P_INTW* P_INTX* 4/4 4. SLOTS --- PEX X16 (x1),PEX X1 (x1),PCI (x2)
0X00011 1.475V 0X10011 1.075V 3 01 0X07 25 P_INTX* P_INTY* P_INTZ* P_INTW* 3/3 5. CODEC --- Realtek ALC655 5.1 Channel Audio
0X00100 1.450V 0X10100 1.050V 4 01 0X08 24 P_INTW* P_INTX* P_INTY* P_INTZ* 2/2 6. LAN PHY --- RTL8201
0X00101 1.425V 0X10101 1.025V 5 01 0X09 23 P_INTZ* P_INTW* P_INTX* P_INTY* 1/1 7. LPC/SIO --- IT8712F
0X00110 1.400V 0X10110 1.000V 6 01 0X0A 22 P_INTY* P_INTZ* P_INTW* P_INTX* 0/0 8. SATA -- INTEGRATED
0X00111 1.375V 0X10111 0.975V 9. PCB Size --- 24.4cmx24.4cm, 4-Layer
0X01000 1.350V 0X11000 0.950V PCI DEVICE MAP
0X01001 1.325V 0X11001 0.925V DEVICE PCI BUS# FUNCTION IDSEL PIN DEVICE ID CHANGE LIST
0X01010 1.300V 0X11010 0.900V MCP51
MCP51 LOGICAL 0X01-0X0F -- --
0X01011 1.275V 0X11011 0.875V PCI BUS 0

0X01100 1.250V 0X11100 0.850V MAC /MAC 0 XA 0 0X56/57

0X01101 1.225V 0X11101 0.825V PCI-PCI BRIDGE 0 X9 0 0X005C

0X01110 1.200V 0X11110 0.800V SATA1 0 X8 0 0X0055

0X01111 1.175V 0X11111 OFF SATA0 0 X8 0 0X0054

C C
IDE 0 X6 0 0X0053
SMBUS ADDRESS MAP
MODEM CODEC 0 X4 1 0X0058
DEVICE SMBUS # ADDRESS
AUDIO CODEC 0 X4 0 0X0059
SLOT
USB 2.0 0 X2 1 0X005B
DIMM 0 0 1010 000 = 0X50
USB 1.1 0 X2 0 0X005A
DIMM 1 0 1010 001 = 0X51
SHAPE TRIM 0 X1 2 0X005F
DIMM 2 0 1010 010 = 0X52
LDT 0 X0 0 0X005E
DIMM 3 0 1010 011 = 0X53
SMBUS2 0 X1 1 0X0052
SIO 1 0101 101 = 0X2D
LEGACY SLAVE 0 ? ? 0X00D3
PCI SLOT 1 1 ARP
LPC 0 X1 0 0X0050/51
PCI SLOT 2 1 ARP
LOGICAL PCI BUS 1 ? ? ?
PCI SLOT 3 1 ARP
PCI SLOT 1
PCI SLOT 4 1 ARP
PCI SLOT 2
DDC BUS A ?
PCI SLOT 3
DDC BUS B ?
B PCI SLOT 4 B

PCI SLOT 5
22U/25DE 5*7 mm

100U/16DE 6.3*11 mm

220U/10DE 6.3*11 mm D
O
470U/16DE 8*11 mm D A D C KA
1000U/10DE 8*14 mm

1500U/16DE 10*25 mm
I GO E BC ECB
3300U/25DE 10*25 mm G S A O I C R G S B E A K
G S
TO-263 TO-252 SOT-223 SOT-23 SOT-23 SOT-23 SOT-23 TO-92 TO-92 TO-92
PHB55N03 20N03 AMS1117 LM431 2N7002 2N3904 BAT54C LM431 2N2222A HSD882-D
90N02 TM3055TL-S SI2303S 2N3906 BAT54S 78L05-D 2N2097A
PHD55N03 SI2301S MMBT2907A LM432
2N2222A

A A

Title
SPEC&CHANGE LIST
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 4 of 39
5 4 3 2 1
 5 4 3 2 1

D D
CPU1A
LAYOUT: Place HT bypass caps on topside
+1.2V_HT +1.2V_HT_CPU near unconnected Clawhammer HT Link
D29 VLDT_A6 VLDT0_B6 AH29 +1.2V_HT_CPU
D27 VLDT_A5 VLDT0_B5 AH27
D25 AG28 +1.2V_HT
VLDT_A4 VLDT0_B4 C101 C97
C28 VLDT_A3 VLDT0_B3 AG26
C26 AF29 1UF 16V 0805 Y5V
VLDT_A2 VLDT0_B2 0.1UF 25V Y5V
B29 VLDT_A1 VLDT0_B1 AE28
B27 VLDT_A0 VLDT0_B0 AF25
C180 C181 C233 C320
HTCPU_UP[15..0] HTCPU_DWN[15..0] 1UF 16V 0805 Y5V
13 HTCPU_UP[15..0] HTCPU_DWN[15..0] 13
HTCPU_UP15 T25 N26 HTCPU_DWN15 1UF 16V 0805 Y5V
HTCPU_UP-15 L0_CADIN_H15 L0_CADOUT_H15 HTCPU_DWN-15 0.1UF 25V Y5V
R25 L0_CADIN_L15 L0_CADOUT_L15 N27
HTCPU_UP14 U27 L25 HTCPU_DWN14 0.1UF 25V Y5V
HTCPU_UP-14 L0_CADIN_H14 L0_CADOUT_H14 HTCPU_DWN-14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
HTCPU_UP13 V25 L26 HTCPU_DWN13
HTCPU_UP-13 L0_CADIN_H13 L0_CADOUT_H13 HTCPU_DWN-13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
HTCPU_UP12 W27 J25 HTCPU_DWN12
HTCPU_UP-12 L0_CADIN_H12 L0_CADOUT_H12 HTCPU_DWN-12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
HTCPU_UP11 AA27 G25 HTCPU_DWN11
HTCPU_UP-11 L0_CADIN_H11 L0_CADOUT_H11 HTCPU_DWN-11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
HTCPU_UP10 AB25 G26 HTCPU_DWN10
HTCPU_UP-10 L0_CADIN_H10 L0_CADOUT_H10 HTCPU_DWN-10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
HTCPU_UP9 AC27 E25 HTCPU_DWN9
HTCPU_UP-9 L0_CADIN_H9 L0_CADOUT_H9 HTCPU_DWN-9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
HTCPU_UP8 AD25 E26 HTCPU_DWN8
HTCPU_UP-8 L0_CADIN_H8 L0_CADOUT_H8 HTCPU_DWN-8
C AC25 L0_CADIN_L8 L0_CADOUT_L8 E27 C
HTCPU_UP7 T27 N29 HTCPU_DWN7
HTCPU_UP-7 L0_CADIN_H7 L0_CADOUT_H7 HTCPU_DWN-7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
HTCPU_UP6 V29 M28 HTCPU_DWN6
HTCPU_UP-6 L0_CADIN_H6 L0_CADOUT_H6 HTCPU_DWN-6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
HTCPU_UP5 V27 L29 HTCPU_DWN5
HTCPU_UP-5 L0_CADIN_H5 L0_CADOUT_H5 HTCPU_DWN-5
V28 L0_CADIN_L5 L0_CADOUT_L5 M29
HTCPU_UP4 Y29 K28 HTCPU_DWN4
HTCPU_UP-4 L0_CADIN_H4 L0_CADOUT_H4 HTCPU_DWN-4
W29 L0_CADIN_L4 L0_CADOUT_L4 K27
HTCPU_UP3 AB29 H28 HTCPU_DWN3
HTCPU_UP-3 L0_CADIN_H3 L0_CADOUT_H3 HTCPU_DWN-3
AA29 L0_CADIN_L3 L0_CADOUT_L3 H27
HTCPU_UP2 AB27 G29 HTCPU_DWN2
HTCPU_UP-2 L0_CADIN_H2 L0_CADOUT_H2 HTCPU_DWN-2
AB28 L0_CADIN_L2 L0_CADOUT_L2 H29
HTCPU_UP1 AD29 F28 HTCPU_DWN1
HTCPU_UP-1 L0_CADIN_H1 L0_CADOUT_H1 HTCPU_DWN-1
AC29 L0_CADIN_L1 L0_CADOUT_L1 F27
HTCPU_UP0 AD27 E29 HTCPU_DWN0
HTCPU_UP-0 L0_CADIN_H0 L0_CADOUT_H0 HTCPU_DWN-0
AD28 L0_CADIN_L0 L0_CADOUT_L0 F29
HTCPU_UP-[15..0] HTCPU_DWN-[15..0]
13 HTCPU_UP-[15..0] HTCPU_DWN-[15..0] 13

HTCPU_UPCLK1 Y25 J26 HTCPU_DWNCLK1

13 HTCPU_UPCLK1 L0_CLKIN_H1 L0_CLKOUT_H1 HTCPU_DWNCLK1 13
HTCPU_UPCLK-1 W25 J27 HTCPU_DWNCLK-1
13 HTCPU_UPCLK-1 L0_CLKIN_L1 L0_CLKOUT_L1 HTCPU_DWNCLK-1 13
HTCPU_UPCLK0 Y27 J29 HTCPU_DWNCLK0
13 HTCPU_UPCLK0 L0_CLKIN_H0 L0_CLKOUT_H0 HTCPU_DWNCLK0 13
HTCPU_UPCLK-0 Y28 K29 HTCPU_DWNCLK-0
13 HTCPU_UPCLK-0 L0_CLKIN_L0 L0_CLKOUT_L0 HTCPU_DWNCLK-0 13
+1.2V_HT_CPU R45 49.9 1% CTLIP1 R27 N25
R44 49.9 1% CTLIN1 L0_CTLIN_H1 L0_CTLOUT_H1
R26 L0_CTLIN_L1 L0_CTLOUT_L1 P25
HTCPU_UPCNTL T29 P28 HTCPU_DWNCNTL
13 HTCPU_UPCNTL L0_CTLIN_H0 L0_CTLOUT_H0 HTCPU_DWNCNTL 13
HTCPU_UPCNTL- R29 P27 HTCPU_DWNCNTL-
13 HTCPU_UPCNTL- L0_CTLIN_L0 L0_CTLOUT_L0 HTCPU_DWNCNTL- 13
B B

BGA754S-DIP

A A

Title
K8 HT
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 5 of 39
5 4 3 2 1
 5 4 3 2 1

CPU1B
AE13 VTT_SENSE VTT_A4 D17 +1.25VTT
VTT_A1 A18
VTT_A2 B17
+1.25VREF_CLAW AG12 MEMVREF1 VTT_A3 C17
VTT_B1 AF16
VTT_B2 AG16
+2.5VDIMM R78 33 1% MEMZN D14 AH16
R79 33 1% MEMZP MEMZN VTT_B3
C14 MEMZP VTT_B4 AJ17

LAYOUT: 10/5/10 MEMRESET_L AG10

D LAYOUT: PLACE WITHIN 1 INCH OF CPU D
MD63 A16 AE8
12 MD[63:0] MEMDATA63 MEMCKEA CKE0 10,11,12
MD62 B15 AE7
MEMDATA62 MEMCKEB CKE1 10,11,12
MD61 A12
MD60 MEMDATA61 DCLK7+
B11 D10
MD59
MD58
MD57
A17
A15
C13
MEMDATA60
MEMDATA59
MEMDATA58
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
C10
E12
E11
DCLK7-
DCLK6+
DCLK6-
DCLK7+
DCLK7-
DCLK6+
10,12
10,12
11,12
Clawhammer DDR Interface
MEMDATA57 MEMCLK_L6 DCLK6- 11,12
MD56 A11 AF8 DCLK5+
MEMDATA56 MEMCLK_H5 DCLK5+ 10,12
MD55 A10 AG8 DCLK5-
MEMDATA55 MEMCLK_L5 DCLK5- 10,12
MD54 B9 AF10 DCLK4+
MEMDATA54 MEMCLK_H4 DCLK4+ 11,12
MD53 C7 AE10 DCLK4-
MEMDATA53 MEMCLK_L4 DCLK4- 11,12
MD52 A6 V3
MD51 MEMDATA52 MEMCLK_H3
C11 V4
MD50
MD49
A9
A5
MEMDATA51
MEMDATA50
MEMCLK_L3
MEMCLK_H2 K5
K4
+1.25VREF_CLAW
MD48 MEMDATA49 MEMCLK_L2 DCLK1+
B5 MEMDATA48 MEMCLK_H1 R5 DCLK1+ 11,12
MD47 C5 P5 DCLK1- +2.5VDIMM
MEMDATA47 MEMCLK_L1 DCLK1- 11,12
MD46 A4 P3 DCLK0+
MEMDATA46 MEMCLK_H0 DCLK0+ 10,12
MD45 E2 P4 DCLK0-
MEMDATA45 MEMCLK_L0 DCLK0- 10,12
MD44 E1
MD43 MEMDATA44 +1.25VREF_CLAW
A3 MEMDATA43 MEMCS_L7 D8
MD42 B3 C8 R30
MD41 MEMDATA42 MEMCS_L6 110 1% C54
E3 MEMDATA41 MEMCS_L5 E8
MD40 F1 E7 0.01UF 50V X7R
MD39 MEMDATA40 MEMCS_L4 -CS3
G2 MEMDATA39 MEMCS_L3 D6 -CS3 11,12
MD38 G1 E6 -CS2
MEMDATA38 MEMCS_L2 -CS2 11,12
MD37 L3 C4 -CS1
MEMDATA37 MEMCS_L1 -CS1 10,12
MD36 L1 E5 -CS0 Change R29 C53 C60 C52 C51 C50 C57
MEMDATA36 MEMCS_L0 -CS0 10,12
C MD35 G3 to 1% 110 1% 0.01UF 50V X7R 33P 50V NPO C
MD34 MEMDATA35 0.1UF 25V Y5V 0.1UF 25V Y5V
J2 MEMDATA34 MEMRASA_L H5 -SRASA 10,12
MD33 L2 D4 0.1UF 25V Y5V 1000P 50V X7R /NI
MEMDATA33 MEMCASA_L -SCASA 10,12
MD32 M1 G5
MEMDATA32 MEMWEA_L -SWEA 10,12
MD31 W1
MD30 MEMDATA31
MD29
W3 MEMDATA30 MEMBANKA1 K3 MEMBAA1 10,12 LAYOUT: Place on the bottom of the LAYOUT: Place 39pF LAYOUT: Locate caps
AC1 MEMDATA29 MEMBANKA0 H3 MEMBAA0 10,12
MD28 AC3 board. EMI cap near output close to socket.
MD27 MEMDATA28
W2 MEMDATA27
MD26 Y1
MD25 MEMDATA26
AC2 MEMDATA25 RSVD_MEMADDA15 E13
MD24 AD1 C12
MD23 MEMDATA24 RSVD_MEMADDA14 MAA13
AE1 MEMDATA23 MEMADDA13 E10 MAA[13:0] 10,12
MD22 AE3 AE6 MAA12
MD21 MEMDATA22 MEMADDA12 MAA11
AG3 MEMDATA21 MEMADDA11 AF3
MD20 AJ4 M5 MAA10
MD19 MEMDATA20 MEMADDA10 MAA9
AE2 MEMDATA19 MEMADDA9 AE5
MD18 AF1 AB5 MAA8
MD17 MEMDATA18 MEMADDA8 MAA7
AH3 MEMDATA17 MEMADDA7 AD3
MD16 AJ3 Y5 MAA6
MD15 MEMDATA16 MEMADDA6 MAA5
AJ5 MEMDATA15 MEMADDA5 AB4
MD14 AJ6 Y3 MAA4
MD13 MEMDATA14 MEMADDA4 MAA3
AJ7 MEMDATA13 MEMADDA3 V5
MD12 AH9 T5 MAA2
MD11 MEMDATA12 MEMADDA2 MAA1
AG5 MEMDATA11 MEMADDA1 T3
MD10 AH5 N5 MAA0
MD9 MEMDATA10 MEMADDA0
AJ9 MEMDATA9
MD8 AJ10 H4
MEMDATA8 MEMRASB_L -SRASB 11,12
MD7 AH11 F5
MEMDATA7 MEMCASB_L -SCASB 11,12
B MD6 AJ11 F4 B
MEMDATA6 MEMWEB_L -SWEB 11,12
MD5 AH15
MD4 MEMDATA5
AJ15 MEMDATA4 MEMBANKB1 L5 MEMBAB1 11,12
MD3 AG11 J5
MEMDATA3 MEMBANKB0 MEMBAB0 11,12
MD2 AJ12
MD1 MEMDATA2
AJ14 MEMDATA1 RSVD_MEMADDB_B15 E14
MD0 AJ16 D12
MEMDATA0 RSVD_MEMADDB_B14 MAB13
12 DQS[17:0] MEMADDB_B13 E9 MAB[13:0] 11,12
DQS17 R1 AF6 MAB12
DQS16 MEMDQS17 MEMADDB_B12 MAB11
A13 MEMDQS16 MEMADDB_B11 AF4
DQS15 A7 M4 MAB10
DQS14 MEMDQS15 MEMADDB_B10 MAB9
C2 MEMDQS14 MEMADDB_B9 AD5
DQS13 H1 AC5 MAB8
DQS12 MEMDQS13 MEMADDB_B8 MAB7
AA1 MEMDQS12 MEMADDB_B7 AD4
DQS11 AG1 AA5 MAB6
DQS10 MEMDQS11 MEMADDB_B6 MAB5
AH7 MEMDQS10 MEMADDB_B5 AB3
DQS9 AH13 Y4 MAB4
DQS8 MEMDQS9 MEMADDB_B4 MAB3
T1 MEMDQS8 MEMADDB_B3 W5
DQS7 A14 U5 MAB2
DQS6 MEMDQS7 MEMADDB_B2 MAB1
A8 MEMDQS6 MEMADDB_B1 T4
DQS5 D1 M3 MAB0
DQS4 MEMDQS5 MEMADDB_B0
J1 MEMDQS4
DQS3 AB1 N3 MECC7
MEMDQS3 MEMCHECK7 MECC[7:0] 12
DQS2 AJ2 N1 MECC6
DQS1 MEMDQS2 MEMCHECK6 MECC5
AJ8 MEMDQS1 MEMCHECK5 U3
DQS0 AJ13 V1 MECC4
MEMDQS0 MEMCHECK4 MECC3
MEMCHECK3 N2
P1 MECC2
MEMCHECK2 MECC1
MEMCHECK1 U1
A U2 MECC0 A
MEMCHECK0
BGA754S-DIP

Title
K8 CNTL/STRAPS
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 6 of 39
5 4 3 2 1
 5 4 3 2 1

LAYOUT: Route +2.5VDDA approx. 50mil wide

and 500mils long.(Reference to ground)
+3.3V_STBY
U2
1 8 SMB_SCL
VDD SMB_CL SMB_SDA SMB_SCL 18,20,22,37
2 D+ SMB_DA 7
C69 SMB_ALLERT- SMB_SDA 18,20,22,37
3 D- ALERT# 6
CPU1C SMB_ALLERT- 33
4 T_CRIT_A# VSS 5
2200P 50V X7R /NI
+2.5VDDA LM90 MSOP8 /NI
D R36 0 /NI D
CHIP_THERM- 18,33
AH25 VDDA1 THERMTRIP_L A20 CPU_THERMTRIP- 16
C84 AJ25 R276 680
47P 50V NPO /NI VDDA2 +2.5VDDA
HTCPU_RST- AF20 A26 R42 0
13 HTCPU_RST- RESET_L THERMDA CPU_THERMDA 33
HTCPU_PWRGD AE18 A27 R40 0 ROUTING : 10/10/10
13 HTCPU_PWRGD PWROK THERMDC CPU_THERMDC 33,34
HTCPU_STOP- AJ27
13 HTCPU_STOP- LDTSTOP_L VID4
VID4 AG13 K8_VID4 37
PLACE WITHIN 1 INCH R49 44.2 1% LVREF1 AF27 AF14 VID3
L0_REF1 VID3 K8_VID3 37
10/5/10 +1.2V_HT_CPU R48 44.2 1% LVREF0 AE26 AG14 VID2
L0_REF0 VID2 VID1 K8_VID2 37
VID1 AF15 K8_VID1 37
CPU_CORE_FB A23 AE15 VID0
31 CPU_CORE_FB COREFB_H VID0 K8_VID0 37
CPU_CORE_FB- A24
31 CPU_CORE_FB- COREFB_L
B23 CORE_SENSE NC AG18
ROUTE AS DIFF PAIR NC AH18
10/5/10 10 AE12 AG17 BP1
VDDIOFB_H NC BP0
AF12 VDDIOFB_L NC AJ18
SNS_+2.5VDIMM AE11
32 VDDIO_SENSE VDDIO_SENSE
13 CPU_CLK C75 3900P 50V X7R CPUCK+ AJ21
R50 169 1% CPUCK- CLKIN_H
AH21 CLKIN_L
13 CPU_CLK- C83 3900P 50V X7R
BPSCLK+ AJ23
BPSCLK- NC
ROUTE AS DIF 20/5/5/5/20 AH23 NC 80.6 1%-->82 1%
LAYOUT: PLACE 169 OHM WITHIN 0.5INCH OF CPU
AE24 AH19 FBCLKOUT+ R53 80.6 1%
NC G_FBCLKOUT_H FBCLKOUT-
AF24 NC G_FBCLKOUT_L AJ19
LAYOUT: Route differentially
+1.25VTT C16 VTT_A5
C AG15 with 20/8/5/8/20 RN37 C
VTT_B5 SCANSHENA
LAYOUT: PLACE WITHIN 0.5 INCH OF CPU 1 2
DBRDY AH17 SCANSHENB 3 4
DBRDY -DBREQ SCANCLK1
DBREQ_L AE19 5 6
SCANCLK2 7 8
C15 NC
D20 SCANCLK1 680 8P4R
TMS NC SCANCLK2
E20 TMS NC C21
TCK E17 D18 SCANEN RN9
-TRST TCK NC SCANSHENB +2.5VDDA +2.5VDIMM
B21 TRST_L NC C19 8 7
TDI A21 B19 SCANSHENA SCANEN 6 5
TDI NC BP1 4 3
BP0 2 1

7
5
3
1
SINCHN C18
-BRN NC TDO 680 8P4R RN38
A19 NC TDO A22
680 8P4R
AF18 R31 0 /NI
NC +2.5VDIMM

8
6
4
2
A28 KEY1
AJ28 KEY0 +2.5VDIMM TDI
-TRST
CLAW_ANALOG3 AE23 D22 TMS
CLAW_ANALOG2 NC RSVD_SCL BPSCLK+ R51 820 TDO
AF23 NC RSVD_SDA C22
CLAW_ANALOG1 AF22 BPSCLK- R52 820
CLAW_ANALOG0 NC
AF21 NC
C1 FREE29 FREE26 B13
J3 FREE31 FREE28 B7
R3 FREE33 FREE30 C3
B AA2 K1 LVREF0 C77 1000P 50V X7R B
FREE35 FREE32 LVREF1 C78 1000P 50V X7R
D3 FREE1 FREE34 R2
AG2 FREE37 FREE36 AA3
B18 FREE4 FREE10 F3
AH1 FREE38 FREE18 C23
+2.5VDDA
AE21 FREE41 FREE19 AG7 Modify circuit +2.5VDDA
C20 FREE7 FREE42 AE22
AG4 FREE11 FREE24 C24
C6 A25 C68 0.01UF 50V X7R /NI SINCHN R76 680
FREE12 FREE25 -BRN R75 680
AG6 FREE13 FREE27 C9
AE9 FREE14
AG9 FREE40

BGA754S-DIP CLAW_ANALOG3 8 7
RN11 CLAW_ANALOG2 6 5
680 8P4R CLAW_ANALOG1 4 3
+2.5VDDA 1 2 HTCPU_PWRGD CLAW_ANALOG0 2 1
3 4 -DBREQ
5 6 DBRDY RN15
7 8 TCK 680 8P4R

RN12
1 2 HTCPU_STOP-
3 4
5 6
7 8 HTCPU_RST-
A +2.5VDDA A
680 8P4R

Title
K8 DDR MEM 0-63
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 7 of 39
5 4 3 2 1
 5 4 3 2 1

CPU1E
B2 VSS1 VSS93 L28
CPU1D AH20 R28
VCORE +2.5VDIMM AB21
W22
M23
VSS3
VSS4
VSS5
VSS94
VSS95
VSS96
W28
AC28
AF28
Clawhammer Power and Ground Connections
VSS6 VSS97
L7 VDD1 VDDIO1 E4 L24 VSS7 VSS98 AH28
AC15 VDD2 VDDIO2 G4 AG25 VSS8 VSS99 C29
H18 VDD3 VDDIO3 J4 AG27 VSS9 VSS100 F2
B20 VDD4 VDDIO4 L4 D2 VSS10 VSS101 H2
E21 VDD5 VDDIO5 N4 AF2 VSS11 VSS102 K2
H22 VDD6 VDDIO7 U4 W6 VSS12 VSS103 M2
J23 W4 Y7 P2 VCORE VCORE
VDD7 VDDIO8 VSS13 VSS104
D H24 VDD8 VDDIO9 AA4 AA8 VSS14 VSS105 T2 D
F26 AC4 AB9 V2 BC4 10UF 10V 0805 Y5V /NI
VDD9 VDDIO10 VSS15 VSS106
N7 VDD10 VDDIO11 AE4 AA10 VSS16 VSS107 Y2
L9 D5 J12 AB2 BC2 10UF 10V 0805 Y5V
VDD11 VDDIO12 VSS17 VSS108
V10 VDD12 VDDIO13 AF5 B14 VSS18 VSS109 AD2
G13 F6 Y15 AH2 C147 10UF 10V 0805 Y5V BC8 10UF 10V 0805 Y5V
VDD13 VDDIO14 VSS19 VSS110
K14 VDD14 VDDIO15 H6 AE16 VSS20 VSS111 B4
Y14 K6 J18 AH4 C146 10UF 10V 0805 Y5V
VDD15 VDDIO16 VSS21 VSS112
AB14 VDD16 VDDIO17 M6 G20 VSS22 VSS113 B6
G15 P6 R20 G6 C132 10UF 10V 0805 Y5V
VDD17 VDDIO18 VSS23 VSS114
J15 VDD18 VDDIO19 T6 U20 VSS24 VSS115 J6
AA15 VDD19 VDDIO20 V6 W20 VSS25 VSS116 L6 LAYOUT: Place in uPGA
H16 VDD20 VDDIO21 Y6 AA20 VSS26 VSS117 N6
K16 AB6 AC20 R6 socket cavity.
VDD21 VDDIO22 VSS27 VSS118
Y16 VDD22 VDDIO23 AD6 AE20 VSS28 VSS119 U6
AB16 VDD23 VDDIO24 D7 AG20 VSS29 VSS120 AA6 LAYOUT: Place
G17 VDD24 VDDIO25 G7 AJ20 VSS30 VSS121 AC6
J17 VDD25 VDDIO26 J7 D21 VSS31 VSS122 AH6 LAYOUT: Place 6 EMI 1000p caps
AA17 VDD26 VDDIO27 AA7 F21 VSS32 VSS123 F7 between VRM &
AC17 VDD27 VDDIO28 AC7 H21 VSS33 VSS124 H7 caps along bottom right
AE17 VDD28 VDDIO29 AF7 K21 VSS34 VSS125 K7 side of CPU,2 in middle CPU..
F18 VDD29 VDDIO30 F8 M21 VSS35 VSS126 M7
K18 VDD30 VDDIO31 H8 P21 VSS36 VSS127 P7 of HT link,and 12 along
Y18 AB8 T21 T7
AB18
VDD31 VDDIO32
AD8 V21
VSS37 VSS128
V7
bottom left side of LAYOUT: Place 1 cap every 1~1.5" along VCORE perimiter.
VDD32 VDDIO33 VSS38 VSS129
AD18 VDD33 VDDIO34 D9 Y21 VSS39 VSS130 AB7 CPU.
AG19 VDD34 VDDIO35 G9 AD21 VSS40 VSS131 AD7
E19 VDD35 VDDIO36 AC9 AG21 VSS41 VSS132 B8
G19 VDD36 VDDIO37 AF9 B22 VSS42 VSS133 G8
C AC19 VDD37 VDDIO38 F10 E22 VSS43 VSS134 J8 C
AA19 VDD38 VDDIO39 AD10 G22 VSS44 VSS135 L8
J19 VDD39 VDDIO40 D11 J22 VSS45 VSS136 N8
F20 VDD40 VDDIO41 AF11 L22 VSS46 VSS137 R8
H20 VDD41 VDDIO42 F12 N22 VSS47 VSS138 U8
K20 VDD42 VDDIO43 AD12 R22 VSS48 VSS139 W8
M20 D13 U22 AC8 +2.5VDIMM
VDD43 VDDIO44 VSS49 VSS140 VCORE +2.5VDIMM
P20 VDD44 VDDIO45 AF13 AG29 VSS50 VSS141 AH8
T20 VDD45 VDDIO46 F14 AA22 VSS51 VSS142 F9
V20 AD14 AC22 H9 BC5 10UF 10V 0805 Y5V /NI C159 0.1UF 25V Y5V
VDD46 VDDIO47 VSS52 VSS143
Y20 VDD47 VDDIO48 F16 AG22 VSS53 VSS144 K9
AB20 AD16 AH22 M9 BC3 10UF 10V 0805 Y5V
VDD48 VDDIO49 VSS54 VSS145
AD20 VDD49 VDDIO50 D15 AJ22 VSS55 VSS146 P9
G21 R4 D23 T9 C141 1UF 16V 0805 Y5V /NI
VDD50 VDDIO6 VCORE VSS56 VSS147
J21 VDD51 F23 VSS57 VSS148 V9
L21 N28 H23 Y9 BC9 10UF 10V 0805 Y5V C86 0.1UF 25V Y5V
VDD52 VDD96 VSS58 VSS149
N21 VDD53 VDD97 U28 K23 VSS59 VSS150 AD9
R21 VDD54 VDD98 AA28 P23 VSS60 VSS151 B10
U21 VDD55 VDD99 AE27 T23 VSS61 VSS152 G10
W21 R7 V23 J10 VCORE
VDD56 VDD100 VSS62 VSS153
AA21 VDD57 VDD101 U7 Y23 VSS63 VSS155 L10
AC21 W7 AB23 N10 BC6 10UF 10V 0805 Y5V /NI
VDD58 VDD102 VSS64 VSS156
F22 VDD59 VDD103 K8 AD23 VSS65 VSS157 R10
K22 M8 AG23 U10 BC7 10UF 10V 0805 Y5V /NI +2.5VDIMM
VDD60 VDD104 VSS66 VSS158
M22 VDD61 VDD105 P8 E24 VSS67 VSS159 W10
P22 VDD62 VDD106 T8 G24 VSS68 VSS160 AC10
T22 VDD63 VDD107 V8 J24 VSS69 VSS161 AH10
V22 Y8 N24 F11 C128 1UF 16V 0805 Y5V
VDD64 VDD108 VSS70 VSS162
Y22 VDD65 VDD109 J9 R24 VSS71 VSS163 H11
B AB22 N9 U24 K11 C170 1UF 16V 0805 Y5V B
VDD66 VDD110 VSS72 VSS164
AD22 VDD67 VDD111 R9 W24 VSS73 VSS165 Y11
E23 U9 AA24 AB11 VCORE
VDD68 VDD112 VSS74 VSS166
G23 VDD69 VDD113 W9 AC24 VSS75 VSS167 AD11
L23 VDD70 VDD114 AA9 AG24 VSS76 VSS168 B12
N23 VDD71 VDD115 H10 AJ24 VSS77 VSS169 G12
R23 K10 B25 AA12 C194 1UF 16V 0805 Y5V
VDD72 VDD116 VSS78 VSS170
U23 VDD73 VDD117 M10 C25 VSS79 VSS171 AC12
W23 VDD74 VDD118 P10 B26 VSS80 VSS172 AH12
AA23 VDD75 VDD119 T10 D26 VSS81 VSS173 F13
AC23 Y10 H26 H13 C137 1UF 16V 0805 Y5V /NI
VDD76 VDD120 VSS82 VSS174
B24 VDD77 VDD121 AB10 M26 VSS83 VSS175 K13
C142 1UF 16V 0805 Y5V /NI
LAYOUT: Located close to socket
D24 VDD78 VDD122 G11 T26 VSS84 VSS176 Y13
F24 VDD79 VDD123 J11 Y26 VSS85 VSS177 AB13
K24 AA11 AD26 AD13 C131 10UF 10V 0805 Y5V
VDD80 VDD124 VSS86 VSS178
M24 VDD81 VDD125 AC11 AF26 VSS87 VSS179 AF17
P24 H12 AH26 G14 C136 1UF 16V 0805 Y5V /NI
VDD82 VDD126 VSS88 VSS180
T24 VDD83 VDD127 K12 C27 VSS89 VSS181 J14
V24 VDD84 VDD128 Y12 B28 VSS90 VSS182 AA14
Y24 VDD85 VDD129 AB12 D28 VSS91 VSS183 AC14
AB24 VDD86 VDD130 J13 G28 VSS92 VSS184 AE14
AD24 VDD87 VDD131 AA13 F15 VSS187 VSS185 D16
AH24 AC13 H15 E15 +1.25VTT +2.5VDIMM
VDD88 VDD132 VSS188 VSS186
AE25 VDD89 VDD133 H14 AB17 VSS206 VSS189 K15
K26 AB26 AD17 AB15 C223 0.1UF 25V Y5V
VDD90 VDD93 VSS207 VSS190
P26 VDD91 VDD94 E28 B16 VSS208 VSS191 AD15
V26 VDD92 VDD95 J28 G18 VSS209 VSS192 AH14
AA18 VSS210 VSS194 E16
AC18 VSS211 VSS195 G16
A BGA754S-DIP D19 J16 A
VSS212 VSS196
F19 VSS213 VSS197 AA16
H19 VSS214 VSS198 AC16
K19 VSS215 VSS199 AE29
Y19 VSS216 VSS223 AJ26
AB19 VSS217 VSS201 E18
AD19 VSS218 VSS202 F17
AF19 VSS219 VSS203 H17
J20 K17 Title
VSS220 VSS204
L20
N20
VSS221 VSS205 Y17 K8 DDR MEM 64-127
VSS222 Size Document Number Rev
Custom 1.3
BGA754S-DIP CRU51-M7
Date: Monday, April 10, 2006 Sheet 8 of 39
5 4 3 2 1
 5 4 3 2 1

2.5V/150mA
D D
+3.3V FB8
BEAD 60 0805 1A /NI
D S +2.5VDDA

Q15

G
2N7002 SOT23 /NI C81
1UF 16V 0805 Y5V

+
R32 R1

-
20 1% /NI
CT7
R24 1K 1% /NI 100UF 16V 5X11 2mm /NI
+12V

Vout=Vref (2.5V) X ( 1+R1/R2 )

=2.55V

R
Change R33 R2
D5 to 1%
1K 1% /NI
LM431 SOT23 /NI

A
C C

B B

A A

Title
AMD-K8-POWER
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 9 of 39
5 4 3 2 1
 5 4 3 2 1

+2.5VDIMM

DIMM1

104
112
128
136
143
156
164
172
180

108
120
148
168
15
22
30
54
62
77
96

38
46
70
85
7
DIMM1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D MAA0 48 2 MD_0 D
6,12 MAA[13:0] A0 D0 MD_1 MD_[63:0] 11,12
MAA1 43 4
MAA2 A1 D1 MD_2
41 A2 D2 6
MAA3 130 8 MD_3
MAA4 A3 D3 MD_4
37 A4 D4 94
MAA5 32 95 MD_5
MAA6 A5 D5 MD_6
125 A6 D6 98
MAA7 29 99 MD_7
MAA8 A7 D7 MD_8
122 A8 D8 12
MAA9 27 13 MD_9
MAA10 A9 D9 MD_10
141 A10 D10 19
MAA11 118 20 MD_11
MAA12 A11 D11 MD_12
115 A12 D12 105
MAA13 167 106 MD_13
A13 D13 MD_14
D14 109
MEMBAA0 59 110 MD_15
6,12 MEMBAA0 MEMBAA1 BA0 D15
52 23 MD_16
6,12 MEMBAA1 BA1 D16
113 24 MD_17
BA2 D17 MD_18
D18 28
157 31 MD_19
6,12 -CS0 CS0 D19
158 114 MD_20
6,12 -CS1 CS1 D20
71 117 MD_21
NC/CS2 D21 MD_22
163 NC/CS3 D22 121
123 MD_23
11,12 DQS_[17:0] D23
DQS_9 97 33 MD_24
DQS_10 DQM0 D24 MD_25
107 DQM1 D25 35
DQS_11 119 39 MD_26 +2.5VDIMM
DQS_12 DQM2 D26 MD_27
129 DQM3 D27 40
DQS_13 149 126 MD_28
DQS_14 DQM4 D28 MD_29
C 159 DQM5 D29 127 C
DQS_15 169 131 MD_30 LAYOUT: Place 39pf +1.25VREF_MEM
DQS_16 DQM6 D30 MD_31 R25 C41
177 DQM7 D31 133 Change
DQS_17 140 53 MD_32 to 1% 100 1% 0.01UF 50V X7R EMI cap near output LAYOUT: Locate caps
DQM8 D32 MD_33
D33 55
-SWEA 63 57 MD_34 close to DIMMs.
6,12
6,12
-SWEA
-SCASA
-SCASA
-SRASA
65
154
WE
CAS
D34
D35 60
146
MD_35
MD_36
+1.25VREF_MEM
6,12 -SRASA RAS D36
147 MD_37 Change R26 C43 C44 C42 C45
CKE0 D37 MD_38 100 1% 0.1UF 25V Y5V 33P 50V NPO 1000P 50V X7R /NI
6,11,12 CKE0 21 CKE0 D38 150 to 1%
CKE1 111 151 MD_39 0.1UF 25V Y5V /NI
6,11,12 CKE1 CKE1 D39
61 MD_40
DCLK5+ D40 MD_41
6,12 DCLK5+ 16 CK0/DNU D41 64
DCLK5- 17 68 MD_42
6,12 DCLK5- CK0/DNU D42
DCLK0+ 137 69 MD_43
6,12 DCLK0+ CK1 D43
DCLK0- 138 153 MD_44
6,12 DCLK0- CK1 D44
DCLK7+ 76 155 MD_45
6,12 DCLK7+ CK2/DNU D45
DCLK7- 75 161 MD_46
6,12 DCLK7- CK2/DNU D46
162 MD_47
DQS_0 D47 MD_48
11,12 DQS_[17:0] 5 DQS0 D48 72
DQS_1 14 73 MD_49
DQS_2 DQS1 D49 MD_50
25 DQS2 D50 79
DQS_3 36 80 MD_51
DQS_4 DQS3 D51 MD_52
56 DQS4 D52 165
DQS_5 67 166 MD_53
DQS_6 DQS5 D53 MD_54
78 DQS6 D54 170
DQS_7 86 171 MD_55
DQS_8 DQS7 D55 MD_56
47 DQS8 D56 83
84 MD_57
11,18 SMB_MEM_SDA D57
B SMBDT 91 87 MD_58 B
11,18 SMBDT SDA D58
SMBCK 92 88 MD_59
11,18 SMBCK SCL D59
174 MD_60
11,18 SMB_MEM_SCL D60
181 175 MD_61
SA0 D61 MD_62
182 SA1 D62 178
183 179 MD_63
SA2 D63
1 44 MECC_0
+1.25VREF_MEM VREF CB0 MECC_[7:0] 11,12
82 45 MECC_1
VDDID CB1 MECC_2
+2.5VDIMM 184 VDDSPD CB2 49
51 MECC_3
CB3 MECC_4
9 NC CB4 134
10 135 MECC_5
NC/RESET CB5 MECC_6
101 NC CB6 142
102 144 MECC_7
NC CB7
173 NC
R38 0 /NI FETEN 103 90 R143 4.7K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC/FETEN WP +2.5VDIMM

DDRAM184 NYLON LOTES B

100
116
124
132
139
145
152
160
176

11 FETEN
11
18
26
34
42
50
58
66
74
81
89
93
3

A A

Title
DDR DIMM1
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 10 of 39
5 4 3 2 1
 5 4 3 2 1

+2.5VDIMM

DIMM2

104
112
128
136
143
156
164
172
180

108
120
148
168
15
22
30
54
62
77
96

38
46
70
85
7
D DIMM2 D

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
6,12 MAB[13:0] MD_0 MD_[63:0] 10,12
MAB0 48 2
MAB1 A0 D0 MD_1
43 A1 D1 4
MAB2 41 6 MD_2
MAB3 A2 D2 MD_3
130 A3 D3 8
MAB4 37 94 MD_4
MAB5 A4 D4 MD_5
32 A5 D5 95
MAB6 125 98 MD_6
MAB7 A6 D6 MD_7
29 A7 D7 99
MAB8 122 12 MD_8
MAB9 A8 D8 MD_9
27 A9 D9 13
MAB10 141 19 MD_10
MAB11 A10 D10 MD_11
118 A11 D11 20
MAB12 115 105 MD_12
MAB13 A12 D12 MD_13
167 A13 D13 106
109 MD_14
MEMBAB0 D14 MD_15
6,12 MEMBAB0 59 BA0 D15 110
MEMBAB1 52 23 MD_16
6,12 MEMBAB1 BA1 D16
113 24 MD_17
BA2 D17 MD_18
D18 28
157 31 MD_19
6,12 -CS2 CS0 D19
158 114 MD_20
6,12 -CS3 CS1 D20
71 117 MD_21
NC/CS2 D21 MD_22
163 NC/CS3 D22 121
123 MD_23
10,12 DQS_[17:0] D23
DQS_9 97 33 MD_24
DQS_10 DQM0 D24 MD_25
107 DQM1 D25 35
C DQS_11 119 39 MD_26 C
DQS_12 DQM2 D26 MD_27
129 DQM3 D27 40
DQS_13 149 126 MD_28
DQS_14 DQM4 D28 MD_29
159 DQM5 D29 127
DQS_15 169 131 MD_30
DQS_16 DQM6 D30 MD_31
177 DQM7 D31 133
DQS_17 140 53 MD_32
DQM8 D32 MD_33
D33 55
-SWEB 63 57 MD_34
6,12 -SWEB WE D34
-SCASB 65 60 MD_35
6,12 -SCASB CAS D35
-SRASB 154 146 MD_36
6,12 -SRASB RAS D36
147 MD_37
CKE0 D37 MD_38
6,10,12 CKE0 21 CKE0 D38 150
CKE1 111 151 MD_39
6,10,12 CKE1 CKE1 D39
61 MD_40
D40 MD_41
6,12 DCLK4+ 16 CK0/DNU D41 64
17 68 MD_42
6,12 DCLK4- CK0/DNU D42
137 69 MD_43
6,12 DCLK1+ CK1 D43
138 153 MD_44
6,12 DCLK1- CK1 D44
76 155 MD_45
6,12 DCLK6+ CK2/DNU D45
75 161 MD_46
6,12 DCLK6- CK2/DNU D46
162 MD_47
DQS_0 D47 MD_48
10,12 DQS_[17:0] 5 DQS0 D48 72
DQS_1 14 73 MD_49
DQS_2 DQS1 D49 MD_50
25 DQS2 D50 79
DQS_3 36 80 MD_51
DQS_4 DQS3 D51 MD_52
56 DQS4 D52 165
DQS_5 67 166 MD_53
DQS_6 DQS5 D53 MD_54
78 DQS6 D54 170
B
DQS_7 86 171 MD_55 B
DQS_8 DQS7 D55 MD_56
47 DQS8 D56 83
84 MD_57
SMBDT D57 MD_58
10,18 SMBDT 91 SDA D58 87
SMBCK 92 88 MD_59
10,18 SMBCK SCL D59
174 MD_60
D60 MD_61
+2.5VDIMM 181 SA0 D61 175
182 178 MD_62
SA1 D62 MD_63
183 SA2 D63 179
MECC_[7:0] 10,12
1 44 MECC_0
+1.25VREF_MEM VREF CB0
82 45 MECC_1
VDDID CB1 MECC_2
+2.5VDIMM 184 VDDSPD CB2 49
51 MECC_3
CB3 MECC_4
9 NC CB4 134
10 135 MECC_5
NC/RESET CB5 MECC_6
101 NC CB6 142
102 144 MECC_7
NC CB7 R142
173 NC
FETEN 103 90 WWP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

10 FETEN NC/FETEN WP +2.5VDIMM

4.7K
DDRAM184 NYLON LOTES B
100
116
124
132
139
145
152
160
176
11
18
26
34
42
50
58
66
74
81
89
93
3

A A

Title
DDR DIMM2
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 11 of 39
5 4 3 2 1
 5 4 3 2 1

+1.25VTT
MD0
MD4
MD5
1
3
5
2
4
6
RN8
10 8P4R
MD_0
MD_4
MD_5
MD_0
MD_4
MD_5
1
3
5
2
4
6
RN5
47 8P4R
DDR Termination +1.25VTT +2.5VDIMM +1.25VTT

MD1 7 8 MD_1 MD_1 7 8 C213 0.1UF 25V Y5V

MD2 1 2 MD_2 DQS_0 1 2 +1.25VTT
MD6 3 4 RN13 MD_6 DQS_9 3 4 RN6 C158 0.1UF 25V Y5V
MD7 5 6 10 8P4R MD_7 MD_2 5 6 47 8P4R MAB2 MECC_5 1 2
MD3 MD_3 MD_6 6 MD[63:0] MAA2 MAA1
7 8 7 8 3 4 RN34
D MD14 1 2 MD_14 MD_11 7 8 MAB1 MECC_0 5 6 47 8P4R D
MD15 3 4 RN19 MD_15 MD_10 5 6 RN14 MAA1 MECC_1 7 8
MD_10 MD_15 6 DQS[17:0] MAB7
MD10 5 6 10 8P4R 3 4 47 8P4R MAB5 1 2
MD11 7 8 MD_11 MD_14 1 2 MAA5 MAA7 3 4 RN23
MD20 1 2 MD_20 CKE1 1 2 MAB6 MAB8 5 6 47 8P4R
MD16 3 4 RN22 MD_16 MD_20 3 4 RN17 MAA6 MAA8 7 8
MD_17 MD_16 10,11 MD_[63:0]
MD17 5 6 10 8P4R 5 6 47 8P4R MAB11 MD_24 1 2
MD21 7 8 MD_21 MD_17 7 8 MAA11 MD_28 3 4 RN26 C85 0.1UF 25V Y5V
MD18 1 2 MD_18 CKE0 1 2 MAA9 MAB6 5 6 47 8P4R
MD_22 MAB12 10,11 DQS_[17:0] MAA6
MD22 3 4 RN25 3 4 RN18 MAB9 7 8
MD19 5 6 10 8P4R MD_19 MAA12 5 6 47 8P4R MAA0 MD_12 1 2
MD23 7 8 MD_23 MAB11 7 8 MAA10 MD_13 3 4 RN10 C297 0.1UF 25V Y5V
MD_24 MD_21 6,10 MAA[13:0] MAB0 DQS_1
MD24 1 2 1 2 5 6 47 8P4R
MD28 3 4 RN27 MD_28 MAA11 3 4 RN20 MAB10 DQS_10 7 8
MD25 5 6 10 8P4R MD_25 MAA9 5 6 47 8P4R MAB4 MD_31 1 2
MD_29 MAB9 6,11 MAB[13:0] MAA2
MD29 7 8 7 8 MAA4 3 4 RN32
MD26 1 2 MD_26 MD_30 1 2 MAB3 MECC_4 5 6 47 8P4R
MD30 3 4 RN31 MD_30 MAA3 3 4 RN30 MAA3 MAB1 7 8
MD27 5 6 10 8P4R MD_27 MD_27 5 6 47 8P4R MAB7 MD_25 1 2
MD31 7 8 MD_31 MAB2 7 8 MAA7 MD_29 3 4 RN28 C269 0.1UF 25V Y5V
MD32 1 2 MD_32 MAB4 1 2 MAB8 DQS_3 5 6 47 8P4R
MD36 3 4 RN39 MD_36 MAA4 3 4 RN29 MAA8 DQS_12 7 8
MD33 5 6 10 8P4R MD_33 MAB3 5 6 47 8P4R MEMBAA1 MD_19 1 2
MD_37 MD_26 6,10 MEMBAA1 MD_23
MD37 7 8 7 8 MEMBAB1 3 4 RN24
MD_34 MD_33 6,11 MEMBAB1 MAB5
MD34 1 2 1 2 MEMBAB0 5 6 47 8P4R
MD_38 6,11 MEMBAB0 MAA5
MD38 3 4 RN43 MD_37 3 4 RN42 MEMBAA0 7 8 C165 0.1UF 25V Y5V
MD_39 DQS_4 6,10 MEMBAA0 -CS1
MD39 5 6 10 8P4R 5 6 47 8P4R
MD_35 DQS_13 6,10 -CS1 -CS3
MD35 7 8 7 8 DQS_5 1 2
MD_40 6,11 -CS3
MD40 1 2 MD_34 1 2 MAB13 DQS_14 3 4 RN53
C MD44 3 4 RN45 MD_44 MD_38 3 4 RN44 MAA13 MD_42 5 6 47 8P4R C94 0.1UF 25V Y5V C
MD45 5 6 10 8P4R MD_45 MEMBAB0 5 6 47 8P4R -SRASA MD_43 7 8
MD41 MD_41 MD_39 6,10 -SRASA
7 8 7 8 -SRASB
MD_48 6,11 -SRASB
MD48 1 2 MD_46 1 2 -SWEA MAA0 1 2
MD_49 6,10 -SWEA
MD49 3 4 RN51 MD_47 3 4 RN57 -SWEB MAA10 3 4 RN35 C277 0.1UF 25V Y5V
MD_52 6,11 -SWEB -CS0 MAB0
MD52 5 6 10 8P4R MD_48 5 6 47 8P4R 5 6 47 8P4R
MD_53 6,10 -CS0 MAB10
MD53 7 8 MD_49 7 8 -SCASA 7 8 C149 0.1UF 25V Y5V
MD_54 6,10 -SCASA
MD54 1 2 -SCASB 1 2 -SCASB MEMBAA0 1 2
MD_50 -CS1 6,11 -SCASB MD_35
MD50 3 4 RN55 3 4 RN52 -CS2 3 4 RN46 C231 0.1UF 25V Y5V C143 0.1UF 25V Y5V
MD_55 -CS2 6,11 -CS2 CKE1 MD_40
MD55 5 6 10 8P4R 5 6 47 8P4R 5 6 47 8P4R
MD_51 -CS3 6,10,11 CKE1 CKE0 MD_44
MD51 7 8 7 8 7 8
MD_60 DQS_15 6,10,11 CKE0 MAB12 -SRASA
MD60 1 2 1 2 1 2
MD56 3 4 RN59 MD_56 DQS_6 3 4 RN62 MAA12 -SRASB 3 4 RN47 C61 0.1UF 25V Y5V
MD61 5 6 10 8P4R MD_61 MD_54 5 6 47 8P4R -SWEA 5 6 47 8P4R
MD57 7 8 MD_57 MD_50 7 8 MD_45 7 8
MD62 1 2 MD_62 MD_55 1 2
MD58 3 4 RN64 MD_58 MD_51 3 4 RN65 C205 0.1UF 25V Y5V
MD63 5 6 10 8P4R MD_63 MD_60 5 6 47 8P4R +1.25VTT +1.25VTT
MD59 7 8 MD_59 MD_56 7 8 C253 0.1UF 25V Y5V C116 0.1UF 25V Y5V
MD8 1 2 MD_8 MD_62 1 2
MD9 3 4 RN16 MD_9 MD_58 3 4 RN70 C108 0.1UF 25V Y5V
MD12 5 6 10 8P4R MD_12 MD_63 5 6 47 8P4R +1.25VTT
MD13 7 8 MD_13 MD_59 7 8
MD42 1 2 MD_42 MD_61 1 2
MD43 RN48 MD_43 MD_57 RN68
MD46
3 4
10 8P4R MD_46 DQS_16
3 4
47 8P4R C125 0.1UF 25V Y5V
LAYOUT: Place alternating caps to GND and
5 6 5 6
MD47 7 8 MD_47 DQS_7 7 8 +2.5VDIMM in a single line along VTT island.
MECC_7 1 2 C234 0.1UF 25V Y5V C133 0.1UF 25V Y5V LAYOUT: Place a cap every 1 inch on VTT
DQS0 R39 0 DQS_0 MEMBAB1 3 4 RN41
B DQS1 R54 0 DQS_1 MD_32 5 6 47 8P4R C82 1UF 16V 0805 Y5V trace between Clawhammer and DDR. B
DQS2 R58 0 DQS_2 MD_36 7 8
DQS3 R65 0 DQS_3 MECC_2 1 2
DQS4 R101 0 DQS_4 MECC_6 3 4 RN40
DQS5 R106 0 DQS_5 MECC_3 5 6 47 8P4R C197 0.1UF 25V Y5V
DQS6 R109 0 DQS_6 MEMBAA1 7 8
DQS7 R130 0 DQS_7 MD_7 1 2 +2.5VDIMM +1.25VTT
DQS8 R70 0 DQS_8 MD_3 3 4 RN7 +2.5VDIMM +1.25VTT
DQS9 R41 0 DQS_9 MD_8 5 6 47 8P4R C100 0.1UF 25V Y5V
DQS10 R56 0 DQS_10 MD_9 7 8
DQS11 R59 0 DQS_11 -SWEB 1 2 C175 0.1UF 25V Y5V C246 0.1UF 25V Y5V
DQS12 R66 0 DQS_12 -CS0 RN50
DQS13 R102 0 DQS_13 MD_41
3 4
47 8P4R
LAYOUT: Add 100pF C74 0.1UF 25V Y5V
5 6
DQS14 R107 0 DQS_14 -SCASA 7 8 and 1000pF VTT fill near C238 0.1UF 25V Y5V
DQS15 R108 0 DQS_15 DQS_8 R71 47
DQS16 R127 0 DQS_16 DQS_2
Clawhammer and near
1 2
DQS17 R74 0 DQS_17 DQS_11 3 4 RN21 C257 0.1UF 25V Y5V DIMMs (Both Sides) C33 0.1UF 25V Y5V
MD_18 5 6 47 8P4R
MD_22 7 8
MD_52 1 2 LAYOUT: Place on backside, evenly spaced around
MD_53 3 4 RN60
MAB13 5 6 47 8P4R +2.5VDIMM VTT fill.
MAA13 7 8
DQS_17 R85 47 CT17 1000UF 6.3V 8X12

C235 0.1UF 25V Y5V

C214 0.1UF 25V Y5V

A
MECC2 1 2 MECC_2 A
6 MECC[7:0] MECC6 MECC_6 MECC_[7:0] 10,11
3 4
MECC3 5 6 MECC_3 RN36 R82 120
MECC7 MECC_7 6,10 DCLK7- DCLK7+ 6,10
7 8 10 8P4R R77 120
MECC4 MECC_4 6,11 DCLK6- DCLK6+ 6,11
1 2 R47 120
MECC5 MECC_5 6,10 DCLK5- DCLK5+ 6,10
3 4 R46 120
MECC0 MECC_0 6,11 DCLK4- DCLK4+ 6,11
5 6 RN33 R60 120
MECC1 MECC_1 6,11 DCLK1- DCLK1+ 6,11
7 8 10 8P4R R61 120 1000UF 6.3V 8X12
6,10 DCLK0- DCLK0+ 6,10 Title
DDR TERMINATION
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 12 of 39
5 4 3 2 1
 5 4 3 2 1

D D

HTCPU_DWN[15..0] U8A HTCPU_UP[15..0]

5 HTCPU_DWN[15..0] HTCPU_UP[15..0] 5
HTCPU_DWN0 Y23 C23 HTCPU_UP0 U8B
HTCPU_DWN1 HT_CPU_RXD+0 HT_CPU_TXD+0 HTCPU_UP1 HTMCP_UP[7..0] HTMCP_DWN[7..0]
HTCPU_DWN2
W24 HT_CPU_RXD+1 C51 HT_CPU_TXD+1 D23
HTCPU_UP2 16 HTMCP_UP[7..0] HTMCP_UP0
C51
HTMCP_DWN0
HTMCP_DWN[7..0] 16
V24 HT_CPU_RXD+2 HT_CPU_TXD+2 E22 AD6 HT_MCP_RXD+0 HT_MCP_TXD+0 AC24
HTCPU_DWN3 HTCPU_UP3 HTMCP_UP1 HTMCP_DWN1
HTCPU_DWN4
U22 HT_CPU_RXD+3 1 OF 6 HT_CPU_TXD+3 F23
HTCPU_UP4 HTMCP_UP2
AC7 HT_MCP_RXD+1 2 OF 6 HT_MCP_TXD+1 AD23
HTMCP_DWN2
R24 HT_CPU_RXD+4 HT_CPU_TXD+4 H22 AA8 HT_MCP_RXD+2 HT_MCP_TXD+2 AC22
HTCPU_DWN5 HTCPU_UP5 HTMCP_UP3 HTMCP_DWN3
HTCPU_DWN6
P24 HT_CPU_RXD+5 CPU HT_CPU_TXD+5 J21
HTCPU_UP6 HTMCP_UP4
AA9 HT_MCP_RXD+3 HT_MCP HT_MCP_TXD+3 AC20
HTMCP_DWN4
P22 HT_CPU_RXD+6 HT_CPU_TXD+6 K21 AD10 HT_MCP_RXD+4 HT_MCP_TXD+4 AB18
HTCPU_DWN7 N22 K23 HTCPU_UP7 HTMCP_UP5 AD11 AA17 HTMCP_DWN5
HTCPU_DWN8 HT_CPU_RXD+7 HT_CPU_TXD+7 HTCPU_UP8 HTMCP_UP6 HT_MCP_RXD+5 HT_MCP_TXD+5 HTMCP_DWN6
Y21 HT_CPU_RXD+8 HT_CPU_TXD+8 D21 AC12 HT_MCP_RXD+6 HT_MCP_TXD+6 AB16
HTCPU_DWN9 V21 F19 HTCPU_UP9 HTMCP_UP7 AC13 AC16 HTMCP_DWN7
HTCPU_DWN10 HT_CPU_RXD+9 HT_CPU_TXD+9 HTCPU_UP10 HT_MCP_RXD+7 HT_MCP_TXD+7
W21 HT_CPU_RXD+10 HT_CPU_TXD+10 F21 AA6 HT_MCP_RXD+8 HT_MCP_TXD+8 AB21
HTCPU_DWN11 T21 G20 HTCPU_UP11 W7 AB20
HTCPU_DWN12 HT_CPU_RXD+11 HT_CPU_TXD+11 HTCPU_UP12 HT_MCP_RXD+9 HT_MCP_TXD+9
R18 HT_CPU_RXD+12 HT_CPU_TXD+12 J19 Y8 HT_MCP_RXD+10 HT_MCP_TXD+10 AB19
HTCPU_DWN13 P16 L17 HTCPU_UP13 V9 W18
HTCPU_DWN14 HT_CPU_RXD+13 HT_CPU_TXD+13 HTCPU_UP14 HT_MCP_RXD+11 HT_MCP_TXD+11
N20 HT_CPU_RXD+14 HT_CPU_TXD+14 L20 Y10 HT_MCP_RXD+12 HT_MCP_TXD+12 W15
HTCPU_DWN15 M17 L18 HTCPU_UP15 AA11 AA15
HTCPU_DWN-[15..0] HT_CPU_RXD+15 HT_CPU_TXD+15 HTCPU_UP-[15..0] HT_MCP_RXD+13 HT_MCP_TXD+13
5 HTCPU_DWN-[15..0] HTCPU_UP-[15..0] 5 V11 HT_MCP_RXD+14 HT_MCP_TXD+14 Y14
HTCPU_DWN-0 Y22 C24 HTCPU_UP-0 W12 W13
HTCPU_DWN-1 HT_CPU_RXD-0 HT_CPU_TXD-0 HTCPU_UP-1 HTMCP_UP-[7..0] HT_MCP_RXD+15 HT_MCP_TXD+15 HTMCP_DWN-[7..0]
W23 HT_CPU_RXD-1 HT_CPU_TXD-1 D24 16 HTMCP_UP-[7..0] HTMCP_DWN-[7..0] 16
HTCPU_DWN-2 V23 E23 HTCPU_UP-2 HTMCP_UP-0 AC6 AC23 HTMCP_DWN-0
HTCPU_DWN-3 HT_CPU_RXD-2 HT_CPU_TXD-2 HTCPU_UP-3 HTMCP_UP-1 HT_MCP_RXD-0 HT_MCP_TXD-0 HTMCP_DWN-1
U21 HT_CPU_RXD-3 HT_CPU_TXD-3 F24 AB7 HT_MCP_RXD-1 HT_MCP_TXD-1 AD22
HTCPU_DWN-4 R23 H23 HTCPU_UP-4 HTMCP_UP-2 AB8 AC21 HTMCP_DWN-2
HTCPU_DWN-5 HT_CPU_RXD-4 HT_CPU_TXD-4 HTCPU_UP-5 HTMCP_UP-3 HT_MCP_RXD-2 HT_MCP_TXD-2 HTMCP_DWN-3
P23 HT_CPU_RXD-5 HT_CPU_TXD-5 J22 AB9 HT_MCP_RXD-3 HT_MCP_TXD-3 AD20
C
HTCPU_DWN-6 P21 K22 HTCPU_UP-6 HTMCP_UP-4 AC10 AC18 HTMCP_DWN-4 C
HTCPU_DWN-7 HT_CPU_RXD-6 HT_CPU_TXD-6 HTCPU_UP-7 HTMCP_UP-5 HT_MCP_RXD-4 HT_MCP_TXD-4 HTMCP_DWN-5
N21 HT_CPU_RXD-7 HT_CPU_TXD-7 K24 AC11 HT_MCP_RXD-5 HT_MCP_TXD-5 AB17
HTCPU_DWN-8 Y20 D22 HTCPU_UP-8 HTMCP_UP-6 AB12 AB15 HTMCP_DWN-6
HTCPU_DWN-9 HT_CPU_RXD-8 HT_CPU_TXD-8 HTCPU_UP-9 HTMCP_UP-7 HT_MCP_RXD-6 HT_MCP_TXD-6 HTMCP_DWN-7
W20 HT_CPU_RXD-9 HT_CPU_TXD-9 E20 AB13 HT_MCP_RXD-7 HT_MCP_TXD-7 AD16
HTCPU_DWN-10 W22 E21 HTCPU_UP-10 Y6 AB22
HTCPU_DWN-11 HT_CPU_RXD-10 HT_CPU_TXD-10 HTCPU_UP-11 HT_MCP_RXD-8 HT_MCP_TXD-8
U20 HT_CPU_RXD-11 HT_CPU_TXD-11 G19 Y7 HT_MCP_RXD-9 HT_MCP_TXD-9 AA20
HTCPU_DWN-12 R19 J18 HTCPU_UP-12 AA7 AA19
HTCPU_DWN-13 HT_CPU_RXD-12 HT_CPU_TXD-12 HTCPU_UP-13 HT_MCP_RXD-10 HT_MCP_TXD-10
P17 HT_CPU_RXD-13 HT_CPU_TXD-13 K17 W9 HT_MCP_RXD-11 HT_MCP_TXD-11 V17
HTCPU_DWN-14 N19 K19 HTCPU_UP-14 W10 V15
HTCPU_DWN-15 HT_CPU_RXD-14 HT_CPU_TXD-14 HTCPU_UP-15 HT_MCP_RXD-12 HT_MCP_TXD-12
N18 HT_CPU_RXD-15 HT_CPU_TXD-15 L19 Y12 HT_MCP_RXD-13 HT_MCP_TXD-13 Y15
W11 HT_MCP_RXD-14 HT_MCP_TXD-14 W14
HTCPU_DWNCLK0 T23 G23 HTCPU_UPCLK0 V13 Y13
5 HTCPU_DWNCLK0 HT_CPU_RX_CLK+0 HT_CPU_TX_CLK+0 HTCPU_UPCLK0 5 HT_MCP_RXD-15 HT_MCP_TXD-15
HTCPU_DWNCLK-0 T22 G24 HTCPU_UPCLK-0
5 HTCPU_DWNCLK-0 HT_CPU_RX_CLK-0 HT_CPU_TX_CLK-0 HTCPU_UPCLK-0 5
HTCPU_DWNCLK1 R21 G22 HTCPU_UPCLK1 HTMCP_UPCLK0 AD9 AC19 HTMCP_DWNCLK0
5 HTCPU_DWNCLK1 HT_CPU_RX_CLK+1 HT_CPU_TX_CLK+1 HTCPU_UPCLK1 5 16 HTMCP_UPCLK0 HT_MCP_RX_CLK+0 HT_MCP_TX_CLK+0 HTMCP_DWNCLK0 16
HTCPU_DWNCLK-1 R20 G21 HTCPU_UPCLK-1 HTMCP_UPCLK-0 AC9 AD19 HTMCP_DWNCLK-0
5 HTCPU_DWNCLK-1 HT_CPU_RX_CLK-1 HT_CPU_TX_CLK-1 HTCPU_UPCLK-1 5 16 HTMCP_UPCLK-0 HT_MCP_RX_CLK-0 HT_MCP_TX_CLK-0 HTMCP_DWNCLK-0 16
U10 HT_MCP_RX_CLK+1 HT_MCP_TX_CLK+1 Y17
HTCPU_DWNCNTL M23 L23 HTCPU_UPCNTL T10 W17
5 HTCPU_DWNCNTL HT_CPU_RXCTL+ HT_CPU_TXCTL+ HTCPU_UPCNTL 5 HT_MCP_RX_CLK-1 HT_MCP_TX_CLK-1
HTCPU_DWNCNTL- M22 L24 HTCPU_UPCNTL-
5 HTCPU_DWNCNTL- HT_CPU_RXCTL- HT_CPU_TXCTL- HTCPU_UPCNTL- 5
HTMCP_UPCNTL AD14 AC15 HTMCP_DWNCNTL
16 HTMCP_UPCNTL HT_MCP_RXCTL+ HT_MCP_TXCTL+ HTMCP_DWNCNTL 16
BR1 150 1%HTCPUCAL_1P2V W19 B24 CPU_CLK HTMCP_UPCNTL- AC14 AD15 HTMCP_DWNCNTL-
+1.2V_HT HT_CPU_CAL_1P2V CLKOUT0_200MHZ+ CPU_CLK 7 16 HTMCP_UPCNTL- HT_MCP_RXCTL- HT_MCP_TXCTL- HTMCP_DWNCNTL- 16
R112 150 1%HTCPUCAL_GND Y19 B23 CPU_CLK-
HT_CPU_CAL_GND CLKOUT0_200MHZ- CPU_CLK- 7
A22 HTMCP_REQ- AB5 B22 CLKOUTCTERM R123 2.37K 1% FOR VER 1.0
BFB4 1P2VPLL_FILT CLKOUT1_200MHZ+ 16 HTMCP_REQ- HTMCP_STOP- HT_MCP_REQ* CLKOUT_CTERM
14,15 1P2VPLL_PWR N16 +1.2V_PLLHTCPU CLKOUT1_200MHZ- B21 16 HTMCP_STOP- AA5 HT_MCP_STOP* SCLKIN_MCLKOUT_200MHZ+ A20
BEAD 60 0805 1A T13 HTMCP_RST- AC5 B20
+1.2V_PLLHTMCP HTCPU_REQ- R133 10K 1% /NI 16 HTMCP_RST- HTMCP_PWRGD HT_MCP_RESET*SCLKIN_MCLKOUT_200MHZ-
HT_CPU_REQ* F18 +3.3V 16 HTMCP_PWRGD AD5 HT_MCP_PWRGD
PLACE ON BC18 BC17 G18 HTCPU_STOP- AB23 HTMCPCAL_1P2V R113 150 1%
HT_CPU_STOP* HTCPU_STOP- 7 HT_MCP_CAL_1P2V +1.2V
10UF 10V 0805 Y5V D20 HTCPU_RST- MCPOUT_25MHZ AC4 AB24 HTMCPCAL_GND R114 150 1%
CHIP HT_CPU_RESET* HTCPU_RST- 7 16 MCPOUT_25MHZ CLKIN_25MHZ HT_MCP_CAL_GND
1UF 10V Y5V E19 HTCPU_PWRGD MCPOUT_200MHZ Y5
HT_CPU_PWRGD HTCPU_PWRGD 7 16 MCPOUT_200MHZ CLKIN_200MHZ+
MCPOUT_200MHZ- W5
BACK 2P5V_PLLHTCPU BFB1 16 MCPOUT_200MHZ- CLKIN_200MHZ-
B +2.5V_PLLHTCPU L16 2P5V_PWR 14,15 B
SIDE BEAD 60 0805 1A
C51G_PBGA_468
C51G_PBGA_468 BC10 BC11
1UF 16V 0805 Y5V /NI
1UF 10V Y5V

A A

Title
C51 (1&2) OF 6
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 13 of 39
5 4 3 2 1
 5 4 3 2 1

PLACE ON CLOSE CHIP < 600 mil

U8C RN72 150 8P4R DACRSET
PE0_OUT[15..0] 8 7
PE0_OUT[15..0] 22
PE0_IN0 J8 C51 L1 PE0_OUT0 6 5
22 PE0_IN0 PE0_IN1 PE0_RX+0 PE0_TX+0 PE0_OUT1
22 PE0_IN1 J6 PE0_RX+1 PE0_TX+1 L3 4 3
PE0_IN2 K9 3 OF 6 L4 PE0_OUT2 2 1 U8D R149
22 PE0_IN2 PE0_IN3 PE0_RX+2 PE0_TX+2 PE0_OUT3 301 1% /NI
22 PE0_IN3 L6 PE0_RX+3 PE0_TX+3 M4
PE0_IN4 L7 PE P1 PE0_OUT4 A5 C14
22 PE0_IN4 PE0_IN5 PE0_RX+4 PE0_TX+4 PE0_OUT5 26 DAC_RED DAC_RED IFPA_TXC+
22 PE0_IN5 M9 PE0_RX+5 PE0_TX+5 R1 26 DAC_GREEN B6 DAC_GREEN C51 IFPA_TXC- B13
PE0_IN6 N8 R3 PE0_OUT6 A6 A15
22 PE0_IN6 PE0_IN7 PE0_RX+6 PE0_TX+6 PE0_OUT7 26 DAC_BLUE DAC_BLUE IFPA_TXD+0
D N6 R4 4 OF 6 D15 D

D
22 PE0_IN7 PE0_IN8 PE0_RX+7 PE0_TX+7 PE0_OUT8 DAC_HSYNC IFPA_TXD+1 Q21
22 PE0_IN8 R6 PE0_RX+8 PE0_TX+8 U4 26 DAC_HSYNC B7 DAC_HSYNC IFPA_TXD+2 A14
PE0_IN9 P3 V1 PE0_OUT9 DAC_VSYNC C7 VGA F14 2N7002 SOT23 /NI
22 PE0_IN9 PE0_IN10 PE0_RX+9 PE0_TX+9 PE0_OUT10 26 DAC_VSYNC DAC_VSYNC IFPA_TXD+3
22 PE0_IN10 R8 PE0_RX+10 PE0_TX+10 W1 IFPA_TXD-0 B15 G RGB/TV 16,20
PE0_IN11 U6 W3 PE0_OUT11 R151 124 1%DACRSET D8 C15
22 PE0_IN11 PE0_RX+11 PE0_TX+11 DAC_RSET IFPA_TXD-1

S
PE0_IN12 T8 AA1 PE0_OUT12 C276 DACVREF D9 B14
22 PE0_IN12 PE0_IN13 PE0_RX+12 PE0_TX+12 PE0_OUT13 0.01UF 50V X7R DAC_VREF IFPA_TXD-2
22 PE0_IN13 U7 PE0_RX+13 PE0_TX+13 AB1 C8 DAC_IDUMP IFPA_TXD-3 E14
PE0_IN14 V4 AC1 PE0_OUT14 A10
22 PE0_IN14 PE0_IN15 PE0_RX+14 PE0_TX+14 PE0_OUT15 +3.3V FB15 3P3V_DAC IFPB_TXC+
22 PE0_IN15 Y3 PE0_RX+15 PE0_TX+15 AD2 A9 +3.3V_DAC IFPB_TXC- B10
PE0_OUT-[15..0] BEAD 60 0805 1A B11
PE0_OUT-0 PE0_OUT-[15..0] 22 IFPB_TXD+4
J7 L2 C274 1UF 16V 0805 Y5V /NI E13
22 PE0_IN-0 PE0_RX-0 PE0_TX-0 PE0_OUT-1 C275 1UF 10V Y5V IFPB_TXD+5
22 PE0_IN-1 J5 PE0_RX-1 PE0_TX-1 M2 IFPB_TXD+6 D13
J9 M3 PE0_OUT-2 B12
22 PE0_IN-2 PE0_RX-2 PE0_TX-2 PE0_OUT-3 IFPB_TXD+7
22 PE0_IN-3 L5 PE0_RX-3 PE0_TX-3 N3 IFPB_TXD-4 A11
L8 P2 PE0_OUT-4 F13
22 PE0_IN-4 PE0_RX-4 PE0_TX-4 PE0_OUT-5 IFPB_TXD-5
22 PE0_IN-5 M8 PE0_RX-5 PE0_TX-5 R2 IFPB_TXD-6 C13
N7 T2 PE0_OUT-6 BFB2 2P5V_PLLGPU H13 C12
22 PE0_IN-6 PE0_RX-6 PE0_TX-6 PE0_OUT-7 13,15 2P5V_PWR BEAD 60 0805 1A +2.5V_PLLGPU IFPB_TXD-7 IFPAB_PROBE C267 0.1UF 25V Y5V /NI
22 PE0_IN-7 N5 PE0_RX-7 PE0_TX-7 T3 IFPAB_PROBE A16
R5 U3 PE0_OUT-8 BC14 1UF 16V 0805 Y5V /NI F15
22 PE0_IN-8 PE0_RX-8 PE0_TX-8 PE0_OUT-9 BC15 1UF 10V Y5V IFPAB_RSET
22 PE0_IN-9 P4 PE0_RX-9 PE0_TX-9 V2
R7 W2 PE0_OUT-10 E16
22 PE0_IN-10 PE0_RX-10 PE0_TX-10 PE0_OUT-11 +2.5V_PLLIFP 2P5V_PLLCORE BFB3
22 PE0_IN-11 U5 PE0_RX-11 PE0_TX-11 Y2 C9 XTAL_IN +2.5V_PLLCORE H12 2P5V_PWR 13,15
T9 AA2 PE0_OUT-12 B9 BC23 BEAD 60 0805 1A
22 PE0_IN-12 PE0_RX-12 PE0_TX-12 PE0_OUT-13 XTAL_OUT BC24 1UF 16V 0805 Y5V /NI
22 PE0_IN-13 U8 PE0_RX-13 PE0_TX-13 AB2
V3 AC2 PE0_OUT-14 F12 D17 1UF 10V Y5V
22 PE0_IN-14 PE0_RX-14 PE0_TX-14 PE0_OUT-15 NC1-DDC_CLK PKG_TEST TEST_MODE_EN R136 1K 1%
22 PE0_IN-15 AA3 PE0_RX-15 PE0_TX-15 AD3 E11 NC2-DDC_DATA TEST_MODE_EN C17
E17 NC3-HPDET
PE0_PRSNT- D1 K1 PE0_REFCLK F17 C18 JTAG_TCK
22 PE0_PRSNT- PE0_PRSNT* PE0_REFCLK+ PE0_REFCLK 22 NC4-EE_CLK JTAG_TCK
K2 PE0_REFCLK- G17 B19 JTAG_TDI
PE0_REFCLK- PE0_REFCLK- 22 NC5-EE_DATA JTAG_TDI
C JTAG_TDO C19 C
PE1_IN G6 G4 PE1_OUT 1P2VPLL_PWR R9 B18 JTAG_TMS
22 PE1_IN PE1_RX+ PE1_TX+ PE1_OUT 22 13,15 1P2VPLL_PWR +1.2V_PLLGPU JTAG_TMS
PE1_IN- H6 G5 PE1_OUT- P9 A19 JTAG_TRST-
22 PE1_IN- PE1_PRSNT- PE1_RX- PE1_TX- PE1_OUT- 22 +1.2V_PLLCORE JTAG_TRST*
E2 G2 PE1_REFCLK H16
22 PE1_PRSNT- PE1_PRSNT* PE1_REFCLK+ PE1_REFCLK 22 +1.2V_PLLIFP
J4 G3 PE1_REFCLK- BC30 BC28 RN61
PE2_RX+ PE1_REFCLK- PE1_REFCLK- 22
K3 H4 1UF 10V Y5V C51G_PBGA_468 JTAG_TCK 1 2
PE2_PRSNT- PE2_RX- PE2_TX+ 1UF 10V Y5V /NI JTAG_TMS
22 PE2_PRSNT- E3 PE2_PRSNT* PE2_TX- J3 3 4
D3 H2 JTAG_TRST- 5 6
PE1_CLKREQ* PE2_REFCLK+ JTAG_TDI
E4 PE2_CLKREQ* PE2_REFCLK- H3 7 8 2P5V_PWR 13,15
F1 TP_PECLK_TEST1
PE_TSTCLK+ TP_PECLK_TEST-1 R179 100 /NI 10K 8P4R /NI
AC3 PE_REFCLK+ PE_TSTCLK- F2
AB3 PE_REFCLK- 26 DAC_RED
G1 PE_RESET-
PE_RST* PE_RESET- 22 26 DAC_GREEN
BFB5 1P2V_PLLPE T11 D2 PE_COMP R161 2.37K 1%
13,15 1P2VPLL_PWR 0 0805 +12V_PLLPE PE_CTERM_GND 26 DAC_BLUE
DAC_VSYNC
BC27 C51G_PBGA_468 BC78 C495 C496
500mils close to c51 10P 50V NPO /NI
1UF 10V Y5V 5:5 10P 50V NPO /NI R315
10P 50V NPO /NI 1K 1%

PLACE ON BACK SIDE

B B

A A

Title
C51 (3&4) OF 6
Size Document Number Rev
Custom
CRU51-M7 1.3

Date: Wednesday, April 12, 2006 Sheet 14 of 39

5 4 3 2 1
 5 4 3 2 1

U8F
C51 DECOUPLING
U8E BFB7 0 0805 C1 V19
+1.2V GND GND
D BFB8 0 0805 AA21 C51 T14 D
GND GND
+1.2V B5 +1.2V_CORE C51 +1.2V_PEA A3 1P2VPEA_PWR AA13 GND GND C20
C6 B3 U14 6 OF 6 R17 C262 1UF 10V Y5V /NI PLACE ON BACK SIDE
+1.2V_CORE +1.2V_PEA GND GND 13,14 2P5V_PWR
D7 C4 H14 AB14 C266 1UF 10V Y5V
+1.2V_CORE +1.2V_PEA GND GND
E8 +1.2V_CORE 5 OF 6 +1.2V_PEA D5 C11 GND GND GND U12 CENTER OF CHIPSET
E9 +1.2V_CORE +1.2V_PEA E6 AB4 GND GND G13
E10 PWR F7 AA4 Y16 BC21 10UF 10V 0805 Y5V
+1.2V_CORE +1.2V_PEA GND GND +1.2V
F10 F8 J15 H21 BC35 1UF 16V 0805 Y5V /NI BC26 10UF 10V 0805 Y5V
+1.2V_CORE +1.2V_PEA GND GND 13,14 1P2VPLL_PWR
F11 F9 E12 C22 BC31 1UF 16V 0805 Y5V /NI
+1.2V_CORE +1.2V_PEA BFB6 BEAD 60 0805 1A GND GND BC20 1UF 10V Y5V BC25 0.1UF 25V Y5V
G11 +1.2V_CORE +1.2V AB10 GND GND AB6
H11 +1.2V_CORE +1.2V_PLL A2 1P2VPLL_PWR 13,14 Y18 GND GND F22
J11 +1.2V_CORE +1.2V_PLL B2 E18 GND GND L22
J12 C2 U18 R22 C314 1UF 10V Y5V
+1.2V_CORE +1.2V_PLL GND GND BC29 1UF 10V Y5V
J13 +1.2V_CORE +1.2V_PLL C3 E15 GND GND V22
J14 +1.2V_CORE +1.2V_PLL D4 Y11 GND GND AA22
+1.2V_PLL E5 U19 GND GND A23
T15 +1.2V_HTMCP +1.2V_PLL F6 N17 GND GND AA23
U13 +1.2V_HTMCP +1.2V_PLL G7 F16 GND GND AA24
U11 +1.2V_HTMCP +1.2V_PLL G8 J17 GND GND L11 1P2VPEA_PWR
Y9 G9 L13 M11 BC43 1UF 16V 0805 Y5V /NI
+1.2V_HTMCP +1.2V_PLL GND GND BC45 1UF 10V Y5V /NI
AB11 +1.2V_HTMCP +1.2V_PLL H10 B1 GND GND N11
AA18 J10 T17 P11 BC38 1UF 10V Y5V /NI
+1.2V_HTMCP +1.2V_PLL GND GND
W16 +1.2V_HTMCP D11 GND GND M12
U16 C16 2P5V_PWR T12 N12
+1.2V_HTMCP +2.5V_CORE 2P5V_PWR 13,14 GND GND
U15 B16 J16 P12 BC40 1UF 10V Y5V
+1.2V_HTMCP +2.5V_CORE GND GND
D19 GND GND M13
B4 +1.2V_PED +2.5V_IFPA G15 H19 GND GND N13
C5 +1.2V_PED +2.5V_IFPA H15 L21 GND GND P13
D6 +1.2V_PED M19 GND GND M14
C E7 +1.2V_PED P19 GND GND N14 C
T19 P14 BC19 1UF 10V Y5V
GND GND +1.2V_HT
K16 L14 L12 C245 0.1UF 25V Y5V
+1.2V_HT +1.2V_HT GND GND
M16 BC16 0.1UF 25V Y5V
+1.2V_HT
R16 +1.2V_HT
M21 +1.2V_HT
J20 +1.2V_HT
T16 +1.2V_HT
U17 +1.2V_HT F3 PE_GND PE_GND K6
C21 +1.2V_HT L9 PE_GND PE_GND M6
H17 +1.2V_HT P8 PE_GND PE_GND P6
N9 PE_GND PE_GND T6
+3.3V D18 +3.3V K4 PE_GND PE_GND W6
C10 +3.3V N4 PE_GND PE_GND W8
T4 H8 C244 0.1UF 25V Y5V /NI
PE_GND PE_GND +3.3V
C51G_PBGA_468 W4 K8
PE_GND PE_GND
Y4 PE_GND PE_GND V6
U9 PE_GND PE_GND F4
H9 PE_GND PE_GND V8
BC32 1UF 16V 0805 Y5V /NI
+1.2V
C51G_PBGA_468
BC34 0.1UF 25V Y5V
C305 1UF 10V Y5V

C304 0.1UF 25V Y5V /NI

+2.5VDDA BC12 0.1UF 25V Y5V
C51 2.5V
B
2.5V @ 500MA AMPS MAX B

R145
0 0805
+5V

2P5V_PWR 13,14
O
A
I

CT14 C374 R1 R122 CT18 C278

100UF 16V 5X11 2mm /NI 49.9 1% 100UF 16V 5X11 2mm
1UF 16V 0805 Y5V /NI 1UF 16V 0805 Y5V /NI

Q20
AZ1117H-ADJ SOT-223
R2 R116
54.9 1%

Vout=Vref (1.25V) X ( 1+R2/R1 )

=2.5V
A A

Title
C51 (5&6) OF 6
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 15 of 39
5 4 3 2 1
 5 4 3 2 1

D D

PCI_AD[31..0] U12B
20 PCI_AD[31..0] PCI_REQ-0
PCI_AD0 AF19 AA22
PCI_AD0 PCI_REQ*0 PCI_REQ-1 PCI_REQ-0 20
PCI_AD1 AB21 MCP51 AE22
PCI_AD1 PCI_REQ*1 PCI_REQ-2 PCI_REQ-1 20
HTMCP_DWN[7..0] U12A HTMCP_UP[7..0] PCI_AD2 AC19 AF21
13 HTMCP_DWN[7..0] HTMCP_UP[7..0] 13 PCI_AD2 PCI_REQ*2 PCI_REQ-3 PCI_REQ-2 20
HTMCP_DWN0 K1 AA1 HTMCP_UP0 PCI_AD3 AA20 2 OF 7 AF22
HT_MCP_RXD+0 HT_MCP_TXD+0 PCI_AD3 PCI_REQ*3/GPIO PCI_REQ-4 PCI_REQ-3 20
HTMCP_DWN1 L1 MCP51 Y1 HTMCP_UP1 PCI_AD4 AA19 AE23
HT_MCP_RXD+1 HT_MCP_TXD+1 PCI_AD4 PCI_REQ*4/GPIO PCI_REQ-4 20
HTMCP_DWN2 M1 AA3 HTMCP_UP2 PCI_AD5 AF20 PCI
HTMCP_DWN3 HT_MCP_RXD+2 HT_MCP_TXD+2 HTMCP_UP3 PCI_AD6 PCI_AD5 PCI_GNT-0
N1 HT_MCP_RXD+3 1 OF 7 HT_MCP_TXD+3 W5 AE19 PCI_AD6 PCI_GNT*0 AE21 PCI_GNT-0 20
HTMCP_DWN4 R1 U5 HTMCP_UP4 PCI_AD7 AE20 AC21 PCI_GNT-1
HT_MCP_RXD+4 HT_MCP_TXD+4 PCI_AD7 PCI_GNT*1 PCI_GNT-2 PCI_GNT-1 20
HTMCP_DWN5 T1 HT T5 HTMCP_UP5 PCI_AD8 AB20 AA21
HT_MCP_RXD+5 HT_MCP_TXD+5 PCI_AD8 PCI_GNT*2 PCI_GNT-3 PCI_GNT-2 20
HTMCP_DWN6 U1 R5 HTMCP_UP6 PCI_AD9 AB19 AB24
HT_MCP_RXD+6 HT_MCP_TXD+6 PCI_AD9 PCI_GNT*3/GPIO PCI_GNT-4 PCI_GNT-3 14,20
HTMCP_DWN7 V1 P5 HTMCP_UP7 PCI_AD10 AA18 AB22
HT_MCP_RXD+7 HT_MCP_TXD+7 PCI_AD10 PCI_GNT*4/GPIO PCI_GNT-4 20
HTMCP_DWN-[7..0] HTMCP_UP-[7..0] PCI_AD11 AB18
13 HTMCP_DWN-[7..0] HTMCP_DWN-0 HTMCP_UP-0 HTMCP_UP-[7..0] 13 PCI_AD11
K2 AA2 PCI_AD12 AE18 AE11 PCI_INTW-
HTMCP_DWN-1 HT_MCP_RXD-0 HT_MCP_TXD-0 HTMCP_UP-1 PCI_AD12 PCI_TNTW* PCI_INTW- 20
L2 Y2 PCI_AD13 AF18 AB11 PCI_INTX-
HTMCP_DWN-2 HT_MCP_RXD-1 HT_MCP_TXD-1 HTMCP_UP-2 PCI_AD13 PCI_TNTX* PCI_INTX- 20
M2 AA4 PCI_AD14 AC17 AC11 PCI_INTY-
HTMCP_DWN-3 HT_MCP_RXD-2 HT_MCP_TXD-2 HTMCP_UP-3 PCI_AD14 PCI_TNTY* PCI_INTY- 20
N2 W6 PCI_AD15 AA17 AA11 PCI_INTZ-
HTMCP_DWN-4 HT_MCP_RXD-3 HT_MCP_TXD-3 HTMCP_UP-4 PCI_AD15 PCI_TNTZ* PCI_INTZ- 20
R2 U6 PCI_AD16 AB15
HTMCP_DWN-5 HT_MCP_RXD-4 HT_MCP_TXD-4 HTMCP_UP-5 PCI_AD17 PCI_AD16 PCI_CLK0 R230 22
T2 HT_MCP_RXD-5 HT_MCP_TXD-5 T6 AF15 PCI_AD17 PCI_CLK0 AE24 PCI_CLKSLOT1 20
HTMCP_DWN-6 U2 R6 HTMCP_UP-6 PCI_AD18 AE15 AF24 PCI_CLK1 R229 22
HTMCP_DWN-7 HT_MCP_RXD-6 HT_MCP_TXD-6 HTMCP_UP-7 PCI_AD18 PCI_CLK1 PCI_CLKSLOT2 20
V2 P6 PCI_AD19 AF14 AD23
HT_MCP_RXD-7 HT_MCP_TXD-7 PCI_AD20 PCI_AD19 PCI_CLK2
AE14 PCI_AD20 PCI_CLK3 AF23
C HTMCP_DWNCLK0 P1 V5 HTMCP_UPCLK0 PCI_AD21 AA14 AB23 PCI_CLK4 R228 22 C
13 HTMCP_DWNCLK0 HT_MCP_RX_CLK+ HT_MCP_TX_CLK+ HTMCP_UPCLK0 13 PCI_AD21 PCI_CLK4
HTMCP_DWNCLK-0 P2 V6 HTMCP_UPCLK-0 PCI_AD22 AB14 AC23 PCI_CLKIN
13 HTMCP_DWNCLK-0 HT_MCP_RX_CLK- HT_MCP_TX_CLK- HTMCP_UPCLK-0 13 PCI_AD22 PCI_CLKIN
PCI_AD23 AC13 PCI_CLK0 C448 10P 50V NPO
HTMCP_DWNCNTL HTMCP_UPCNTL PCI_AD24 PCI_AD23 PCI_CLK1 C442 10P 50V NPO
13 HTMCP_DWNCNTL W1 HT_MCP_RXCTL+ HT_MCP_TXCTL+ N5 HTMCP_UPCNTL 13 AB13 PCI_AD24
HTMCP_DWNCNTL- W2 N6 HTMCP_UPCNTL- PCI_AD25 AE13 PCI_CLK4 C438 10P 50V NPO
13 HTMCP_DWNCNTL- HT_MCP_RXCTL- HT_MCP_TXCTL- HTMCP_UPCNTL- 13 PCI_AD25
PCI_AD26 AA12
HTMCP_REQ- MCPOUT_200MHZ PCI_AD27 PCI_AD26 PCI_GNT-3
13 HTMCP_REQ- AD1 HT_MCP_REQ* CLKOUT_200MHZ+ AC1 MCPOUT_200MHZ 13 AF13 PCI_AD27 RGB/TV 14,20
HTMCP_STOP- AA5 AC2 MCPOUT_200MHZ- PCI_AD28 AB12 PCI_GNT-4
13 HTMCP_STOP- HT_MCP_STOP* CLKOUT_200MHZ- MCPOUT_200MHZ- 13 PCI_AD28 GPIO_LOAD 20
PCI_AD29 AF12
R200 150 1% 25MHZ_R R201 22 PCI_AD30 PCI_AD29
AB1 HT_MCP_COMP_GND1 CLKOUT_25MHZ Y5 MCPOUT_25MHZ 13 AE12 PCI_AD30
R199 49.9 1% AB2 PCI_AD31 AF11
HT_MCP_COMP_GND2 HTMCP_PWRGD PCI_C/BE-[3..0] PCI_AD31
HT_MCP_PWRGD AD2 HTMCP_PWRGD 13 20 PCI_C/BE-[3..0]
HT_VLD F22 PCI_C/BE-0 AD19
35 HT_VLD HT_VLD PCI_CBE*0
CPU_VLD N26 AE1 HTMCP_RST- PCI_C/BE-1 AB17
31 CPU_VLD CPU_VLD HT_MCP_RST* HTMCP_RST- 13 PCI_CBE*1
M24 J6 PCI_C/BE-2 AA15
+2.5VDIMM MEM_VLD THERMTRIP*/GPIO CPU_THERMTRIP- 7 PCI_CBE*2
HTVDD_EN F23 K6 TERM_GNDR191 562 1% PCI_C/BE-3 AA13
38 HTVDD_EN HTVDD_EN CLK200MHZ_TERM_GND PCI_CBE*3
CPUVDD_EN N25
31 CPUVDD_EN CPUVDD_EN MCP51_TCK
H22 PCI_FRAME- AC15 LPC_AD[3..0]
JTAG_TCK 20 PCI_FRAME- PCI_FRAME* LPC_AD[3..0] 33,34
M6 H21 MCP51_TDI PCI_IRDY- AD15 K24 LPC_AD0
+1.5V +3.3V_PLL_CPU_HT +1.5V_PLL_CPU_HT JTAG_TDI 20 PCI_IRDY- PCI_IRDY* LPC_AD0
FB21 M5 H23 PCI_TRDY- AB16 H26 LPC_AD1
+3.3V +3.3V_PLL_CPU_HT JTAG_TDO 20 PCI_TRDY- PCI_TRDY* LPC_AD1
BEAD 60 0805 1A D26 MCP51_TMS PCI_STOP- AE16 H25 LPC_AD2
JTAG_TMS 20 PCI_STOP- PCI_STOP* LPC_AD2
F25 MCP51_TRST- RN98 PCI_DEVSEL- AA16 K22 LPC_AD3
JTAG_TRST* 20 PCI_DEVSEL- PCI_DEVSEL* LPC_AD3
C377 C384 C390 C395 10K 8P4R PCI_PAR AE17
20 PCI_PAR PCI_PAR
0.1UF 25V Y5V /NI MCP51G_PBGA_508 MCP51_TDI 1 2 PCI_PERR- AF16 G25 LPC_FRAME-
20 PCI_PERR- PCI_PERR*/GPIO LPC_FRAME* LPC_FRAME- 33,34
1UF 16V 0805 Y5V /NI MCP51_TMS 3 4 PCI_SERR- AF17 K21 LPC_DRQ0-
+3.3V 20 PCI_SERR- PCI_SERR* LPC_DRQ0* LPC_DRQ0- 33
0.1UF 25V Y5V MCP51_TCK 5 6 PCI_PME- AD11 K23 LPC_DRQ1-R245 8.2K
20 PCI_PME- PCI_PME*/GPIO LPC_DRQ1*/LPC_CS* +3.3V
0.01UF 50V X7R /NI MCP51_TRST- 7 8 PCI_CLKRUN- AF25 L22 LPC_SERIRQ
20 PCI_CLKRUN- PCI_CLKRUN*/GPIO LPC_SERIRQ LPC_SERIRQ 33
PCI_RESET0- AE25 PCI_RESET*0 H24
+1.2V_HT R154 0 /NI HTVDD_EN PCI_RESET1- LPC_PWRDWN*/GPIO
B AD24 PCI_RESET*1 B
VCORE R10 2K /NI CPUVDD_EN RN76 R238 33 1% PCI_RESET2 AE26 PCI_RESET*2 F26 LPC_CLK0 R257 22
PCI_RESET3- LPC_CLK0 LPCCLK_SIO 33
680 8P4R W22 PCI_RESET*3
HTMCP_RST- 1 2 LPC_RESET- L26 LPC_RESET*4 G26 LPC_CLK1 R256 22
LPC_CLK1 LPCCLK_FLASH 34
HTMCP_PWRGD 3 4 RN89 C473 10P 50V NPO
HTMCP_STOP- 5 6 1 2 PCI_RESET3- MCP51G_PBGA_508 C474 10P 50V NPO
23 PCIRST_IDE-
HTMCP_REQ- 7 8 3 4 PCI_RESET1-
+3.3V 20 PCIRST_SLOT2-
5 6 PCI_RESET0-
20 PCIRST_SLOT1-
7 8 LPC_RESET-
34 LPCRST_FLASH-
33 8P4R
R260 33 1% LPC_RESET-
33 LPCRST_SIO-

A A

Title
MCP51 (1&2) OF 7
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 16 of 39
5 4 3 2 1
 5 4 3 2 1

D D
H1 JSATA1
1 U12C IDE_PDD[15..0]
IDE_PDD[15..0] 23
2 SATA_A0_TX_P_C C441 0.01UF 50V X7R SATA_A0_TX_P B20 F8 IDE_PDD0
SATA_A0_TX_N_C C453 0.01UF 50V X7R SATA_A0_TX_N A20 SATA_A0_TX+ IDE_DATA_P0 IDE_PDD1
3 SATA_A0_TX- MCP51 IDE_DATA_P1 D8
4 A9 IDE_PDD2
5 SATA_A0_RX_N_C C437 0.01UF 50V X7R SATA_A0_RX_N A19
SATA_A0_RX- 3 OF 7 IDE_DATA_P2
IDE_DATA_P3 E9 IDE_PDD3
6 SATA_A0_RX_P_C C423 0.01UF 50V X7R SATA_A0_RX_P B19 A10 IDE_PDD4
SATA_A0_RX+ IDE_DATA_P4 IDE_PDD5
7 IDE IDE_DATA_P5 E10
H2 C10 IDE_PDD6
SATA CONNECTOR IDE_DATA_P6 IDE_PDD7
IDE_DATA_P7 E11
H1 JSATA2 SATA IDE_DATA_P8 F11 IDE_PDD8
1 D10 IDE_PDD9
SATA_A1_TX_P_C C411 0.01UF 50V X7R SATA_A1_TX_P B18 IDE_DATA_P9 IDE_PDD10
2 SATA_A1_TX+ IDE_DATA_P10 F10
3 SATA_A1_TX_N_C C421 0.01UF 50V X7R SATA_A1_TX_N A18 B10 IDE_PDD11
SATA_A1_TX- IDE_DATA_P11 IDE_PDD12
4 IDE_DATA_P12 F9
5 SATA_A1_RX_N_C C410 0.01UF 50V X7R SATA_A1_RX_N A17 B9 IDE_PDD13
SATA_A1_RX_P_C C408 0.01UF 50V X7R SATA_A1_RX_P B17 SATA_A1_RX- IDE_DATA_P13 IDE_PDD14
6 SATA_A1_RX+ IDE_DATA_P14 E8
7 A8 IDE_PDD15
IDE_DATA_P15
H2
SATA CONNECTOR A6 IDE_ADDR_P0
IDE_ADD_P0 IDE_ADDR_P0 23
D6 IDE_ADDR_P1
IDE_ADD_P1 IDE_ADDR_P1 23
B6 IDE_ADDR_P2
IDE_ADD_P2 IDE_ADDR_P2 23
B15 SATA_B0_TX+
A15 A5 IDE_CS1_P-
SATA_B0_TX- IDE_CS1_P* IDE_CS1_P- 23
B5 IDE_CS3_P-
IDE_CS3_P* IDE_CS3_P- 23
A16 B7 IDE_DACK_P-
SATA_B0_RX- IDE_DACK_P* IDE_DACK_P- 23
B16 F7 IDE_IOW_P-
SATA_B0_RX+ IDE_IOW_P* IDE_IOW_P- 23
E6 IDE_INTR_P
IDE_INTR_P IDE_INTR_P 23
C B8 IDE_DREQ_P C
IDE_DREQ_P IDE_DREQ_P 23
E7 IDE_IOR_P-
IDE_IOR_P* IDE_IOR_P- 23
A7 IDE_IORDY_P
IDE_IORDY_P IDE_IORDY_P 23
C6 CBLE_DET_P
CBLE_DET_P CBLE_DET_P 23
B13 IDE_SDD[15..0]
SATA_B1_TX+ IDE_SDD[15..0] 23
A13 E4 IDE_SDD0
SATA_B1_TX- IDE_DATA_S0 IDE_SDD1
IDE_DATA_S1 D1
A14 D4 IDE_SDD2
SATA_B1_RX- IDE_DATA_S2 IDE_SDD3
B14 SATA_B1_RX+ IDE_DATA_S3 C2
B2 IDE_SDD4
IDE_DATA_S4 IDE_SDD5
IDE_DATA_S5 C3
A3 IDE_SDD6
IDE_DATA_S6 IDE_SDD7
IDE_DATA_S7 A4
B4 IDE_SDD8
IDE_DATA_S8 IDE_SDD9
IDE_DATA_S9 B3
A2 IDE_SDD10
IDE_DATA_S10 IDE_SDD11
IDE_DATA_S11 B1
SATA_HDLED- C20 C1 IDE_SDD12
21 SATA_HDLED- SATA_LED*/GPIO IDE_DATA_S12
TP_SATA_TSTCLK_P D14 D2 IDE_SDD13
BR6 100 /NI TP_SATA_TSTCLK_N SATA_TSTCLK+ IDE_DATA_S13 IDE_SDD14
C14 SATA_TSTCLK- IDE_DATA_S14 E3
F13 E5 IDE_SDD15
SATA_TEST IDE_DATA_S15
SATA_TERMP F14 G4 IDE_ADDR_S0
SATA_TERM+ IDE_ADD_S0 IDE_ADDR_S0 23
G6 IDE_ADDR_S1
IDE_ADD_S1 IDE_ADDR_S1 23
BR5 2.49K 1% SATA_TERMN E14 G2 IDE_ADDR_S2
SATA_TERM- IDE_ADD_S2 IDE_ADDR_S2 23
FB24 +1.5V_PLL_SP_VDD F18 G1 IDE_CS1_S-
+1.5V +1.5V_PLL_SP_VDD IDE_CS1_S* IDE_CS1_S- 23
BEAD 60 0805 1A G3 IDE_CS3_S-
IDE_CS3_S* IDE_CS3_S- 23
F5 IDE_DACK_S-
IDE_DACK_S* IDE_DACK_S- 23
B C457 C456 C455 E1 IDE_IOW_S- B
IDE_IOW_S* IDE_IOW_S- 23
1UF 16V 0805 Y5V /NI F6 IDE_INTR_S
IDE_INTR_S IDE_INTR_S 23
0.1UF 25V Y5V E2 IDE_DREQ_S
IDE_DREQ_S IDE_DREQ_S 23
0.01UF 50V X7R /NI F2 IDE_IOR_S-
IDE_IOR_S* IDE_IOR_S- 23
F1 IDE_IORDY_S
IDE_RDY_S IDE_IORDY_S 23
G5 CBLE_DET_S
18 +3.3V_PLL_SP_SS CABLE_DET_S/GPIO CBLE_DET_S 23

+1.5V F19 +1.5V_PLL_SP_SS IDE_COMP_3P3 B11 IDE_COMP_3P3V R205 120

+3.3V
FB25 +3.3V_PLL_SP_SS D20 A11 IDE_COMP_GND R213 120
+3.3V +3.3V_PLL_SP_SS IDE_COMP_GND
0
MCP51G_PBGA_508
C375 C464 C463 C462
0.1UF 25V Y5V
10UF 10V 0805 Y5V
0.1UF 25V Y5V
0.01UF 50V X7R /NI

A A

Title
MCP51 (3) OF 7
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 17 of 39
5 4 3 2 1
 5 4 3 2 1

+3.3V_DUAL

R253
10K 1% /NI AC_RST*
1 = *RGMII
AC_RST- 0 = MII
SPDIF0
R254 (SIO CLK)
10K 1% 1 = 24MHZ
0 = *14.318MHZ
D * = DEFAULT D
U12D
AUD_14MHZ_IN R22 AC26 USB_0
29 AUD_14MHZ_IN AC97_CLK USB+0 USB_0 27
AC_BITCLK U26 MCP51 AC25 USB_0-
29 AC_BITCLK AC_BITCLK USB-0 USB_0- 27
AC_SDOUT T25 AB26 USB_1
29 AC_SDOUT AC_SDATA_OUT0/GPIO USB+1 USB_1 27
AC_SDIN_0 USB_1-
29 AC_SDIN_0
AC_SDATA_IN1
R26 AC_SDATA_IN0/GPIO 4 OF 7 USB-1 AB25
USB_2
USB_1- 27
T24 AC_SDATA_IN1/GPIO USB+2 AA26 USB_2 27
AC_SDATA_IN2 USB_2-
U21 AC_SDATA_IN2/GPIO USB USB-2 AA25
USB_3
USB_2- 27
USB+3 Y26 USB_3 27
AC_RST- U25 AC97 Y25 USB_3-
29 AC_RST- AC_RESET* USB-3 USB_3- 27
W26 USB_4
USB+4 USB_4 27
AC_SYNC R21 GPIO W25 USB_4-
29 AC_SYNC AC_SYNC/GPIO USB-4 USB_4- 27
R308 V24 USB_5
SPDIF USB+5 USB_5 27
T26 V23 USB_5-
29,30 SPDIFO SPDIF0/GPIO USB-5 USB_5- 27
DDC_CLK AE10 V26 USB_6
26 DDC_CLK DDC_CLK0/GPIO USB+6 USB_6 27
0 /NI DDC_DATA AF10 V25 USB_6-
26 DDC_DATA DDC_DATA0/GPIO USB-6 USB_6- 27
AA10 T22 USB_7
DDC_CLK1/GPIO USB+7 USB_7 27
AB10 T23 USB_7-
DDC_DATA1/GPIO USB-7 USB_7- 27
AF9 HPLUG_DET0/GPIO
RN102 C24 Y24 USB_BKPNL_3_2_OC-
SPDIF LCD_BKL_CTL/GPIO USB_OC0*/GPIO USB_BKPNL_3_2_OC- 27
+3.3V 1 2 D24 Y23 USB_BKPNL_5_4_OC-
LCD_BKL_PWR/GPIO USB_OC1*/GPIO USB_BKPNL_5_4_OC- 27
3 4 TP_CPUVID5 C25 U22 USB_FNTPNL_7_6_OC-
LCD_BKL_ON/GPIO USB_OC2*/GPIO USB_FNTPNL_7_6_OC- 27
5 6 AC_SDATA_IN2 J4 V22 USB_FNTPNL_1_0_OC-
GPIO_1/SLAVE_READY USB_OC3*/GPIO USB_FNTPNL_1_0_OC- 27
7 8 AC_SDATA_IN1 J3 AD25 USB_GND R242 732 1%
GPIO_2/CPU_SLP* USB_RBIAS_GND
J5 GPIO_3/CPU_CLKRUN*
10K 8P4R RGMII_RESET- AE2 J22 A20GATE +2.5VDIMM
36 RGMII_RESET- GPIO_4/AGPSTP*/SUS_STAT* A20GATE/GPIO A20GATE 33
RN103 K5 A24 INTRUDER- +3.3V_DUAL
GPIO_5/SYS_SHUTDOWN* INTRUDER*
+3.3V_DUAL 1 2 LLB- J2 GPIO_6/NFERR*/SYS_PERR* EXT_SMI*/GPIO M26 EXTSMI-
EXTSMI- 21,33
RN105
3 4 LID- 34 FLASH_RECOVERY-
FLASH_RECOVERY- J1
GPIO_7/FERR*/SYS_SERR* RI*/GPIO M25 SER_RI-
SER_RI- 28
2.7K 8P4R
C 5 6 AC9 E26 SPEAKER 1 2 C
GPIO_8/CR_VID0 SPKR SPEAKER 21 +3.3V_DUAL
7 8 AB9 D23 PWBTOUT- R193 R144 R194 3 4
GPIO_9/CR_VID1 PWRBTN* PWBTOUT- 33
AA9 M23 IO_PME- 10K 1% 2.7K 2.7K 5 6
GPIO_10/CR_VID2 SIO_PME*/GPIO IO_PME- 33
10K 8P4R J21 SIO_KBRST- 7 8
KBRDRSTIN*/GPIO SIO_KBRST- 33
P24 AC3 PE_WAKE-
GPIO_11/CPU_VID0 PE_WAKE* PE_WAKE- 22
P25 H1 SMB_MEM_SCL
GPIO_12/CPU_VID1 SMB_CLK0/GPIO SMB_MEM_SCL 10,11
P22 H2 SMB_MEM_SDA
GPIO_13/CPU_VID2 SMB_DATA0/GPIO SMB_MEM_SDA 10,11
P26 M21 SMB_SCL
GPIO_14/CPU_VID3 SMB_CLK1/GPIO SMB_SCL 7,20,22,37
R25 L25 SMB_SDA
GPIO_15/CPU_VID4 SMB_DATA1/GPIO SMB_SDA 7,20,22,37
M22 SMB_ALERT-
TP_CPUVID5 SMB_ALERT*/GPIO +3.3V_VBAT
P23 GPIO_16/CPU_VID5 +3.3V_VBAT A23 +3.3V_VBAT 25,33,37
J26 BUF_SIO_CLK_R R247 22
BUF_SIO_CLK BUF_SIO_CLK 33
LID- B25 N21 SUS_CLK_R R255 22
LID*/GPIO SUS_CLK/GPIO SUSCLK 33
C55 0.1UF 25V Y5V B24 K25 CHIP_THERM-
SLP_DEEP* THERM*/GPIO CHIP_THERM- 7,33
R246 51K E22 F21 FP_RESET- SUSCLK
25,33,37 +3.3V_VBAT +3.3V_DUAL V3P3_DEEP RSTBTN* FP_RESET- 21,37
1

LLB- G22 C469 C468 C467 1 = SLAVE

JCMOS1 C80 1UF 10V Y5V LLB* SLP_S5- 10P 50V NPO /NI 0.1UF 25V Y5V
SLP_S5* C26 SLP_S5- 21,32 0 = *NORMAL
2 RTC_RST- A25 F24 SLP_S3- 10P 50V NPO /NI
RTC_RST* SLP_S3* SLP_S3- 24,33
HEADER 1X3 B26 PWRGD_SB * = DEFAULT
PWRGD_SB PWRGD_SB 35
B22 N22 MCP51_PWRGD R249 10K 1% /NI
+1.5V +1.5V_PLL_LEG PWRGD MCP51_PWRGD 35 +3.3V_DUAL
17 +3.3V_PLL_SP_SS +3.3V_PLL_SP_SS A22 L21 CPUFAN_TACH
+3.3V_PLL_LEG FANRPM/GPIO CPUFAN_CNTL R244 10K 1%
3

FANCTL0/GPIO J25
Y21 K26 SYSFAN_CNTL
+1.5V +3.3V_PLL_USB_CORE +1.5V_PLL_USB FANCTL1/GPIO
FB26 AD26 D25 SB_TEST R248 1K 1%
+3.3V +3.3V_PLL_USB TEST_MODE_EN
BEAD 60 0805 1A RN92
MCP51G_PBGA_508 1 2
C376 C459 C460 C461 C380 BC70 3 4
0.1UF 25V Y5V /NI 0.01UF 50V X7R /NI +3.3V 5 6
CLEAR CMOS CONTROL 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 7 8
0.1UF 25V Y5V +3.3V
B B
1-2 NORMAL 0.01UF 50V X7R /NI 10K 8P4R /NI +3.3V

2-3 CLEAR CMOS

R6
USB_1- 1 2 R250 4.7K
CMOS CLEAR USB_1
USB_0-
3
5
4
6
RN94
15K 8P4R
10K 1% /NI

JUMPER USB_0
USB_3-
USB_3
7
1
8
2
RN96 R243 1M INTRUDER-
SPEAKER CHIP_THERM-

3 4 25,33,37 +3.3V_VBAT
USB_2- 5 6 15K 8P4R R261
1

USB_2 7 8 10K 1%
USB_5- 1 2 JCI1
USB_5 3 4 RN97 HEADER 1X2
USB_4- 5 6 15K 8P4R
USB_4 7 8
USB_6-
2

1 2
USB_6 3 4 RN95
USB_7- 5 6 15K 8P4R
USB_7 7 8

A A

Title
MCP51 (4) OF 7
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 18 of 39
5 4 3 2 1
 5 4 3 2 1

U12G
D RN77 0 8P4R U12E AF26 N16 D
GND GND
36 RGMII_TXD0 7 8 AE7 RGMII_TD0/MII_TD0 NC E19 AF1 GND MCP51 GND N15
36 RGMII_TXD1 5 6 AF6 RGMII_TD1/MII_TD1 MCP51 NC D12 AD22 GND GND N14 TOP SIDE CAP BACK SIDE CAP
3 4 AB6 E12 AD20 7 OF 7 N13 C454 0.1UF 25V Y5V BC73 1UF 16V 0805 Y5V /NI
36 RGMII_TXD2 RGMII_TD2/MII_TD2 NC GND GND +3.3V +1.5V
1 2 AA6 5 OF 7 E25 AD18 N12 BC77 0.1UF 25V Y5V BC65 0.1UF 25V Y5V
36 RGMII_TXD3 RGMII_TD3/MII_TD3 NC GND GND
BR3 0 AA7 AE9 AD16 GND N11 BC62 0.1UF 25V Y5V
36 RGMII_TXCLK RGMII_TXC/MII_TXCLK NC GND GND
BR4 0 AB7 LAN AD14 N10 BC52 0.1UF 25V Y5V BACK SIDE CAP
36 RGMII_TXCTL RGMII_TX_CTL/MII_TXEN GND GND
AD12 M16 BC51 0.1UF 25V Y5V /NI +1.2V BC49 0.1UF 25V Y5V /NI
RGMII_RXD0 X2 GND GND BC53 0.1UF 25V Y5V /NI
36 RGMII_RXD0 AF7 RGMII_RD0/MII_RXD0 AD10 GND GND M15
RGMII_RXD1 AF8 CLOCK E21 XTALIN AD8 M14 TOP SIDE CAP BC72 0.1UF 25V Y5V
36 RGMII_RXD1 RGMII_RD0/MII_RXD1 XTALIN GND GND
RGMII_RXD2 AD7 AD6 M13 +1.5V_DUAL C392 0.1UF 25V Y5V /NI BC57 0.1UF 25V Y5V /NI
36 RGMII_RXD2 RGMII_RD0/MII_RXD2 GND GND
RGMII_RXD3 AB8 D22 XTALOUT 25MHZ 20PF 30PPM AD4 M12 C391 0.1UF 25V Y5V /NI BC55 0.1UF 25V Y5V
36 RGMII_RXD3 RGMII_RD0/MII_RXD3 XTALOUT GND GND
RGMII_RXCLK AC7 AC24 M11 BC50 0.1UF 25V Y5V
36 RGMII_RXCLK RGMII_RXC/MII_RXCLK GND GND
+3.3V_DUAL RGMII_RXCTL AE8 AB3 M3 TOP SIDE CAP BC63 0.1UF 25V Y5V /NI
36 RGMII_RXCTL RGMII_RX_CTL/MII_RXDV GND GND
R203 1K 1% C465 C466 AA24 L24 +5V BC59 0.1UF 25V Y5V BC74 0.1UF 25V Y5V
RGMII_VREF 15P 50V NPO GND GND BC58 0.1UF 25V Y5V /NI BC54 0.1UF 25V Y5V /NI
AF4 MII_VREF Y3 GND GND L16
R204 1K 1% 15P 50V NPO W24 L15 BC64 0.1UF 25V Y5V
C400 0.1UF 25V Y5V RGMII_MDC GND GND BC61 0.1UF 25V Y5V
36 RGMII_MDC AF5 MII_MDC V3 GND GND L14
36 RGMII_MDIO RGMII_MDIO AE6 U24 L13 BC75 0.1UF 25V Y5V /NI
MII_MDIO GND GND BC60 0.1UF 25V Y5V /NI
36 MII_RXER AD3 MII_RXER/GPIO U14 GND GND L12
36 MII_COL AC4 U13 L11 BC56 0.1UF 25V Y5V /NI
MII_COL GND GND
36 MII_CRS AF2 MII_CRS T16 GND GND K14
AE5 MII_PWRDWN/GPIO T15 GND GND K13
+3.3V_DUAL R202 10K 1% AA8 T14 K3
MII_INTR/GPIO GND GND
T13 GND GND J24
R192 22 BUF_25MHZ_R AC5 X3 T12 H3
36 BUF_25M BUF_25MHZ GND GND
+3.3V_DUAL C22 XTALIN_RTC T11 G24
XTALIN_RTC GND GND
+1.5V_DUAL AE4 +1.2V_PLL_MAC_DUAL T3 GND GND F3
FB22 +3.3V_PLL_MAC_DUAL AB5 B23 XTALOUT_RTC 32.768KHZ 12.5PF 20PPM R24 E24
BEAD 60 0805 1A +3.3V_PLL_MAC_DUAL XTALOUT_RTC GND GND
C R16 GND GND D3 C
MCP51G_PBGA_508 R15 C23
C335 C381 C382 C383 C394 C393 C470 C472 GND GND
R14 GND GND C11
0.1UF 25V Y5V /NI 15P 50V NPO R13 C9
1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V 15P 50V NPO GND GND
R12 GND GND C7
0.1UF 25V Y5V 0.01UF 50V X7R /NI R11 C5
0.01UF 50V X7R /NI GND GND
P17 GND GND A26
P16 GND GND A1
P15 GND GND H5
P14 GND GND H6
P13 GND GND U4
P12 GND GND R4
P11 GND GND N4
P10 GND GND L4
P3 GND GND W4
N24 GND GND L5
N17 GND GND L6

F20 SATA_GND SATA_GND C21

E18 SATA_GND SATA_GND C19
D18 SATA_GND SATA_GND C17
D16 SATA_GND SATA_GND C15
E20 C13 +3.3V
SATA_GND SATA_GND
C18 SATA_GND SATA_GND E13
C16 SATA_GND SATA_GND B12
B21 SATA_GND SATA_GND A12 1.5V_SP_A 440mA
A21 +1.5V 1.5V_SP_D 164mA
SATA_GND
+ 1A 1.5V_PLL_SP_DVDD 20mA
MCP51G_PBGA_508 CT37 1.5V_PLL_SP_AVDD 160mA
B 100UF 16V 5X11 2mm 1.5V_PLL_CPU_HT 71mA B
1.5V_PLL_SP_SS 10mA
1.5V_PLL_LEG 4mA
Q35
1.5V_PLL_USB_CORE 16mA
R1 R195
U12F I 1K 1%
+1.2V U17 +1.2V +5V Y22 +5V O
U16 +1.2V +5V F12 A +
U15 MCP51 CT41
+3.3V_DUAL +1.2V 100UF 16V 5X11 2mm
U12 +1.2V +3.3V AD21 +3.3V
U11 6 OF 7 AD17 AZ1117H-ADJ SOT-223 R197
+1.5V_DUAL +1.2V +3.3V 200 1%
U10 +1.2V +3.3V AD13 R2
T17 +1.2V PWR +3.3V AD9
+
CT35 +1.2V_DUAL @ 145MA AMPS MAX T10
R17
+1.2V +3.3V AD5
C12
100UF 16V 5X11 2mm +1.2V +3.3V
R10 +1.2V +3.3V C8
M17 +1.2V +3.3V C4
M10 +1.2V
Q34 R189
R1
100 1%
L17 +1.2V +3.3V_DUAL Y6 +3.3V_DUAL Vout=Vref (1.25V) X ( 1+R2/R1 )
I L10 +1.2V +3.3V_DUAL T21
O K17 P21 =1.5V
+1.2V +3.3V_DUAL
A + K16 +1.2V +3.3V_DUAL G21
CT38
100UF 16V 5X11 2mm R1 R2 +1.2V K15
K12
+1.2V
W21
AZ1117H-ADJ SOT-223 R190 +1.2V +3.3V_USB_DUAL
20 1% NI 0 +1.25V K11
K10
+1.2V +3.3V_USB_DUAL V21
+1.2V
R2 1K 1% 40.2 1% +1.3V +1.5V_SP_A F17
U3 +1.2V_HT +1.5V_SP_A E17

A
1K 1% 82 1% +1.35V R3
N3
+1.2V_HT +1.5V_SP_A F16
E16 +1.5V_SP_A BFB9 A
+1.2V_HT +1.5V_SP_A +1.5V
L3 BEAD 60 0805 1A
+1.2V_HT
W3 +1.2V_HT +1.5V_SP_D E15
+1.5V_SP_D F15
Vout=Vref (1.25V) X ( 1+R2/R1 ) +1.5V_DUAL AE3 +1.5V
+1.2_DUAL
AF3 +1.2_DUAL
=1.25V C389 BC71 BC67 BC66 BC76
MCP51G_PBGA_508 1UF 16V 0805 Y5V /NI 0.1UF 25V Y5V /NI 0.1UF 25V Y5V
C332 0.1UF 25V Y5V 1UF 16V 0805 Y5V /NI Title
0.1UF 25V Y5V MCP51 (5&6&7) OF 7
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 19 of 39
5 4 3 2 1
 5 4 3 2 1

+3.3V +5V -12V PCI1 +12V +5V +3.3V +3.3V_DUAL +3.3V +5V -12V PCI2 +12V +5V +3.3V +3.3V_DUAL
PCI SLOT 120PIN U PCI SLOT 120PIN U
B1 -12V TRST_L A1 B1 -12V TRST_L A1
B2 TCK +12V A2 B2 TCK +12V A2
B3 GND TMS A3 B3 GND TMS A3
B4 TDO TDI A4 B4 TDO TDI A4
B5 5V 5V A5 B5 5V 5V A5
D B6 5V INTA_L A6 PCI_INTY- 16 B6 5V INTA_L A6 PCI_INTW- 16 D
16 PCI_INTZ- B7 INTB_L INTC_L A7 PCI_INTW- 16 16 PCI_INTX- B7 INTB_L INTC_L A7 PCI_INTY- 16
16 PCI_INTX- B8 INTD_L 5V A8 16 PCI_INTZ- B8 INTD_L 5V A8
B9 PRSNT1_L RSRVD A9 B9 PRSNT1_L RSRVD A9
B10 RSRVD +Vio A10 B10 RSRVD +Vio A10
B11 PRSNT2_L RSRVD A11 B11 PRSNT2_L RSRVD A11
B12 GND GND A12 B12 GND GND A12
B13 GND GND A13 B13 GND GND A13
B14 RSRVD RSRVD A14 B14 RSRVD RSRVD A14
B15 GND RST_L A15 PCIRST_SLOT1- 16 B15 GND RST_L A15 PCIRST_SLOT2- 16
16 PCI_CLKSLOT1 B16 CLK +Vio A16 16 PCI_CLKSLOT2 B16 CLK +Vio A16
B17 A17 PCI_GNT-1 B17 A17 PCI_GNT-2
PCI_REQ-1 GND GNT_L +3.3V PCI_REQ-2 GND GNT_L
B18 REQ_L GND A18 B18 REQ_L GND A18
B19 A19 PCI_PME- B19 A19 PCI_PME-
+Vio RSRVD PCI_PME- 16 +Vio RSRVD PCI_PME- 16
PCI_AD31 B20 A20 PCI_AD30 PCI_AD31 B20 A20 PCI_AD30
PCI_AD29 AD31 AD30 PCI_AD29 AD31 AD30
B21 AD29 3.3V A21 B21 AD29 3.3V A21
B22 A22 PCI_AD28 C429 C431 B22 A22 PCI_AD28
PCI_AD27 GND AD28 PCI_AD26 0.1UF 25V Y5V /NI 1000P 50V X7R PCI_AD27 GND AD28 PCI_AD26
B23 AD27 AD26 A23 B23 AD27 AD26 A23
PCI_AD25 B24 A24 PCI_AD25 B24 A24
AD25 GND PCI_AD24 AD25 GND PCI_AD24
B25 3.3V AD24 A25 B25 3.3V AD24 A25
PCI_C/BE-3 B26 A26 PCI_AD22 PCI_C/BE-3 B26 A26 PCI_AD24
PCI_AD23 C/BE3_L IDSEL PCI_AD23 C/BE3_L IDSEL
B27 AD23 3.3V A27 B27 AD23 3.3V A27
B28 A28 PCI_AD22 B28 A28 PCI_AD22
PCI_AD21 GND AD22 PCI_AD20 PCI_AD21 GND AD22 PCI_AD20
B29 AD21 AD20 A29 B29 AD21 AD20 A29
PCI_AD19 B30 A30 PCI_AD19 B30 A30
AD19 GND PCI_AD18 AD19 GND PCI_AD18
B31 3.3V AD18 A31 B31 3.3V AD18 A31
PCI_AD17 B32 A32 PCI_AD16 PCI_AD17 B32 A32 PCI_AD16
PCI_C/BE-2 AD17 AD16 PCI_C/BE-2 AD17 AD16
B33 C/BE2_L 3.3V A33 B33 C/BE2_L 3.3V A33
B34 GND FRAME_L A34 PCI_FRAME- 16 B34 GND FRAME_L A34 PCI_FRAME- 16
C 16 PCI_IRDY- B35 IRDY_L GND A35 16 PCI_IRDY- B35 IRDY_L GND A35 C
B36 3.3V TRDY_L A36 PCI_TRDY- 16 B36 3.3V TRDY_L A36 PCI_TRDY- 16
16 PCI_DEVSEL- B37 DEVSEL_L GND A37 16 PCI_DEVSEL- B37 DEVSEL_L GND A37
B38 GND STOP_L A38 PCI_STOP- 16 B38 GND STOP_L A38 PCI_STOP- 16
PCI_LOCK- B39 A39 PCI_LOCK- B39 A39
LOCK_L 3.3V LOCK_L 3.3V
16 PCI_PERR- B40 PERR_L SDONE A40 SMB_SCL 7,18,22,37 16 PCI_PERR- B40 PERR_L SDONE A40 SMB_SCL 7,18,22,37
B41 3.3V SBO_L A41 SMB_SDA 7,18,22,37 B41 3.3V SBO_L A41 SMB_SDA 7,18,22,37
16 PCI_SERR- B42 SERR_L GND A42 16 PCI_SERR- B42 SERR_L GND A42
B43 3.3V PAR A43 PCI_PAR 16 B43 3.3V PAR A43 PCI_PAR 16
PCI_C/BE-1 B44 A44 PCI_AD15 PCI_C/BE-1 B44 A44 PCI_AD15
PCI_AD14 C/BE1_L AD15 PCI_AD14 C/BE1_L AD15
B45 AD14 3.3V A45 B45 AD14 3.3V A45
B46 A46 PCI_AD13 B46 A46 PCI_AD13
PCI_AD12 GND AD13 PCI_AD11 PCI_AD12 GND AD13 PCI_AD11
B47 AD12 AD11 A47 B47 AD12 AD11 A47
PCI_AD10 B48 A48 PCI_AD10 B48 A48
AD10 GND PCI_AD9 AD10 GND PCI_AD9
B49 M66EN AD9 A49 B49 M66EN AD9 A49 +3.3V
B50 5V KEY 5V KEY A50 B50 5V KEY 5V KEY A50
B51 A51 B51 A51 C403 1UF 16V 0805 Y5V /NI
PCI_AD8 5V KEY 5V KEY PCI_C/BE-0 PCI_AD8 5V KEY 5V KEY PCI_C/BE-0 C446 1UF 16V 0805 Y5V
B52 AD8 C/BE0_L A52 B52 AD8 C/BE0_L A52
PCI_AD7 B53 A53 PCI_AD7 B53 A53 C443 1UF 16V 0805 Y5V /NI
AD7 3.3V PCI_AD6 AD7 3.3V PCI_AD6 C445 0.1UF 25V Y5V /NI
B54 3.3V AD6 A54 B54 3.3V AD6 A54
PCI_AD5 B55 A55 PCI_AD4 PCI_AD5 B55 A55 PCI_AD4 C425 0.1UF 25V Y5V
PCI_AD3 AD5 AD4 PCI_AD3 AD5 AD4 C444 1000P 50V X7R
B56 AD3 GND A56 B56 AD3 GND A56
B57 A57 PCI_AD2 B57 A57 PCI_AD2
PCI_AD1 GND AD2 PCI_AD0 PCI_AD1 GND AD2 PCI_AD0
B58 AD1 AD0 A58 B58 AD1 AD0 A58
B59 +Vio +Vio A59 B59 +Vio +Vio A59
PCI_ACK64- B60 A60 PCI_REQ64A- PCI_ACK64- B60 A60 PCI_REQ64B-
ACK64_L REQ64_L ACK64_L REQ64_L
B61 5V 5V A61 B61 5V 5V A61
B62 A62 B62 A62 +5V CT42 100UF 16V 5X11 2mm /NI
5V 5V PCI_AD[31..0] 16 5V 5V
PCI_C/BE-[3..0] 16
B C427 1UF 16V 0805 Y5V /NI B
C449 1UF 16V 0805 Y5V /NI
C450 1UF 16V 0805 Y5V /NI
C451 0.1UF 25V Y5V
C426 0.1UF 25V Y5V
+3.3V C452 0.1UF 25V Y5V /NI

PCI_SERR- 1 2
16 PCI_SERR- PCI_PERR- RN85 +12V CT39 100UF 16V 5X11 2mm /NI
16 PCI_PERR- 3 4
PCI_LOCK- 5 6 8.2K 8P4R
PCI_STOP- 7 8
16 PCI_STOP- PCI_DEVSEL-
16 PCI_DEVSEL- 1 2
PCI_TRDY- 3 4 RN84
16 PCI_TRDY- PCI_FRAME- 8.2K 8P4R
16 PCI_FRAME- 5 6
PCI_IRDY- 7 8
16 PCI_IRDY- PCI_ACK64-
PCI_REQ64A-
1
3
2
4 RN86
PCI SLOT 1 PCI SLOT 2
PCI_REQ64B- 5 6 8.2K 8P4R
7
1
8
2
PCICLK PCI_CLKSLOT1 PCI_CLKSLOT2
PCI_REQ-0 3 4 RN81
16 PCI_REQ-0 PCI_REQ-1 8.2K 8P4R
16 PCI_REQ-1 PCI_REQ-2
5
7
6
8
INTR PCI_INTY* PCI_INTW*
16 PCI_REQ-2 PCI_INTY-
16 PCI_INTY- 1 2
PCI_REQ-4 RN82
16 PCI_REQ-4 PCI_INTW-
3
5
4
6 8.2K 8P4R IDSEL PCI_AD22 PCI_AD24
16 PCI_INTW- PCI_CLKRUN- 7
16 PCI_CLKRUN- 8
PCI_PME- 1 2
16 PCI_PME- +3.3V_DUAL
PCI_INTX- RN83
A
16 PCI_INTX- PCI_REQ-3
3
5
4
6 8.2K 8P4R GNT/REQ PCI_GNT*1/REQ*1 PCI_GNT*2/REQ*2 A
16 PCI_REQ-3 PCI_INTZ-
16 PCI_INTZ- 7 8
16 PCI_GNT-4 1 2
3 4 RN80
16 PCI_GNT-0 8.2K 8P4R /NI
16 PCI_GNT-1 5 6
16 PCI_GNT-2 7 8 +3.3V
R224
14,16 PCI_GNT-3 8.2K /NI
Title
PCI SLOT 1&2
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 20 of 39
5 4 3 2 1
 5 4 3 2 1

D D

SPK_DAT

C
SLEEPBTNJ 18,33
FPQ3 FPRN3 NO S3 :
2N3904 SOT23
EMI EMI NO S3 : 1 2
FPC6 FPC5 3 4
ADD RN1 Q1
470P 50V X7R /NI 470P 50V X7R /NI ADD R1 R2 5 6
10K 1% SPK1

E
SPEAKER FPR3 7 8 S3 : ADD
18 SPEAKER
S3 : ALL(WITHOUT R3)
270 8P4R
REMOVE
FPRN1 R1 R2
1 2 +5V FP_8_10

C
+3.3V
3 4 +5V_STBY
5 6
JPANEL1 +5V FPQ4 FPQ1
7 8 Q1

SEL_LED_PWR
1
3
5
7
HEADER 2X12 N_P18_20 /NI FP_12 E
10K 8P4R FPRN4 2N3904 SOT23 C

B
1 2 B
100 8P4R 3 4 FPR7 R1
330 /NI 2N3906 SOT23

2
4
6
8
5 6
C SPK_VCC 7 8 C
CRNT_LMT_HDDLED1 9 10 FP_8_10 FPRN2
FPD3 1N4148 SMD HDD_LED- 11 12 FP_12 1 2 BASE_PNP_TR
23 IDEACTPJ K A FPR9 33 1%
13 14 RN1 3 4

FPD2 1N4148 SMD

15
CRNT_LMT_HDDLED217
16 EMI EMI FPR8
5
7
6
8
ACPI_LED 33
23 IDEACTSJ K A FPC8 FPC7 0 /NI
19 R2
21 22 FPR10 470P 50V X7R /NI 2.2K 8P4R
17 SATA_HDLED- FPD1 1N4148 SMD 23 24 56 470P 50V X7R /NI FPR6 2.2K
K A +5V_STBY
+5V
FPR12
100 /NI
FPC9
470P 50V X7R /NI

C
+3.3V_DUAL

Stuff R3
FPR4 for FPR1 FPR2 10K 1% /NI
24 RST_BT_
MiniPC SLP_S5- 18,32

B
22K

design
FPR5 10K 1%
+2.5VDIMM
PWRBTN- 33
+3.3V TO +3.3V_DUAL FOR VER:0.94 FPQ5 FPQ2
+3.3V_DUAL FPR4 10K 1% FPC1 FPC3 2N3904 SOT23 2N3904 SOT23 FPQ6
0.1UF 25V Y5V 2N3904 SOT23
FPR11 33 1% 470P 50V X7R /NI
18,37 FP_RESET- +5V_STBY

B FPC2 FPC4 B
1UF 16V 0805 Y5V /NI
470P 50V X7R /NI
PWRSW_ 24

33 IRTX

33 IRRX

A A

Title
FRONT PANEL HEADER
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 21 of 39
5 4 3 2 1
 5 4 3 2 1

PCI-EX1
+3.3V +12V_P +12V_P +3.3V +3.3V PCI-EX1_1
+3.3V_DUAL PCI_Express_x16 +3.3V_DUAL +12V_P +12V_P +3.3V
B1 A1 PCI_Express_x1
+12V PRSNT1# PE2_PRSNT- 14
B2 +12V +12V A2 B1 +12V1 PRSNT1# A1
B3 RSVD1 +12V A3 B2 +12V2 +12V3 A2
B4 A4 RN75 B3 A3
GND GND PE_TCK 1 RSVD1 +12V4 RN73
7,18,20,37 SMB_SCL B5 SMCLK JTAG2 A5 2 B4 GND GND A4
B6 A6 PE_TDI 3 4 B5 A5 PE_TCK1 1 2
7,18,20,37 SMB_SDA SMDAT JTAG3 7,18,20,37 SMB_SCL SMCLK JTAG2 PE_TDI1 3
B7 GND JTAG4 A7 5 6 7,18,20,37 SMB_SDA B6 SMDAT JTAG3 A6 4
B8 A8 PE_TMS 7 8 +3.3V B7 A7 5 6
PE_TRST_0 +3.3 JTAG5 GND JTAG4 PE_TMS1 7
B9 JTAG1 +3.3V A9 B8 +3.3V1 JTAG5 A8 8 +3.3V
B10 A10 10K 8P4R PE_TRST_1 B9 A9
3.3VAUX +3.3V JTAG1 +3.3V2 10K 8P4R
D 18 PE_WAKE- B11 WAKE# PERST# A11 PE_RESET- 14 B10 3.3VAUX +3.3V3 A10 D
18 PE_WAKE- B11 WAKE# PERST# A11 PE_RESET- 14
Mechanical Key C336 22P 50V NPO /NI
B12 A12 Mechanical Key
0.1UF 25V Y5V RSVD2 GND
B13 GND REFCLK+ A13 PE0_REFCLK 14 B12 RSVD2 GND A12
PE0_OUT0 C341 PE0TX_0+ B14 A14 0.1UF 25V Y5V B13 A13
PETP0 REFCLK- PE0_REFCLK- 14 GND REFCLK+ PE1_REFCLK 14
PE0_OUT-0 C340 PE0TX_0- B15 A15 C326 PE1TX_1+ B14 A14
PETN0 GND 14 PE1_OUT PETP0 REFCLK- PE1_REFCLK- 14
0.1UF 25V Y5V B16 A16 C327 PE1TX_1- B15 A15
GND PERP0 PE0_IN0 14 14 PE1_OUT- PETN0 GND
B17 A17 0.1UF 25V Y5V B16 A16
14 PE0_PRSNT- PRSNT2#1 PERN0 PE0_IN-0 14 GND PERP0 PE1_IN 14
B18 GND GND A18 14 PE1_PRSNT- B17 PRSNT2# PERN0 A17 PE1_IN- 14
0.1UF 25V Y5V B18 A18
PE0_OUT1 C342 PE0TX_1+ End of the x1 Connector GND GND
B19 PETP1 RSVD5 A19
PE0_OUT-1 C343 PE0TX_1- End of the x1 Connector
B20 PETN1 GND A20
0.1UF 25V Y5V B21 A21
GND PERP1 PE0_IN1 14
0.1UF 25V Y5V B22 A22 3GPIOX1
GND PERN1 PE0_IN-1 14
PE0_OUT2 C344 PE0TX_2+ B23 A23
PE0_OUT-2 C345 PE0TX_2- PETP2 GND
B24 PETN2 GND A24
0.1UF 25V Y5V B25 A25
GND PERP2 PE0_IN2 14
0.1UF 25V Y5V B26 A26 +12V Change to +12V_P
GND PERN2 PE0_IN-2 14
PE0_OUT3 C346 PE0TX_3+ B27 A27 RN74
PE0_OUT-3 C347 PE0TX_3- PETP3 GND PE_TRST_0
B28 PETN3 GND A28 1 2
0.1UF 25V Y5V B29 A29 3 4 PE_TRST_1
GND PERP3 PE0_IN3 14
B30 A30 5 6 PE0_PRSNT-
RSVD3 PERN3 PE0_IN-3 14
B31 A31 7 8 PE1_PRSNT- +3.3V
PRSNT2#2 GND +3.3V
B32 GND RSVD6 A32
0.1UF 25V Y5V 10K 8P4R CT40 1000UF 6.3V 8X12 /NI
PE0_OUT4 C348 PE0TX_4+ End of the x4 Connector
B33 PETP4 RSVD7 A33
PE0_OUT-4 C349 PE0TX_4- B34 A34
0.1UF 25V Y5V PETN4 GND
B35 GND PERP4 A35 PE0_IN4 14
C 0.1UF 25V Y5V B36 A36 C399 1UF 16V 0805 Y5V C
GND PERN4 PE0_IN-4 14
PE0_OUT5 C350 PE0TX_5+ B37 A37 C329 1UF 16V 0805 Y5V /NI
PE0_OUT-5 C351 PE0TX_5- PETP5 GND C306 1UF 16V 0805 Y5V /NI
B38 PETN5 GND A38
0.1UF 25V Y5V B39 A39 C325 0.1UF 25V Y5V /NI
GND PERP5 PE0_IN5 14
0.1UF 25V Y5V B40 A40 +12V_P CT31 100UF 16V 5X11 2mm C324 0.1UF 25V Y5V /NI
GND PERN5 PE0_IN-5 14
PE0_OUT6 C352 PE0TX_6+ B41 A41 C307 0.1UF 25V Y5V /NI
PE0_OUT-6 C353 PE0TX_6- PETP6 GND C398 1UF 16V 0805 Y5V /NI
B42 PETN6 GND A42
0.1UF 25V Y5V B43 A43 C330 1UF 16V 0805 Y5V /NI
GND PERP6 PE0_IN6 14
0.1UF 25V Y5V B44 A44 C331 1UF 16V 0805 Y5V /NI
GND PERN6 PE0_IN-6 14
PE0_OUT7 C354 PE0TX_7+ B45 A45 C372 0.1UF 25V Y5V /NI
PE0_OUT-7 C355 PE0TX_7- PETP7 GND C328 0.1UF 25V Y5V /NI +3.3V_DUAL
B46 PETN7 GND A46
0.1UF 25V Y5V B47 A47 C373 0.1UF 25V Y5V /NI
GND PERP7 PE0_IN7 14
B48 PRSNT2#3 PERN7 A48 PE0_IN-7 14
B49 A49 C338 0.1UF 25V Y5V /NI
0.1UF 25V Y5V GND GND C339 0.1UF 25V Y5V /NI
PE0_OUT8 C356 PE0TX_8+ End of the x8 Connector C337 0.1UF 25V Y5V /NI
B50 PETP8 RSVD8 A50
PE0_OUT-8 C357 PE0TX_8- B51 A51 +5V
0.1UF 25V Y5V PETN8 GND
B52 GND PERP8 A52 PE0_IN8 14
0.1UF 25V Y5V B53 A53 C497 0.1UF 25V Y5V
GND PERN8 PE0_IN-8 14
PE0_OUT9 C358 PE0TX_9+ B54 A54
PE0_OUT-9 C359 PE0TX_9- PETP9 GND
B55 PETN9 GND A55
0.1UF 25V Y5V B56 A56
GND PERP9 PE0_IN9 14
0.1UF 25V Y5V B57 A57 FOR EMI
GND PERN9 PE0_IN-9 14
PE0_OUT10 C360 PE0TX_10+ B58 A58
PE0_OUT-10 C361 PE0TX_10- PETP10 GND
B59 PETN10 GND A59
0.1UF 25V Y5V B60 A60
GND PERP10 PE0_IN10 14
0.1UF 25V Y5V B61 A61
GND PERN10 PE0_IN-10 14
PE0_OUT11 C362 PE0TX_11+ B62 A62
PE0_OUT-11 C363 PE0TX_11- PETP11 GND
B63 PETN11 GND A63
B 0.1UF 25V Y5V B64 A64 B
GND PERP11 PE0_IN11 14
0.1UF 25V Y5V B65 A65
GND PERN11 PE0_IN-11 14
PE0_OUT12 C364 PE0TX_12+ B66 A66
PE0_OUT-12 C365 PE0TX_12- PETP12 GND
B67 PETN12 GND A67
0.1UF 25V Y5V B68 A68
GND PERP12 PE0_IN12 14
0.1UF 25V Y5V B69 A69
GND PERN12 PE0_IN-12 14
PE0_OUT13 C366 PE0TX_13+ B70 A70
PE0_OUT-13 C367 PE0TX_13- PETP13 GND
B71 PETN13 GND A71
0.1UF 25V Y5V B72 A72
GND PERP13 PE0_IN13 14
0.1UF 25V Y5V B73 A73
GND PERN13 PE0_IN-13 14
PE0_OUT14 C368 PE0TX_14+ B74 A74
PE0_OUT-14 C369 PE0TX_14- PETP14 GND
B75 PETN14 GND A75
0.1UF 25V Y5V B76 A76
GND PERP14 PE0_IN14 14
0.1UF 25V Y5V B77 A77
GND PERP14 PE0_IN-14 14
PE0_OUT15 C370 PE0TX_15+ B78 A78
PE0_OUT-15 C371 PE0TX_15- PETP15 GND
B79 PETN15 GND A79
0.1UF 25V Y5V B80 A80
GND PERP15 PE0_IN15 14
14 PE0_OUT[15..0] B81 PRSNT2#4 PERN15 A81 PE0_IN-15 14
14 PE0_OUT-[15..0] B82 RSVD4 GND A82
End of the x16 Connector

3GPIOX16

A A

Title
PCIEXPRESS
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 22 of 39
5 4 3 2 1
 5 4 3 2 1

17 IDE_PDD[15..0] IDE1
R152 10K 1% BOX 2X20 N20 B

16 PCIRST_IDE- 1 RESET GND 2

IDE_PDD7 3 4 IDE_PDD8
IDE_PDD6 DD7 DD8 IDE_PDD9
5 DD6 DD9 6
D IDE_PDD5 7 8 IDE_PDD10 D
IDE_PDD4 DD5 DD10 IDE_PDD11
9 DD4 DD11 10
IDE_PDD3 11 12 IDE_PDD12
IDE_PDD2 DD3 DD12 IDE_PDD13
13 DD2 DD13 14
IDE_PDD1 15 16 IDE_PDD14
IDE_PDD0 DD1 DD14 IDE_PDD15
17 DD0 DD15 18
R93 4.7K 19 20
+3.3V GND NC
17 IDE_DREQ_P 21 DMARQ GND 22
17 IDE_IOW_P- 23 DIOW GND 24
17 IDE_IOR_P- 25 DIOR GND 26
17 IDE_IORDY_P 27 IORDY CSEL 28
17 IDE_DACK_P- 29 DMACK GND 30
17 IDE_INTR_P 31 INTRQ NC 32
17 IDE_ADDR_P1 33 DA1 PDIAG 34 CBLE_DET_P 17
17 IDE_ADDR_P0 35 DA0 DA2 36
17 IDE_CS1_P- 37 CS0 CS1 38
39 40 R96
21 IDEACTPJ DASP GND
R94 8.2K /NI 15K
+3.3V

R92 R95
5.6K 10K 1% PRIMARY IDE

17 IDE_CS3_P-
17 IDE_ADDR_P2

C 17 IDE_SDD[15..0] C

R132 10K 1% IDE2

16 PCIRST_IDE- 1 RESET GND 2

IDE_SDD7 3 4 IDE_SDD8
IDE_SDD6 DD7 DD8 IDE_SDD9
5 DD6 DD9 6
IDE_SDD5 7 8 IDE_SDD10
IDE_SDD4 DD5 DD10 IDE_SDD11
9 DD4 DD11 10
IDE_SDD3 11 12 IDE_SDD12
IDE_SDD2 DD3 DD12 IDE_SDD13
13 DD2 DD13 14
IDE_SDD1 15 16 IDE_SDD14
IDE_SDD0 DD1 DD14 IDE_SDD15
17 DD0 DD15 18
+3.3V R90 4.7K 19 20
GND NC
17 IDE_DREQ_S 21 DMARQ GND 22
17 IDE_IOW_S- 23 DIOW GND 24
17 IDE_IOR_S- 25 DIOR GND 26
17 IDE_IORDY_S 27 IORDY CSEL 28
17 IDE_DACK_S- 29 DMACK GND 30
17 IDE_INTR_S 31 INTRQ NC 32
17 IDE_ADDR_S1 33 DA1 PDIAG 34 CBLE_DET_S 17
17 IDE_ADDR_S0 35 DA0 DA2 36
17 IDE_CS1_S- 37 CS0 CS1 38
39 40 R91
21 IDEACTSJ DASP GND
R87 8.2K /NI 15K
+3.3V
BOX 2X20 N20 Y
R89 R88
B
5.6K 10K 1% SECONDARY IDE B

17 IDE_CS3_S-
17 IDE_ADDR_S2

A A

Title
IDE CONNECTORS
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 23 of 39
5 4 3 2 1
 5 4 3 2 1

MH1 MH4
PAD200-8 /NI PAD200-8 /NI -12V +5V +3.3V +5V +5V_STBY +12V +5V_STBY
1 5 1 5 Impedance Testing Coupon +5V_STBY
2 6 2 6
3 (NPTH) 7 3 (NPTH) 7 +5V
JP1 JATXPWR1
4 8 4 8
NC1 13 1
1 R67 R63 3.3V 3.3V
MH7 2 4.7K /NI 10K 1%
PAD200-8 /NI MH2 HEADER 1X2 D 150 /NI
POWER CONN DECOUPING 14 -12V 3.3V 2
9

9
1 5 PAD200-8 /NI JP2 15 3
GND GND
2 6 1 5 1
3 7 2 6 NC2 +5V +3.3V 16 4
(NPTH)
2 33 PS_ON- PSON 5V
D 4 8 3 (NPTH) 7 D
4 8 HEADER 1X2 D 150 /NI C112 0.1UF 25V Y5V C87 0.1UF 25V Y5V 17 5
C104 0.1UF 25V Y5V /NI R68 4.7K /NI Q18 C151 GND GND
18,33 SLP_S3-
U4 2N3904 SOT23 /NI 470P 50V X7R 18 6
NC3 GND 5V R57
9

NC4 CP1 10K 1%

9

CP2 19 GND GND 7

+5V CP3
CP4 -5V 20 NC POK 8 PWRGD_PS 32,35
NC5 CP5
CP6 21 5V 5VSB 9
29,30 AUD_GND NC6
CP7
22 10

MH5 MH8
CP8
CP9
CP10
POWER 23
5V

5V
12V

12V 11
PAD200-8 /NI PAD200-8 /NI
1
2
5
6
1
2
5
6
MATXCUT /NI CONNECTOR C119 C169
0.1UF 25V Y5V /NI
24 GND DET 12

3 (NPTH) 7 3 (NPTH) 7 0.1UF 25V Y5V /NI

4 8 4 8 POWER CONN ATX 24P C110 C99 C124
0.1UF 25V Y5V
+12V 470P 50V X7R
+12V +5V 0.1UF 25V Y5V
+5V
9

E
R162 R7 B Q4 R3 R12
4.7K /NI +12V_P
1K 1% /NI
2SB1202 TO252 /NI
0 0805
10K 1% LINEAR FAN CHANGE TO 10K
NO LINEAR FAN CHANGE TO 22K

C
C 33 FAN_CTL1 C

JCFAN1

4
PWRSW1 R168 R5 R13 1K 1%
15K /NI 3 33K /NI 3 FAN1 33
+ 2
3 1 1 R8 470 /NI
1
2 -
U11A WAFER 1X3 +
21 PWRSW_ 4 2 LM324 SO14 CT2 CPU

11
CT26 R176 100UF 16V 5X11 2mm /NI
L1 L2 22UF 25V 5X11 2mm /NI 22K /NI

TP6151L-4 /NI

+12V +5V
FOR VER:1.1 +5V
R306 330 /NI R277 4.7K /NI

R278 1K 1% /NI Q45

R307 330 /NI R279 2N2907 SOT23 /NI R280 R178
+5V
SYSTEM1

D
RSTSW2

KA

KA

KA
4.7K /NI 10K 1%
Q46 0 0805
3 1 R281 G 2N7002 SOT23 /NI JSFAN1
33 FAN_CTL2
R177 1K 1%
3 FAN2 33

S
51 1% /NI
2
21 RST_BT_ 4 2 1

K
B L1 L2 WAFER 1X3 + B
CT30 D21 D22 D23
100UF 16V 5X11 2mm /NI BAV99 SOT23
+5V BAV99 SOT23
TP6151L /NI BAV99 SOT23 /NI

+12V +5V
+5V
+5V R285 4.7K /NI

R286 1K 1% /NI Q47

R287 2N2907 SOT23 /NI R288 R282
NB FAN
D

4.7K /NI 10K 1% /NI

Q48 0 0805 /NI
LED_5VSB LED_DIMM R289 G 2N7002 SOT23 /NI JNBFAN1
33 FAN_CTL3
R300 R301 R283 1K 1% /NI
+2.6V_SUS 3 FAN3 33
S

330 /NI 330 /NI 51 1% /NI

+5V_STBY 2
1
+2.5VDIMM WAFER 1X3 /NI +
CT45
R302 R303 R304 R305 100UF 16V 5X11 2mm /NI
330 /NI 330 /NI 470 /NI 470 /NI

+12V
D16 D17 D18 D19 JSFAN2
A RED CHIP LED 0805 /NI RED CHIP LED 0805 /NI RED CHIP LED 0805 /NI RED CHIP LED 0805 /NI 3 A
2
1
SYSTEM2
LEDD0 33 WAFER 1X3 /NI
LEDD1 33

LED_D2 LED_D1 Title

ATX POWER & FAN CONTROL
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 24 of 39
5 4 3 2 1
 5 4 3 2 1

D D

+5V

FLOPPY

2
4
6
8
CONNECTOR R251
150
RN87
150 8P4R
FDD1

1
3
5
7
1 2 FRWC- 33
D14
3 4
+3.3V_STBY A 6
7 8 FINDEX- 33
KA 9 10
+3.3V_VBAT 18,33,37 FMOA- 33
11 12 FDSB- 33
R159 VBATREFK
1K 1% 13 14 FDSA- 33
C308 C309 C310 15 16 FMOB- 33
0.1UF 25V Y5V 17 18 FDIR- 33
BAT1 BAT54C SOT23 1UF 16V 0805 Y5V 19 20 FSTEP- 33
BATTERY HOLDER-1 10UF 10V 0805 Y5V 21 22 FWD- 33
23 24 FWEN- 33
25 26 FTRAK0- 33
27 28 FWP- 33
29 30 FRDATA- 33
31 32 FHEAD- 33
33 34 FDSKCHG- 33
C C
BOX 2X17 N5 W
C485
0.1UF 25V Y5V /NI

USB_PWR

FB2 BEAD 60 0805 1A KB_FB_VCC5

1 2 C9
3 4 RN4 0.1UF 25V Y5V JKBMS1
5 6 2.2K 8P4R
7 8 MINI DIN CONN PC99

KDAT FB3 FB_KDAT 1

33 KDAT
BEAD 60 0805 1A 2
3
4
KCLK FB4 FB_KCLK 5
33 KCLK
BEAD 60 0805 1A 6
MDAT FB5 FB_MDAT 7
33 MDAT
BEAD 60 0805 1A 8
9
10
MCLK FB6 FB_MCLK 11
33 MCLK
BEAD 60 0805 1A 12
MTH'S

C18 C16 C13 C10

G1
G2
G3
G4
G5
B
KEYBOARD & MOUSE 47P 50V NPO
47P 50V NPO
B

47P 50V NPO

47P 50V NPO

FB7 0 0805 /NI Data Switch solution

A A

Title
FLOOY ,KEYBOARD & MOUSE ,CMOS CLEAR
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 25 of 39
5 4 3 2 1
 A B C D E

R86 0 /NI
14 DAC_HSYNC
R84 0 /NI
14 DAC_VSYNC

+5V

4 4

+5V
U5A

14
SN74ACT08 PS1
1 FB12 BEAD 60 0805 1A
3 R97 22
U5B POLY FUSE 1.1A

14
14 DAC_HSYNC 2
SN74ACT08 +5V +5V R100 0 0805 /NI C198
4 0.1UF 25V Y5V
14 DAC_VSYNC
R83 22

7
6
5

R80 R99 +5V JVGA1

2.2K 2.2K VGA CONN PC99 SHORT

7
6
VGA_R FB11 INDUCTOR 68NH 300MA 0805 MONRED_A 1
11
7
VGA_G FB10 INDUCTOR 68NH 300MA 0805 MONGREEN_A 2
R98 33 1% MONSDA_A 12
18 DDC_DATA
8
VGA_B FB9 INDUCTOR 68NH 300MA 0805 MONBLUE_A 3
MONHSYNC_A 13
DDCPOWER_A 9
4
MONVSYNC_A 14
10
5
3 R72 33 1% MONSCL_A 15 3
18 DDC_CLK
KA

KA

KA

KA

KA

KA

KA
D11 D7 D6 D8 D12 D9 D10

G1
G2
R73 R69 R64 C184 C166 C152 C183 C186 C188 C192 C173 C171 C167 C191 C98
150 1% 150 1% 150 1% 10P 50V NPO FB1 100P 50V NPO 33P 50V NPO 0.1UF 25V Y5V
10P 50V NPO 0 0805 47P 50V NPO 33P 50V NPO
10P 50V NPO 47P 50V NPO 33P 50V NPO
A

K
100P 50V NPO 470P 50V X7R /NI VGA CONNECTOR
BAT54S SOT23 /NI BAT54S SOT23 /NI
BAT54S SOT23 /NI BAT54S SOT23 /NI
BAT54S SOT23 /NI BAT54S SOT23 /NI
+3.3V BAT54S SOT23 /NI SVIDEO FILTERS OPTIONS
+5V

C1 L1 C1 L1
+5V

+3.3V C501 0.1UF 25V Y5V 22PF 1.8UH 270PF 330PF

C498 0.1UF 25V Y5V
8.2PF 0.56UH 82PF 82PF

14 DAC_RED FB28 2 1 BEAD 60 0805 1A VGA_R

14 DAC_GREEN FB29 2 1 BEAD 60 0805 1A VGA_G FOR EMI
14 DAC_BLUE FB30 2 1 BEAD 60 0805 1A VGA_B

2 2

1 1

Title
VGA CONNECTOR
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 26 of 39
A B C D E
 5 4 3 2 1

USB_PWR

+5V

1
USB_PWR R110 5.1K
USB_BKPNL_3_2_OC- 18
JUSBV1
2 HEADER 1X3 R111 10K 1%
D
USB LAN C207 D
470P 50V X7R /NI
USB R103 PS2
+5V_STBY
JUSBLAN1A
POLY FUSE 1.1A

3
B1 VCC0
0 0805 /NI
USB_PWR R104 5.1K UST3- B2
USB_BKPNL_5_4_OC- 18 DATA0-
C19 470P 50V X7R /NI R105 10K 1% UST3+ B3 DATA0+
JUSB1 B4 GND0
G3 G1
1 5 GND2 G3
UST4- 2 6
UST4+ 3 7 G4
UST5- GND3
4 8 A1 VCC1
UST5+ G4 G2 G5
UST2- GND4
A2 DATA1-
USB CONN G6
C215 C219 C209 C212 UST2+ GND5
A3 DATA1+
10P 50V NPO /NI 10P 50V NPO /NI
10P 50V NPO /NI A4 GND1
FB13 0 0805 10P 50V NPO /NI C259 C264 C272 C268 CT12
10P 50V NPO /NI 10P 50V NPO /NI RJ45USBA CONN
10P 50V NPO /NI 22UF 25V 5X11 2mm
10P 50V NPO /NI

H1 H2 H3 H4
C 1 8 UST5- 1 8 UST3- 1 8 UST0+ 1 8 UST7+ C
18 USB_5- 1 8 18 USB_3- 1 8 18 USB_0 1 8 18 USB_7 1 8

2 7 UST5+ 2 7 UST3+ 2 7 UST0- 2 7 UST7-

18 USB_5 2 7 18 USB_3 2 7 18 USB_0- 2 7 18 USB_7- 2 7
3 6 UST4- 3 6 UST2+ 3 6 UST1+ 3 6 UST6+
18 USB_4- 3 6 18 USB_2 3 6 18 USB_1 3 6 18 USB_6 3 6

4 5 UST4+ 4 5 UST2- 4 5 UST1- 4 5 UST6-

18 USB_4 4 5 18 USB_2- 4 5 18 USB_1- 4 5 18 USB_6- 4 5
SMD CHOKE 0.5A/90U SMD CHOKE 0.5A/90U SMD CHOKE 0.5A/90U /NI SMD CHOKE 0.5A/90U /NI
RN49 RN67 RN90 RN101
1 2 UST4+ 1 2 UST2- 1 2 UST1- 1 2 UST6-
18 USB_4 18 USB_2- 18 USB_1- 18 USB_6-
3 4 UST4- 3 4 UST2+ 3 4 UST1+ 3 4 UST6+
18 USB_4- 18 USB_2 18 USB_1 18 USB_6
5 6 UST5+ 5 6 UST3+ 5 6 UST0- 5 6 UST7-
18 USB_5 18 USB_3 18 USB_0- 18 USB_7-
7 8 UST5- 7 8 UST3- 7 8 UST0+ 7 8 UST7+
18 USB_5- 18 USB_3- 18 USB_0 18 USB_7
0 8P4R /NI 0 8P4R /NI 0 8P4R 0 8P4R

+5V
1

JUSBV2
2 HEADER 1X3
B B
R263 PS4
+5V_STBY
3

0 0805 /NI POLY FUSE 1.1A

USBPWR R233 5.1K USBPWR R234 5.1K
USB_FNTPNL_7_6_OC- 18 USB_FNTPNL_1_0_OC- 18
R239 10K 1% R240 10K 1%

C482 470P 50V X7R /NI C447 470P 50V X7R /NI

JUSB2 JUSB3
1 2 1 2
UST7- 3 4 UST6- UST0- 3 4 UST1-
UST7+ 5 6 UST6+ UST0+ 5 6 UST1+
7 8 7 8
10 10
C478 C477 C481 C480 C434 C436 CT44 C432 C433
10P 50V NPO /NI HEADER 2X5 N9 W 10P 50V NPO /NI 10P 50V NPO /NI HEADER 2X5 N9 W 22UF 25V 5X11 2mm
10P 50V NPO /NI 10P 50V NPO /NI 10P 50V NPO /NI 10P 50V NPO /NI
10P 50V NPO /NI

A A

Title
USB INTERFACE
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 27 of 39
5 4 3 2 1
 5 4 3 2 1

R214 RN79 RN93 RN100 RN78 Ver091 Update

D +3.3V_STBY 2.2K 2.2K 8P4R 2.2K 8P4R D
D15 2.2K 8P4R 2.2K 8P4R
+5V
1N4148 SMD
LPT

2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
D3 1N4148 SMD -XRI1

2
4
6
8
RN2
PARALLEL - CONNECTOR

1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
10K 8P4R JPRNT1
1
3
5
7
G1
RN91 33 8P4R
P_PRD3 1 2 PRD3 -STB 1
18 SER_RI- 33 PD3 AFD
P_PRD2 3 4 PRD2 14
C

33 PD2 PRD0
P_PRD1 5 6 PRD1 2
33 PD1
P_PRD0 7 8 PRD0 P_-ERR 15
33 PD0 33 EEROR# PRD1
D2 3
CT3 RN99 33 8P4R -INIT 16
1N4148 SMD /NI P_PRD7 1 2 PRD7 PRD2 4
33 PD7
E

22UF 25V 5X11 2mm /NI P_PRD6 3 4 PRD6 -SLIN 17

33 PD6
P_PRD5 5 6 PRD5 PRD3 5
33 PD5
Q2 P_PRD4 7 8 PRD4 18
2N3904 SOT23 WAKE ON LAN 33
33
33
PD4
STB#
ALF#
P_-STB
P_-AFD
1
3
2
4
-STB
AFD
PRD4 6
19
P_-INIT 5 6 -INIT PRD5 7
33 INIT#
P_-SLIN 7 8 -SLIN 20
33 SLCTIN#
PRD6 8
RN88 33 8P4R 21
C PRD7 9 C
22
P_-ACK 10
33 ACK#
23
COM1 33 BUSY
P_BUSY 11
24
P_PE 12
33 PE
+5V +12V 25
JCOM1 P_SLCT 13
33 SLCT
U1 D CONN 9PIN PC99
20 VCC V+ 1 G2
19 2 RIN1 1
33 DCD1# ROUT1 RIN1 RIN2 C102
33 DSR1# 18 ROUT2 RIN2 3 6 G3
17 4 RIN3 2 C106 C113 C115
33 SINA ROUT3 RIN3
16 5 DOUT1 7 G2 C109 100P 50V NPO
33 RTS1# DIN1 DOUT1 DOUT2 100P 50V NPO 100P 50V NPO D CON 25PIN HIGH RISE PC99
15 DIN2 DOUT2 6 3
33 SOUTA RIN4 100P 50V NPO
33 CTS1# 14 ROUT4 RIN4 7 8 G1
13 8 DOUT3 4 +5V +12V -12V 100P 50V NPO
33 DTR1# DIN3 DOUT3 -XRI1
12 ROUT5 RIN5 9 9
33 RI1#
11 GND V- 10 5

ST75185CTR TSSOP C49 100P 50V NPO

P_-ERR
C59 100P 50V NPO COM PORT C35 C34 C72

PRD1
PRD3
PRD4
PRD5
PRD6

-SLIN

PRD2

PRD0
-INIT

-STB
-12V C62 100P 50V NPO 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI

AFD
C65 100P 50V NPO 0.1UF 25V Y5V /NI
C67 100P 50V NPO C127 C134 C150
C73 100P 50V NPO C123 C88 C95
C71 100P 50V NPO 100P 50V NPO C120 C90 C138
C76 100P 50V NPO 100P 50V NPO C117 C130 C93
B
NEAR COM1 & COM2 100P 50V NPO B
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO
100P 50V NPO

A A

R309 0

Title
FOR EMI
LPT & COM1 & COM2(COLAY)
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 28 of 39
5 4 3 2 1
 5 4 3 2 1

+5V

C499 0.1UF 25V Y5V JCDIN1

CD_L 1 L
CD_G 2 GND
3 GND
FOR EMI CD_R 4 R
WAFER 1X4 BLACK
PORT_D_R 30
AR11 AR12 AR10
D 47K 47K 47K D
PORT_D_L 30
FRONT OUT CD in connector AUD_GND 24,30

1UF 10V Y5V AC27

STR_MIC_L 30
1UF 10V Y5V AC26
STR_MIC_R 30
Verfout bias for stereo microphone.
VCC5_AUD
STR MIC--->FRONT PANEL AD3 4.7K
A K AR23
STR_MIC_L 30
AR16 1N4148 SMD
AUD_GND 24,30
AC23 1UF 10V Y5V 4.7K

AD4 4.7K
VOCR A K AR24

100UF 16V 6.3X5 2.5mm

100UF 16V 5X11 2mm
STR_MIC_R 30
VOBR AR15

1UF 16V 0805 Y5V

1UF 16V 0805 Y5V

1N4148 SMD

0.1UF 25V Y5V

4.7K
AC19 1UF 10V Y5V

1UF 10V Y5V

AUD_GND 24,30 AUD_GND 24,30

C
Verfout bias for backpanel microphone. C

AC17

AC16
+ + + + AC21
1000P 50V X7R AC22 4.7K AR9 K A
30 PORT_B_L

AC30

AC29

AC14

AC15
VCC5_AUD 1000P 50V X7R AD2 1N4148 SMD
4.7K AR8 K A VOBR
VCC5_AUD 30 PORT_B_R
AD1 1N4148 SMD

AU1 VOBR

36

35

34

33

32

31

30

29

28

27

26

25
FRONT-R

FRONT-L

MIC2-VREFO/AFILT2

LINE1-VREFO-L/AFILT1
Sense B/FMIC1

DCVOL/VREFO2

MIC1-VREFO-R/FMIC2

LINE2-VREFO/JD4

MIC1-VREFO-L

VREF

AVSS1

AVDD1
AC24
0.1UF 25V Y5V LINE IN AR13
37 LINE1-VREFO-R LINE1-R 24 PORT_C_R 30 5.6K
AC7 1UF 10V Y5V
24,30 AUD_GND
38 AVDD2 LINE1-L 23 PORT_C_L 30
AC8 1UF 10V Y5V AUD_GND 24,30
39 SURR-L MIC1-R 22 PORT_B_R 30
AC9 1UF 10V Y5V
40 JDREF/NC/JD3 MIC1-L 21 PORT_B_L 30
AC10 1UF 10V Y5V
41 SURR-R CD-R 20
MIC-IN
42 19 CD_R
24,30 AUD_GND AVSS2 CD-GND AC11 1UF 10V Y5V

Reserve to fine tune accuracy of

43 18 CD_G
CEN CD-L AC12 1UF 10V Y5V
B 44 LFE MIC2-R/JD1 17 CD_L
AC13 1UF 10V Y5V Jack Sensing B

45 SurrBack-L/GPIO0 MIC2-L/JD2 16

46 SurrBack-R/XTLSEL LINE2-R/AUX-R 15

47 SPDIFI/EAPD LINE2-L/AUX-L 14
GPIO1/XTLO

AR21 0
SDATA-OUT

48 13
GPIO0/XTLI

18,30 SPDIFO SPDIFO Sense A/Phone

SDATA-IN

PCBEEP
RESET#
BIT-CLK
DVDD1

DVDD2
DVSS1

DVSS2

SYNC

AR20 0 /NI CODEC ALC655

10

11

12

+3.3V
1

+3.3V

AR25 2 1 BEAD 60 0805 1A

AR19 10
AC18

AC25 1UF 10V Y5V

1UF 10V Y5V

AC_RST- AC_RST- 18
AC_SYNC
AC_SYNC 18
AR14 22 AC_SDIN_0
AC_SDIN_0 18
A A
18 AUD_14MHZ_IN AC_BITCLK
AR17 22 AC_BITCLK 18
AC20
AR18
10P 50V NPO 10K 1% /NI

AC_SDOUT Title
AC_SDOUT 18
AUDIO CODEC
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 29 of 39
5 4 3 2 1
 5 4 3 2 1

LINE-IN
JAUDIO1D 32 LINE_IN_L LINE_INL AL6 2 1 BEAD 60 0805 1A PORT_C_L 29
33
34
35 LINE_IN_R LINE_INR AL5 2 1 BEAD 60 0805 1A PORT_C_R 29
1
AUDIO JACK 3L
D AR7 AR6 D
CONN_GND 22K 22K
AC4 AC3
100P 50V NPO /NI
100P 50V NPO /NI
AUD_GND 24,29
LINE-OUT

G2

G1
JAUDIO1C 22 LINE_OUT_L LINE_OUTL AL2 2 1 BEAD 60 0805 1A PORT_D_L 29
23 JAUDIO1A
24 G2 G1
25 LINE_OUT_R LINE_OUTR AL1 2 1 BEAD 60 0805 1A PORT_D_R 29
1
AUDIO JACK 3L H1 G3
CONN_GND AC2 AR2 AR1 R313 0
22K 22K
AC1 24,29 AUD_GND G4 G5
100P 50V NPO /NI 100P 50V NPO /NI
AUD_GND 24,29
FOR EMI AUDIO JACK 3L

G4

G3
MIC-IN
JAUDIO1B 2 AL3 2 1 BEAD 60 0805 1A PORT_B_L
PORT_B_L 29
3
4
5 AL4 2 1 BEAD 60 0805 1A PORT_B_R IO_GND
PORT_B_R 29
1
AUDIO JACK 3L

AR4 AR5
AC5 AC6 22K 22K
C CONN_GND 100P 50V NPO /NI
100P 50V NPO /NI C
AUD_GND 24,29

2 1 AUD_GND 24,29
AR3 0 0805
VCC5_AUD

IO_GND

JFAUDIO1
STR_MIC_L 1 2
29 STR_MIC_L AUD_GND 24,29
STR_MIC_R 3 4 2 1
29 STR_MIC_R AUD_GND 24,29
LINE_OUTR 5 6 LINE_OUT_R AR22 0 0805
7
LINE_OUTL 9 10 LINE_OUT_L
AUDIO ANALOG POWER LINE_INR
LINE_INL
11 12 LINE_IN_R
LINE_IN_L
13 14

HEADER 2X7 N8
AU2
78L05 TO-92

+12V VCC5_AUD
G
O
I

B B
1

AC32
+

1
0.1UF 25V Y5V 2
1

AC31
-
2

ACT1
100UF 16V 5X11 2mm 0.1UF 25V Y5V
2

AUD_GND 24,29

+5V
BEAD 60 0805 1A JSPDIF_OUT1
2 1 1
2 SPDIFO 18,29
A AL7 3 A

AC28 WAFER 1X3 BLACK

1UF 16V 0805 Y5V

Title
AUDIO PORT
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 30 of 39
5 4 3 2 1
 5 4 3 2 1

+5V

+3.3V +3.3V PD1 PR11

ISL6566CR FOR K8 939 POWER CKT D

+12V SS12/5817 SMA /NI 4.7 0805 +12V

+12V
PC7 1UF 16V 0805 Y5V

8
6
4
2
PRN1 PL4 INDUCTOR 1.0UH
VIN
PR2 PR5 PR1 1K 8P4R /NI PR6 +12V_P
5.6K /NI 10K 1% 1K 1% /NI PU1 4.7 0805 VIN PCT1 PCT8 PCT3 PC20

7
ISL6566CR + + + +
PC3 1UF 16V 0805 Y5V PCT9 PC25 1UF 16V 0805 Y5V

7
5
3
1
38 VID4 33

VCC
37 VID_OUT4 PVCC1
39 VID3 30 PR9 2.7 0805 100UF 16V 5X11 2mm /NI 1500UF 16V 10X20X5 LR O

D
37 VID_OUT3 BOOT1
40 VID2 1UF 16V 0805 Y5V 1500UF 16V 10X20X5 LR O
37 VID_OUT2
1 VID1 PC5 PC23 1500UF 16V 10X20X5 LR O
37 VID_OUT1
2 VID0 0.1UF 25V Y5V 1UF 16V 0805 Y5V
37 VID_OUT0
3 DACSEL/VID5 31 PR28 2.7 0805 G
UGATE1 PQ3
16 CPU_VLD 35 PGOOD
37 ENLL FDD8880 TO252 PL1
16 CPUVDD_EN

S
PC1 0.1UF 25V Y5V 29
PHASE1 VCORE
INDUCTOR 1.1UH 30A D

D
PR3 PC2 0.1UF 25V Y5V 0.8V~1.55V/80A

D
1K 1% /NI 32 PR7 1.8K PR31
ISEN1 2.7 0805 PCT6 PCT5 PCT2 PCT4
Change Value 34 PR30 0 0805 G + + + +
PR10 PC6 LGATE1 PQ2
8 COMP G
5.6K 4700P 50V X7R +12V FDD8880 TO252 3300UF 6.3V 10X25X5 LR O

S
PR29 0 0805 PQ1 PC18 3300UF 6.3V 10X25X5 LR O

S
PC8 470P 50V X7R 1000P 50V X7R 3300UF 6.3V 10X25X5 LR O
Change Value 3300UF 6.3V 10X25X5 LR O
C 9 PR17 R55 10K 1% C
FB 4.7 0805 FDD8880 TO252
VIN
VCORE PR16 1K 1% 10 24 PC9 1UF 16V 0805 Y5V
VDIFF PVCC2
26 PR18 2.7 0805

D
BOOT2
PR20
51 1%
37 OVL
OVL PC10
0.1UF 25V Y5V
PC22
1UF 16V 0805 Y5V FOR T 系列
Change Value 27 PR32 2.7 0805 G
PR19 100 1% UGATE2 PQ4 VCORE
7 CPU_CORE_FB 12 VSEN FDD8880 TO252 PL2

S
PC12 1000P 50V X7R /NI 28
PHASE2 INDUCTOR 1.1UH 30A D
11

D
7 CPU_CORE_FB- RGND

D
PR12 150K /NI 25 PR15 1.8K PR35
+5V ISEN2
PR21 PC11 6 2.7 0805 PCT7
51 1% 1000P 50V X7R /NI PR8 10K 1% /NI OFST PR33 0 0805
LGATE2 23 G +
PQ5 G
OFFSET FDD8880 TO252 3300UF 6.3V 10X25X5 LR O
+12V

S
PR34 0 0805 PQ6 PC21
-10mV

S
1000P 50V X7R

36 PR26 R62 10K 1%

FS 4.7 0805
VIN FDD8880 TO252
Over Voltage Controller : PR4
5 REF PC16 1UF 16V 0805 Y5V
PVCC3 18
Vout=VCOREFB+ X ( 1+PR19 / RB ) 200K PC4
0.01UF 50V X7R 21 PR23 2.7 0805

D
BOOT3
B B
4 PC15 PC19
VRM10 0.1UF 25V Y5V 1UF 16V 0805 Y5V +12V_P
PR22 10K 1% 13 20 PR36 2.7 0805 G JATXPWR2
OCSET UGATE3 PQ7 1 1 4 4
FDD8880 TO252 PL3 2 3
2 3

S
14 ICOMP PHASE3 22 5 H1 H2 6
INDUCTOR 1.1UH 30A D

D
PC13

D
0.01UF 50V X7R /NI 15 19 PR24 1.8K PR39 POWER CONN ATX12V 2X2
ISUM ISEN3 2.7 0805
GND

16 17 PR37 0 0805 G
IREF LGATE3 PQ8 G
FDD8880 TO252
41

S
PC17 BOTTOM PAD PR38 0 0805 PQ9 PC24

S
0.01UF 50V X7R 1000P 50V X7R
CONNECT TO GND
THROUGH 10vias R81 10K 1%
FDD8880 TO252

PR27 PR13 30K 1%

10K 1% PR14 30K 1%
PC14 PR25 30K 1%

0.1UF 25V Y5V

A A
over voltage , control from ATXP01
RB
PR40 4.02K 1% /NI OVL
37 OV_VCORE0
PR41 2.37K 1% /NI OVL
37 OV_VCORE1 Title
PR42 1.58K 1% /NI OVL VCORE POWER SUPPLY
37 OV_VCORE2
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 31 of 39
5 4 3 2 1
 5 4 3 2 1

MEM_VDD
MEM_STR
+3.3V

S
NO S3 : REMOVE +12V
+5V_STBY R35 4.7K G
Q14
DUALS_FET_GATE FDD8880 TO252
+5V_STBY +3.3V
R34 +3.3V_DUAL

D
D 10K 1% D
+3.3V_DUAL
R37 Q16
1K 1% /NI 2N3904 SOT23
CT46
R43 4.7K Q13 100UF 16V 5X11 2mm CT6
24,35 PWRGD_PS 2N3904 SOT23 Q12 100UF 16V 5X11 2mm /NI
SS12/5817 SMA
C47
3900P 50V X7R /NI
+3.3V_STBY

+12V +5V_STBY

R4 R9 C56 + CT8
1K 1% 1K 1% 1000UF 6.3V 8X12
1UF 10V Y5V

GND
Q3
+5V_STBY BAT54C SOT23

D
Q8
C R14 G PHB66N03 TO263 C
+5V_STBY 1K 1%
R22

S
R15 10K 1% Q5
2N3904 SOT23
VDDIO_SENSE 7
R16

D
10K 1% /NI C12 15K
1UF 16V 0805 Y5V /NI +2.5VDIMM +2.5VDIMM
R17 4.7K G Q6 CONNECT FEEDBACK
18,21 SLP_S5-
R1
NEAR LOAD

C
S
NDS351N SOT23 1K 1%
+1.25VTT C502 R1
+5V_STBY +2.5VDIMM D4 R + +
+2.6VDIMM_FB 37
10UF 10V 0805 Y5V /NI CT28 CT1
U3
9

LM431 SOT23 CONNECT FEEDBACK 1000UF 6.3V 8X12

A
R316 R20 1000UF 6.3V 8X12
GND2

+ C504 1K 1% /NI R317 16K 1% NEAR LOAD

4 VOUT VIN 1
CT10 1UF 16V 0805 Y5V CT47 R2 JDDR_OV>3V
1000UF 6.3V 8X12 5 8 100K 100UF 16V 5X11 2mm 1
NC NC1
R1 2
7 NC2 REFEN 3 3
+5V_STBY Vout=Vref (2.5V) X ( 1+R1/R2 )
6 2 C505 C506 R318 HEADER 1X3 /NI
VCTNL GND1 100K =2.6136V DEFOUT : PIN(2_3)
1UF 10V Y5V
CT48 RT9173C SOP8EXP 1UF 10V Y5V /NI
22UF 25V 5X11 2mm

B USE RT9173-->R1 1K /NI B

USE RT9199-->R1 ADD 1K

+1.25VTT
CT5
+

100UF 16V 5X11 2mm

CT24
+

100UF 16V 5X11 2mm

+1.25VTT

C20
A A
0.1UF 25V Y5V /NI

Title
PLL DELAY / PWRGD / MEM VREG
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 32 of 39
5 4 3 2 1
 5 4 3 2 1

NO USE FUNCTION ADD R4 R5-->10K

VIN3 R319 10K 1% /NI
+5V
R269 4.7K VIN7 R320 10K 1% /NI GNDA
KBC'S ROM:1/BUILT IN,0/EXT.+5V R270 4.7K
PDR7 R3
PD7 28 GNDA 7,34
PDR6 R4 C490
28 DCD1# PD6 28
PDR5 0.1UF 25V Y5V
28 RI1# PD5 28 A
PDR4
28 CTS1# PD4 28
PDR3
28 DTR1# PD3 28
PDR2
28 RTS1# PD2 28
PDR1
28 DSR1# PD1 28
D PDR0 D
28 SOUTA PD0 28
28 SINA STB# 28
ALF# 28
EEROR# 28
INIT# 28
SLCTIN# 28
ACK# 28
BUSY 28 VREF
PE 28
SLCT 28

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
U14 8716 : R1-->BEAD 60 0805 1A C409 R223
8716 : C1-->1UF 1UF 10V Y5V 30K 1%
From CPU

CTS2#
RI2#
DCD2#
SIN1
SOUT1
DSR1#
RTS1#
DTR1#
CTS1#
RI1#
DCD1#
GNDD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
STB#
AFD#
ERR#
INIT#
SLIN#
ACK#
8712 : R1-->0 0805 CPU_THERMDA 7
1 DTR2# BUSY 102 8716 : C1-->1UF /NI C1 CPU_THERMDC 7,34
2 101 C507 1UF 10V Y5V /NI
RTS2# PE
3 DSR2# SLCT 100
R321 0 0805
Routed by differential
+5V 4 VCC VCC 99 +5V
5 98 VIN0 R1 C418 FB23
SOUT2 VIN0 VIN0 34
6 97 VIN1 3900P 50V X7R
SIN2 VIN1 VIN1 34
7 96 VIN2 BEAD 60 0805 1A
24 FAN1 FAN_TAC1 VIN2 VIN2 34
GP35: To generate an 24 FAN_CTL1 8 FAN_CTL1 VIN3 95 VIN3
VIN4
VIN3 34
9 94
event for the function 24
24
FAN2
FAN_CTL2 10
FAN_TAC2/GP52
FAN_CTL2/GP51
VIN4
VIN5 93 VIN5 VIN4
VIN5
34
34
THERMAL SHUTDOWN 24 FAN3 11 FAN_TAC3/GP37 VIN6 92 VIN6
VIN6 34
24 FAN_CTL3 12 FAN_CTL3/GP36 VIN7 91 VIN7
VREF
VIN7 34 A GP55: To provide BIOS
13 90
C
7,18 CHIP_THERM-
14
WTI#/GP35
VID4/GP34
VREF
TMPIN1 89 7,34 GNDA
Write Protection C
To CK8-04 15 GNDD TMPIN2 88 Function (Boot Block
16 87
17
VID3/GP33
VID2/GP32
TMPIN3
GNDA 86 Lock).
18 VID1/GP31 [5VSB PWR WELL] CIRRX/GP55 85
SMB_ALLERT- FWH_TBL- 34
19 VID0/GP30 [5VSB PWR WELL] SCRPRES#/GP10 84 SMB_ALLERT- 7 +3.3V_DUAL
20 JSBB2/GP27 [5VSB PWR WELL] MCLK 83 MCLK 25
21 JSBB1/GP26 [5VSB PWR WELL] MDAT 82 MDAT 25
37 VDIMM1 22 JSBCY/GP25 [5VSB PWR WELL] KCLK 81 KCLK 25
37 VDIMM0 23 JSBCX/GP24 [5VSB PWR WELL] KDAT 80 KDAT 25
24 LEDD1 24 79 R212
JSAB2/GP23 [5VSB PWR WELL] SCLK/GP40 EXTSMI- 18,21 4.7K
24 LEDD0 25 JSAB1/GP22 [5VSB PWR WELL] SDAT/GP41 78 SLEEPBTNJ 18,21
37 VCORE1 26 JSACY/GP21 [5VSB PWR WELL] RING#/GP53 77 To POWER LED
27 76
37 VCORE0
28
JSACX/GP20 [5VSB PWR WELL] PSON#/GP42
75 IO_PWIN circuit
MIDI_OUT/GP17 [5VSB PWR WELL] PANSWH#/GP43
51K P/U is R271 51K
29 MIDI_IN/GP16 GNDD 74
IO_PME- ACPI_LED 21
30 73
necessaried +3.3V
31
CIRTX/GP15 [PU51K]
SCRRST/GP14
[5VSB PWR WELL] PME#/GP54
[5VSB PWR WELL] PWRON#GP44 72 IO_POUT
on IX version +5V
32
33
SCRFET#/GP13 [5VSB PWR WELL] PSIN/GP45 71
70
LPC I/O 34
SCRIO/GP12
SCRCLK/GP11
[5VSB PWR WELL] IRRX/GP46
VBAT 69 R226 4.7K
+5V_STBY
R211 10K 1%
+3.3V_DUAL
35 68 R227 1M
LPC_PD# VCC [VBAT/5VSB PWR WELL] ] COPEN# IRRX 21
36 67
CLKRUN#/GP50

LPCRST_SIO- LPCPD# VCCH

16 LPCRST_SIO- 37 LRESET# IRTX/GP47 66 +3.3V_VBAT 18,25,37
LPC_DRQ0- 38 65
16 LPC_DRQ0- LDRQ# DSKCHG#
DENSEL#

WGATE#
WDATA#
LFRAME

RDATA#
HDSEL#
SERIRQ

C471

INDEX#
PCICLK

MTRA#
MTRB#
DRVA#
DRVB#
KRST#

STEP#

TRK0#
CLKIN
GNDD

WPT#
0.1UF 25V Y5V
GP54: To generate an
GA20
LAD0
LAD1
LAD2
LAD3

DIR#
B event for the function B
+3.3V IT8712FIX 8716 : R2-->10 SLEEP BUTTON, POWER
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
R2 8712 : R2-->0
R272 8.2K R322 0
+5V_STBY ON BY
LPC_SERIRQ CT49 KB/MOUSE,RING-IN
16 LPC_SERIRQ C487 +
LPC_FRAME- 100UF 16V 5X11 2mm
16,34 LPC_FRAME- 0.1UF 25V Y5V IO_PME- 18
LPC_AD0
16,34 LPC_AD0
16,34 LPC_AD1
LPC_AD1
LPC_AD2
To Power Supplier
16,34 LPC_AD2 LPC_AD3 IRTX 21 PS_ON- 24
16,34 LPC_AD3 SIO_KBRST- R273 0
18 SIO_KBRST-
18 A20GATE
A20GATE
LPCCLK_SIO
R262 0
R215 33 1%
From Power Button
16 LPCCLK_SIO PWRBTN- 21
FDSKCHG- 25
BUF_SIO_CLK
18 BUF_SIO_CLK FWP- 25
FINDEX- 25
R216 33 1%
To SB
24 FTRAK0- 25 PWBTOUT- 18
R259 R258 R275 R274
MHz 10K 1% 10K 1% 0 /NI 0 /NI
FRDATA- 25
FWEN- 25
FHEAD- 25 From SB
FSTEP- 25 SLP_S3- 18,24
+3.3V
FDIR- 25
FWD- 25
C419
FDSB- 25
470P 50V X7R /NI
FDSA- 25
FMOB- 25
A FMOA- 25 A
RN108
FRWC- 25
1 2 SUSCLK
3 4 LPC_PD#
+3.3V 5 6 LPC_DRQ0-
+5V_STBY 7 8 ACPI_LED
EXTSMI- R210 4.7K +3.3V_DUAL
4.7K 8P4R
RN104 SUSCLK SMB_ALLERT- R225 4.7K Title
18 SUSCLK +5V_STBY
+3.3V 1
3
2
4
LPC_AD0
LPC_AD1
LPC SUPER I/O IT8712F
5 6 LPC_AD2 Size Document Number Rev
Custom 1.3
7 8 LPC_AD3 CRU51-M7
8.2K 8P4R Date: Wednesday, April 12, 2006 Sheet 33 of 39
5 4 3 2 1
 5 4 3 2 1

Voltage Sensing
VCORE +1.2V +3.3V +5V +12V +2.5VDIMM +1.2V_HT +5V_STBY

D R217 R218 R219 R220 R208 R206 R284 R209 D

10K 1% 10K 1% 10K 1% 6.8K 30K 1% 10K 1% 10K 1% 6.8K /NI

ROM1 33 VIN0
33 VIN1
4MB 33 VIN2
16,33 LPC_AD[3..0] 33 VIN3
FLASH 33 VIN4
LPC_AD0 13 1
LPC_AD1 LAD0 NC1 33 VIN5
14 LAD1 NC2 22 33 VIN6
LPC_AD2 15 26
LPC_AD3 LAD2 NC3 33 VIN7
17 LAD3 NC4 27

23 24 FLASH_INIT
16,33 LPC_FRAME- FRAME* INIT* R207 R221 R222
31 18 10K 1% 10K 1% 10K 1% /NI
16 LPCCLK_FLASH LCLK RES1
RES2 19
16 LPCRST_FLASH- 2 RESET* RES3 20
RES4 21 A A A
FWH_WP- 7 25
WP* VDD1 +3.3V
VDD2 32
FWH_TBL- 8
33 FWH_TBL- TBL* C476 C475
GPI0 6
29 5 0.1UF 25V Y5V /NI C412 C413 C414 C415 C416 C491 C492 C417
GND
MODE GPI1 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
BIOS PROTECT 28 CS* GPI2 4
16 3 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
FUNCTION GND GPI3
30 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
GPI4 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
C 7,33 GNDA C
ID0 12
ID1 11 A
ID2 10
+3.3V 9
RN109 ID3
1 2 FWH_WP-
3 4 FWH_TBL- PLCC SOCKET 32PIN
FLASH_INIT
5
7
6
8
ADD SOCKET TO (BOM) MOTHERBOARD
4.7K 8P4R

RECOVERY HEADER

JUMPER 1-2 NORMAL

JUMPER REMOVED RECOVERY +3.3V

R196
1K 1%
B B
FLASH_RECOVERY-
18 FLASH_RECOVERY-

R198
10K 1%

A A

Title
FLASH ROM & H/W MON
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 34 of 39
5 4 3 2 1
 5 4 3 2 1

D D

MCP51_PWRGD 18

C319
0.1UF 25V Y5V /NI

24,32 PWRGD_PS PWRGD_PS R231 5.1K

C C

R232
10K 1%

+3.3V_DUAL

+3.3V_DUAL
B B

R252
15K
+5V_STBY R268 +5V_STBY
10K 1% PWRGD_SB
PWRGD_SB 18
HT_VLD
HT_VLD 16
R266 R265 C479
D

10K 1% 8.2K 1UF 10V Y5V

D
Q42 C489
+1.2V_HT
G 2N7002 SOT23 POWER SEQUENCING Q39
0.1UF 25V Y5V /NI G 2N7002 SOT23
+5V_STBY
S

HT_BASE

S
R267 6.34K 1% Q41
2N3904 SOT23 R264 PWRGD_Q1 Q40
30K 1% 2N3904 SOT23
C488 C483 C484
0.1UF 25V Y5V C486
0.1UF 25V Y5V
0.1UF 25V Y5V 10UF 10V 0805 Y5V

A A

Title
POWER SEQUENCING
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 35 of 39
5 4 3 2 1
 5 4 3 2 1

+5V
+5V
RN54 C500 0.1UF 25V Y5V
1 2 RXD0 C503 0.1UF 25V Y5V
19 RGMII_RXD0
3 4 RXD1
19 RGMII_RXD1
5 6 RXD2
19 RGMII_RXD2
7 8 RXD3 FOR EMI
19 RGMII_RXD3
FOR EMI
0 8P4R
U6
RTL8201BL : R1(NC); C1(NC)
D RGMII_MDC 25 32 PWFBOUT RTL8201CL/CP : R1(0 ohm); C1(0.1uF) D
19 RGMII_MDC MDC PWFBOUT
RGMII_MDIO 26 36 AVDD1 R1
19 RGMII_MDIO MDIO AVDD33
RGMII_TXD0 6 48 AVDD2
19 RGMII_TXD0 TXD0 DVDD33
RGMII_TXD1 5 PWFBOUT R124 0
19 RGMII_TXD1 TXD1
RGMII_TXD2 4 29 JUSBLAN1B
19 RGMII_TXD2 TXD2 AGND
RGMII_TXD3 3 35 C248 0.1UF 25V Y5V 1
19 RGMII_TXD3 TXD3 AGND TCT
RGMII_TXCTL 2 45 C1 11 LINK_LED
19 RGMII_TXCTL TXEN DGND GLED-
7 TXD+ 2 RN56
19 RGMII_TXCLK TXC TX0+
R119 0 22 12 330 8P4R
19 RGMII_RXCTL RXDV GLED+
RXD0 21 27 TXD- 3 1 2
RXD0 NC TX0- AVDD2
RXD1 20 13 3 4
RXD2 RXD1 RXIN+ YLED-
19 RXD2 4 TX1+ 5 6
RXD3 18 14 7 8 SPEED_LED
19 RGMII_RXCLK R120
MII_COL
22 16
RXD3
RXC
RTL8201 TPRX+ 31 RXIN+
RXIN-
RXIN- 5 TX1-
YLED+

19 MII_COL 1 COL TPRX- 30

19 MII_CRS MII_CRS 23 6
MII_RXER CRS TX2+
19 MII_RXER 24 RXER/FXEN GND G1
46 33 TXD- RTL8201BL:R3-->6.04K 1% 7 G2
19 BUF_25M X1 TPTX- TX2- GND
47 34 TXD+ G7
X2 TPTX+ GND
RTL8201CL:R3-->2K 1% 8 TX3+ GND G8
LINK_LED 9 R125 R135
LED1 LED0/PHYAD0 R121 2K 1% R129 51 1%
10 LED1/PHYAD1 RTSET 28 9 TX3-
LED2 12 43 ISOLATE 51 1% R140
SPEED_LED LED2/PHYAD2 ISOLATE RPTR 51 1% 51 1%
13 LED3/PHYAD3 RPTR 40 R3 10 RCT
LED3 15 39 SPEED C250 C261
LED4/PHYAD4 SPEED DUPLEX RJ45USBA CONN
DUPLEX 38 R2
PWFBIN 8 37 ANE 0.1UF 25V Y5V 0.1UF 25V Y5V
AVDD2 PWFBIN ANE LDPS R126 0 PWFBOUT
14 DVDD33 LDPS 41
44 MII_L NEAR CONNECTOR NEAR PHY
MII/SNIB/RTT3 RESETT R134 0 /NI C254 0.1UF 25V Y5V
C 11 DGND RESETB 42 RGMII_RESET- 18 C
17 DGND
RTL8201BL : R2(NC)
RTL8201CL TQFP48 RN69 RTL8201CL/CP : R2(0 ohm)
RPTR 2 5.6K 8P4R
PHY address set to 00001h LDPS
1
3 4
SPEED FB16
5 6
DUPLEX 7 8 AVDD2 AVDD1
AVDD2
BEAD 60 0805 1A
ISOLATE 1 2 C289
MII_L 3 4 RN71 0.1UF 25V Y5V
ANE 5 6 5.6K 8P4R
LINK_LED 7 8 AVDD2

FB14
R279 is reserved for
PWFBIN PWFBOUT
8201CL/CP LED Mode LINK_LED AVDD2
Change to compatible BEAD 60 0805 1A
MII_COL R128 5.1K /NI C252 CT22
with BL MII_RXER R117 5.1K /NI 0.1UF 25V Y5V C258 22UF 25V 5X11 2mm
MII_CRS R118 5.1K /NI 0.1UF 25V Y5V
D20
A K

1N4148 SMD SPEED_LED 1 2

R280 is reserved for LED3 3 4 RN58 AVDD2
LED2 5 6 5.6K 8P4R
ensuring 8201BL/CL/CP LED1 7 8
B latch to UTP Mode. B

C280 C240
1UF 16V 0805 Y5V
AVDD1 AVDD2 AVDD2 0.1UF 25V Y5V FB18
BEAD 60 0805 1A
R281 is reserved for C279 AVDD2
+3.3V_STBY
C270 C285
ensuring 8201CL/CP 0.1UF 25V Y5V 0.1UF 25V Y5V /NI 0.1UF 25V Y5V /NI
latch to normal C281 C241
1UF 16V 0805 Y5V /NI
operation mode. 0.1UF 25V Y5V /NI
AVDD2

RESETT R131 5.1K

RGMII_MDIO R115 1.5K 1%

C263 0.1UF 25V Y5V

A A

Title
LAN (RTL8100B)
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 36 of 39
5 4 3 2 1
 5 4 3 2 1

D D

7 K8_VID4 R11 1K 1% VID_OUT4 31

VCORE0 VCORE1
+3.3V RN1 VCORE_OVL GPIO0 GPIO1
7 K8_VID3 2 1 VID_OUT3 31
7 K8_VID2 4 3 VID_OUT2 31 Default
7 K8_VID1 6 5 VID_OUT1 31 1.550V 1 1
C493 8 7 DIMM0 DIMM1
7 K8_VID0 VID_OUT0 31
0.1UF 25V Y5V /NI Dimm over volgate GPIO GPIO
1K 8P4R 3 4 1.602V 0 1
1K -----> FOR IT8203 /NI Default 1 1
+3.3V_STBY
1K /NI -----> FOR ADD IT8203
2.72V 0 1 1.653V 1 0
+3.3V 2.82V 1 0
1.705V 0 0
2.93V 0 0
R290
2
4
6
8

RN110 R291 1K 1% /NI

1K 8P4R /NI 1K 1% /NI U15
IT8203 OV_DIMM0 R292 22K /NI OV_VCORE0 R293 3K 1% /NI
+2.6VDIMM_FB 32 OVL 31
1
3
5
7

1 3V_SB TEST/ASEL 28
OV_DIMM0 2 27 OV_DIMM1 R294 12.1K 1% /NI OV_VCORE1 R295 1.5K 1% /NI
GPIO3 GPIO6 OV_HT0 38 +2.6VDIMM_FB 32 OVL 31
OV_DIMM1 3 26
GPIO4 GPIO7 OV_HT1 38
4 PGIO5 GPIO8 25 OV_CHIP0 38
7 K8_VID0 5 VID_IN0 GPIO9 24 OV_CHIP1 38
7 K8_VID1 6 VID_IN1 VID_OUT0 23 VID_OUT0 31 +3.3V_VBAT 18,25,33
7 K8_VID2 7 VID_IN2 VID_OUT1 22 VID_OUT1 31
7 K8_VID3 8 VID_IN3 VID_OUT2 21 VID_OUT2 31
7 K8_VID4 9 20 R296
VID_IN4 VID_OUT3 VID_OUT3 31
10 19 10M /NI
31 OV_VCORE0 GPIO0 VID_OUT4 VID_OUT4 31
31 OV_VCORE1 11 GPIO1 VBAT 18 +3.3V_VBAT 18,25,33 10M -----> FOR INTEL CHIP
31 OV_VCORE2 12 GPIO2 SLOTOCC# 17 0 /NI -----> FOR K8 CPU
13 SDA GND 16
7,18,20,22 SMB_SDA
14 SCL RSTOUT# 15 FP_RESET- 18,21
7,18,20,22 SMB_SCL R297
C 0 /NI C
ATXP3 SSOP28 /NI 1UF 10V Y5V -----> FOR INTEL CHIP
0-----> FOR K8 CPU

R2 26.1K 1%
+2.6VDIMM_FB 32

R18
12.1K 1%
C

+2.6VDIMM_FB VDIMM0 VDIMM1

B B
Default
B

2.656V 1 1
C

E
C

Q1
BT2222A SOT23 2.72V 0 1
Q9
+5V_STBY +5V_STBY BT2222A SOT23
B

2.82V 1 0
B

RN106
7 8
8
6
4
2

5 6 Q44 NEAR +2.6V 2.93V 0 0

RN3 33 VDIMM1 3 4 2N3904 SOT23 Q43
33 VDIMM0 1 2 2N3904 SOT23
1K 8P4R
10K 8P4R R23 3K 1%
7
5
3
1

OVL 31
VCORE_OVL VCORE0 VCORE1
R19 Default
1.5K 1% 1 1
1.550V
C

1.602V 0 1

1.653V 1 0
B

E
C

E
C

Q10 1.705V 0 0
BT2222A SOT23
Q7
+5V_STBY BT2222A SOT23
B

RN107
7 8
5 6 Q36
33 VCORE0 3 4 2N3904 SOT23 Q37
33 VCORE1 1 2 2N3904 SOT23
A A
10K 8P4R NEAR PWM

Title
OVER VOLTAGE
Size Document Number Rev
C 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 37 of 39
5 4 3 2 1
 5 4 3 2 1

CK51 CORE
+5V
D D

+5V +5V_STBY

+3.3V_STBY

L5 R156 +
RH TYPE BEAD 2.7 0805 D13 CT25

K A
RT9202NC/RT9214 SS12/5817 SMA 100UF 16V 5X11 2mm

R173 15K
C318 VIN_5V Q22 R148
R1
I 200 1%
Q32 + O
R172 1UF 16V 0805 Y5V FDD8880 TO252 C317 CT34 A +
RT9202/RT9214NC 15K /NI U10 1UF 10V Y5V CT21

5
1000UF 6.3V 8X12 100UF 16V 5X11 2mm
7 1 C299
HT AZ1117H-ADJ SOT-223 R147

VCC
COMP BOOT R175 2.7 0805 0.1UF 25V Y5V 330
UGATE 2 R2
R171 R166 10 INDUCTOR 1UH D
20K /NI C322 PHASE 8 +1.2V +1.2V @ 10A AMPS MAX +1.2V_HT
C323 15P 50V NPO /NI L4 +1.2V

GND
6 FB 4 R165 2.7 0805 R187 + + R180
LGATE Q29 2.7 0805 CT29 CT33 100 1% R1
4700P 50V X7R /NI RT9214 SOP8 FDD8880 TO252 1000UF 6.3V 8X12 Vout=Vref (1.25V) X ( 1+R2/R1 )
1000UF 6.3V 8X12 BC13
3

+ =3.3V
C333 CT27 0.1UF 25V Y5V
C 1000P 50V X7R R183 820 /NI 100UF 16V 5X11 2mm C
OV_CHIP1 37
R186 1.6K /NI
OV_CHIP0 37
Vout=0.8(1+R1/R2)----for RT9202
R181
接在一起用相同的GND 200 1% R1 , R2 阻值不要選超過 K ohm
VIA
R2
CORE VOLTAGE OV_CHIP0 OV_CHIP1
+3.3V_DUAL
+1.2V 1 1
R155 +1.25V 0 1
10K 1%
+3.3V +1.3V 1 0
ADD AN ENABLE CKT - LOW IS OFF
Q26 Q23 3.3V MUST BE PWR ON BEFOR 5V +1.35V 0 0
2N3904 SOT23 2N3904 SOT23 OR SOFT START WILL NOT WORK.
C_ENBL2 R153 4.7K

+2.5VDDA +12V_P

+5V
R182

D
Q30 5.1K
B 2N7002 SOT23 B
G R184
Q31 5.1K

S
REF_2.5V 2N3904 SOT23
R185 4.7K

Q33
2N3904 SOT23
R188 47K
HTVDD_EN 16
C334
1UF 16V 0805 Y5V
+12V_P
+12V Change to +12V_P
+3.3V

C321 +
R174 0.1UF 25V Y5V CT13

D
680 100UF 16V 5X11 2mm
4

V1 10 +
8 G Q19
9 FDD8880 TO252
-
R167 U11C

S
649 1% LM324 SO14
11

R310 0
+1.2V_HT
HT A

Vout=V1=1.22V
+1.2V_HT @ 850MA AMPS
MAX
+
CT15
37 OV_HT0 R298 412 1% /NI 1000UF 6.3V 8X12
R299 130 1% /NI Title
37 OV_HT1
C51 CORE
Size Document Number Rev
Custom 1.3
CRU51-M7
Date: Wednesday, April 12, 2006 Sheet 38 of 39
5 4 3 2 1
 5 4 3 2 1

D D

JDDR_OV>3V(2_3)
JUMPER 2P R /NI
(BAT1)
JUSBV1(1_2)
JUMPER 2P R
電池

JUSBV2(1_2)
JUMPER 2P R
New JPANEL1 含IR
3V BATTERY SONY
JPANEL1 2*12
JPANEL1(2_4) JPANEL1(14_16)
JFAUDIO1(5_6) (ROM1) HEADER 1X2 HEADER 1X2_3
JUMPER 2P B JPANEL1(6_8_10_12)
PLED
FLASH ROM JPANEL1(19_24)
JFAUDIO1(9_10) IR
JUMPER 2P B
JPANEL1(1_3_5_7) JPANEL1(13_15)
C C
PLCC 4MF+L SPK JPANEL1(9_11)
JFAUDIO1(11_12) HLED RST_3
JUMPER 2P B (CPU1)

JFAUDIO1(13_14)
JUMPER 2P B

JCMOS1(1_2)
JUMPER 2P B

PCB K8RM

(U8)

PCB

北橋散熱片

B CRU51-M7 1.3 B

(PCB)
NBHN

泡棉 (U12)

POLON 245x220 南橋散熱片

SBNP SMALL

A A

Title
BOM
Size Document Number Rev
B 1.3
CRU51-M7
Date: Monday, April 10, 2006 Sheet 39 of 39
5 4 3 2 1